library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity wyswietlacz is
port(i: in bit_vector(3 downto 0);
p: in bit;
clk: in bit;
o: out std_logic_vector(6 downto 0);
o2: out std_logic_vector(6 downto 0));
end wyswietlacz;
architecture beh of wyswietlacz is
signal liczba: unsigned(9 downto 0);
signal liczba2: std_logic_vector(9 downto 0);
signal liczba02: unsigned(9 downto 0);
signal liczba22: std_logic_vector(9 downto 0);
SIGNAL liczsek : STD_LOGIC_VECTOR(24 DOWNTO 0);
begin
process(clk) is
begin
IF (clk'EVENT AND clk = '1') THEN
liczsek <= liczsek + '1';
END IF;
end process;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (liczsek = 0) THEN
liczba <= liczba + 1;
liczba2 <= std_logic_vector(liczba);
if liczba >= 9 then
liczba <= to_unsigned(0000000000,10);
end if;
if liczba = 0 then
liczba02 <= liczba02 + 1;
if liczba02 >= 9 then
liczba02 <= to_unsigned(0000000000,10);
end if;
liczba22 <= std_logic_vector(liczba02);
end if;
END IF;
END IF;
END PROCESS;
with liczba2 select
o <= "1000000" when "0000000000",
"1111001" when "0000000001",
"0100100" when "0000000010",
"0110000" when "0000000011",
"0011001" when "0000000100",
"0010010" when "0000000101",
"0000010" when "0000000110",
"1111000" when "0000000111",
"0000000" when "0000001000",
"0010000" when "0000001001",
"XXXXXXX" when others;
with liczba22 select
o2 <= "1000000" when "0000000000",
"1111001" when "0000000001",
"0100100" when "0000000010",
"0110000" when "0000000011",
"0011001" when "0000000100",
"0010010" when "0000000101",
"0000010" when "0000000110",
"1111000" when "0000000111",
"0000000" when "0000001000",
"0010000" when "0000001001",
"XXXXXXX" when others;
end beh;