1. `include "defines.vh"
2. module signal_generation_unit (
3.         input  wire  [`STAGE_COUNT-1:0] pipeline_stage,
4.         input  wire [`OPCODE_COUNT-1:0] opcode_type,
5.         input  wire  [`GROUP_COUNT-1:0] opcode_group,
6.         output wire [`SIGNAL_COUNT-1:0] signals
7.     );
8.  
9.     /* Control signals */
10.  
11.     /* Register interface logic */
12.          /* TODO 4: STS */
13.          /* TODO 7: register reads */
14.     assign signals
15.          [`CONTROL_REG_RR_READ] =
16.             (pipeline_stage == `STAGE_ID) &&
17.             (opcode_group[`GROUP_ALU_TWO_OP] || opcode_type == `TYPE_STS || opcode_type == `TYPE_LD_Y);
18.     assign signals[`CONTROL_REG_RR_WRITE] = 0;
19.     assign signals[`CONTROL_REG_RD_READ] =
20.             (pipeline_stage == `STAGE_ID) &&
21.             (opcode_group[`GROUP_ALU] || opcode_type == `TYPE_LDS || opcode_type == `TYPE_LD_Y);
22.     assign signals[`CONTROL_REG_RD_WRITE] =
23.                                 /* TODO 3: LDI */
24.                                 /* TODO 5,6,7: register writes */
25.             (pipeline_stage == `STAGE_WB) &&
26.             (opcode_group[`GROUP_ALU] || opcode_type == `TYPE_LDI || opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_MOV || opcode_type == `TYPE_LDS);
27.        
28.     /* Memory interface logic */
29.          /* TODO 5,6: LOADs */
30.     assign signals[`CONTROL_MEM_READ] =
31.            (pipeline_stage == `STAGE_MEM) &&
32.            (opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_LDS);
33.          /* TODO 4: STS
34.          inspectati bus_interface_unit.v */
35.     assign signals[`CONTROL_MEM_WRITE] =
36.            (pipeline_stage == `STAGE_MEM) &&
37.            (opcode_type == `TYPE_STS);
38. endmodule