entity ffXY is
port X, Y, Z, CLK, CLR: in std_logic;
Q: out std_logic;
end ffXY;
architecture comportamento of ffXY is
signal BQ, proximo: std_logic;
signal XY: std_logic_vector(1 downto 0);
begin
process (CLK, CLR)
begin
if (CLR = '1') then
BQ <= 0;
elsif (CLK'event and CLK = '1') then
if (X = '0' and Y = '0') then
BQ <= Q;
elsif (X = '1' and Y = '0') then
BQ <= Z;
elsif (X = '0' and Y = '1') then
BQ <= not Z;
elsif (X = '1' and Y = '1') then
BQ <= not Q;
end if;
end if;
end process;
Q <= BQ;
end comportamento;
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