- --------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 14:40:59 12/17/2018
- -- Design Name:
- -- Module Name: C:/Users/lab/lab500/lab5test.vhd
- -- Project Name: lab500
- -- Target Device:
- -- Tool versions:
- -- Description:
- --
- -- VHDL Test Bench Created by ISE for module: lab55
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- -- Notes:
- -- This testbench has been automatically generated using types std_logic and
- -- std_logic_vector for the ports of the unit under test. Xilinx recommends
- -- that these types always be used for the top-level I/O of a design in order
- -- to guarantee that the testbench will bind correctly to the post-implementation
- -- simulation model.
- --------------------------------------------------------------------------------
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --USE ieee.numeric_std.ALL;
- ENTITY lab5test IS
- END lab5test;
- ARCHITECTURE behavior OF lab5test IS
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT lab55
- PORT(
- DI : IN std_logic_vector(7 downto 0);
- RDY : IN std_logic;
- RST : IN std_logic;
- CLK : IN std_logic;
- CE : IN std_logic;
- Y : OUT std_logic
- );
- END COMPONENT;
- --Inputs
- signal DI : std_logic_vector(7 downto 0) := (others => '0');
- signal RDY : std_logic := '0';
- signal RST : std_logic := '0';
- signal CLK : std_logic := '0';
- signal CE : std_logic := '1';
- --Outputs
- signal Y : std_logic;
- type data_type is array (0 to 18) of std_logic_vector(7 downto 0);
- -- Clock period definitions
- constant CLK_period : time := 10 ns;
- signal data : data_type :=(
- X"15",
- X"15",
- X"15",
- X"3B",
- X"42",
- X"42",
- X"42",
- X"15",
- X"15",
- X"15",
- X"3B",
- X"42",
- X"42",
- X"3B",
- X"42",
- X"42",
- X"42",
- X"15",
- X"15"
- );
- BEGIN
- -- Instantiate the Unit Under Test (UUT)
- uut: lab55 PORT MAP (
- DI => DI,
- RDY => RDY,
- RST => RST,
- CLK => CLK,
- CE => CE,
- Y => Y
- );
- -- Clock process definitions
- CLK_process :process
- begin
- CLK <= '0';
- wait for CLK_period/2;
- CLK <= '1';
- wait for CLK_period/2;
- end process;
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait until falling_edge (clk);
- wait for CLK_period;
- for i in 0 to 18 loop
- wait until falling_edge(Clk);
- RDY <= '1';
- DI <= data(i);
- wait for CLK_period;
- RDY <= '0';
- wait for CLK_period;
- wait until falling_edge(Clk);
- RDY <= '1';
- -- DI <= X"F0";
- wait for CLK_period;
- RDY <= '0';
- wait for CLK_period;
- wait until falling_edge(Clk);
- RDY <= '1';
- DI <= data(i);
- wait for CLK_period;
- RDY <= '0';
- wait for CLK_period;
- END loop;
- wait;
- end process;
- END;
- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 14:16:45 12/17/2018
- -- Design Name:
- -- Module Name: lab55 - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity lab55 is
- Port ( DI : in STD_LOGIC_VECTOR (7 downto 0);
- RDY : in STD_LOGIC;
- RST : in STD_LOGIC;
- CLK : in STD_LOGIC;
- CE : in STD_LOGIC;
- Y : out STD_LOGIC);
- end lab55;
- architecture Behavioral of lab55 is
- type state_type is (q0,q1,q2,q3,q4);
- signal state, next_state : state_type;
- begin
- process1 : process (CLK)
- begin
- if CE = '1' then
- if rising_edge(CLK) then
- if RST = '1' then
- state <= q0;
- elsif RDY = '1' then
- state <= next_state;
- end if;
- end if;
- end if;
- end process process1;
- process2 : process (state, RDY)
- begin
- next_state <= state;
- case state is
- when q0 =>
- if DI = X"3B" then
- next_state <=q1;
- else
- next_state <=q0;
- end if;
- when q1 =>
- if DI = X"42" then
- next_state <= q2;
- else
- next_state <= q0;
- end if;
- when q2 =>
- if DI = X"42" then
- next_state <= q3;
- else
- next_state <= q0;
- end if;
- when q3 =>
- if DI = X"42" then
- next_state <= q4;
- else
- next_state <=q0;
- end if;
- when q4 =>
- if DI = X"3B" then
- next_state <= q1;
- else
- next_state <= q0;
- end if;
- end case;
- end process process2;
- Y<='1' when state = q4 else '0';
- end Behavioral;