1. LIBRARY ieee;
2. USE ieee.std_logic_1164.ALL;
3. USE ieee.std_logic_arith.ALL;
4.  
5. ENTITY ram_dual IS
6.         PORT (
7.                         clock: IN STD_LOGIC;
8.                         data: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
9.                         write_address: IN INTEGER RANGE 0 to 31;
10.                         read_address: IN INTEGER RANGE 0 to 31;
11.                         we: IN STD_LOGIC;
12.                         q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
13. );
14. END ram_dual;
15.  
16. ARCHITECTURE rtl OF ram_dual IS
17. TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(3 DOWNTO 0);
18. SIGNAL ram_block: MEM;
19. SIGNAL read_address_reg : INTEGER RANGE 0 to 31;
20. BEGIN
21.                 PROCESS (clock)
22.                         BEGIN
23.                         IF (clock1'event AND clock1 = '1') THEN
24.                                 IF (we = '1') THEN
25.                                         ram_block(write_address) <= data;
26.                                 else q <= ram_block(read_address);--mozliwe ze trzeba bedzie bez elsa znaczy end if; potem q<=...
27.                                 END IF;
28.                         END IF;
29.       END PROCESS;
30.  
31.  
32. END rtl;
33.  
34. -------------------------------------------------------------
35.  
36. LIBRARY ieee;
37. USE ieee.std_logic_1164.ALL;
38. USE ieee.std_logic_arith.ALL;
39.  
40. ENTITY ram IS
41.         PORT ( data: IN std_logic_vector (3 downto 0);
42.         wren,clock, acc, acc2: IN std_logic;
43. END ram;
44.  
45. architecture behavior of ram is
46.         signal wyjscie: std_logic_vector(0 to 3);
47.         signal address: integer Range 0 to 31 := 0;
48.         signal address2: integer Range 0 to 31 := 0;
49.         signal v1: std_logic_vector (0 to 3);
50.         signal v2: std_logic_vector (0 to 3);
51.  
52.         component ram_dual IS
53.                 Port(  
54.                         clock: IN STD_LOGIC;
55.                         data: IN STD_LOGIC_VECTOR (3 downto 0);
56.                         write_address: IN Integer Range 0 to 31 := 0;
57.                         read_address: IN Integer Range 0 to 31 := 0;
58.                         we: In STD_LOGIC;
59.                         q: OUT STD_LOGIC_VECTOR (3 downto 0));
60.         end component ram_dual;
61.  
62.         PROCESS(clock)
63.                 BEGIN
64.                         IF (acc'event AND acc = '1') THEN
65.                                 address <= address + 1;
66.                                 v1 <= conv_std_logic_vector (address, 4);
67.                         END IF;
68.                
69.                         IF(acc2'event AND acc2 = '1') THEN
70.                                 address2 <= address2 + 1;
71.                                 v2 <= conv_std_logic_vector(address2,4);
72.                         END IF;
73.         END PROCESS;
74.        
75. ram_one: ram_dual port map(clock, data, address, address2, wren, wyjscie);     
76.                
77. END behavior;
78.