1. ----------------------------------------------------------------------------------
2. -- Company:
3. -- Engineer:
4. --
5. -- Create Date:    13:14:18 03/22/2019
6. -- Design Name:
7. -- Module Name:    modul - Behavioral
8. -- Project Name:
9. -- Target Devices:
10. -- Tool versions:
11. -- Description:
12. --
13. -- Dependencies:
14. --
15. -- Revision:
16. -- Revision 0.01 - File Created
17. -- Additional Comments:
18. --
19. ----------------------------------------------------------------------------------
20. library IEEE;
21. use IEEE.STD_LOGIC_1164.ALL;
22.  
23. -- Uncomment the following library declaration if using
24. -- arithmetic functions with Signed or Unsigned values
25. --use IEEE.NUMERIC_STD.ALL;
26.  
27. -- Uncomment the following library declaration if instantiating
28. -- any Xilinx primitives in this code.
29. --library UNISIM;
30. --use UNISIM.VComponents.all;
31.  
32. entity modul is
33.   Port ( clk      : in STD_LOGIC;
34.          reset    : in STD_LOGIC;
35.          OW_DQ    : inout STD_LOGIC;
36.          ow_pres  : out STD_LOGIC);    
37. end modul;
38.  
39. architecture Behavioral of modul is
40.  
41. component IOBUF
42.    Port ( IO : inout STD_LOGIC;
43.           I  : in STD_LOGIC;
44.           O  : out STD_LOGIC;
45.           T  : in STD_LOGIC);
46. end component;
47.  
48. signal ow_in   :std_logic;
49. signal ow_out  :std_logic;
50.  
51.  
52. begin
53.  
54. buff : IOBUF
55.    port map( I => '0',
56.              T => ow_out,
57.              O => ow_in,
58.              IO => OW_DQ);
59.  
60. ow_out <= '0';
61.  -- SYMULACJA?
62. ow_out <= '1';
63.  
64. ow_pres <= not ow_in;
65. end Behavioral;
66.  
67.