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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 21.10.2020 15:08:15
  6. -- Design Name:
  7. -- Module Name: tb - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20.  
  21.  
  22. library IEEE;
  23. use IEEE.STD_LOGIC_1164.ALL;
  24.  
  25. -- Uncomment the following library declaration if using
  26. -- arithmetic functions with Signed or Unsigned values
  27. --use IEEE.NUMERIC_STD.ALL;
  28.  
  29. -- Uncomment the following library declaration if instantiating
  30. -- any Xilinx leaf cells in this code.
  31. --library UNISIM;
  32. --use UNISIM.VComponents.all;
  33.  
  34. entity tb is
  35. --  Port ( );
  36. end tb;
  37.  
  38. architecture Behavioral of tb is
  39.     component top
  40.     Port ( clk_i : in std_logic;
  41.            sw_i : in  std_logic_vector(7 downto 0);
  42.            btn_i : in  std_logic_vector(3 downto 0);
  43.            led7_an_o : out  std_logic_vector(3 downto 0);
  44.            led7_seg_o : out  std_logic_vector(7 downto 0));
  45.     end component;
  46.  
  47.     signal clk_i : std_logic := '0';
  48.     signal sw_i : std_logic_vector(7 downto 0) := (others => '0');
  49.     signal btn_i : std_logic_vector(3 downto 0) := (others => '0');
  50.     signal led7_an_o : std_logic_vector(3 downto 0);
  51.     signal led7_seg_o : std_logic_vector(7 downto 0);
  52.  
  53. begin
  54.    uut: top
  55.    port map ( clk_i => clk_i,
  56.               sw_i => sw_i,
  57.               btn_i => btn_i,
  58.               led7_an_o => led7_an_o,
  59.               led7_seg_o => led7_seg_o);
  60.              
  61.     clk_i <= not clk_i after 5 ns; --okres zegara to 10 ns, czli 100MHz
  62.      
  63.    stim : process
  64.    begin
  65.         sw_i <= "00000011";
  66.                 btn_i <= "0000";
  67.                 wait for 10 ns;
  68.         btn_i <= "0001";
  69.                 wait for 10 ns;
  70.         btn_i <= "0000";
  71.         wait for 10 ns;
  72.         sw_i <= "00010011";
  73.         wait for 10 ns;
  74.         btn_i <= "0001";
  75.         wait for 10 ns;
  76.         btn_i <= "0000";
  77.         wait for 10 ns;
  78.         sw_i <= "00000011";
  79.         wait;
  80.    end process;
  81.  
  82.  
  83. end Behavioral;
  84.