1. ----------------------------------------------------------------------------------
2.  
3. -- Company:
4.  
5. -- Engineer:
6.  
7. --
8.  
9. -- Create Date:    14:59:23 03/03/2018
10.  
11. -- Design Name:
12.  
13. -- Module Name:    TOP - Behavioral
14.  
15. -- Project Name:
16.  
17. -- Target Devices:
18.  
19. -- Tool versions:
20.  
21. -- Description:
22.  
23. --
24.  
25. -- Dependencies:
26.  
27. --
28.  
29. -- Revision:
30.  
31. -- Revision 0.01 - File Created
32.  
33. -- Additional Comments:
34.  
35. --
36.  
37. ----------------------------------------------------------------------------------
38.  
39. library IEEE;
40.  
41. use IEEE.STD_LOGIC_1164.ALL;
42.  
43.  
44.  
45. -- Uncomment the following library declaration if using
46.  
47. -- arithmetic functions with Signed or Unsigned values
48.  
49. --use IEEE.NUMERIC_STD.ALL;
50.  
51.  
52.  
53. -- Uncomment the following library declaration if instantiating
54.  
55. -- any Xilinx primitives in this code.
56.  
57. --library UNISIM;
58.  
59. --use UNISIM.VComponents.all;
60.  
61.  
62.  
63. entity TOP is
64.  
65.     Port ( rst_i : in  STD_LOGIC;
66.  
67.            clk_i : in  STD_LOGIC;
68.  
69.            led_o : out  STD_LOGIC_VECTOR (1 downto 0));
70.  
71. end TOP;
72.  
73.  
74.  
75. architecture Behavioral of TOP is
76.  
77. component grayCounter
78.  
79.  
80.  
81.         Port ( clk : in  STD_LOGIC;
82.  
83.            rst : in  STD_LOGIC;
84.  
85.            counter_out : out  STD_LOGIC_VECTOR (1 downto 0));
86.  
87.  
88.  
89. end component;
90.  
91. begin
92.  
93.  
94.  
95.         c: grayCounter
96.  
97.         port map(
98.  
99.         rst => rst_i,
100.  
101.         clk => clk_i,
102.  
103.         counter_out => led_o);
104.  
105.  
106.  
107. end Behavioral;
108.  
109.  
110.  
111.