1. module mux2to1_3bit(input [2:0] in0, input [2:0] in1, input select, output reg [2:0] muxOut);
2.   //WRITE CODE HERE
3.         always@(select)
4.         begin
5.         case(select)
6.         1'b0 : muxOut = in0;
7.         1'b1 : muxOut = in1;
8.         endcase
9.         end
10.  
11. endmodule
12.  
13. // select 0 = in0 1 = in1
14. module mux2to1_8bit(input [7:0] in0, input [7:0] in1, input select, output reg [7:0] muxOut);
15.    //WRITE CODE HERE
16.          always@(select)
17.         begin
18.         case(select)
19.         1'b0 : muxOut = in0;
20.         1'b1 : muxOut = in1;
21.         endcase
22.         end
23.        
24. endmodule
25.  
26.  
27. module mux8to1_1bit(input in0, input in1, input in2, input in3, input in4, input in5, input in6, input in7, input[2:0] select,output reg muxOut);
28.    //WRITE CODE HERE
29.          always@(select)
30.          begin
31.          case(select)
32.                 3'b000 : muxOut = in0;
33.                 3'b001 : muxOut = in1;
34.                 3'b010 : muxOut = in2;
35.                 3'b011 : muxOut = in3;
36.                 3'b100 : muxOut = in4;
37.                 3'b101 : muxOut = in5;
38.                 3'b110 : muxOut = in6;
39.                 3'b111 : muxOut = in7;
40.         endcase
41.         end
42. endmodule
43.  
44. module barrelshifter(input[2:0] shiftAmt, input[7:0] b, input[2:0] oper, output[7:0] shiftOut);
45.            //WRITE CODE HERE
46.                  wire [7:0]l1;
47.                  wire [7:0]l2;
48.                  wire [2:0]w1;
49.                  wire [2:0]w2;
50.                  wire [2:0]w3;
51.  
52.                  mux2to1_3bit M0(.in0(3'b000), .in1(oper[2:0]), .select(shiftAmt[0]), .muxOut(w1[2:0]));
53.                  mux2to1_3bit M1(.in0(3'b000), .in1(oper[2:0]), .select(shiftAmt[1]), .muxOut(w2[2:0]));
54.                  mux2to1_3bit M3(.in0(3'b000), .in1(oper[2:0]), .select(shiftAmt[2]), .muxOut(w3[2:0]));
55.  
56.                  mux8to1_1bit m0(.in0(b[0]), .in1(b[1]), .in2(b[1]), .in3(b[1]), .in4(1'b0), .in5(b[7]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[0]));
57.                  mux8to1_1bit m1(.in0(b[1]), .in1(b[2]), .in2(b[2]), .in3(b[2]), .in4(b[0]), .in5(b[0]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[1]));
58.                  mux8to1_1bit m2(.in0(b[2]), .in1(b[3]), .in2(b[3]), .in3(b[3]), .in4(b[1]), .in5(b[1]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[2]));
59.                  mux8to1_1bit m3(.in0(b[3]), .in1(b[4]), .in2(b[4]), .in3(b[4]), .in4(b[2]), .in5(b[2]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[3]));
60.                  mux8to1_1bit m4(.in0(b[4]), .in1(b[5]), .in2(b[5]), .in3(b[5]), .in4(b[3]), .in5(b[3]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[4]));
61.                  mux8to1_1bit m5(.in0(b[5]), .in1(b[6]), .in2(b[6]), .in3(b[6]), .in4(b[4]), .in5(b[4]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[5]));
62.                  mux8to1_1bit m6(.in0(b[6]), .in1(b[7]), .in2(b[7]), .in3(b[7]), .in4(b[5]), .in5(b[5]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[6]));
63.                  mux8to1_1bit m7(.in0(b[7]), .in1(b[7]), .in2(1'b0), .in3(b[0]), .in4(b[6]), .in5(b[6]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[7]));
64.  
65.                  mux8to1_1bit n0(.in0(l1[0]), .in1(l1[2]), .in2(l1[2]), .in3(l1[2]), .in4(1'b0), .in5(l1[6]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[0]));
66.                  mux8to1_1bit n1(.in0(l1[1]), .in1(l1[3]), .in2(l1[3]), .in3(l1[3]), .in4(1'b0), .in5(l1[7]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[1]));
67.                  mux8to1_1bit n2(.in0(l1[2]), .in1(l1[4]), .in2(l1[4]), .in3(l1[4]), .in4(l1[0]), .in5(l1[0]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[2]));
68.                  mux8to1_1bit n3(.in0(l1[3]), .in1(l1[5]), .in2(l1[5]), .in3(l1[5]), .in4(l1[1]), .in5(l1[1]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[3]));
69.                  mux8to1_1bit n4(.in0(l1[4]), .in1(l1[6]), .in2(l1[6]), .in3(l1[6]), .in4(l1[2]), .in5(l1[2]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[4]));
70.                  mux8to1_1bit n5(.in0(l1[5]), .in1(l1[7]), .in2(l1[7]), .in3(l1[7]), .in4(l1[3]), .in5(l1[3]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[5]));
71.                  mux8to1_1bit n6(.in0(l1[6]), .in1(l1[7]), .in2(1'b0), .in3(l1[0]), .in4(l1[4]), .in5(l1[4]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[6]));
72.                  mux8to1_1bit n7(.in0(l1[7]), .in1(l1[7]), .in2(1'b0), .in3(l1[1]), .in4(l1[5]), .in5(l1[5]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[7]));
73.  
74.                  mux8to1_1bit o0(.in0(l2[0]), .in1(l2[4]), .in2(l2[4]), .in3(l2[4]), .in4(1'b0), .in5(l2[4]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[0]));
75.                  mux8to1_1bit o1(.in0(l2[1]), .in1(l2[5]), .in2(l2[5]), .in3(l2[5]), .in4(1'b0), .in5(l2[5]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[1]));
76.                  mux8to1_1bit o2(.in0(l2[2]), .in1(l2[6]), .in2(l2[6]), .in3(l2[6]), .in4(1'b0), .in5(l2[6]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[2]));
77.                  mux8to1_1bit o3(.in0(l2[3]), .in1(l2[7]), .in2(l2[7]), .in3(l2[7]), .in4(1'b0), .in5(l2[7]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[3]));
78.                  mux8to1_1bit o4(.in0(l2[4]), .in1(l2[7]), .in2(1'b0), .in3(l2[0]), .in4(l2[0]), .in5(l2[0]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[4]));
79.                  mux8to1_1bit o5(.in0(l2[5]), .in1(l2[7]), .in2(1'b0), .in3(l2[1]), .in4(l2[1]), .in5(l2[1]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[5]));
80.                  mux8to1_1bit o6(.in0(l2[6]), .in1(l2[7]), .in2(1'b0), .in3(l2[2]), .in4(l2[2]), .in5(l2[2]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[6]));
81.                  mux8to1_1bit o7(.in0(l2[7]), .in1(l2[7]), .in2(1'b0), .in3(l2[3]), .in4(l2[3]), .in5(l2[3]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[7]));
82.  
83. endmodule
84.  
85. // Alu operations are: 00 for alu1, 01 for add, 10 for sub(alu1-alu2) , 11 for AND, 100 for OR and 101 for NOT(alu1)
86. module alu(input [7:0] aluIn1, input [7:0] aluIn2, input [2:0]aluOp, output reg [7:0] aluOut);
87.        //WRITE CODE HERE
88.                          wire w1;
89.                          always@(aluOp)
90.                          begin
91.                          case(aluOp)
92.                                 3'b000 : aluOut[7:0] = aluIn1[7:0];
93.                                 3'b001 : aluOut[7:0] = aluIn1[7:0] + aluIn2[7:0];
94.                                 3'b010 : aluOut[7:0] = aluIn1[7:0] - aluIn2[7:0];
95.                                 3'b011 : aluOut[7:0] = aluIn1[7:0] & aluIn2[7:0];
96.                                 3'b100 : aluOut[7:0] = aluIn1[7:0] | aluIn2[7:0];
97.                                 3'b101 : aluOut[7:0] = ~aluIn1[7:0];
98.                                 endcase
99.                         end
100. endmodule
101.  
102.  
103. module shifterAndALU(input [7:0]inp1, input [7:0] inp2, input [2:0]shiftlmm, input selShiftAmt, input [2:0]oper, input selOut, output [7:0] out);
104.            //WRITE CODE HERE
105.                  wire [7:0]l1;
106.                  wire [7:0]l2;
107.                  wire [2:0]l3;
108.  
109.                  alu a1(.aluIn1(inp1[7:0]), .aluIn2(inp2[7:0]), .aluOp(oper[2:0]), .aluOut(l1[7:0]));
110.  
111.                  mux2to1_3bit a2(.in0(inp2[2:0]), .in1(shiftlmm[2:0]), .select(selShiftAmt), .muxOut(l3[2:0]));
112.  
113.                  barrelshifter a3(.shiftAmt(l3[2:0]), .b(inp1[7:0]), .oper(oper[2:0]), .shiftOut(l2[7:0]));
114.  
115.                  mux2to1_8bit a4(.in0(l1[7:0]), .in1(l2[7:0]), .select(selOut), .muxOut(out[7:0]));
116.  
117. endmodule
118.  
119. //TestBench ALU
120. module testbenchALU();
121.         // Input
122.         reg [7:0] inp1, inp2;
123.         reg [2:0] aluOp;
124.         reg [2:0] shiftlmm;
125.         reg selShiftAmt, selOut;
126.         // Output
127.         wire [7:0] aluOut;
128.  
129.         shifterAndALU shifterAndALU_Test (inp1, inp2, shiftlmm, selShiftAmt, aluOp, selOut, aluOut);
130.  
131.         initial
132.                 begin
133.                         $dumpfile("testALU.vcd");
134.         $dumpvars(0,testbenchALU);
135.                         inp1 = 8'd80; //80 in binary is 1010000
136.                         inp2 = 8'd20; //20 in binary is 10100
137.                         shiftlmm = 3'b010;
138.  
139.                         aluOp=3'd0; selOut = 1'b0;// normal output = 80
140.  
141.                         #10 aluOp = 3'd0; selOut = 1'b1; selShiftAmt = 1'b1; //No shift output = 80
142.  
143.                         #10 aluOp=3'd1; selOut = 1'b0;// normal add     output => 20 + 80 = 100
144.  
145.                         #10 aluOp = 3'd1; selOut = 1'b1; selShiftAmt = 1'b1; // arithmetic shift right of 80 by 2 places = 20
146.  
147.                         #10 aluOp=3'd2; selOut = 1'b0; // normal sub output => 80 - 20 = 60
148.  
149.                         #10 aluOp = 3'd2; selOut = 1'b1; selShiftAmt = 1'b0; // logical shift right of 80 by 4 places = 0
150.  
151.                         #10 aluOp=3'd3; selOut = 1'b0;// normal and output => 80 & 20 = 16
152.  
153.                         #10 aluOp = 3'd3; selOut = 1'b1; selShiftAmt = 1'b0; // Circular Shift Right of 80 by 4 places = 5
154.  
155.                         #10 aluOp=3'd4; selOut = 1'b0;// normal or output => 80 | 20 = 84
156.  
157.                         #10 aluOp = 3'd4; selOut = 1'b1; selShiftAmt = 1'b1; // Logical Shift Left of 80 by 2 bits = 64
158.  
159.                         #10 aluOp=3'd5; selOut = 1'b0; // normal not of 80 = 175
160.  
161.                         #10 aluOp = 3'd5; selOut = 1'b1; selShiftAmt = 1'b0; // Circular left shift of 80 by 4 bits = 5
162.  
163.                         #10 inp1=8'd15; inp2=8'd26; aluOp=3'd2; selOut = 1'b0;//sub overflow
164.                         // (15 - 26) = -11 and its a 8 bit number so, 256-11 = 245 output => 245 (since it is unsigned decimal)
165.  
166.                         #10 inp1=8'd150; inp2=8'd150; aluOp=3'd1; selOut = 1'b0;// add overflow
167.                         //(150+150) = 300 and its a 8 bit number so, 300-256 = 44 output=> 44.
168.  
169.                         #10 inp1=8'b0000_0000; aluOp=3'd5; selOut = 1'b0;//not overflow
170.                         // not(0) = all 1. Since its a 8 bit number output=>255
171.  
172.                         #10 $finish;
173.                 end
174.  
175. endmodule
176.