library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--brojilo broji (3 bita), sklopka1 zaustavi i freeza brojilo, sklopka2 obrne redoslijed brojanja gore-dolje
entity moving_light is
--TO DO 1 -> deklarirati ulaz "clk" (STD_LOGIC) i izlaz "output" (STD_LOGIC_VECTOR) veličine 8 bita
Port (
clk : IN STD_LOGIC;
output : OUT STD_LOGIC_VECTOR (2 downto 0);
sw1, sw2 : IN STD_LOGIC
);
end moving_light;
architecture Behavioral of moving_light is
--TO DO 2 -> definirati korisnički tip podataka naziva "state" koji može imati vrijednosti "state0", ... "state7"
type state is (state0, state1, state2, state3, state4, state5, state6, state7);
--TO DO 3 -> deklarirati signale "current_state" i "next_state" koji su tipa "state"
SIGNAL current_state, next_state : state;
--TO DO 4 -> deklarirati signal "clk_div" koji je tipa STD_LOGIC
SIGNAL temp : STD_LOGIC_VECTOR (2 downto 0);
SIGNAL clk_div : STD_LOGIC;
begin
--TO DO 5 -> instancirati generički djelitelj frekvencije na način da od ulaznog singala takta kreira signal takta frekvencije 2 Hz, 0.5 s
clk_2Hz : entity work.generic_divider generic map (25000000) port map (clk, clk_div);
----Lower section of FSM----
process(clk_div)
begin
--TO DO 6 -> na rastući brid signala takta "clk_div" signalu "current_state" pridružiti vrijednost signala "next_state"
if(rising_edge(clk_div)) then
current_state <= next_state;
end if;
end process;
----Upper section of FSM----
process(current_state)
begin
if(sw2 = '0') then
if(sw1 = '1') then
output <= temp;
end if;
if (sw1 = '0') then
case current_state is
when state0 =>
output <= "000";
temp <= "000";
next_state <= state1;
when state1 =>
output <= "001";
temp <= "001";
next_state <= state2;
when state2 =>
output <= "010";
temp <= "010";
next_state <= state3;
when state3 =>
output <= "011";
temp <= "011";
next_state <= state4;
when state4 =>
output <= "100";
temp <= "100";
next_state <= state5;
when state5 =>
output <= "101";
temp <= "101";
next_state <= state6;
when state6 =>
output <= "110";
temp <= "110";
next_state <= state7;
when state7 =>
output <= "111";
temp <= "111";
next_state <= state0;
end case;
end if;
end if;
if(sw2 = '1') then
if(sw1 = '1') then
output <= temp;
end if;
if (sw1 = '0') then
case current_state is
when state0 =>
output <= "000";
temp <= "000";
next_state <= state7;
when state1 =>
output <= "001";
temp <= "001";
next_state <= state0;
when state2 =>
output <= "010";
temp <= "010";
next_state <= state1;
when state3 =>
output <= "011";
temp <= "011";
next_state <= state2;
when state4 =>
output <= "100";
temp <= "100";
next_state <= state3;
when state5 =>
output <= "101";
temp <= "101";
next_state <= state4;
when state6 =>
output <= "110";
temp <= "110";
next_state <= state5;
when state7 =>
output <= "111";
temp <= "111";
next_state <= state6;
end case;
end if;
end if;
end process;
end Behavioral;
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