library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port (
A : in signed(15 downto 0);
B : in signed(15 downto 0);
Salu : in bit_vector (3 downto 0);
LDF : in bit;
clk : in bit;
Y : out signed (15 downto 0);
C,Z,S,P : out std_logic
);
end entity;
architecture rtl of alu is
begin
process (Salu, A, B, clk)
variable res,AA,BB,CC: signed (16 downto 0);
variable CF,ZF,SF,PF : std_logic;
variable i : integer range 0 to 15;
variable pomoc: boolean;
variable ilosc: integer range 15 downto 0:=0;
variable temp: integer range 99 downto 0;
variable temp1: integer range 9 downto 0;
begin
AA(16) := A(15);
AA(15 downto 0) := A;
BB(16) := B(15);
BB(15 downto 0) := B;
CC(0) := CF;
CC(16 downto 1) := "0000000000000000";
case Salu is
when "0000" => res := AA; --MOV arg1,arg2
when "0001" => res := AA+BB; --ADD arg1,arg2
when "0010" => res := AA-BB; --SUB arg1,arg2
when "0011" => res := AA; --LD arg1, arg2
when "0100" => res(3 downto 0):= BB(7 downto 4); --LDHI arg1, arg2
when "0101" => res(3 downto 0):= BB(3 downto 0); --LDLO arg1, arg2
when "0110" => res := AA or BB; --OR arg1,arg2
when "0111" => if(AA = BB) then
res:=(others=>'0');
else
res :=(0=>'1',others=>'0');
end if;--CMPNE arg1,arg2,wynik
when "1000" => --res(7 downto 0):= ((AA(7 downto 4)*10)+(AA(3 downto 0))) ;
--res(15 downto 8) := "00000000"; --BCDtoB arg1
temp:=to_integer((AA(7 downto 4)));
temp:= temp*10;
temp1:=to_integer(AA(3 downto 0));
temp:=temp + temp1;
res:=to_signed(temp,17);
when others => res:= null;
end case;
Y <= res(15 downto 0);
Z <= ZF; -- Flaga zero
S <= SF; -- Flaga ujemnosci
C <= CF; -- Flaga przeniesienia
P <= PF; -- Flaga parzystosci
if (clk'event and clk='1') then
if (LDF='1') then
ilosc:=0;
if (res = "00000000000000000") then ZF:='1';
else ZF:='0';
end if;
if (res(15)='1') then SF:='1';
else SF:='0';
end if;
CF := res(16) xor res(15);
for i in 0 to 15 loop
if(res(i) = '1') then
ilosc:=ilosc + 1;
end if;
end loop;
if(ilosc mod 2 = 0) then
PF:='1';
else PF:='0';
end if;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Rejestry is
port(
clk : in std_logic;
DI : in signed (15 downto 0);
BA : in signed (15 downto 0);
Sbb : in signed (3 downto 0);
Sbc : in signed (3 downto 0);
Sba : in signed (3 downto 0);
Sid : in signed (2 downto 0);
Sa : in signed (2 downto 0);
BB : out signed (15 downto 0);
BC : out signed (15 downto 0);
ADR : out signed (15 downto 0);
IRout : out signed (15 downto 0)
);
end entity;
architecture rtl of Rejestry is
begin
process (clk, Sbb, Sbc, Sba, Sid, Sa, DI)
variable IR, TMP, A, B, C, ES,DS,CS: signed (15 downto 0);
variable AD, PC, SP, ATMP : signed (15 downto 0); -- zapytac ile bitow
variable AP1,AP2 : signed (7 downto 0);
begin
if (clk'event and clk='1') then
case Sid is
when "001" => PC := PC + 1;
when "010" => SP := SP + 1;
when "011" => AD := AD + 1;
--when "100" => PC := PC - 1;
when "101" => SP := SP - 1;
when "110" => AD := AD - 1;
when others =>null;
end case;
case Sba is
when "0000" => IR := BA;
when "0001" => TMP := BA;
when "0010" => A := BA;
when "0011" => B := BA;
when "0100" => C := BA;
when "0101" => ES := BA;
when "0110" => DS := BA;
when "0111" => CS := BA;
when "1000" => AD := BA;
when "1001" => PC := BA;
when "1010" => SP := BA;
when "1011" => ATMP := BA;
when "1100" => AP1 := BA(7 downto 0); --tutaj trzeba zapytac
when "1101" => AP2 := BA(15 downto 8); -- zapytac
end case;
end if;
case Sbb is
when "0000" => BB <= DI;
when "0001" => BB <= TMP;
when "0010" => BB <= A;
when "0011" => BB <= B;
when "0100" => BB <= C;
when "0101" => BB <= ES;
when "0110" => BB <= DS;
when "0111" => BB <= CS;
when "1000" => BB <= AD;
when "1001" => BB <= PC;
when "1010" => BB <= SP;
when "1011" => BB <= ATMP;
when "1100" => BB(7 downto 0) <= AP1; --zapytac
when "1101" => BB(7 downto 0) <= AP2; --zapytac
end case;
case Sbc is
when "0000" => BC<= DI;
when "0001" => BC <= TMP;
when "0010" => BC <= A;
when "0011" => BC <= B;
when "0100" => BC <= C;
when "0101" => BC <= ES;
when "0110" => BC <= DS;
when "0111" => BC <= CS;
when "1000" => BC <= AD;
when "1001" => BC <= PC;
when "1010" => BC <= SP;
when "1011" => BC <= ATMP;
when "1100" => BC(7 downto 0) <= AP1; --zapytac
when "1101" => BC(7 downto 0) <= AP2; --zapytac
end case;
case Sa is
when "000" => ADR <= AD;
when "001" => ADR <= PC;
when "010" => ADR <= SP;
when "011" => ADR <= ATMP;
when "100" => ADR <= ES;
when "101" => ADR <= DS;
when "110" => ADR <= CS;
end case;
IRout <= IR;
end process;
end rtl;
--wspolpraca z pamiecia
--nie do konca zrobiona
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity busint is
port
(
ADR : in signed(31 downto 0);
DO : in signed(15 downto 0);
SEG : in signed(9 downto 0);
OFS :in signed(5 downto 0);
Smar, Smbr, WRin, RDin : in bit;
AD : out signed (31 downto 0);
D : inout signed (15 downto 0);
DI : out signed(15 downto 0);
QWE : in bit;
WR, RD : out bit
);
end entity;
architecture rtl of busint is
begin
process(Smar, ADR, Smbr, DO, D, WRin, RDin)
variable MBRin, MBRout: signed(15 downto 0);
variable MAR : signed(31 downto 0);
begin
if(Smar='1') then
if(QWE = '1')then MAR(15 downto 6) := SEG;
MAR(5 downto 0):=OFS;
else MAR := ADR;
end if;
end if;
if(Smbr='1') then MBRout := DO; end if;
if (RDin='1') then MBRin := D; end if;
if (WRin='1') then D <= MBRout;
else D <= "ZZZZZZZZZZZZZZZZ";
end if;
DI <= MBRin;
AD <= MAR;
WR <= WRin;
RD <= RDin;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity control is
port(
clk : in std_logic;
IR : in signed(15 downto 0);
reset, C, Z, S, INT : in std_logic;
Salu, Sbb, Sbc, Sba : out bit_vector(3 downto 0);
Sid : out bit_vector(2 downto 0);
Sa : out bit_vector(2 downto 0);
LDF, Smar, Smbr, WR, RD,INTA, MIO : out bit
);
end entity;
architecture rtl of control is
type state_type is (fetch, dec, wait_1, call_1, call_2, call_3, call_4, ret_1, ret_2, ret_3, push, pop_1, pop_2, neg, inc, dec_1, not_1, shr,
shl, mov_r, mov_rm, add, sub, cmp, and_1, or_1, xor_1, in_r, out_IO, jump_1, jump_2, long_jump, r_2_16, mov_a1_a2, bcdtoB, mov, add_a1_a2, sub_a1_a2, ld, ldhi,
ldlo, or_2, cmpne, r_2_32, m9);
signal state : state_type;
begin
process (clk, reset)
begin
if reset = '1' then
state <= fetch;
elsif (clk'event and clk='1') then
case state is
when fetch=>
state <= dec;
when dec=>
case IR(15 downto 13) is
when "000" =>
case IR(12 downto 11) is
when "00" =>
if(INT='0') then state <= fetch;
else state <= m9;
end if;
when "01" => state <= wait_1;
when "10" => state <= call_1;
when "11" => state <= ret_1;
when others => state <= fetch;
end case;
when "001" =>
case IR(12 downto 8) is
when "00000" => state <= push;
when "00001" => state <= pop_1;
when "00010" => state <= neg;
when "00011" => state <= inc;
when "00100" => state <= dec_1;
when "00101" => state <= not_1;
when "00110" => state <= shr;
when "00111" => state <= shl;
when "01000" => state <= mov_r;
when "01001" => state <= mov_rm;
when "01010" => state <= add;
when "01011" => state <= sub;
when "01100" => state <= cmp;
when "01101" => state <= and_1;
when "01110" => state <= or_1;
when "01111" => state <= xor_1;
when "10000" => state <= in_r;
when "10001" => state <= out_IO;
when "10010" => state <= bcdtoB;
when others => state <= fetch;
end case;
when "010" => state <= jump_1;
when "011" => state <= jump_2;
when "100" =>
case IR(12 downto 8) is
when "00000" => state <= mov;
when "00001" => state <= add_a1_a2;
when "00010" => state <= sub_a1_a2;
when "00011" => state <= ld;
when "00100" => state <= ldhi;
when "00101" => state <= ldlo;
when "00110" => state <= or_2;
when "00111" => state <= cmpne;
when others => state <= fetch;
end case;
when "101" => state <= r_2_32;
when others => state <= fetch;
end case;
when wait_1=>
if INT = '1' then state <= m9;
else state <= wait_1;
end if;
when call_1 => state <= call_2;
when call_2 => state <= call_3;
when call_3 => state <= call_4;
when call_4 =>
if INT = '1' then state <= m9;
else state <= fetch;
end if;
when others => state <= fetch;
end case;
end if;
end process;
process (state)
begin
case state is
when fetch =>
Sa <= "001"; Sbb <= "0000"; Sba <= "0000"; Sid <="001"; Sbc <="0000"; MIO <='1';
Smar <='1'; Smbr <= '0'; WR <='0'; RD <='1'; Salu <="0000"; LDF <='0'; INTA <='0';
when dec =>
Sa <= "000"; Sbb <= "0000"; Sba <= "0000"; Sid <="000"; Sbc <="0000"; MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='0'; RD <='0'; Salu <="0000"; LDF <='0'; INTA <='0';
when wait_1 =>
Sa <= "000"; Sbb <= "0000"; Sba <= "0000"; Sid <="000"; Sbc <="0000"; MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='0'; RD <='0'; Salu <="0000"; LDF <='0'; INTA <='0';
when call_1 =>
Sa <= "010"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1';
Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0000"; LDF <='0'; INTA <='0';
when mov_a1_a2 =>
Sa <= "001"; Sbb<=to_bitvector(std_logic_vector(IR(7 downto 4))) ; Sba <= "0001"; Sid <="001"; Sbc <=to_bitvector(std_logic_vector(IR(3 downto 0))); MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='1'; RD <='0'; Salu <="0000"; LDF <='1'; INTA <='0';
when add_a1_a2 =>
Sa <= "001"; Sbb<=to_bitvector(std_logic_vector(IR(7 downto 4))) ; Sba <= "0001"; Sid <="001"; Sbc <=to_bitvector(std_logic_vector(IR(3 downto 0))); MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='1'; RD <='0'; Salu <="0001"; LDF <='1'; INTA <='0';
when sub_a1_a2 =>
Sa <= "001"; Sbb<=to_bitvector(std_logic_vector(IR(7 downto 4))) ; Sba <= "0001"; Sid <="001"; Sbc <=to_bitvector(std_logic_vector(IR(3 downto 0))); MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='1'; RD <='0'; Salu <="0010"; LDF <='1'; INTA <='0';
when ld =>
Sa <= "001"; Sbb<=to_bitvector(std_logic_vector(IR(7 downto 4))) ; Sba <= "0001"; Sid <="001"; Sbc <=to_bitvector(std_logic_vector(IR(3 downto 0))); MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='1'; RD <='0'; Salu <="0011"; LDF <='1'; INTA <='0';
--ldh1
when ldhi =>
Sa <= "001"; Sbb<=to_bitvector(std_logic_vector(IR(7 downto 4))) ; Sba <= "0001"; Sid <="001"; Sbc <=to_bitvector(std_logic_vector(IR(3 downto 0))); MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='1'; RD <='0'; Salu <="0100"; LDF <='1'; INTA <='0';
--ldlo
when ldlo =>
Sa <= "001"; Sbb<=to_bitvector(std_logic_vector(IR(7 downto 4))) ; Sba <= "0001"; Sid <="001"; Sbc <=to_bitvector(std_logic_vector(IR(3 downto 0))); MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='1'; RD <='0'; Salu <="0101"; LDF <='1'; INTA <='0';
--or
when or_2 =>
Sa <= "001"; Sbb<=to_bitvector(std_logic_vector(IR(7 downto 4))) ; Sba <= "0001"; Sid <="001"; Sbc <=to_bitvector(std_logic_vector(IR(3 downto 0))); MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='1'; RD <='0'; Salu <="0110"; LDF <='1'; INTA <='0';
--cmpne
when cmpne =>
Sa <= "001"; Sbb<=to_bitvector(std_logic_vector(IR(7 downto 4))) ; Sba <= "0001"; Sid <="001"; Sbc <=to_bitvector(std_logic_vector(IR(3 downto 0))); MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='1'; RD <='0'; Salu <="0111"; LDF <='1'; INTA <='0';
--BCDtoB
when bcdtoB =>
Sa <= "001"; Sbb<=to_bitvector(std_logic_vector(IR(7 downto 4))) ; Sba <= "0001"; Sid <="001"; Sbc <="0000"; MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='1'; RD <='0'; Salu <="1000"; LDF <='1'; INTA <='0';
when others =>
Sa <= "000"; Sbb <= "0000"; Sba <= "0000"; Sid <="000"; Sbc <="0000"; MIO <='1';
Smar <='0'; Smbr <= '0'; WR <='0'; RD <='0'; Salu <="0000";
LDF <='0'; INTA <='0';
end case;
end process;
end rtl;
