1. LIBRARY ieee;
2. USE ieee.std_logic_1164.all;
3. ENTITY sumator IS
4.     PORT (a, b, c : IN     STD_LOGIC;
5.             c1, s          : OUT STD_LOGIC);
6. END sumator;
7.  
8. ARCHITECTURE LogicFunction OF sumator IS
9. BEGIN
10.     c1 <= (a AND b) OR (a AND c) OR (b AND c);
11.     s <= (NOT a AND NOT b AND c) OR (a AND NOT b AND NOT c) OR (a AND b AND c) OR (NOT a AND b AND NOT c);
12.     END LogicFunction;
13.    
14.  
15.    
16. LIBRARY ieee;
17. USE ieee.std_logic_1164.all;
18. entity sumator4 is
19.     port (a, a1, a2, a3, b, b1, b2, b3:         in     std_logic;
20.             s, s1, s2, s3, cs:                         out     std_logic);
21. end sumator4;
22.  
23. architecture behv of sumator4 is
24.     component sumator is
25.     port(a, b, c:            in     std_logic;
26.             c1, s:             out    std_logic);
27.     end component;
28.     signal c1, c2, c3: std_logic;
29. begin
30.     M1: sumator port map(a, b, '0', c1, s);
31.     M2: sumator port map(a1, b1, c1, c2, s1);
32.     M3: sumator port map(a2, b2, c2, c3, s2);
33.     M4: sumator port map(a3, b3, c3, cs, s3);
34. end behv;