Starting C/RTL cosimulation ...
C:/Xilinx/Vitis_HLS/2022.2/bin/vitis_hls.bat C:/Users/Alex/Documents/VitisHls/Task_1/solution1/cosim.tcl
INFO: [HLS 200-10] Running 'C:/Xilinx/Vitis_HLS/2022.2/bin/unwrapped/win64.o/vitis_hls.exe'
INFO: [HLS 200-10] For user 'Alex' on host 'desktop-8m0u2qg' (Windows NT_amd64 version 6.2) on Wed Nov 16 12:00:15 +0200 2022
INFO: [HLS 200-10] In directory 'C:/Users/Alex/Documents/VitisHls'
Sourcing Tcl script 'C:/Users/Alex/Documents/VitisHls/Task_1/solution1/cosim.tcl'
INFO: [HLS 200-1510] Running: source C:/Users/Alex/Documents/VitisHls/Task_1/solution1/cosim.tcl
INFO: [HLS 200-1510] Running: open_project Task_1 
INFO: [HLS 200-10] Opening project 'C:/Users/Alex/Documents/VitisHls/Task_1'.
INFO: [HLS 200-1510] Running: set_top do_for_hw 
INFO: [HLS 200-1510] Running: add_files ../ClionProjects/VitisHls/Task_1/do_for.cpp 
INFO: [HLS 200-10] Adding design file '../ClionProjects/VitisHls/Task_1/do_for.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb ../ClionProjects/VitisHls/Task_1/do_for_tests.cpp 
INFO: [HLS 200-10] Adding test bench file '../ClionProjects/VitisHls/Task_1/do_for_tests.cpp' to the project
INFO: [HLS 200-1510] Running: open_solution solution1 -flow_target vivado 
INFO: [HLS 200-10] Opening solution 'C:/Users/Alex/Documents/VitisHls/Task_1/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-1611] Setting target device to 'xc7z020-clg400-1'
INFO: [HLS 200-1505] Using flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2022.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xc7z020clg400-1 
INFO: [HLS 200-1510] Running: create_clock -period 10 -name default 
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-1510] Running: cosim_design -rtl vhdl 
Running Dispatch Server on port: 51697
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench ...
   Build using "C:/Xilinx/Vitis_HLS/2022.2/tps/win64/msys64/mingw64/bin/g++"
   Compiling do_for_tests.cpp_pre.cpp.tb.cpp
   Compiling apatb_do_for_hw.cpp
   Compiling do_for.cpp_pre.cpp.tb.cpp
   Compiling apatb_do_for_hw_ir.ll
   Generating cosim.tv.exe
INFO: [COSIM 212-302] Starting C TB testing ... 
************************************************************
Running three of the loop in hardware 
Final int = 1953125000
************************************************************
INFO: [COSIM 212-333] Generating C post check test bench ...
INFO: [COSIM 212-12] Generating RTL test bench ...
INFO: [COSIM 212-1] *** C/RTL co-simulation file generation completed. ***
INFO: [COSIM 212-322] Starting VHDL simulation. 
INFO: [COSIM 212-15] Starting XSIM ...

C:UsersAlexDocumentsVitisHlsTask_1solution1simvhdl>set PATH= 

C:UsersAlexDocumentsVitisHlsTask_1solution1simvhdl>call C:/Xilinx/Vivado/2022.2/bin/xelab xil_defaultlib.apatb_do_for_hw_top glbl -Oenable_linking_all_libraries  -prj do_for_hw.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims -L unisims_ver -L xpm  -L floating_point_v7_0_20 -L floating_point_v7_1_15 --lib "ieee_proposed=./ieee_proposed" -s do_for_hw  
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe xil_defaultlib.apatb_do_for_hw_top glbl -Oenable_linking_all_libraries -prj do_for_hw.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims -L unisims_ver -L xpm -L floating_point_v7_0_20 -L floating_point_v7_1_15 --lib ieee_proposed=./ieee_proposed -s do_for_hw 
Multi-threading is on. Using 2 slave threads.
Determining compilation order of HDL files.
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/AESL_sim_pkg.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/do_for_hw.autotb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'apatb_do_for_hw_top'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/do_for_hw.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'do_for_hw'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/do_for_hw_mul_32s_32s_32_2_1.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'do_for_hw_mul_32s_32s_32_2_1'
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_textio
Compiling module work.glbl
Compiling architecture behav of entity xil_defaultlib.do_for_hw_mul_32s_32s_32_2_1 [do_for_hw_mul_32s_32s_32_2_1(nu...]
Compiling architecture behav of entity xil_defaultlib.do_for_hw [do_for_hw_default]
Compiling architecture behav of entity xil_defaultlib.apatb_do_for_hw_top
Built simulation snapshot do_for_hw

****** xsim v2022.2 (64-bit)
  **** SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
  **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source xsim.dir/do_for_hw/xsim_script.tcl
# xsim {do_for_hw} -autoloadwcfg -tclbatch {do_for_hw.tcl}
Time resolution is 1 ps
source do_for_hw.tcl
## run all
Note: simulation done!
Time: 265 ns  Iteration: 1  Process: /apatb_do_for_hw_top/generate_sim_done_proc  File: C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/do_for_hw.autotb.vhd
Failure: NORMAL EXIT (note: failure is to force the simulator to stop)
Time: 265 ns  Iteration: 1  Process: /apatb_do_for_hw_top/generate_sim_done_proc  File: C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/do_for_hw.autotb.vhd
$finish called at time : 265 ns
## quit
INFO: [Common 17-206] Exiting xsim at Wed Nov 16 12:00:46 2022...
INFO: [COSIM 212-316] Starting C post checking ...
************************************************************
Running three of the loop in hardware 
Final int = 1953125000
************************************************************
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
INFO: [HLS 200-111] Finished Command cosim_design CPU user time: 1 seconds. CPU system time: 0 seconds. Elapsed time: 17.567 seconds; current allocated memory: 5.863 MB.
INFO: [HLS 200-112] Total CPU user time: 4 seconds. Total CPU system time: 1 seconds. Total elapsed time: 31.507 seconds; peak allocated memory: 580.090 MB.
Finished C/RTL cosimulation