library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Musica is
    Port ( clk : in  STD_LOGIC;
           a : in  STD_LOGIC;
           altavoz : inout  STD_LOGIC);
end Musica;

architecture musica_arch of Musica is

signal cont : std_logic_vector (16 downto 0);
constant cont_max: std_logic_vector :="11011101111100100";  -- frecuencia de LA

begin
	process (clk)
		begin
		if clk'event and clk= '1' then
			cont <= cont+1;
			if cont= cont_max then
				cont <="00000000000000000";
			end if;
		end if;
	end process;
	
	process (altavoz) 
		begin
		if a= '1' then 
			altavoz <= cont (16);
		else 
			altavoz <= '0';
		end if;	
	end process;

end musica_arch;