module ALU_tb;

    // Parameters
    parameter CLK_PERIOD = 10; // Clock period in ns

    // Signals
    reg [31:0] operand1;
    reg [31:0] operand2;
    reg [4:0] operation_select;
    wire [31:0] result;
    wire Z, N, C, V;

    // Instantiate the ALU module
    alu32 dut (
        .operand1(operand1),
        .operand2(operand2),
        .operation_select(operation_select),
        .result(result),
        .Z(Z),
        .N(N),
        .C(C),
        .V(V)
    );

    // Clock Generation
    reg clk = 0;
    always #((CLK_PERIOD / 2)) clk = ~clk;

    // Test stimulus
    initial begin
        // Initialize inputs
        operand1 = 32'h12345678;
        operand2 = 32'h87654321;
        
        // Test LD (Load) operation
        operation_select = 5'b00001; // LD
        #20;
        
        // Test ADD operation
        operation_select = 5'b00011; // ADD
        #20;
        
        // Test SUB operation
        operation_select = 5'b00100; // SUB
        #20;
        
        // Test AND operation
        operation_select = 5'b00101; // AND
        #20;
        
        // Test OR operation
        operation_select = 5'b00110; // OR
        #20;
        
        // Test XOR operation
        operation_select = 5'b00111; // XOR
        #20;
        
        // Test INV operation
        operation_select = 5'b01000; // INV
        #20;
        
        // Test SHL operation
        operation_select = 5'b01001; // SHL
        #20;
        
        // Test SHR operation
        operation_select = 5'b01010; // SHR
        #20;
        
        // End simulation
        $finish;
    end

endmodule