---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21.10.2020 15:08:15 -- Design Name: -- Module Name: tb - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity tb is -- Port ( ); end tb; architecture Behavioral of tb is component top Port ( clk_i : in std_logic; sw_i : in std_logic_vector(7 downto 0); btn_i : in std_logic_vector(3 downto 0); led7_an_o : out std_logic_vector(3 downto 0); led7_seg_o : out std_logic_vector(7 downto 0)); end component; signal clk_i : std_logic := '0'; signal sw_i : std_logic_vector(7 downto 0) := (others => '0'); signal btn_i : std_logic_vector(3 downto 0) := (others => '0'); signal led7_an_o : std_logic_vector(3 downto 0); signal led7_seg_o : std_logic_vector(7 downto 0); begin uut: top port map ( clk_i => clk_i, sw_i => sw_i, btn_i => btn_i, led7_an_o => led7_an_o, led7_seg_o => led7_seg_o); clk_i <= not clk_i after 5 ns; --okres zegara to 10 ns, czli 100MHz stim : process begin sw_i <= "00000011"; btn_i <= "0000"; wait for 10 ns; btn_i <= "0001"; wait for 10 ns; btn_i <= "0000"; wait for 10 ns; sw_i <= "00010011"; wait for 10 ns; btn_i <= "0001"; wait for 10 ns; btn_i <= "0000"; wait for 10 ns; sw_i <= "00000011"; wait; end process; end Behavioral;