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-- Company: 

-- Engineer: 

-- 

-- Create Date:    15:01:39 03/03/2018 

-- Design Name: 

-- Module Name:    dff - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;



-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;



-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;



entity dff is

    Port ( rst : in  STD_LOGIC;

           d : in  STD_LOGIC;

           clk : in  STD_LOGIC;

           outd : out  STD_LOGIC);

end dff;



architecture Behavioral of dff is

begin



process( clk, rst) is

begin

		if rst = '1' then

		outd <= '0';

		else

			if rising_edge(clk) then

			outd <= d;

			end if;

		end if;

		

end process;



end Behavioral;