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-- Company: 

-- Engineer: 

-- 

-- Create Date:    14:59:23 03/03/2018 

-- Design Name: 

-- Module Name:    TOP - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;



-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;



-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;



entity TOP is

    Port ( rst_i : in  STD_LOGIC;

           clk_i : in  STD_LOGIC;

           led_o : out  STD_LOGIC_VECTOR (1 downto 0));

end TOP;



architecture Behavioral of TOP is

component grayCounter



	Port ( clk : in  STD_LOGIC;

           rst : in  STD_LOGIC;

           counter_out : out  STD_LOGIC_VECTOR (1 downto 0));



end component;

begin



	c: grayCounter

	port map(

	rst => rst_i,

	clk => clk_i,

	counter_out => led_o);



end Behavioral;