-- This is the 4 bits counter -- 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity s211311224bc is
port(
       clk : in std_logic;                      -- clock port
       clr : in std_logic;                      -- clear port
       load : in std_logic;
        ud : in std_logic;                      -- up / down control port
         d : in std_logic_vector (3 downto 0);
         q : out std_logic_vector(3 downto 0)  -- output port of counting vale
    
);
end s211311224bc;

architecture a of s211311224bc is
 signal sq : std_logic_vector(3 downto 0);   -- counting signal object
    signal sclr, intclr : std_logic;            -- clear signal object
    signal sclk : std_logic;                    -- internal clock            
begin
     
     process (intclr, clk, load, ud)               -- BCD up/down counter
     begin
          if intclr = '0' then                  -- internal reset signal
             if ud = '1' then sq <= "0000";     -- initial value for up counter
             elsif ud = '0' then sq <= "1001";  -- initial value for down counter
             end if;
             
          elsif clk'event and clk = '0' then
             if load = '0' then sq <= d;
             else
    if ud = '1' then sq <= sq + 1;    -- up counting
    elsif ud = '0' then sq <= sq - 1; -- down counting
    end if;        
   end if;
  end if;
     end process;
                  
     sclr <= '0' when ud = '1' and sq = "1010" else    -- to judge sreset status for up / down counting status
             '0' when ud = '0' and sq = "1111" else
             '1';
             
     intclr <= sclr and clr;                        -- to get internal reset signal
                     
     q <= sq;                                   -- to get counting value  
end a;