library IEEE;
use IEEE.std_logic_1164.ALL;

entity system_testbench is 
end entity system_testbench;

architecture behaviour of system_testbench is
component system 
port (clk, reset, x : in std_logic;
Y : out std_logic_vector (2 downto 0));
end component;

signal clk, reset, x : std_logic;
signal Y : std_logic_vector (2 downto 0);

begin

lb11: entity work.system
port map (clk, reset, x, Y);

clk <= '0'after 0 ns,
'1' after 5 ns when clk /= '1'
else '0' after 5 ns;

reset <= '1' after 0 ns,
'0' after 20 ns;

x <= '0' after 0 ns,
'1' after 30 ns,
'0' after 40 ns,
'0' after 50 ns,
'1' after 60 ns,
'1' after 70 ns,
'0' after 80 ns,
'1' after 90 ns,
'0' after 100 ns,
'1' after 110 ns,
'1' after 120 ns,
'0' after 130 ns,
'0' after 140 ns;

end architecture behaviour;