LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sumator IS
    PORT (a, b, c : IN     STD_LOGIC;
            c1, s          : OUT STD_LOGIC);
END sumator;

ARCHITECTURE LogicFunction OF sumator IS
BEGIN
    c1 <= (a AND b) OR (a AND c) OR (b AND c);
    s <= (NOT a AND NOT b AND c) OR (a AND NOT b AND NOT c) OR (a AND b AND c) OR (NOT a AND b AND NOT c);
    END LogicFunction;
   

   
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity sumator4 is
    port (a, a1, a2, a3, b, b1, b2, b3:         in     std_logic;
            s, s1, s2, s3, cs:                         out     std_logic);
end sumator4;

architecture behv of sumator4 is
    component sumator is
    port(a, b, c:            in     std_logic;
            c1, s:             out    std_logic);
    end component;
    signal c1, c2, c3: std_logic;
begin
    M1: sumator port map(a, b, '0', c1, s);
    M2: sumator port map(a1, b1, c1, c2, s1);
    M3: sumator port map(a2, b2, c2, c3, s2);
    M4: sumator port map(a3, b3, c3, cs, s3);
end behv;