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  1. ----------------------------------------------------------------------------------
  2.  
  3. -- Company:
  4.  
  5. -- Engineer:
  6.  
  7. --
  8.  
  9. -- Create Date:    11:49:21 03/03/2018
  10.  
  11. -- Design Name:
  12.  
  13. -- Module Name:    generator - Behavioral
  14.  
  15. -- Project Name:
  16.  
  17. -- Target Devices:
  18.  
  19. -- Tool versions:
  20.  
  21. -- Description:
  22.  
  23. --
  24.  
  25. -- Dependencies:
  26.  
  27. --
  28.  
  29. -- Revision:
  30.  
  31. -- Revision 0.01 - File Created
  32.  
  33. -- Additional Comments:
  34.  
  35. --
  36.  
  37. ----------------------------------------------------------------------------------
  38.  
  39. library IEEE;
  40.  
  41. use IEEE.STD_LOGIC_1164.ALL;
  42.  
  43.  
  44.  
  45. -- Uncomment the following library declaration if using
  46.  
  47. -- arithmetic functions with Signed or Unsigned values
  48.  
  49. --use IEEE.NUMERIC_STD.ALL;
  50.  
  51.  
  52.  
  53. -- Uncomment the following library declaration if instantiating
  54.  
  55. -- any Xilinx primitives in this code.
  56.  
  57. --library UNISIM;
  58.  
  59. --use UNISIM.VComponents.all;
  60.  
  61.  
  62.  
  63. entity generator is
  64.  
  65.     Port (
  66.  
  67.          
  68.  
  69.          data : in  STD_LOGIC_VECTOR (7 downto 0);
  70.  
  71.          parity : out STD_LOGIC
  72.  
  73.          
  74.  
  75.          );
  76.  
  77. end generator;
  78.  
  79.  
  80.  
  81. architecture Behavioral of generator is
  82.  
  83.  
  84.  
  85.         --signal internal : STD_LOGIC_VECTOR ( 5 downto 0); --Wewntrzne poczenia midzy xorami
  86.  
  87.  
  88.  
  89. begin
  90.  
  91.  
  92.  
  93.  
  94.  
  95. --      internal(0) <= data(0) xor data(1);
  96.  
  97. --      internal(1) <= data(2) xor data(3);
  98.  
  99. --      internal(2) <= data(4) xor data(5);
  100.  
  101. --      internal(3) <= data(6) xor data(7);
  102.  
  103.        
  104.  
  105. --      internal(4) <= internal(0) xor internal(1);
  106.  
  107. --      internal(5) <= internal(2) xor internal(3);
  108.  
  109.        
  110.  
  111. --      parity <= internal(4) xnor internal(5);
  112.  
  113.  
  114.  
  115. parity <= data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7);
  116.  
  117.  
  118.  
  119.  
  120.  
  121. end Behavioral;
  122.  
  123.  
  124.  
  125.