`timescale 1ns / 1ps


module tb();

reg clock_t;
reg in_50_t;
reg in_100_t;
reg reset_t;
wire cioco_t;

moore moore(
.clock(clock_t),
.in_50(in_50_t),
.in_100(in_100_t),
.reset(reset_t),
.cioco(cioco_t)
);


initial begin
    clock_t = 0;
    forever #1 clock_t = ~clock_t;
end

initial begin

    reset_t=1;
    in_50_t=0;
    in_100_t=0;
    
    #10
    reset_t=0;
    in_50_t=0;
    in_100_t=1;
    
    #10
    in_50_t=0;
    in_100_t=1;
    
    #10
    in_50_t=1;
    in_100_t=0;
    
    #10
    in_50_t=1;
    in_100_t=1;
    
    #10
    in_50_t=0;
    in_100_t=0;
    
    #100 $stop();

end


endmodule