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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:45:29 04/08/2019 
-- Design Name: 
-- Module Name:    licznik - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity licznik is
    Port ( clock : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           q_out : out  STD_LOGIC_VECTOR (2 downto 0));
end licznik;

architecture Behavioral of licznik is
signal rejestry_d :std_logic_vector (2 downto 0):="000";

begin
	process (clock, reset)
		begin
			if reset = '0' then
				rejestry_d <="000";
			elsif clock'event and clock = '1' then
				rejestry_d(0) <= (rejestry_d(2) and rejestry_d(1)) or (not rejestry_d(0));
				rejestry_d(1) <= ((not rejestry_d(1)) and rejestry_d(0)) or (rejestry_d(1) and (not rejestry_d(0)));
				rejestry_d(2) <= (rejestry_d(2) and (not rejestry_d(0))) or (rejestry_d(2) and (not rejestry_d(1))) or ((not rejestry_d(2)) and rejestry_d(1) and rejestry_d(0));
			end if;
		end process;
	q_out <= rejestry_d;
end Behavioral;