library ieee;
use ieee.std_logic_1164.all;

entity comparator2 is
port(a,b: in std_logic_vector(1 downto 0);
     ut_a, ut_b, ut_c, ut_d, ut_e, ut_f, ut_g:out std_logic);
 end comparator2;

 architecture Expression of comparator2 is 
 begin
 ut_e <= ((not(b(1))) and (a(0))) or ((not(b(1))) and (a(1))) or ((a(0)) and (a(1))) or ((not(b(1))) and (not(b(0)))) or ((b(1)) and (a(1)) and (not(b(0))));

 ut_c <= ((not(a(1))) and (b(1))) or ((not(a(1))) and (b(0))) or ((not(a(1))) and (not(a(0)))) or ((b(1)) and (b(0))) or ((b(1)) and (a(1)) and (not(a(0))));

 ut_g <= '0';
 ut_d <= '0';
 ut_a <= '1';
 ut_b <= '1';
 ut_f <= '1';

 end Expression;