LIBRARY ieee;
USE ieee.std_logic_1164.ALL; 
USE ieee.std_logic_arith.ALL; 

ENTITY ram_dual IS
	PORT (
			clock: IN STD_LOGIC;
			data: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
			write_address: IN INTEGER RANGE 0 to 31;
			read_address: IN INTEGER RANGE 0 to 31;
			we: IN STD_LOGIC;
			q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END ram_dual;

ARCHITECTURE rtl OF ram_dual IS
TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ram_block: MEM;
SIGNAL read_address_reg : INTEGER RANGE 0 to 31;
BEGIN
		PROCESS (clock)
			BEGIN
			IF (clock1'event AND clock1 = '1') THEN
				IF (we = '1') THEN
					ram_block(write_address) <= data;
				else q <= ram_block(read_address);--mozliwe ze trzeba bedzie bez elsa znaczy end if; potem q<=...
				END IF;
			END IF;
      END PROCESS;


END rtl; 

-------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL; 
USE ieee.std_logic_arith.ALL; 

ENTITY ram IS
	PORT ( data: IN std_logic_vector (3 downto 0);
	wren,clock, acc, acc2: IN std_logic;
END ram;

architecture behavior of ram is
	signal wyjscie: std_logic_vector(0 to 3);
	signal address: integer Range 0 to 31 := 0;
	signal address2: integer Range 0 to 31 := 0;
	signal v1: std_logic_vector (0 to 3);
	signal v2: std_logic_vector (0 to 3);

	component ram_dual IS
		Port(	
			clock: IN STD_LOGIC;
			data: IN STD_LOGIC_VECTOR (3 downto 0);
			write_address: IN Integer Range 0 to 31 := 0;
			read_address: IN Integer Range 0 to 31 := 0;
			we: In STD_LOGIC;
			q: OUT STD_LOGIC_VECTOR (3 downto 0));
	end component ram_dual;

	PROCESS(clock)
		BEGIN 
			IF (acc'event AND acc = '1') THEN
				address <= address + 1;
				v1 <= conv_std_logic_vector (address, 4);
			END IF;
		
			IF(acc2'event AND acc2 = '1') THEN
				address2 <= address2 + 1;
				v2 <= conv_std_logic_vector(address2,4);
			END IF;
	END PROCESS;
	
ram_one: ram_dual port map(clock, data, address, address2, wren, wyjscie);	
		
END behavior;