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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:14:18 03/22/2019 
-- Design Name: 
-- Module Name:    modul - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity modul is
  Port ( clk      : in STD_LOGIC;
         reset    : in STD_LOGIC;
         start    : in STD_LOGIC;
         OW_DQ    : inout STD_LOGIC;
         ow_pres  : out STD_LOGIC);    
end modul;

architecture Behavioral of modul is
type state_type is (INIT,B,C,D)
signal state: state_type;

component IOBUF
   Port ( IO : inout STD_LOGIC;
          I  : in STD_LOGIC;
          O  : out STD_LOGIC;
          T  : in STD_LOGIC);
end component;

signal ow_in   :std_logic;
signal ow_out  :std_logic;


begin

buff : IOBUF
   port map( I => '0',
             T => ow_out,
             O => ow_in,
             IO => OW_DQ);

   when init =>   if start = '1' then 
                    ow_out <= '0'; 
                    counter <= 5000;
                    state <= B;
                  end;
                  
	when B =>      if clk = 0 then  
                    ow_out <= '1';
                    state <= C; 
                  end if; 
 
   when C =>      reset <= '0'
                  if(clk = 150) then  
                    reset <= '1'; 
                    state <= D;
   
   when D =>      ow_pres <= not ow_in;
                  state<= init;
   
end Behavioral;