module test_1(
	input[15:0] a,b,
	input[0:0] c_en,sel_en,h_ab,h_sel,gate_en,
	output reg[0:0] gt_lo_eq,
	output reg[7:0] h_out,
	output reg[31:0] err_out,
	output reg[2:0] sum_2a,
	output reg[15:0] rsr_b,out_xor
		);

integer i,j;

initial begin

	gt_lo_eq = 1'b0; 
	sum_2a = 3'b000; 
	h_out = 7'b0000000;

	for (i=0; i<16; i=i+1) begin
	rsr_b[i] = 1'b0;
	out_xor[i] = 1'b0;
	end
	for (i=0; i<32; i=i+1) begin
	err_out[i] = 1'b0;
	end

end

always @(c_en, sel_en, gate_en)  begin

	if(c_en == 1 && sel_en == 1 && gate_en == 1)
	begin
	for(i=0; i<32; i=i+1)
	err_out[i] = 1'b1;
	end

	else begin
		for (i=0; i<32; i=i+1)
		err_out[i] = 1'b0;

		if (c_en == 1) 
		begin
			if(a > b)
			begin
			gt_lo_eq = 1'b0;
			end

			else if(a<b)
			begin
			gt_lo_eq = ~(1'b0);
			end

			else 
			begin
			gt_lo_eq = ~gt_lo_eq;
			end
		end
	end

	if (sel_en == 1) 
	begin 
		if(h_ab == 0 && h_sel == 0) 
		begin
			h_out = a[15:8];
		end

		else if (h_ab == 0 && h_sel == 1) 
		begin
			h_out = a[7:0];
		end
		
		else if (h_ab == 1 && h_sel == 0)
		begin
			h_out = b[15:8];
		end
		
		else if (h_ab == 1 && h_sel == 1)
		begin
			h_out = b[7:0];
		end
	end

	if(gate_en == 1)
		begin
		i = &b;
		
		for(j=0;j<16;j=j+1)
		out_xor[j] = a[j] ^ i;

		end
end
	always@(*) begin

	sum_2a = 3'b000;

	for(i=0; i<=15; i = i+2)
	begin
		sum_2a = sum_2a + a[i];
	end
	
	rsr_b[15:12] = b[3:0];
	rsr_b[11:0] = b[11:0];

	if(gate_en == 1)
		begin
		i = &b;
		
		for(j=0;j<16;j=j+1)
		out_xor = a[j] ^ i;

		end
end

endmodule



TESTBENCH:

module test_1_tb;
	reg[15:0] a_tb,b_tb;
	reg[0:0] c_en_tb,sel_en_tb,h_ab_tb,h_sel_tb,gate_en_tb;
	wire[0:0] gt_lo_eq_tb;
	wire[7:0] h_out_tb;
	wire[31:0] err_out_tb;
	wire[2:0] sum_2a_tb;
	wire[15:0] rsr_b_tb,out_xor_tb;

test_1 testbench(
	.a(a_tb),
	.b(b_tb),
	.c_en(c_en_tb),
	.sel_en(sel_en_tb),
	.h_ab(h_ab_tb),
	.h_sel(h_sel_tb),
	.gate_en(gate_en_tb),
	.gt_lo_eq(gt_lo_eq_tb),
	.h_out(h_out_tb),
	.err_out(err_out_tb),
	.sum_2a(sum_2a_tb),
	.rsr_b(rsr_b_tb),
	.out_xor(out_xor_tb)
	);

initial	begin
//Testeaza aici

	c_en_tb = 1'b0;
	sel_en_tb = 1'b1;
	gate_en_tb = 1'b1;
	h_ab_tb = 1'b0;
	h_sel_tb = 1'b0;
	a_tb = 16'b1111111111111111;
	b_tb = 16'b0110000000000001;

end


initial begin
	$monitor("Pentru a=%b, b=%b c_en = %b, sel_en =%b s gate_en = %b obtinem: gt_lo_eq = %b, h_out = %b, sum_2a = %b, rsr_b = %b, out_xor = %b, err_out = %b",
	a_tb, b_tb, c_en_tb, sel_en_tb, gate_en_tb, gt_lo_eq_tb, h_out_tb, sum_2a_tb, rsr_b_tb, out_xor_tb, err_out_tb);

end
endmodule