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-- Company: 

-- Engineer:

--

-- Create Date:   15:08:17 03/03/2018

-- Design Name:   

-- Module Name:   C:/Users/Janek/Desktop/iup4/iup4/d_test.vhd

-- Project Name:  iup4

-- Target Device:  

-- Tool versions:  

-- Description:   

-- 

-- VHDL Test Bench Created by ISE for module: dff

-- 

-- Dependencies:

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes: 

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test.  Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation 

-- simulation model.

--------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

 

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

 

ENTITY d_test IS

END d_test;

 

ARCHITECTURE behavior OF d_test IS 

 

    -- Component Declaration for the Unit Under Test (UUT)

 

    COMPONENT dff

    PORT(

         rst : IN  std_logic;

         d : IN  std_logic;

         clk : IN  std_logic;

         outd : OUT  std_logic

        );

    END COMPONENT;

    



   --Inputs

   signal rst : std_logic := '0';

   signal d : std_logic := '0';

   signal clk : std_logic := '0';



 	--Outputs

   signal outd : std_logic;



   -- Clock period definitions

   constant clk_period : time := 100 ns;

 

BEGIN

 

	-- Instantiate the Unit Under Test (UUT)

   uut: dff PORT MAP (

          rst => rst,

          d => d,

          clk => clk,

          outd => outd

        );



   -- Clock process definitions

   clk_process :process

   begin

		clk <= '0';

		wait for clk_period/2;

		clk <= '1';

		wait for clk_period/2;

   end process;

 



   -- Stimulus process

   stim_proc: process

   begin		

      -- hold reset state for 100 ns.

      wait for 100 ns;	



      --wait for clk_period*10;

		d <= '1';

		

		wait for 305 ns;

		

		rst <= '1';

		

		wait for 20 ns;

		

		rst <= not rst;

		

		wait for 80 ns;

		d <= '0';

      -- insert stimulus here 



      wait;

   end process;



END;