rdAddr: process(resetAddrManager, RX_FRAMECLK_I) variable timer : integer range 0 to RX_GB_READ_DLY; variable readAddress : integer range 0 to 7; begin if resetAddrManager = '1' then readAddress := 1; readRSM_s <= e0_wait; timer := 0; READY_O <= '0'; READ_ADDRESS_O <= (others => '0'); elsif rising_edge(RX_FRAMECLK_I) then if RX_CLKEN_i = '1' then case readRSM_s is when e0_wait => if timer >= RX_GB_READ_DLY then readRSM_s <= e1_read; else timer := timer + 1; end if; when e1_read => readAddress := readAddress + 1; if readAddress = 1 then -- Ready after one full read to be sure that all register contains true data READY_O <= '1'; end if; end case; READ_ADDRESS_O <= std_logic_Vector(to_unsigned(readAddress, 3)); end if; end if; end process;