module mux2to1_3bit(input [2:0] in0, input [2:0] in1, input select, output reg [2:0] muxOut);
  //WRITE CODE HERE
	always@(select)
	begin
	case(select)
	1'b0 : muxOut = in0;
	1'b1 : muxOut = in1;
	endcase
	end

endmodule

// select 0 = in0 1 = in1
module mux2to1_8bit(input [7:0] in0, input [7:0] in1, input select, output reg [7:0] muxOut);
   //WRITE CODE HERE
	 always@(select)
 	begin
 	case(select)
 	1'b0 : muxOut = in0;
 	1'b1 : muxOut = in1;
 	endcase
 	end
	
endmodule


module mux8to1_1bit(input in0, input in1, input in2, input in3, input in4, input in5, input in6, input in7, input[2:0] select,output reg muxOut);
   //WRITE CODE HERE
	 always@(select)
	 begin
	 case(select)
	 	3'b000 : muxOut = in0;
		3'b001 : muxOut = in1;
		3'b010 : muxOut = in2;
		3'b011 : muxOut = in3;
		3'b100 : muxOut = in4;
		3'b101 : muxOut = in5;
		3'b110 : muxOut = in6;
		3'b111 : muxOut = in7;
	endcase
	end
endmodule

module barrelshifter(input[2:0] shiftAmt, input[7:0] b, input[2:0] oper, output[7:0] shiftOut);
	   //WRITE CODE HERE
		 wire [7:0]l1;
		 wire [7:0]l2;
		 wire [2:0]w1;
		 wire [2:0]w2;
		 wire [2:0]w3;

		 mux2to1_3bit M0(.in0(3'b000), .in1(oper[2:0]), .select(shiftAmt[0]), .muxOut(w1[2:0]));
		 mux2to1_3bit M1(.in0(3'b000), .in1(oper[2:0]), .select(shiftAmt[1]), .muxOut(w2[2:0]));
		 mux2to1_3bit M3(.in0(3'b000), .in1(oper[2:0]), .select(shiftAmt[2]), .muxOut(w3[2:0]));

		 mux8to1_1bit m0(.in0(b[0]), .in1(b[1]), .in2(b[1]), .in3(b[1]), .in4(1'b0), .in5(b[7]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[0]));
		 mux8to1_1bit m1(.in0(b[1]), .in1(b[2]), .in2(b[2]), .in3(b[2]), .in4(b[0]), .in5(b[0]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[1]));
		 mux8to1_1bit m2(.in0(b[2]), .in1(b[3]), .in2(b[3]), .in3(b[3]), .in4(b[1]), .in5(b[1]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[2]));
		 mux8to1_1bit m3(.in0(b[3]), .in1(b[4]), .in2(b[4]), .in3(b[4]), .in4(b[2]), .in5(b[2]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[3]));
		 mux8to1_1bit m4(.in0(b[4]), .in1(b[5]), .in2(b[5]), .in3(b[5]), .in4(b[3]), .in5(b[3]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[4]));
		 mux8to1_1bit m5(.in0(b[5]), .in1(b[6]), .in2(b[6]), .in3(b[6]), .in4(b[4]), .in5(b[4]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[5]));
		 mux8to1_1bit m6(.in0(b[6]), .in1(b[7]), .in2(b[7]), .in3(b[7]), .in4(b[5]), .in5(b[5]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[6]));
		 mux8to1_1bit m7(.in0(b[7]), .in1(b[7]), .in2(1'b0), .in3(b[0]), .in4(b[6]), .in5(b[6]), .in6(1'b0), .in7(1'b0), .select(w1[2:0]), .muxOut(l1[7]));

		 mux8to1_1bit n0(.in0(l1[0]), .in1(l1[2]), .in2(l1[2]), .in3(l1[2]), .in4(1'b0), .in5(l1[6]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[0]));
		 mux8to1_1bit n1(.in0(l1[1]), .in1(l1[3]), .in2(l1[3]), .in3(l1[3]), .in4(1'b0), .in5(l1[7]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[1]));
		 mux8to1_1bit n2(.in0(l1[2]), .in1(l1[4]), .in2(l1[4]), .in3(l1[4]), .in4(l1[0]), .in5(l1[0]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[2]));
		 mux8to1_1bit n3(.in0(l1[3]), .in1(l1[5]), .in2(l1[5]), .in3(l1[5]), .in4(l1[1]), .in5(l1[1]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[3]));
		 mux8to1_1bit n4(.in0(l1[4]), .in1(l1[6]), .in2(l1[6]), .in3(l1[6]), .in4(l1[2]), .in5(l1[2]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[4]));
		 mux8to1_1bit n5(.in0(l1[5]), .in1(l1[7]), .in2(l1[7]), .in3(l1[7]), .in4(l1[3]), .in5(l1[3]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[5]));
		 mux8to1_1bit n6(.in0(l1[6]), .in1(l1[7]), .in2(1'b0), .in3(l1[0]), .in4(l1[4]), .in5(l1[4]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[6]));
		 mux8to1_1bit n7(.in0(l1[7]), .in1(l1[7]), .in2(1'b0), .in3(l1[1]), .in4(l1[5]), .in5(l1[5]), .in6(1'b0), .in7(1'b0), .select(w2[2:0]), .muxOut(l2[7]));

		 mux8to1_1bit o0(.in0(l2[0]), .in1(l2[4]), .in2(l2[4]), .in3(l2[4]), .in4(1'b0), .in5(l2[4]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[0]));
		 mux8to1_1bit o1(.in0(l2[1]), .in1(l2[5]), .in2(l2[5]), .in3(l2[5]), .in4(1'b0), .in5(l2[5]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[1]));
		 mux8to1_1bit o2(.in0(l2[2]), .in1(l2[6]), .in2(l2[6]), .in3(l2[6]), .in4(1'b0), .in5(l2[6]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[2]));
		 mux8to1_1bit o3(.in0(l2[3]), .in1(l2[7]), .in2(l2[7]), .in3(l2[7]), .in4(1'b0), .in5(l2[7]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[3]));
		 mux8to1_1bit o4(.in0(l2[4]), .in1(l2[7]), .in2(1'b0), .in3(l2[0]), .in4(l2[0]), .in5(l2[0]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[4]));
		 mux8to1_1bit o5(.in0(l2[5]), .in1(l2[7]), .in2(1'b0), .in3(l2[1]), .in4(l2[1]), .in5(l2[1]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[5]));
		 mux8to1_1bit o6(.in0(l2[6]), .in1(l2[7]), .in2(1'b0), .in3(l2[2]), .in4(l2[2]), .in5(l2[2]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[6]));
		 mux8to1_1bit o7(.in0(l2[7]), .in1(l2[7]), .in2(1'b0), .in3(l2[3]), .in4(l2[3]), .in5(l2[3]), .in6(1'b0), .in7(1'b0), .select(w3[2:0]), .muxOut(shiftOut[7]));

endmodule

// Alu operations are: 00 for alu1, 01 for add, 10 for sub(alu1-alu2) , 11 for AND, 100 for OR and 101 for NOT(alu1)
module alu(input [7:0] aluIn1, input [7:0] aluIn2, input [2:0]aluOp, output reg [7:0] aluOut);
       //WRITE CODE HERE
			 wire w1;
			 always@(aluOp)
			 begin
			 case(aluOp)
			 	3'b000 : aluOut[7:0] = aluIn1[7:0];
				3'b001 : aluOut[7:0] = aluIn1[7:0] + aluIn2[7:0];
				3'b010 : aluOut[7:0] = aluIn1[7:0] - aluIn2[7:0];
				3'b011 : aluOut[7:0] = aluIn1[7:0] & aluIn2[7:0];
				3'b100 : aluOut[7:0] = aluIn1[7:0] | aluIn2[7:0];
				3'b101 : aluOut[7:0] = ~aluIn1[7:0];
				endcase
			end
endmodule


module shifterAndALU(input [7:0]inp1, input [7:0] inp2, input [2:0]shiftlmm, input selShiftAmt, input [2:0]oper, input selOut, output [7:0] out);
	   //WRITE CODE HERE
		 wire [7:0]l1;
		 wire [7:0]l2;
		 wire [2:0]l3;

		 alu a1(.aluIn1(inp1[7:0]), .aluIn2(inp2[7:0]), .aluOp(oper[2:0]), .aluOut(l1[7:0]));

		 mux2to1_3bit a2(.in0(inp2[2:0]), .in1(shiftlmm[2:0]), .select(selShiftAmt), .muxOut(l3[2:0]));

		 barrelshifter a3(.shiftAmt(l3[2:0]), .b(inp1[7:0]), .oper(oper[2:0]), .shiftOut(l2[7:0]));

		 mux2to1_8bit a4(.in0(l1[7:0]), .in1(l2[7:0]), .select(selOut), .muxOut(out[7:0]));

endmodule

//TestBench ALU
module testbenchALU();
	// Input
	reg [7:0] inp1, inp2;
	reg [2:0] aluOp;
	reg [2:0] shiftlmm;
	reg selShiftAmt, selOut;
	// Output
	wire [7:0] aluOut;

	shifterAndALU shifterAndALU_Test (inp1, inp2, shiftlmm, selShiftAmt, aluOp, selOut, aluOut);

	initial
		begin
			$dumpfile("testALU.vcd");
     	$dumpvars(0,testbenchALU);
			inp1 = 8'd80; //80 in binary is 1010000
			inp2 = 8'd20; //20 in binary is 10100
			shiftlmm = 3'b010;

			aluOp=3'd0; selOut = 1'b0;// normal output = 80

			#10 aluOp = 3'd0; selOut = 1'b1; selShiftAmt = 1'b1; //No shift output = 80

			#10 aluOp=3'd1; selOut = 1'b0;// normal add	output => 20 + 80 = 100

			#10 aluOp = 3'd1; selOut = 1'b1; selShiftAmt = 1'b1; // arithmetic shift right of 80 by 2 places = 20

			#10 aluOp=3'd2; selOut = 1'b0; // normal sub output => 80 - 20 = 60

			#10 aluOp = 3'd2; selOut = 1'b1; selShiftAmt = 1'b0; // logical shift right of 80 by 4 places = 0

			#10 aluOp=3'd3; selOut = 1'b0;// normal and output => 80 & 20 = 16

			#10 aluOp = 3'd3; selOut = 1'b1; selShiftAmt = 1'b0; // Circular Shift Right of 80 by 4 places = 5

			#10 aluOp=3'd4; selOut = 1'b0;// normal or output => 80 | 20 = 84

			#10 aluOp = 3'd4; selOut = 1'b1; selShiftAmt = 1'b1; // Logical Shift Left of 80 by 2 bits = 64

			#10 aluOp=3'd5; selOut = 1'b0; // normal not of 80 = 175

			#10 aluOp = 3'd5; selOut = 1'b1; selShiftAmt = 1'b0; // Circular left shift of 80 by 4 bits = 5

			#10 inp1=8'd15; inp2=8'd26; aluOp=3'd2; selOut = 1'b0;//sub overflow
			// (15 - 26) = -11 and its a 8 bit number so, 256-11 = 245 output => 245 (since it is unsigned decimal)

			#10 inp1=8'd150; inp2=8'd150; aluOp=3'd1; selOut = 1'b0;// add overflow
			//(150+150) = 300 and its a 8 bit number so, 300-256 = 44 output=> 44.

			#10 inp1=8'b0000_0000; aluOp=3'd5; selOut = 1'b0;//not overflow
			// not(0) = all 1. Since its a 8 bit number output=>255

			#10 $finish;
		end

endmodule