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From Mahdi Shokoufi - 401110115, 2 Months ago, written in Verilog.
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  1. module 1to2dec(inp, en, out);
  2.  input inp, en;
  3.  output out[1:0];
  4.  wire inp_n, en_n;
  5.  assign inp_n = ~inp;
  6.  assign en_n = ~en;
  7.  assign out[0] = ~(inp_n & en_n);
  8.  assign out[1] = ~(inp & en_n);
  9. endmodule;
  10.  
  11. module 1to2dec(inp0, inp1, en, out);
  12.  input inp0, inp1, en;
  13.  output out[3:0];
  14.  wire s[1:0];
  15.  assign s[0] = 1to2dec(.inp(inp1), .en(en))[0];
  16.  assign s[1] = 1to2dec(.inp(inp1), .en(en))[1];
  17.  assign out[0] = 1to2dec(.inp(inp0), .en(c[0]))[0];
  18.  assign out[1] = 1to2dec(.inp(inp0), .en(c[0]))[1];
  19.  assign out[2] = 1to2dec(.inp(inp0), .en(c[1]))[0];
  20.  assign out[0] = 1to2dec(.inp(inp0), .en(c[1]))[1];
  21. endmodule;