Facebook
From Cream Wigeon, 1 Month ago, written in Plain Text.
Embed
Download Paste or View Raw
Hits: 25
  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 14.10.2020 16:24:58
  6. -- Design Name:
  7. -- Module Name: tb - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20.  
  21.  
  22. library IEEE;
  23. use IEEE.STD_LOGIC_1164.ALL;
  24.  
  25. -- Uncomment the following library declaration if using
  26. -- arithmetic functions with Signed or Unsigned values
  27. --use IEEE.NUMERIC_STD.ALL;
  28.  
  29. -- Uncomment the following library declaration if instantiating
  30. -- any Xilinx leaf cells in this code.
  31. --library UNISIM;
  32. --use UNISIM.VComponents.all;
  33.  
  34. entity tb is
  35. --  Port ( );
  36. end tb;
  37.  
  38. architecture Behavioral of tb is
  39.  
  40. component top is
  41.  
  42.     Port ( clk_i : in STD_LOGIC;
  43.  
  44.            rst_i : in STD_LOGIC;
  45.  
  46.            led_o : out STD_LOGIC_VECTOR (2 downto 0));
  47.  
  48. end component top;
  49.  
  50. signal clk_i : STD_LOGIC := '0';
  51. signal rst_i : STD_LOGIC := '0';
  52. signal led_o : std_logic_vector(2 downto 0);
  53.  
  54. begin
  55.  
  56. dut: top port map(
  57.     clk_i => clk_i,
  58.     rst_i => rst_i,
  59.     led_o => led_o);
  60.    
  61. clk_i <= not clk_i after 10ns;
  62.  
  63. stim: process
  64.     begin
  65.         wait for 100ns;
  66.         rst_i <= '1';
  67.         wait for 100ns;
  68.         rst_i <= '0';
  69.         wait;
  70.     end process;
  71.  
  72.  
  73. end Behavioral;
  74.