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  1. 2.4.6. Executing PROC_DLATCH pass (convert process syncs to latches).
  2. 2.8.1.6. Executing PROC_DLATCH pass (convert process syncs to latches).
  3. 2.16.4.6. Executing PROC_DLATCH pass (convert process syncs to latches).
  4. Generating RTLIL representation for module `\$_DLATCH_N_'.
  5. Generating RTLIL representation for module `\$_DLATCH_P_'.
  6. Mapping \$_DLATCH_P_.$ternary$/usr/local/bin/../share/yosys/ecp5/latches_map.v:10$31584 ($mux).
  7. Finding identical cells in module `\$_DLATCH_P_'.
  8. Running muxtree optimizer on module \$_DLATCH_P_..
  9.   Optimizing cells in module \$_DLATCH_P_.
  10. Finding identical cells in module `\$_DLATCH_P_'.
  11. Finding unused cells or wires in module \$_DLATCH_P_..
  12. Mapping saturn_core.$auto$simplemap.cc:517:simplemap_dlatch$14852 using \$_DLATCH_P_.
  13. Mapping saturn_core.$auto$simplemap.cc:517:simplemap_dlatch$14853 using \$_DLATCH_P_.
  14. Mapping saturn_core.$auto$simplemap.cc:517:simplemap_dlatch$14854 using \$_DLATCH_P_.
  15. Mapping saturn_core.$auto$simplemap.cc:517:simplemap_dlatch$14855 using \$_DLATCH_P_.
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