Library IEEE;
use IEEE.STD_LOGIC_1164.All;
entity z1 is
port(
Ledr : out std_Logic_vector(2 downto 0);
sw : in std_Logic_vector(2 downto 0);
);
architecture z1 of zad1 VHDL is
begin process(sw)
begin
case sw is
when
"000" => ledr <= "000";
"001" => ledr <= "100";
"010" => ledr <= "001";
"011" => ledr <= "010";
"100" => ledr <= "010";
"101" => ledr <= "110";
"110" => ledr <= "011";
end case;
end process;
end z1;
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