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-- Company:
-- Engineer:
--
-- Create Date: 10:37:46 03/12/2018
-- Design Name:
-- Module Name: VGA_1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VGA_1 is
Port ( Clk_50MHz : in STD_LOGIC;
red_out : out STD_LOGIC;
green_out : out STD_LOGIC;
blue_out : out STD_LOGIC;
VGA_HS : out STD_LOGIC;
test : in STD_LOGIC;
VGA_VS : out STD_LOGIC);
end VGA_1;
architecture Behavioral of VGA_1 is
signal licznik : std_logic_vector (31 downto 0);
signal horizontal_counter : std_logic_vector (10 downto 0);
signal vertical_counter : std_logic_vector (10 downto 0);
begin
process (Clk_50MHz) begin
if Clk_50MHz'event and Clk_50MHz = '1' then
horizontal_counter <= horizontal_counter+"00000000001";
if (horizontal_counter="10000010000") then
vertical_counter <= vertical_counter+"00000000001";
horizontal_counter <= "00000000000";
end if;
if (vertical_counter="01010011010") then
vertical_counter <= "00000000000";
end if;
end if;
if (horizontal_counter > "00000000000" ) and (horizontal_counter < "00001111001" ) then
VGA_HS <= '0';
else
VGA_HS <= '1';
end if;
if (vertical_counter > "00000000000" )and (vertical_counter < "00000000111" )then
VGA_VS <= '0';
else
VGA_VS <= '1';
end if;
if(horizontal_counter < "00101101101" ) or(horizontal_counter > "01001100111" or (vertical_counter > "00111110100" ) ) then
red_out <= '0';
green_out <= '0';
blue_out <= '0';
else
red_out <= '1';
green_out <= '1';
blue_out <= '1';
end if;
end process;
end Behavioral;
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