1. -- Testbench created online at:
2. --   https://www.doulos.com/knowhow/perl/vhdl-testbench-creation-using-perl/
3. -- Copyright Doulos Ltd
4.  
5. library IEEE;
6. use IEEE.Std_logic_1164.all;
7. use IEEE.Numeric_Std.all;
8. -- use IEEE.std_logic_arith.all;
9.  
10. entity fir_tb is
11.  
12. attribute dont_touch : string;
13. attribute dont_touch of fir_tb : entity is "true|yes";
14.  
15. end;
16.  
17. architecture bench of fir_tb is
18.  
19.   component fir
20.    Port (
21.    clk: in std_logic;
22.    data_in: in unsigned(7 downto 0);
23.    data_out: out unsigned(7 downto 0);
24.    en: in std_logic;
25.    load: in std_logic;
26.    start: in std_logic;
27.    reset: in std_logic
28.    );
29.   end component;
30.  
31.   attribute dont_touch of fir : component is "true|yes";
32.  
33.   signal clk: std_logic;
34.   signal data_in: unsigned(7 downto 0);
35.   signal data_out: unsigned(7 downto 0);
36.   signal en: std_logic;
37.   signal load: std_logic;
38.   signal start: std_logic;
39.   signal reset: std_logic ;
40.  
41.   constant clock_period: time := 10 ns;
42.   signal stop_the_clock: boolean;
43.  
44. begin
45.  
46.   uut: fir port map ( clk      => clk,
47.                       data_in  => data_in,
48.                       data_out => data_out,
49.                       en       => en,
50.                       load     => load,
51.                       start    => start,
52.                       reset    => reset );                    
53.  
54.   stimulus: process
55.   begin
56.  
57.     -- Put initialisation code here
58.  
59.     reset <= '1';
60.     en <= '1';
61.     load <= '0';
62.     start <= '0';
63.     data_in <= (others => '0');        
64.     wait for 5 ns;
65.     reset <= '0';
66.     wait for 10 ns;
67.    
68.     -- Put test bench stimulus code here
69.     load <= '1';
70.     wait for 10 ns;
71.     data_in <= "00000001";
72.     wait for 10 ns;
73.     data_in <= "00000010";
74.     wait for 10 ns;
75.     data_in <= "00000100";
76.     wait for 10 ns;
77.     data_in <= "00001000";
78.     wait for 10 ns;
79.     data_in <= "00010000";
80.     wait for 10 ns;
81.     data_in <= "00100000";
82.     wait for 10 ns;
83.     data_in <= "01000000";
84.     wait for 10 ns;
85.     data_in <= "10000000";
86.     wait for 10 ns;
87.     load <= '0';
88.    
89.     wait for 10 ns;
90.     start <= '1';
91.     wait for 100 ns;
92.    
93.     reset <= '1';
94.     wait for 5 ns;
95.     reset <= '0';
96.     wait for 30 ns;
97.    
98.    
99.  
100.     stop_the_clock <= true;
101.     wait;
102.   end process;
103.  
104.   clocking: process
105.   begin
106.     while not stop_the_clock loop
107.       clk <= '0', '1' after clock_period / 2;
108.       wait for clock_period;
109.     end loop;
110.     wait;
111.   end process;
112.  
113. end;
114.