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bcm57711-freebsd113-patch safest cryptocurrency exchange

From dslreports, 3 Years ago, written in Plain Text.
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  1. diff --git a/sys/dev/bxe/bxe.c b/sys/dev/bxe/bxe.c
  2. index cf8cfb66e..43d3e5f6a 100644
  3. --- a/sys/dev/bxe/bxe.c
  4. +++ b/sys/dev/bxe/bxe.c
  5. @@ -104,7 +104,7 @@ static struct bxe_device_type bxe_devs[] = {
  6.          BRCM_VENDORID,
  7.          CHIP_NUM_57711,
  8.          PCI_ANY_ID, PCI_ANY_ID,
  9. -        "QLogic NetXtreme II BCM57711 10GbE"
  10. +        "QLogic NetXtreme II BCM57711 10GbE [BELL BYPASS]"
  11.      },
  12.      {
  13.          BRCM_VENDORID,
  14. @@ -140,7 +140,7 @@ static struct bxe_device_type bxe_devs[] = {
  15.          BRCM_VENDORID,
  16.          CHIP_NUM_57810,
  17.          PCI_ANY_ID, PCI_ANY_ID,
  18. -        "QLogic NetXtreme II BCM57810 10GbE"
  19. +        "QLogic NetXtreme II BCM57810 10GbE [BELL BYPASS]"
  20.      },
  21.      {
  22.          BRCM_VENDORID,
  23. diff --git a/sys/dev/bxe/bxe_elink.c b/sys/dev/bxe/bxe_elink.c
  24. index e3ad174c4..af28a6636 100644
  25. --- a/sys/dev/bxe/bxe_elink.c
  26. +++ b/sys/dev/bxe/bxe_elink.c
  27. @@ -391,7 +391,8 @@ Theotherbitsarereservedandshouldbezero*/
  28.  #define MDIO_PMA_REG_8727_PCS_GP       0xc842
  29.  #define MDIO_PMA_REG_8727_OPT_CFG_REG      0xc8e4
  30.  
  31. -#define MDIO_AN_REG_8727_MISC_CTRL     0x8309
  32. +#define MDIO_AN_REG_8727_MISC_CTRL1        0x8308
  33. +#define MDIO_AN_REG_8727_MISC_CTRL2        0x8309
  34.  #define    MDIO_PMA_REG_8073_CHIP_REV          0xc801
  35.  #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS        0xc820
  36.  #define MDIO_PMA_REG_8073_XAUI_WA          0xc841
  37. @@ -882,6 +883,7 @@ typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
  38.  
  39.  #define ELINK_SFP_EEPROM_CON_TYPE_ADDR     0x2
  40.     #define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN   0x0
  41. +   #define ELINK_SFP_EEPROM_CON_TYPE_VAL_SC    0x1
  42.     #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC    0x7
  43.     #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER    0x21
  44.     #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45  0x22
  45. @@ -5042,6 +5044,15 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
  46.                      0x1000);
  47.         ELINK_DEBUG_P0(sc, "set SGMII AUTONEG\n");
  48.     } else {
  49. +       if (fiber_mode && (phy->req_line_speed == ELINK_SPEED_2500) &&
  50. +           (phy->speed_cap_mask &
  51. +            (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
  52. +             PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))) {
  53. +           elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
  54. +                    MDIO_WC_REG_SERDESDIGITAL_MISC1,
  55. +                    0x6010);
  56. +       }
  57. +
  58.         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
  59.                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
  60.         val16 &= 0xcebf;
  61. @@ -5052,6 +5063,7 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
  62.             val16 |= 0x2000;
  63.             break;
  64.         case ELINK_SPEED_1000:
  65. +       case ELINK_SPEED_2500:
  66.             val16 |= 0x0040;
  67.             break;
  68.         default:
  69. @@ -9069,6 +9081,7 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
  70.         break;
  71.     }
  72.     case ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
  73. +   case ELINK_SFP_EEPROM_CON_TYPE_VAL_SC:
  74.     case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
  75.     case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
  76.         check_limiting_mode = 1;
  77. @@ -9082,7 +9095,8 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
  78.             (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
  79.             ELINK_DEBUG_P0(sc, "1G SFP module detected\n");
  80.             phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
  81. -           if (phy->req_line_speed != ELINK_SPEED_1000) {
  82. +           if ((phy->req_line_speed != ELINK_SPEED_1000) &&
  83. +               (phy->req_line_speed != ELINK_SPEED_2500)) {
  84.                 uint8_t gport = params->port;
  85.                 phy->req_line_speed = ELINK_SPEED_1000;
  86.                 if (!CHIP_IS_E1x(sc)) {
  87. @@ -10146,6 +10160,7 @@ static void elink_8727_config_speed(struct elink_phy *phy,
  88.     uint16_t tmp1, val;
  89.     /* Set option 1G speed */
  90.     if ((phy->req_line_speed == ELINK_SPEED_1000) ||
  91. +       (phy->req_line_speed == ELINK_SPEED_2500) ||
  92.         (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
  93.         ELINK_DEBUG_P0(sc, "Setting 1G force\n");
  94.         elink_cl45_write(sc, phy,
  95. @@ -10155,6 +10170,22 @@ static void elink_8727_config_speed(struct elink_phy *phy,
  96.         elink_cl45_read(sc, phy,
  97.                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
  98.         ELINK_DEBUG_P1(sc, "1.7 = 0x%x\n", tmp1);
  99. +       if ((phy->req_line_speed == ELINK_SPEED_2500) &&
  100. +           (phy->speed_cap_mask &
  101. +            (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
  102. +             PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))) {
  103. +           elink_cl45_read_and_write(sc, phy,
  104. +                         MDIO_AN_DEVAD,
  105. +                         MDIO_AN_REG_8727_MISC_CTRL2,
  106. +                         ~(1<<5));
  107. +           elink_cl45_write(sc, phy,
  108. +                    MDIO_AN_DEVAD,
  109. +                    MDIO_AN_REG_8727_MISC_CTRL1, 0x0010);
  110. +       } else {
  111. +           elink_cl45_write(sc, phy,
  112. +                    MDIO_AN_DEVAD,
  113. +                    MDIO_AN_REG_8727_MISC_CTRL1, 0x001C);
  114. +       }
  115.         /* Power down the XAUI until link is up in case of dual-media
  116.          * and 1G
  117.          */
  118. @@ -10176,7 +10207,7 @@ static void elink_8727_config_speed(struct elink_phy *phy,
  119.  
  120.         ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
  121.         elink_cl45_write(sc, phy,
  122. -                MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
  123. +                MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL2, 0);
  124.         elink_cl45_write(sc, phy,
  125.                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
  126.     } else {
  127. @@ -10184,8 +10215,11 @@ static void elink_8727_config_speed(struct elink_phy *phy,
  128.          * registers although it is default
  129.          */
  130.         elink_cl45_write(sc, phy,
  131. -                MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
  132. +                MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL2,
  133.                  0x0020);
  134. +       elink_cl45_write(sc, phy,
  135. +                MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL1,
  136. +                0x001C);
  137.         elink_cl45_write(sc, phy,
  138.                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
  139.         elink_cl45_write(sc, phy,
  140. @@ -10477,6 +10511,11 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
  141.         vars->line_speed = ELINK_SPEED_10000;
  142.         ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
  143.                params->port);
  144. +   } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
  145. +       link_up = 1;
  146. +       vars->line_speed = ELINK_SPEED_2500;
  147. +       ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G\n",
  148. +              params->port);
  149.     } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
  150.         link_up = 1;
  151.         vars->line_speed = ELINK_SPEED_1000;
  152. @@ -10508,7 +10547,8 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
  153.     }
  154.  
  155.     if ((ELINK_DUAL_MEDIA(params)) &&
  156. -       (phy->req_line_speed == ELINK_SPEED_1000)) {
  157. +       ((phy->req_line_speed == ELINK_SPEED_1000) ||
  158. +        (phy->req_line_speed == ELINK_SPEED_2500))) {
  159.         elink_cl45_read(sc, phy,
  160.                 MDIO_PMA_DEVAD,
  161.                 MDIO_PMA_REG_8727_PCS_GP, &val1);
  162. @@ -12530,6 +12570,7 @@ static const struct elink_phy phy_warpcore = {
  163.                ELINK_SUPPORTED_100baseT_Full |
  164.                ELINK_SUPPORTED_1000baseT_Full |
  165.                ELINK_SUPPORTED_1000baseKX_Full |
  166. +              ELINK_SUPPORTED_2500baseX_Full |
  167.                ELINK_SUPPORTED_10000baseT_Full |
  168.                ELINK_SUPPORTED_10000baseKR_Full |
  169.                ELINK_SUPPORTED_20000baseKR2_Full |
  170. @@ -12716,6 +12757,7 @@ static const struct elink_phy phy_8727 = {
  171.     .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
  172.     .mdio_ctrl  = 0,
  173.     .supported  = (ELINK_SUPPORTED_10000baseT_Full |
  174. +              ELINK_SUPPORTED_2500baseX_Full |
  175.                ELINK_SUPPORTED_1000baseT_Full |
  176.                ELINK_SUPPORTED_FIBRE |
  177.                ELINK_SUPPORTED_Pause |
  178. @@ -13067,6 +13109,7 @@ static elink_status_t elink_populate_int_phy(struct bxe_softc *sc, uint32_t shme
  179.             break;
  180.         case PORT_HW_CFG_NET_SERDES_IF_SFI:
  181.             phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
  182. +                      ELINK_SUPPORTED_2500baseX_Full |
  183.                        ELINK_SUPPORTED_10000baseT_Full |
  184.                        ELINK_SUPPORTED_FIBRE |
  185.                        ELINK_SUPPORTED_Pause |

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