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/dts-v1/;

/ {

#address-cells = <0x02>;

model = "SWEET";

qcom,board-id = <0x2e 0x00>;

#size-cells = <0x02>;

interrupt-parent = <0x01>;

qcom,msm-name = "SDMMAGPIE";

compatible = "qcom,sdmmagpie-qrd\0qcom,sdmmagpie\0qcom,qrd";

qcom,pmic-name = "PM6150";

qcom,msm-id = <0x16d 0x00>;

energy-costs {

compatible = "sched-energy";

phandle = <0x4d5>;

core-cost0 {

busy-cost-data = <0x493e0 0x0a 0x8ca00 0x12 0xbb800 0x17 0xf8700 0x24 0x130b00 0x34 0x143700 0x43 0x16da00 0x4c 0x189c00 0x5c 0x1a1300 0x71 0x1b8a00 0x77>;

idle-cost-data = <0x10 0x0c 0x08 0x06>;

phandle = <0x02>;

};

cluster-cost0 {

busy-cost-data = <0x493e0 0x05 0x8ca00 0x05 0xbb800 0x05 0xf8700 0x07 0x130b00 0x08 0x143700 0x0a 0x16da00 0x0a 0x189c00 0x0c 0x1a1300 0x0e 0x1b8a00 0x0e>;

idle-cost-data = <0x05 0x04 0x03 0x02 0x01>;

phandle = <0x03>;

};

core-cost1 {

busy-cost-data = <0x493e0 0xa6 0x9f600 0xf2 0xc4e00 0x125 0xef100 0x1a8 0x10b300 0x1d6 0x127500 0x26d 0x143700 0x2a4 0x17bb00 0x3cd 0x1a1300 0x424 0x1c2000 0x512 0x1d9700 0x552 0x211b00 0x709 0x21b100 0x7d0 0x240900 0x916 0x249f00 0xa08>;

idle-cost-data = <0x64 0x50 0x3c 0x28>;

phandle = <0x0c>;

};

cluster-cost1 {

busy-cost-data = <0x493e0 0x13 0x9f600 0x15 0xc4e00 0x15 0xef100 0x19 0x10b300 0x1a 0x127500 0x20 0x143700 0x21 0x17bb00 0x29 0x1a1300 0x2b 0x1c2000 0x31 0x1d9700 0x32 0x211b00 0x3c 0x21b100 0x3d 0x240900 0x3e 0x249f00 0x3f>;

idle-cost-data = <0x05 0x04 0x03 0x02 0x01>;

phandle = <0x0d>;

};

};

soc {

#address-cells = <0x01>;

#size-cells = <0x01>;

compatible = "simple-bus";

ranges = <0x00 0x00 0x00 0xffffffff>;

phandle = <0x2a7>;

qcom,wb-display@0 {

cell-index = <0x00>;

label = "wb_display";

compatible = "qcom,wb-display";

phandle = <0x55e>;

};

funnel@6a05000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-ddr-0";

compatible = "arm,primecell";

reg = <0x6a05000 0x1000>;

phandle = <0x453>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x24b>;

phandle = <0x233>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x24c>;

phandle = <0x24d>;

};

};

};

};

mailbox@af20000 {

interrupts = <0x00 0x81 0x00>;

#mbox-cells = <0x01>;

label = "display_rsc";

qcom,drv-id = <0x00>;

compatible = "qcom,tcs-drv";

reg = <0xaf20000 0x100 0xaf21c00 0x3000>;

phandle = <0xcf>;

qcom,tcs-config = <0x00 0x01 0x01 0x01 0x02 0x02 0x03 0x00>;

};

qcom,npu-npu-ddr-bwmon@9960300 {

reg-names = "base\0global_base";

interrupts = <0x00 0x16d 0x04>;

compatible = "qcom,bimc-bwmon4";

qcom,hw-timer-hz = <0x124f800>;

qcom,mport = <0x00>;

qcom,count-unit = <0x10000>;

reg = <0x9960300 0x300 0x9960200 0x200>;

phandle = <0x31b>;

qcom,target-dev = <0xc8>;

};

qcom,mdss_dsi_xiaomi_f4_41_06_0a_fhd_cmd {

qcom,ulps-enabled;

qcom,disp-doze-backlight-threshold = <0x08>;

qcom,mdss-dsi-bl-min-level = <0x02>;

qcom,mdss-pan-physical-width-dimension = <0x45>;

qcom,mdss-dsi-panel-name = "xiaomi f4 41 06 0a fhd cmd dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x95>;

qcom,mdss-dsi-bl-xiaomi-f4-41-flag;

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-t-clk-post = <0x0e>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-panel-id = <0x00>;

qcom,mdss-dsi-panel-fod-dimlayer-enabled;

qcom,mdss-dsi-mode-sel-gpio-state = "single_port";

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-bl-max-level = <0x7ff>;

qcom,bl-update-flag = "delay_until_first_frame";

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,mdss-dsi-panel-dc-demura-threshold = <0x106>;

qcom,disp-fod-off-dimming-delay = <0x55>;

qcom,dispparam-enabled;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-bl-default-level = <0x218>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-bl-dcs-type-ss-ea;

qcom,mdss-dsi-reset-sequence = <0x00 0x01 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-panel-on-dimming-delay = <0xc8>;

qcom,mdss-dsi-t-clk-pre = <0x33>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x53a>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-panel-sleepwrmod = <0x00>;

qcom,panel-supply-entries = <0x521>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,platform-te-gpio = <0x174 0x0a 0x00>;

qcom,esd-err-irq-gpio = <0x174 0x20 0x2002>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-brightness-max-level = <0x7ff>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,mdss-dsi-dispparam-demura-level8-command-state = "dsi_lp_mode";

qcom,display-topology = <0x01 0x00 0x01>;

qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x04>;

qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dc-demura-l1-command = [39 01 00 00 00 00 02 fe 20 39 01 00 00 00 00 02 bc 00 39 01 00 00 00 00 02 fe 00];

qcom,mdss-dsi-panel-jitter = <0x05 0x01>;

qcom,mdss-dsi-nolp-command = [39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 25 06 39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 1f 08 39 01 00 00 00 00 02 2f 15 39 01 00 00 00 00 02 29 c0 39 01 00 00 00 00 02 fe 22 39 01 00 00 00 00 02 77 00 39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 38 00];

qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode";

qcom,mdss-dsi-dispparam-demura-leveld-command = [39 01 00 00 00 00 02 fe 20 39 01 00 00 00 00 02 bc 0d 39 01 00 00 00 00 02 fe 00];

qcom,mdss-dsi-dispparam-dc-off-command-state = "dsi_hs_mode";

qcom,mdss-dsi-dispparam-dc-on-command-state = "dsi_hs_mode";

qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode";

qcom,mdss-dsi-doze-lbm-command = [39 00 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 39 00 39 01 00 00 00 00 02 fe 72 39 01 00 00 00 00 02 69 0a 39 01 00 00 00 00 02 fe 22 39 01 00 00 00 00 02 77 02 39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 1f 00 39 01 00 00 00 00 02 2f 05 39 01 00 00 00 00 02 29 c1 39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 25 16];

qcom,mdss-dsi-dispparam-hbm-fod-on-command = <0x39010000 0x30002fe 0xa0390000 0x02 0x25063900 0x00 0x2fea039 0x00 0x21f08 0x39000000 0x22f 0x15390000 0x02 0x29c03900 0x00 0x2fe2239 0x00 0x27700 0x39000000 0x2fe 0x390000 0x02 0x38003900 0x00 0x2fe0039 0x1000000 0x253e0>;

qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 e8];

qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-hbm-fod-off-command = [39 01 00 00 03 00 02 fe 00 39 01 00 00 00 00 02 53 20];

qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 28];

qcom,mdss-dsi-dispparam-demura-level2-command = [39 01 00 00 00 00 02 fe 20 39 01 00 00 00 00 02 bc 02 39 01 00 00 00 00 02 fe 00];

qcom,mdss-dsi-dispparam-dc-on-command = <0x39000000 0x2fe 0x40390000 0x02 0x1db83900 0x00 0x2fed039 0x00 0x27101 0x39010000 0x10002fb 0xaa390000 0x02 0xfe743900 0x00 0x20e6039 0x00 0x21001 0x39000000 0x211 0x390000 0x02 0x12003900 0x00 0x2130039 0x00 0x21400 0x39000000 0x215 0x390000 0x02 0x22603900 0x00 0x2430039 0x00 0x2451f 0x39000000 0x24a 0xff390000 0x02 0x61603900 0x00 0x2fe4039 0x00 0x21df8 0x39000000 0x2fe 0xd0390000 0x02 0x71023901 0x1400 0x2fbaa39 0x1000000 0x2fe00>;

qcom,mdss-dsi-dispparam-dc-off-command = <0x39000000 0x2fe 0x40390000 0x02 0x1db83900 0x00 0x2fed039 0x00 0x27101 0x39010000 0x10002fb 0xaa390000 0x02 0xfe743900 0x00 0x20e7f39 0x00 0x21008 0x39000000 0x211 0x8390000 0x02 0x12073900 0x00 0x2130639 0x00 0x21405 0x39000000 0x215 0x2390000 0x02 0x227f3900 0x00 0x2433f39 0x00 0x24511 0x39000000 0x24a 0x6f390000 0x02 0x617f3900 0x00 0x2fe4039 0x00 0x21df8 0x39000000 0x2fe 0xd0390000 0x02 0x71023901 0x1400 0x2fbaa39 0x1000000 0x2fe00>;

qcom,mdss-dsi-panel-height = <0x924>;

qcom,mdss-dsi-on-command = [39 00 00 00 00 00 02 fe 40 39 00 00 00 00 00 02 70 04 39 01 00 00 00 00 02 4d 32 39 00 00 00 00 00 02 fe 40 39 00 00 00 00 00 02 be 17 39 00 00 00 00 00 02 bf bb 39 00 00 00 00 00 02 c0 dd 39 01 00 00 00 00 02 c1 ff 39 00 00 00 00 00 02 fe d0 39 00 00 00 00 00 02 03 24 39 01 00 00 00 00 02 04 03 39 00 00 00 00 00 02 fe 00 39 00 00 00 00 00 02 c2 08 39 00 00 00 00 00 02 fe 00 39 00 00 00 00 00 02 35 00 39 01 00 00 00 00 03 51 00 00 05 01 00 00 64 00 02 11 00 05 01 00 00 00 00 02 29 00];

qcom,mdss-dsi-h-front-porch = <0x1c>;

qcom,mdss-dsi-dispparam-demura-level2-command-state = "dsi_lp_mode";

qcom,mdss-dsi-h-back-porch = <0x24>;

qcom,mdss-dsi-dispparam-dc-demura-l1-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-demura-leveld-command-state = "dsi_lp_mode";

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsi-panel-clockrate = <0x4190ab00>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x04>;

qcom,mdss-dsi-doze-hbm-command = [39 00 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 39 00 39 01 00 00 00 00 02 fe 72 39 01 00 00 00 00 02 69 ff 39 01 00 00 00 00 02 fe 22 39 01 00 00 00 00 02 77 02 39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 1f 00 39 01 00 00 00 00 02 2f 05 39 01 00 00 00 00 02 29 c1 39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 25 16];

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dc-demura-l2-command = [39 01 00 00 00 00 02 fe 20 39 01 00 00 00 00 02 bc 04 39 01 00 00 00 00 02 fe 00];

qcom,mdss-dsi-dispparam-dimmingoff-command = [15 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 20];

qcom,mdss-dsi-panel-phy-timings = <0x220808 0x25220908 0x6020400>;

qcom,mdss-dsi-v-back-porch = <0x04>;

qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode";

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-dispparam-demura-level8-command = [39 01 00 00 00 00 02 fe 20 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 fe 00];

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode";

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 14 00 02 10 00];

qcom,mdss-dsi-dispparam-dc-demura-l2-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dimmingon-command = [15 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 28];

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

};

};

qcom,msm-sen-auxpcm {

qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;

qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;

qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;

qcom,msm-auxpcm-interface = "senary";

qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;

qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;

qcom,msm-cpudai-afe-clk-ver = <0x02>;

qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;

compatible = "qcom,msm-auxpcm-dev";

qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;

phandle = <0x4b8>;

qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;

};

cti@601e000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti14";

compatible = "arm,primecell";

reg = <0x601e000 0x1000>;

phandle = <0x483>;

};

hwlock {

syscon = <0x8f 0x00 0x1000>;

compatible = "qcom,tcsr-mutex";

phandle = <0x91>;

#hwlock-cells = <0x01>;

};

tmc@6b09000 {

arm,primecell-periphid = <0x3b961>;

clock-names = "apb_pclk";

reg-names = "tmc-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tmc-etf-swao";

compatible = "arm,primecell";

reg = <0x6b09000 0x1000>;

phandle = <0x42b>;

coresight-csr = <0x1d6>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1f6>;

phandle = <0x1f5>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x1f7>;

phandle = <0x1f8>;

};

};

};

};

qcom,lpass@62400000 {

qcom,smem-state-names = "qcom,force-stop";

qcom,smem-id = <0x1a7>;

qcom,sysmon-id = <0x01>;

qcom,vdd_mx-uV-uA = <0x181 0x00>;

qcom,ssctl-instance-id = <0x14>;

clock-names = "xo";

qcom,proxy-timeout-ms = <0x2710>;

memory-region = <0xa1>;

clocks = <0x2f 0x00>;

qcom,signal-aop;

qcom,complete-ramdump;

qcom,pas-id = <0x01>;

interrupts-extended = <0x01 0x00 0xa2 0x01 0xa2 0x00 0x00 0xa2 0x01 0x00 0xa2 0x02 0x00 0xa2 0x03 0x00>;

vdd_lpi_mx-supply = <0xa0>;

compatible = "qcom,pil-tz-generic";

qcom,vdd_cx-uV-uA = <0x181 0x00>;

interrupt-names = "qcom,wdog\0qcom,err-fatal\0qcom,err-ready\0qcom,proxy-unvote\0qcom,stop-ack";

reg = <0x62400000 0x100>;

qcom,smem-states = <0xa3 0x00>;

mboxes = <0x1c 0x00>;

qcom,proxy-clock-names = "xo";

qcom,proxy-reg-names = "vdd_lpi_cx\0vdd_lpi_mx";

qcom,firmware-name = "adsp";

vdd_lpi_cx-supply = <0x9f>;

mbox-names = "adsp-pil";

};

qcom,gpucc {

#reset-cells = <0x01>;

qcom,gpu_cc_gmu_clk_src-opp-handle = <0x22>;

reg-names = "cc_base";

qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <0x21>;

#clock-cells = <0x01>;

vdd_mx-supply = <0x1f>;

compatible = "qcom,gpucc-sdmmagpie\0syscon";

reg = <0x5090000 0x9000>;

phandle = <0x2b>;

vdd_cx-supply = <0x1d>;

vdd_gfx-supply = <0x20>;

};

rpmh-regulator-lcxlvl {

compatible = "qcom,rpmh-arc-regulator";

qcom,resource-name = "lcx.lvl";

mboxes = <0x1b 0x00>;

regulator-pm6150-l8 {

regulator-max-microvolt = <0x10000>;

regulator-min-microvolt = <0x11>;

regulator-name = "pm6150_l8_level";

qcom,init-voltage-level = <0x11>;

qcom,set = <0x03>;

phandle = <0x9f>;

};

};

qcom,rpm-stats@c300000 {

reg-names = "phys_addr_base\0offset_addr";

qcom,num-records = <0x03>;

compatible = "qcom,rpm-stats";

reg = <0xc300000 0x1000 0xc3f0004 0x04>;

};

gpu-bw-tbl {

compatible = "operating-points-v2";

phandle = <0x2a3>;

opp-1017 {

opp-hz = <0x00 0xf27>;

};

opp-300 {

opp-hz = <0x00 0x478>;

};

opp-451 {

opp-hz = <0x00 0x6b8>;

};

opp-1353 {

opp-hz = <0x00 0x1429>;

};

opp-1804 {

opp-hz = <0x00 0x1ae1>;

};

opp-200 {

opp-hz = <0x00 0x2fa>;

};

opp-681 {

opp-hz = <0x00 0xa25>;

};

opp-1555 {

opp-hz = <0x00 0x172b>;

};

opp-547 {

opp-hz = <0x00 0x826>;

};

opp-100 {

opp-hz = <0x00 0x17d>;

};

opp-0 {

opp-hz = <0x00 0x00>;

};

opp-825 {

opp-hz = <0x00 0xc4b>;

};

};

qcom,dsi-display@10 {

qcom,dsi-phy-num = <0x00 0x01>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x52c>;

qcom,dsi-ctrl-num = <0x00 0x01>;

qcom,display-type = "primary";

label = "dsi_dual_sharp_wqhd_cmd_display";

phandle = <0x549>;

};

tmc@6047000 {

arm,primecell-periphid = <0x3b961>;

coresight-ctis = <0x1d5 0x1d5>;

clock-names = "apb_pclk";

reg-names = "tmc-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tmc-etf";

arm,default-sink;

compatible = "arm,primecell";

reg = <0x6047000 0x1000>;

phandle = <0x420>;

coresight-csr = <0x1d6>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1d8>;

phandle = <0x1d2>;

};

};

port@1 {

reg = <0x01>;

endpoint {

slave-mode;

remote-endpoint = <0x1d9>;

phandle = <0x1da>;

};

};

};

};

etm@7640000 {

arm,primecell-periphid = <0xbb95d>;

clock-names = "apb_pclk";

clocks = <0x19 0x00>;

cpu = <0x17>;

qcom,tupwr-disable;

coresight-name = "coresight-etm6";

compatible = "arm,primecell";

reg = <0x7640000 0x1000>;

phandle = <0x442>;

port {

endpoint {

remote-endpoint = <0x223>;

phandle = <0x21b>;

};

};

};

interrupt-controller@17a00000 {

#redistributor-regions = <0x01>;

interrupts = <0x01 0x09 0x04>;

interrupt-parent = <0x1a>;

redistributor-stride = <0x00 0x20000>;

compatible = "arm,gic-v3";

#interrupt-cells = <0x03>;

reg = <0x17a00000 0x10000 0x17a60000 0x100000>;

phandle = <0x1a>;

interrupt-controller;

};

usbpd_pm {

mi,pd-bus-curr-compensate = <0x64>;

mi,pd-ffc-bat-volt-max = <0x1176>;

mi,pd-bat-curr-max = <0x1770>;

mi,pd-bat-volt-max = <0x1162>;

compatible = "xiaomi,usbpd-pm";

status = "ok";

mi,pd-bus-curr-max = <0xbb8>;

mi,pd-bus-volt-max = <0x2ee0>;

};

cti@601b000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti11";

compatible = "arm,primecell";

reg = <0x601b000 0x1000>;

phandle = <0x480>;

};

cti@6a12000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-ddr_dl_1_cti2";

compatible = "arm,primecell";

reg = <0x6a12000 0x1000>;

phandle = <0x465>;

};

tpdm@684c000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-prng";

compatible = "arm,primecell";

reg = <0x684c000 0x1000>;

phandle = <0x458>;

port {

endpoint {

remote-endpoint = <0x253>;

phandle = <0x236>;

};

};

};

qcom,gdsc@17d03c {

qcom,no-status-check-on-disable;

qcom,gds-timeout = <0x1f4>;

regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x17d03c 0x04>;

phandle = <0x1cc>;

};

jtagmm@7740000 {

clock-names = "core_clk";

reg-names = "etm-base";

clocks = <0x19 0x00>;

compatible = "qcom,jtagv8-mm";

qcom,coresight-jtagmm-cpu = <0x18>;

reg = <0x7740000 0x1000>;

phandle = <0x2af>;

};

tpdm@6940000 {

arm,primecell-periphid = <0x3b968>;

vddcx-supply = <0x1c5>;

clock-names = "apb_pclk\0gpu_apb_clk";

reg-names = "tpdm-base";

clocks = <0x19 0x00 0x2b 0x08>;

coresight-name = "coresight-tpdm-gpu";

vdd-supply = <0x24e>;

compatible = "arm,primecell";

status = "disabled";

qcom,tpdm-regs = "vddcx\0vdd";

reg = <0x6940000 0x1000>;

regulator-names = "vddcx\0vdd";

phandle = <0x456>;

qcom,tpdm-clks = "gpu_apb_clk";

qcom,msr-fix-req;

port {

endpoint {

remote-endpoint = <0x251>;

phandle = <0x250>;

};

};

};

qcom,msm-dai-tdm-sec-tx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9011>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9111>;

phandle = <0x4bd>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-sec-tx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9011>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x289>;

};

};

rpmh-regulator-ldoa15 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa15";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l15 {

regulator-max-microvolt = <0x1d0d80>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x19e100>;

regulator-min-microvolt = <0x19e100>;

regulator-name = "pm6150_l15";

qcom,set = <0x03>;

phandle = <0x40a>;

};

};

qcom,msm-pcm-loopback-low-latency {

qcom,msm-pcm-loopback-low-latency;

compatible = "qcom,msm-pcm-loopback";

phandle = <0x48f>;

};

spi@0x88c000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x17c>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

interrupts = <0x00 0x25c 0x00>;

clocks = <0x27 0x4a 0x27 0x67 0x27 0x68>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x168>;

spi-max-frequency = <0x2faf080>;

dma-names = "tx\0rx";

compatible = "qcom,spi-geni";

pinctrl-1 = <0x17d>;

status = "disabled";

reg = <0x88c000 0x4000>;

phandle = <0x356>;

dmas = <0x165 0x00 0x03 0x01 0x40 0x00 0x165 0x01 0x03 0x01 0x40 0x00>;

};

qcom,ipe1 {

clock-control-debugfs = "true";

clock-names = "ipe_1_ahb_clk\0ipe_1_areg_clk\0ipe_1_axi_clk\0ipe_1_clk_src\0ipe_1_clk";

reg-names = "ipe1_top";

reg-cam-base = <0x91000>;

cell-index = <0x01>;

clocks = <0x29 0x48 0x29 0x49 0x29 0x4a 0x29 0x47 0x29 0x4b>;

ipe1-vdd-supply = <0x1ba>;

clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo";

compatible = "qcom,cam-ipe";

src-clock-name = "ipe_1_clk_src";

status = "ok";

reg = <0xac91000 0x3000>;

regulator-names = "ipe1-vdd";

phandle = <0x395>;

qcom,cam-cx-ipeak = <0x1a3 0x03>;

clock-rates = <0x00 0x00 0x00 0x1443fd00 0x00 0x00 0x00 0x00 0x19a14780 0x00 0x00 0x00 0x00 0x1efe9200 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600 0x00>;

};

qcom,csiphy@ace6000 {

clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk";

reg-names = "csiphy";

reg-cam-base = <0xe6000>;

csi-vdd-voltage = <0x124f80>;

cell-index = <0x03>;

interrupts = <0x00 0x25f 0x00>;

clocks = <0x29 0x1b 0x29 0x24 0x29 0x27 0x29 0x23 0x29 0x22>;

gdscr-supply = <0x1ae>;

clock-cntl-level = "svs\0svs_l1\0turbo";

compatible = "qcom,csiphy-v1.2\0qcom,csiphy";

src-clock-name = "csi3phytimer_clk_src";

mipi-csi-vdd-supply = <0x1a8>;

status = "ok";

interrupt-names = "csiphy";

reg = <0xace6000 0x2000>;

regulator-names = "gdscr\0refgen";

phandle = <0x37b>;

refgen-supply = <0x1af>;

clock-rates = <0x16e36000 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00>;

};

rpmh-regulator-smpa5 {

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "smpa5";

mboxes = <0x1b 0x00>;

regulator-pm6150-s5 {

regulator-max-microvolt = <0x1f20c0>;

qcom,init-voltage = <0x1a9c80>;

regulator-min-microvolt = <0x1a9c80>;

regulator-name = "pm6150_s5";

qcom,set = <0x03>;

phandle = <0x3fe>;

};

};

qcom,cci@ac4a000 {

pinctrl-names = "cam_default\0cam_suspend";

#address-cells = <0x01>;

pinctrl-0 = <0x1b0 0x1b1>;

clock-names = "cci_0_clk\0cci_0_clk_src";

reg-names = "cci";

reg-cam-base = <0x4a000>;

cell-index = <0x00>;

gpio-req-tbl-num = <0x00 0x01 0x02 0x03>;

interrupts = <0x00 0x1cc 0x00>;

clocks = <0x29 0x15 0x29 0x16>;

gdscr-supply = <0x1ae>;

#size-cells = <0x00>;

gpio-req-tbl-label = "CCI_I2C_DATA0\0CCI_I2C_CLK0\0CCI_I2C_DATA1\0CCI_I2C_CLK1";

clock-cntl-level = "lowsvs";

compatible = "qcom,cci";

src-clock-name = "cci_0_clk_src";

pinctrl-1 = <0x1b2 0x1b3>;

status = "ok";

interrupt-names = "cci";

reg = <0xac4a000 0x1000>;

regulator-names = "gdscr";

phandle = <0x37c>;

clock-rates = <0x00 0x23c3460>;

gpio-req-tbl-flags = <0x01 0x01 0x01 0x01>;

gpios = <0x174 0x11 0x00 0x174 0x12 0x00 0x174 0x13 0x00 0x174 0x14 0x00>;

qcom,eeprom@2 {

rgltr-max-voltage = <0x1b7740>;

cell-index = <0x02>;

cci-device = <0x00>;

rgltr-load-current = <0x2bf20>;

cam_vio-supply = <0x562>;

rgltr-cntrl-support;

cci-master = <0x01>;

compatible = "qcom,eeprom";

rgltr-min-voltage = <0x1b7740>;

status = "ok";

reg = <0x02>;

regulator-names = "cam_vio";

phandle = <0x56a>;

};

qcom,i2c_custom_mode {

hw-tsu-sto = <0x28>;

cci-clk-src = <0x23c3460>;

hw-tsp = <0x03>;

hw-trdhld = <0x06>;

hw-thigh = <0x26>;

hw-tlow = <0x38>;

status = "ok";

hw-thd-dat = <0x16>;

hw-tsu-sta = <0x28>;

hw-scl-stretch-en = <0x01>;

phandle = <0x37f>;

hw-tbuf = <0x3e>;

hw-thd-sta = <0x23>;

};

qcom,cam-sensor@3 {

rgltr-max-voltage = <0x1b7740 0x2ab980 0x00>;

pinctrl-names = "cam_default\0cam_suspend";

eeprom-src = <0x571>;

pinctrl-0 = <0x573 0x574 0x575>;

clock-names = "cam_clk";

cell-index = <0x03>;

gpio-req-tbl-num = <0x00 0x01 0x02>;

sensor-position-yaw = <0xb4>;

cci-device = <0x00>;

clocks = <0x29 0x56>;

rgltr-load-current = <0x2bf20 0x1d4c0 0x00>;

actuator-src = <0x572>;

cam_vio-supply = <0x562>;

rgltr-cntrl-support;

cam_vana-supply = <0x56b>;

gpio-req-tbl-label = "CAMIF_MCLK1\0CAMM_RESET\0CAMD_CUSTOM1";

gpio-reset = <0x01>;

csiphy-sd-index = <0x03>;

clock-cntl-level = "turbo";

gpio-custom1 = <0x02>;

cci-master = <0x01>;

gpio-no-mux = <0x00>;

compatible = "qcom,cam-sensor";

rgltr-min-voltage = <0x1b7740 0x2ab980 0x00>;

led-flash-src = <0x570>;

sensor-position-roll = <0x5a>;

pinctrl-1 = <0x576 0x577 0x578>;

status = "ok";

reg = <0x03>;

regulator-names = "cam_vio\0cam_vana\0cam_clk";

sensor-position-pitch = <0x00>;

cam_clk-supply = <0x1ae>;

clock-rates = <0x124f800>;

gpio-req-tbl-flags = <0x01 0x00 0x00>;

gpios = <0x174 0x10 0x00 0x174 0x18 0x00 0x174 0x58 0x00>;

};

qcom,eeprom@0 {

cam_v_custom1-supply = <0x406>;

rgltr-max-voltage = <0x1b7740 0x10c8e0 0x10c8e0 0x00>;

pinctrl-names = "cam_default\0cam_suspend";

pinctrl-0 = <0x563 0x564>;

clock-names = "cam_clk";

cell-index = <0x00>;

gpio-req-tbl-num = <0x00 0x01>;

cci-device = <0x00>;

clocks = <0x29 0x54>;

rgltr-load-current = <0x2bf20 0x1d4c0 0x1d4c0 0x00>;

cam_vio-supply = <0x562>;

rgltr-cntrl-support;

gpio-req-tbl-label = "CAMIF_MCLK0\0CAMW_RESET";

gpio-reset = <0x01>;

csiphy-sd-index = <0x00>;

clock-cntl-level = "turbo";

cam_vdig-supply = <0x406>;

sensor-mode = <0x00>;

cci-master = <0x00>;

gpio-no-mux = <0x00>;

compatible = "qcom,eeprom";

rgltr-min-voltage = <0x1b7740 0x10c8e0 0x10c8e0 0x00>;

pinctrl-1 = <0x565 0x566>;

status = "ok";

reg = <0x00>;

regulator-names = "cam_vio\0cam_vdig\0cam_v_custom1\0cam_clk";

phandle = <0x569>;

cam_clk-supply = <0x1ae>;

clock-rates = <0x124f800>;

gpio-req-tbl-flags = <0x01 0x00>;

gpios = <0x174 0x0f 0x00 0x174 0x1a 0x00>;

};

qcom,i2c_standard_mode {

hw-tsu-sto = <0xcc>;

cci-clk-src = <0x23c3460>;

hw-tsp = <0x03>;

hw-trdhld = <0x06>;

hw-thigh = <0xc9>;

hw-tlow = <0xae>;

status = "ok";

hw-thd-dat = <0x16>;

hw-tsu-sta = <0xe7>;

hw-scl-stretch-en = <0x00>;

phandle = <0x37d>;

hw-tbuf = <0xe3>;

hw-thd-sta = <0xa2>;

};

qcom,actuator@0 {

rgltr-max-voltage = <0x2ab980>;

cell-index = <0x00>;

cci-device = <0x00>;

rgltr-load-current = <0x35b60>;

rgltr-cntrl-support;

cam_vaf-supply = <0x40b>;

cci-master = <0x00>;

compatible = "qcom,actuator";

rgltr-min-voltage = <0x2ab980>;

reg = <0x00>;

regulator-names = "cam_vaf";

phandle = <0x568>;

};

qcom,cam-res-mgr {

compatible = "qcom,cam-res-mgr";

status = "ok";

};

qcom,eeprom@3 {

rgltr-max-voltage = <0x1b7740>;

cell-index = <0x03>;

cci-device = <0x00>;

rgltr-load-current = <0x2bf20>;

cam_vio-supply = <0x562>;

rgltr-cntrl-support;

cci-master = <0x01>;

compatible = "qcom,eeprom";

rgltr-min-voltage = <0x1b7740>;

status = "ok";

reg = <0x03>;

regulator-names = "cam_vio";

phandle = <0x571>;

};

qcom,cam-sensor@2 {

rgltr-max-voltage = <0x1b7740 0x2ab980 0x00>;

pinctrl-names = "cam_default\0cam_suspend";

eeprom-src = <0x56a>;

pinctrl-0 = <0x56c 0x56d>;

clock-names = "cam_clk";

cell-index = <0x02>;

gpio-req-tbl-num = <0x00 0x01>;

sensor-position-yaw = <0x00>;

cci-device = <0x00>;

clocks = <0x29 0x50>;

rgltr-load-current = <0x2bf20 0x1d4c0 0x00>;

cam_vio-supply = <0x562>;

rgltr-cntrl-support;

cam_vana-supply = <0x56b>;

gpio-req-tbl-label = "CAMIF_MCLK0\0CAMF_RESET";

gpio-reset = <0x01>;

csiphy-sd-index = <0x01>;

clock-cntl-level = "turbo";

sensor-mode = <0x00>;

cci-master = <0x01>;

gpio-no-mux = <0x00>;

compatible = "qcom,cam-sensor";

rgltr-min-voltage = <0x1b7740 0x2ab980 0x00>;

sensor-position-roll = <0x10e>;

pinctrl-1 = <0x56e 0x56f>;

status = "ok";

reg = <0x02>;

regulator-names = "cam_vio\0cam_vana\0cam_clk";

sensor-position-pitch = <0x00>;

cam_clk-supply = <0x1ae>;

clock-rates = <0x124f800>;

gpio-req-tbl-flags = <0x01 0x00>;

gpios = <0x174 0x0d 0x00 0x174 0x17 0x00>;

};

qcom,i2c_fast_plus_mode {

hw-tsu-sto = <0x11>;

cci-clk-src = <0x23c3460>;

hw-tsp = <0x03>;

hw-trdhld = <0x03>;

hw-thigh = <0x12>;

hw-tlow = <0x14>;

status = "ok";

hw-thd-dat = <0x0e>;

hw-tsu-sta = <0x12>;

hw-scl-stretch-en = <0x00>;

phandle = <0x5b0>;

hw-tbuf = <0x18>;

hw-thd-sta = <0x0f>;

};

qcom,cam-sensor@0 {

cam_v_custom1-supply = <0x406>;

rgltr-max-voltage = <0x1b7740 0x100590 0x10c8e0 0x00>;

pinctrl-names = "cam_default\0cam_suspend";

eeprom-src = <0x569>;

pinctrl-0 = <0x563 0x564>;

clock-names = "cam_clk";

cell-index = <0x00>;

gpio-req-tbl-num = <0x00 0x01>;

sensor-position-yaw = <0xb4>;

cci-device = <0x00>;

clocks = <0x29 0x54>;

rgltr-load-current = <0x2bf20 0x1d4c0 0x1d4c0 0x00>;

actuator-src = <0x568>;

cam_vio-supply = <0x562>;

rgltr-cntrl-support;

gpio-req-tbl-label = "CAMIF_MCLK0\0CAMW_RESET";

gpio-reset = <0x01>;

csiphy-sd-index = <0x00>;

clock-cntl-level = "turbo";

cam_vdig-supply = <0x406>;

sensor-mode = <0x00>;

cci-master = <0x00>;

gpio-no-mux = <0x00>;

compatible = "qcom,cam-sensor";

rgltr-min-voltage = <0x1b7740 0x100590 0x10c8e0 0x00>;

led-flash-src = <0x567>;

sensor-position-roll = <0x5a>;

pinctrl-1 = <0x565 0x566>;

status = "ok";

reg = <0x00>;

regulator-names = "cam_vio\0cam_vdig\0cam_v_custom1\0cam_clk";

sensor-position-pitch = <0x00>;

cam_clk-supply = <0x1ae>;

clock-rates = <0x124f800>;

gpio-req-tbl-flags = <0x01 0x00>;

gpios = <0x174 0x0f 0x00 0x174 0x1a 0x00>;

};

qcom,actuator@1 {

rgltr-max-voltage = <0x2ab980>;

cell-index = <0x01>;

cci-device = <0x00>;

rgltr-load-current = <0x35b60>;

rgltr-cntrl-support;

cam_vaf-supply = <0x40b>;

cci-master = <0x01>;

compatible = "qcom,actuator";

rgltr-min-voltage = <0x2ab980>;

reg = <0x01>;

regulator-names = "cam_vaf";

phandle = <0x572>;

};

qcom,i2c_fast_mode {

hw-tsu-sto = <0x28>;

cci-clk-src = <0x23c3460>;

hw-tsp = <0x03>;

hw-trdhld = <0x06>;

hw-thigh = <0x26>;

hw-tlow = <0x38>;

status = "ok";

hw-thd-dat = <0x16>;

hw-tsu-sta = <0x28>;

hw-scl-stretch-en = <0x00>;

phandle = <0x37e>;

hw-tbuf = <0x3e>;

hw-thd-sta = <0x23>;

};

};

qcom,cam-cdm-intf {

cdm-client-names = "vfe\0jpegdma\0jpegenc\0fd\0lrmecdm";

num-hw-cdm = <0x01>;

cell-index = <0x00>;

label = "cam-cdm-intf";

compatible = "qcom,cam-cdm-intf";

status = "ok";

};

qcom,rpmh-master-stats@b221200 {

compatible = "qcom,rpmh-master-stats-v1";

reg = <0xb221200 0x60>;

};

qcom,cpucc@18321000 {

#address-cells = <0x01>;

reg-names = "osm_l3_base\0osm_pwrcl_base\0osm_perfcl_base";

#size-cells = <0x01>;

#clock-cells = <0x01>;

compatible = "qcom,clk-cpu-osm-sdmmagpie";

reg = <0x18321000 0x1400 0x18323000 0x1400 0x18325800 0x1400>;

phandle = <0xc0>;

l3-devs = <0x24 0x25 0x26>;

qcom,limits-dcvs@18350800 {

qcom,affinity = <0x01>;

interrupts = <0x00 0x21 0x04>;

#thermal-sensor-cells = <0x00>;

compatible = "qcom,msm-hw-limits";

reg = <0x18350800 0x1000 0x18325800 0x1000>;

phandle = <0x0f>;

};

qcom,limits-dcvs@18358800 {

qcom,affinity = <0x00>;

interrupts = <0x00 0x20 0x04>;

#thermal-sensor-cells = <0x00>;

compatible = "qcom,msm-hw-limits";

reg = <0x18358800 0x1000 0x18323000 0x1000>;

phandle = <0x05>;

};

};

qcom,gmu@506a000 {

vddcx-supply = <0x1c5>;

clock-names = "gmu_clk\0cxo_clk\0axi_clk\0memnoc_clk";

reg-names = "kgsl_gmu_reg\0kgsl_gmu_pdc_cfg\0kgsl_gmu_pdc_seq";

qcom,msm-bus,name = "cnoc";

interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>;

clocks = <0x2b 0x0b 0x2b 0x0e 0x27 0x1b 0x27 0x2b>;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

label = "kgsl-gmu";

vdd-supply = <0x24e>;

compatible = "qcom,gpu-gmu";

interrupt-names = "kgsl_hfi_irq\0kgsl_gmu_irq";

reg = <0x506a000 0x31000 0xb290000 0x10000 0xb490000 0x10000>;

regulator-names = "vddcx\0vdd";

phandle = <0x22>;

qcom,msm-bus,vectors-KBps = <0x1a 0x2734 0x00 0x00 0x1a 0x2734 0x00 0x64>;

qcom,gmu-pwrlevels {

#address-cells = <0x01>;

#size-cells = <0x00>;

compatible = "qcom,gmu-pwrlevels";

qcom,gmu-pwrlevel@0 {

reg = <0x00>;

qcom,gmu-freq = <0x00>;

};

qcom,gmu-pwrlevel@1 {

reg = <0x01>;

qcom,gmu-freq = <0xbebc200>;

};

};

gmu_kernel {

iommus = <0x1cd 0x05>;

compatible = "qcom,smmu-gmu-kernel-cb";

phandle = <0x4d4>;

};

gmu_user {

iommus = <0x1cd 0x04>;

compatible = "qcom,smmu-gmu-user-cb";

phandle = <0x4d3>;

};

};

qcom,mdss_dsi_ctrl1@ae96000 {

clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk";

reg-names = "dsi_ctrl\0disp_cc_base";

cell-index = <0x01>;

interrupts = <0x05 0x00>;

clocks = <0x2a 0x07 0x2a 0x08 0x2a 0x0a 0x2a 0x20 0x2a 0x21 0x2a 0x18>;

interrupt-parent = <0x1a6>;

label = "dsi-ctrl-1";

vdda-1p2-supply = <0x1a8>;

compatible = "qcom,dsi-ctrl-hw-v2.3";

reg = <0xae96000 0x400 0xaf08000 0x04>;

phandle = <0x373>;

qcom,ctrl-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,ctrl-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x5528>;

qcom,supply-name = "vdda-1p2";

qcom,supply-max-voltage = <0x12cc80>;

reg = <0x00>;

qcom,supply-min-voltage = <0x1174c0>;

};

};

qcom,core-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,core-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x00>;

qcom,supply-name = "refgen";

qcom,supply-max-voltage = <0x00>;

reg = <0x00>;

qcom,supply-min-voltage = <0x00>;

};

};

};

hwevent@0x014066f0 {

clock-names = "apb_pclk";

reg-names = "ddr-ch0-cfg\0ddr-ch23-cfg\0ddr-ch0-ctrl\0ddr-ch23-ctrl";

clocks = <0x19 0x00>;

coresight-name = "coresight-hwevent";

compatible = "qcom,coresight-hwevent";

reg = <0x14066f0 0x04 0x14166f0 0x04 0x1406038 0x04 0x1416038 0x04>;

phandle = <0x45d>;

coresight-csr = <0x1d6>;

};

qcom,dsi-display@29 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x53d>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_g7b_37_02_0b_video_display";

phandle = <0x555>;

};

qcom,cpu6-cpu-llcc-lat {

qcom,src-dst-ports = <0x01 0x302>;

governor = "performance";

compatible = "qcom,devbw";

phandle = <0xc2>;

qcom,active-only;

operating-points-v2 = <0xbc>;

};

qcom,cam_smmu {

compatible = "qcom,msm-cam-smmu";

status = "ok";

phandle = <0x386>;

msm_cam_smmu_ife {

iommus = <0x30 0x900 0x460 0x30 0xd00 0x460 0x30 0x880 0x460 0x30 0xc80 0x460 0x30 0x820 0x440 0x30 0xc20 0x440 0x30 0x920 0x460 0x30 0xd20 0x460 0x30 0x8a0 0x460 0x30 0xca0 0x460 0x30 0x940 0x460 0x30 0xd40 0x460 0x30 0x8c0 0x460 0x30 0xcc0 0x460>;

label = "ife";

compatible = "qcom,msm-cam-smmu-cb";

iova-mem-map {

phandle = <0x387>;

iova-mem-region-io {

iova-region-len = <0xd8c00000>;

iova-region-name = "io";

status = "ok";

iova-region-id = <0x03>;

iova-region-start = <0x7400000>;

};

};

};

msm_cam_smmu_lrme {

iommus = <0x30 0x11c0 0x00 0x30 0x1240 0x00>;

label = "lrme";

compatible = "qcom,msm-cam-smmu-cb";

iova-mem-map {

phandle = <0x38c>;

iova-mem-region-io {

iova-region-len = <0xd2800000>;

iova-region-name = "io";

status = "ok";

iova-region-id = <0x03>;

iova-region-start = <0xd800000>;

};

iova-mem-region-shared {

iova-region-len = <0x6400000>;

iova-region-name = "shared";

status = "ok";

iova-region-id = <0x01>;

iova-region-start = <0x7400000>;

};

};

};

msm_cam_smmu_cpas_cdm {

iommus = <0x30 0x1000 0x00>;

label = "cpas-cdm0";

compatible = "qcom,msm-cam-smmu-cb";

iova-mem-map {

phandle = <0x38a>;

iova-mem-region-io {

iova-region-len = <0xd8c00000>;

iova-region-name = "io";

status = "ok";

iova-region-id = <0x03>;

iova-region-start = <0x7400000>;

};

};

};

msm_cam_smmu_fd {

iommus = <0x30 0x12c0 0x20 0x30 0x12e0 0x20>;

label = "fd";

compatible = "qcom,msm-cam-smmu-cb";

iova-mem-map {

phandle = <0x38b>;

iova-mem-region-io {

iova-region-len = <0xd8c00000>;

iova-region-name = "io";

status = "ok";

iova-region-id = <0x03>;

iova-region-start = <0x7400000>;

};

};

};

msm_cam_smmu_icp {

iommus = <0x30 0x1180 0x00 0x30 0x11e0 0x00 0x30 0x11a0 0x00 0x30 0x1200 0x00 0x30 0x1260 0x00 0x30 0x1220 0x00 0x30 0x1042 0x00 0x30 0x1300 0x60 0x30 0x1320 0x60>;

label = "icp";

compatible = "qcom,msm-cam-smmu-cb";

iova-mem-map {

phandle = <0x389>;

iova-mem-qdss-region {

iova-region-len = <0x100000>;

qdss-phy-addr = <0x16790000>;

iova-region-name = "qdss";

status = "ok";

iova-region-id = <0x05>;

iova-region-start = <0x10b00000>;

};

iova-mem-region-secondary-heap {

iova-region-len = <0x100000>;

iova-region-name = "secheap";

status = "ok";

iova-region-id = <0x04>;

iova-region-start = <0x10a00000>;

};

iova-mem-region-firmware {

iova-region-len = <0x500000>;

iova-region-name = "firmware";

status = "ok";

iova-region-id = <0x00>;

iova-region-start = <0x00>;

};

iova-mem-region-io {

iova-region-len = <0xa9c00000>;

iova-region-name = "io";

status = "ok";

iova-region-id = <0x03>;

iova-region-start = <0x10c00000>;

};

iova-mem-region-shared {

iova-region-len = <0x9600000>;

iova-region-name = "shared";

status = "ok";

iova-region-id = <0x01>;

iova-region-start = <0x7400000>;

};

};

};

msm_cam_smmu_jpeg {

iommus = <0x30 0x1280 0x20 0x30 0x12a0 0x20>;

label = "jpeg";

compatible = "qcom,msm-cam-smmu-cb";

iova-mem-map {

phandle = <0x388>;

iova-mem-region-io {

iova-region-len = <0xd8c00000>;

iova-region-name = "io";

status = "ok";

iova-region-id = <0x03>;

iova-region-start = <0x7400000>;

};

};

};

msm_cam_smmu_secure {

qcom,secure-cb;

label = "cam-secure";

compatible = "qcom,msm-cam-smmu-cb";

};

msm_cam_icp_fw {

memory-region = <0x1b6>;

label = "icp";

compatible = "qcom,msm-cam-smmu-fw-dev";

};

};

syscon@0x5091008 {

compatible = "syscon";

reg = <0x5091008 0x04>;

phandle = <0xce>;

};

qcom,smp2p_interrupt_rdbg_5_out {

qcom,smem-state-names = "rdbg-smp2p-out";

compatible = "qcom,smp2p-interrupt-rdbg-5-out";

qcom,smem-states = <0x1be 0x00>;

};

funnel@0x6041000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-in0";

compatible = "arm,primecell";

reg = <0x6041000 0x1000>;

phandle = <0x422>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1de>;

phandle = <0x1db>;

};

};

port@3 {

reg = <0x06>;

endpoint {

slave-mode;

remote-endpoint = <0x1e1>;

phandle = <0x226>;

};

};

port@1 {

reg = <0x04>;

endpoint {

slave-mode;

remote-endpoint = <0x1df>;

phandle = <0x22c>;

};

};

port@4 {

reg = <0x07>;

endpoint {

slave-mode;

remote-endpoint = <0x1e2>;

phandle = <0x225>;

};

};

port@2 {

reg = <0x04>;

endpoint {

slave-mode;

remote-endpoint = <0x1e0>;

phandle = <0x1e3>;

};

};

};

};

qcom,gdsc@16b004 {

qcom,poll-cfg-gdscr;

regulator-name = "pcie_0_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x16b004 0x04>;

phandle = <0x321>;

};

qcom,dsi-display@7 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x529>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_sim_dsc_375_cmd_display";

phandle = <0x546>;

};

sdcc1ice@7C8000 {

clock-names = "ice_core_clk_src\0ice_core_clk\0bus_clk\0iface_clk";

qcom,bus-vector-names = "MIN\0MAX";

qcom,msm-bus,name = "sdcc_ice_noc";

qcom,instance-type = "sdcc";

clocks = <0x27 0x6f 0x27 0x6e 0x27 0x6b 0x27 0x6c>;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,op-freq-hz = <0x11e1a300 0x00 0x00 0x00>;

compatible = "qcom,ice";

reg = <0x7c8000 0x8000>;

phandle = <0x2d7>;

qcom,msm-bus,vectors-KBps = <0x01 0x2f5 0x00 0x00 0x01 0x2f5 0x3e8 0x00>;

qcom,enable-ice-clk;

};

cx_ipeak@01fed000 {

compatible = "qcom,cx-ipeak-v2";

reg = <0x1fed000 0x8008>;

phandle = <0x1a3>;

};

qcom,csiphy@ace0000 {

clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk";

reg-names = "csiphy";

reg-cam-base = <0xe0000>;

csi-vdd-voltage = <0x124f80>;

cell-index = <0x00>;

interrupts = <0x00 0x1dd 0x00>;

clocks = <0x29 0x1b 0x29 0x24 0x29 0x1d 0x29 0x1c>;

gdscr-supply = <0x1ae>;

clock-cntl-level = "svs\0svs_l1\0turbo";

compatible = "qcom,csiphy-v1.2\0qcom,csiphy";

src-clock-name = "csi0phytimer_clk_src";

mipi-csi-vdd-supply = <0x1a8>;

status = "ok";

interrupt-names = "csiphy";

reg = <0xace0000 0x2000>;

regulator-names = "gdscr\0refgen";

phandle = <0x378>;

refgen-supply = <0x1af>;

clock-rates = <0x16e36000 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x11e1a300 0x00>;

};

qcom,dsi-display@19 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x531>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_rm69299_visionox_amoled_vid_display";

phandle = <0x54f>;

};

qcom,gdsc@ab008b4 {

clock-names = "ahb_clk";

qcom,support-hw-trigger;

clocks = <0x27 0x9b>;

regulator-name = "mvs1_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0xab008b4 0x04>;

phandle = <0x1a2>;

};

tpdm@6b03000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-swao-1";

compatible = "arm,primecell";

reg = <0x6b03000 0x1000>;

phandle = <0x430>;

qcom,msr-fix-req;

port {

endpoint {

remote-endpoint = <0x1ff>;

phandle = <0x1fd>;

};

};

};

qcom,msm-dai-tdm-sec-rx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9010>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9110>;

phandle = <0x4bc>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-sec-rx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9010>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x288>;

};

};

qcom,qupv3_0_geni_se@0x8c0000 {

qcom,iommu-s1-bypass;

qcom,bus-mas-id = <0x97>;

qcom,bus-slv-id = <0x200>;

compatible = "qcom,qupv3-geni-se";

reg = <0x8c0000 0x2000>;

phandle = <0x168>;

qcom,iommu_qupv3_0_geni_se_cb {

iommus = <0x30 0x203 0x00>;

compatible = "qcom,qupv3-geni-se-cb";

phandle = <0x34c>;

};

};

rpmh-regulator-ldoc8 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoc8";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150l-l8 {

regulator-max-microvolt = <0x1cfde0>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x1b7740>;

regulator-min-microvolt = <0x1b7740>;

regulator-name = "pm6150l_l8";

qcom,set = <0x03>;

phandle = <0x412>;

};

};

qcom,cc-debug {

qcom,gpucc = <0x2b>;

clock-names = "xo_clk_src";

clocks = <0x2f 0x00>;

#clock-cells = <0x01>;

qcom,cc-count = <0x08>;

qcom,gcc = <0x27>;

qcom,dispcc = <0x2a>;

compatible = "qcom,debugcc-sdmmagpie";

qcom,mccc = <0x2e>;

phandle = <0x2b2>;

qcom,videocc = <0x28>;

qcom,npucc = <0x2c>;

qcom,cpucc = <0x2d>;

qcom,camcc = <0x29>;

};

qcom,gdsc@509106c {

hw-ctrl-addr = <0xcc>;

qcom,no-status-check-on-disable;

qcom,gds-timeout = <0x1f4>;

parent-supply = <0x1d>;

qcom,clk-dis-wait-val = <0x08>;

regulator-name = "gpu_cx_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x509106c 0x04>;

phandle = <0x1c5>;

};

qcom,icnss@18800000 {

iommus = <0x30 0x240 0x01>;

qcom,smmu-s1-bypass;

vdd-1.8-xo-supply = <0x34>;

qcom,wlan-msa-memory = <0x100000>;

reg-names = "membase\0smmu_iova_base\0smmu_iova_ipa";

qcom,vdd-cx-mx-config = <0x9c400 0x9c400>;

interrupts = <0x00 0x19e 0x00 0x00 0x19f 0x00 0x00 0x1a0 0x00 0x00 0x1a1 0x00 0x00 0x1a2 0x00 0x00 0x1a3 0x00 0x00 0x1a4 0x00 0x00 0x1a5 0x00 0x00 0x1a6 0x00 0x00 0x1a7 0x00 0x00 0x1a8 0x00 0x00 0x1a9 0x00>;

vdd-3.3-ch0-supply = <0x33>;

compatible = "qcom,icnss";

qcom,wlan-msa-fixed-region = <0xb7>;

reg = <0x18800000 0x800000 0xa0000000 0x10000000 0xb0000000 0x10000>;

phandle = <0x30e>;

vdd-1.3-rfa-supply = <0x32>;

vdd-cx-mx-supply = <0xb8>;

qcom,smp2p_map_wlan_1_in {

interrupts-extended = <0xb9 0x00 0x00 0xb9 0x01 0x00>;

interrupt-names = "qcom,smp2p-force-fatal-error\0qcom,smp2p-early-crash-ind";

};

};

ipa_smmu_uc {

iommus = <0x30 0x522 0x00>;

qcom,smmu-s1-bypass;

qcom,iova-mapping = <0x40400000 0x1fc00000>;

compatible = "qcom,ipa-smmu-uc-cb";

phandle = <0x31e>;

};

qcom,chd_gold {

qcom,config-arr = <0x18060060 0x18070060>;

label = "gold";

qcom,threshold-arr = <0x18060058 0x18070058>;

compatible = "qcom,core-hang-detect";

};

i2c@0xa84000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x186>;

clock-names = "se-clk\0m-ahb\0s-ahb";

interrupts = <0x00 0x162 0x00>;

clocks = <0x27 0x59 0x27 0x69 0x27 0x6a>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x182>;

dma-names = "tx\0rx";

compatible = "qcom,i2c-geni";

pinctrl-1 = <0x187>;

status = "ok";

reg = <0xa84000 0x4000>;

phandle = <0x35b>;

dmas = <0x183 0x00 0x01 0x03 0x40 0x00 0x183 0x01 0x01 0x03 0x40 0x00>;

gt9896@5d {

pinctrl-names = "pmx_ts_active\0pmx_ts_suspend";

goodix,power-off-delay-us = <0x1388>;

goodix,input-max-y = <0x95f>;

goodix,vdd-gpio = <0x174 0x5a 0x00>;

goodix,reset-gpio = <0x174 0x08 0x00>;

pinctrl-0 = <0x58f>;

tpd-filter-custom-speed = <0x00 0x00 0x00>;

goodix,firmware-version = "6885b1";

tpd-filter-custom-prameters = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;

goodix,panel-max-x = <0x437>;

interrupts = <0x09 0x00>;

goodix,touch-game-param-config3 = <0x04 0x04 0x03 0x01>;

interrupt-parent = <0x174>;

goodix,touch-game-param-config1 = <0x03 0x03 0x01 0x03>;

vtouch-supply = <0x414>;

goodix,avdd-name = "vtouch";

compatible = "goodix,gt9896";

tpd-filter-enable = <0x01>;

pinctrl-1 = <0x590 0x591>;

status = "ok";

goodix,panel-max-p = <0x100>;

goodix,irq-flags = <0x02>;

goodix,input-max-x = <0x437>;

goodix,power-on-delay-us = <0x64>;

goodix,panel-max-y = <0x95f>;

reg = <0x5d>;

goodix,panel-max-id = <0x0a>;

tpd-filter-pixel-density = <0xa1>;

goodix,panel-max-w = <0x100>;

goodix,touch-game-param-config2 = <0x02 0x04 0x02 0x03>;

goodix,config-version = "6885v9c";

goodix,irq-gpio = <0x174 0x09 0x00>;

sensor0 {

normal-cfg;

};

};

};

rpmh-regulator-smpf1 {

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "smpf1";

mboxes = <0x1b 0x00>;

regulator-pm8009-s1 {

regulator-max-microvolt = <0x14c080>;

qcom,init-voltage = <0x103c40>;

regulator-min-microvolt = <0x103c40>;

regulator-name = "pm8009_s1";

qcom,set = <0x03>;

phandle = <0x400>;

};

};

qcom,cpu6-cpu-llcc-latmon {

qcom,cachemiss-ev = <0x2a>;

qcom,core-dev-table = <0xc4c70 0x11e1 0x10b170 0x1bc6 0x1433e0 0x23c3 0x1a1300 0x300a 0x253500 0x379c>;

qcom,cpulist = <0x17 0x18>;

compatible = "qcom,arm-memlat-mon";

phandle = <0x316>;

qcom,target-dev = <0xc2>;

};

rpmh-regulator-ldof6 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldof6";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm8009-l6 {

regulator-max-microvolt = <0x2c4fc0>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x292340>;

regulator-min-microvolt = <0x292340>;

regulator-name = "pm8009_l6";

qcom,set = <0x03>;

phandle = <0x41b>;

};

};

qcom,dispcc@af00000 {

#reset-cells = <0x01>;

reg-names = "cc_base";

#clock-cells = <0x01>;

compatible = "qcom,dispcc-sdmmagpie\0syscon";

reg = <0xaf00000 0x20000>;

phandle = <0x2a>;

vdd_cx-supply = <0x1d>;

};

qcom,qup_uart@0x890000 {

pinctrl-names = "default\0sleep";

pinctrl-0 = <0x175 0x176 0x177>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

clocks = <0x27 0x4c 0x27 0x67 0x27 0x68>;

qcom,wrapper-core = <0x168>;

interrupts-extended = <0x01 0x00 0x25d 0x00 0x174 0x38 0x00>;

compatible = "qcom,msm-geni-serial-hs";

pinctrl-1 = <0x175 0x176 0x177>;

status = "disabled";

reg = <0x890000 0x4000>;

phandle = <0x353>;

qcom,wakeup-byte = <0xfd>;

};

qcom,venus@aae0000 {

qcom,ahb-freq = <0xbebc200>;

clock-names = "xo\0core\0ahb";

qcom,msm-bus,name = "pil-venus";

qcom,proxy-timeout-ms = <0x64>;

memory-region = <0xb5>;

clocks = <0x28 0x0a 0x28 0x07 0x28 0x01>;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,core-freq = <0xbebc200>;

qcom,pas-id = <0x09>;

vdd-supply = <0xb4>;

compatible = "qcom,pil-tz-generic";

reg = <0xaae0000 0x4000>;

qcom,msm-bus,vectors-KBps = <0x3f 0x200 0x00 0x00 0x3f 0x200 0x00 0x4a380>;

qcom,proxy-clock-names = "xo\0core\0ahb";

qcom,proxy-reg-names = "vdd";

qcom,firmware-name = "venus";

};

qcom,vidc1 {

qcom,allowed-clock-rates = <0xbebc200>;

iris-ctl-supply = <0xb4>;

sku-index = <0x01>;

clock-names = "video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk";

vcodec-supply = <0x1a1>;

interrupts = <0x00 0xae 0x04>;

cvp-supply = <0x1a2>;

clocks = <0x28 0x08 0x28 0x03 0x28 0x05 0x28 0x07 0x28 0x04 0x28 0x06 0x28 0x09>;

compatible = "qcom,msm-vidc\0qcom,sdmmagpie-vidc";

status = "ok";

reg = <0xaa00000 0x200000>;

phandle = <0x369>;

qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk";

qcom,clock-configs = <0x00 0x00 0x00 0x01 0x01 0x01 0x00>;

venus_bus_ddr {

qcom,bus-governor = "msm-vidc-ddr";

label = "venus-ddr";

compatible = "qcom,msm-vidc,bus";

qcom,bus-slave = <0x200>;

qcom,bus-master = <0x3f>;

qcom,bus-range-kbps = <0x3e8 0x63af88>;

};

qcom,msm-vidc,mem_cdsp {

memory-region = <0x1a4>;

compatible = "qcom,msm-vidc,mem-cdsp";

};

non_secure_cb {

iommus = <0x30 0x1080 0x60>;

virtual-addr-pool = <0x25800000 0xba800000>;

label = "venus_ns";

compatible = "qcom,msm-vidc,context-bank";

buffer-types = <0xfff>;

};

secure_non_pixel_cb {

iommus = <0x30 0x1084 0x60>;

qcom,secure-context-bank;

virtual-addr-pool = <0x1000000 0x24800000>;

label = "venus_sec_non_pixel";

compatible = "qcom,msm-vidc,context-bank";

buffer-types = <0x480>;

};

arm9_bus_ddr {

qcom,bus-governor = "performance";

label = "venus-arm9-ddr";

compatible = "qcom,msm-vidc,bus";

qcom,bus-slave = <0x200>;

qcom,bus-master = <0x3f>;

qcom,bus-range-kbps = <0x3e8 0x3e8>;

};

bus_cnoc {

qcom,bus-governor = "performance";

label = "cnoc";

compatible = "qcom,msm-vidc,bus";

qcom,bus-slave = <0x254>;

qcom,bus-master = <0x01>;

qcom,bus-range-kbps = <0x3e8 0x3e8>;

};

secure_bitstream_cb {

iommus = <0x30 0x1081 0x04>;

qcom,secure-context-bank;

virtual-addr-pool = <0x500000 0xdfb00000>;

label = "venus_sec_bitstream";

compatible = "qcom,msm-vidc,context-bank";

buffer-types = <0x241>;

};

secure_pixel_cb {

iommus = <0x30 0x1083 0x20>;

qcom,secure-context-bank;

virtual-addr-pool = <0x500000 0xdfb00000>;

label = "venus_sec_pixel";

compatible = "qcom,msm-vidc,context-bank";

buffer-types = <0x106>;

};

};

qcom,ipa_fws {

qcom,pil-force-shutdown;

memory-region = <0xc9>;

qcom,pas-id = <0x0f>;

compatible = "qcom,pil-tz-generic";

qcom,firmware-name = "ipa_fws";

};

qcom,aopclk {

#clock-cells = <0x01>;

compatible = "qcom,aop-qmp-clk";

phandle = <0x19>;

mboxes = <0x1c 0x00>;

mbox-names = "qdss_clk";

};

qcom,wcd-dsp-glink {

compatible = "qcom,wcd-dsp-glink";

qcom,wdsp-channels = "g_glink_ctrl\0g_glink_persistent_data_nild\0g_glink_persistent_data_ild\0g_glink_audio_data";

status = "disabled";

phandle = <0x599>;

};

funnel@7810000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-apss-merg";

compatible = "arm,primecell";

reg = <0x7810000 0x1000>;

phandle = <0x432>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x202>;

phandle = <0x201>;

};

};

port@5 {

reg = <0x05>;

endpoint {

slave-mode;

remote-endpoint = <0x207>;

phandle = <0x20b>;

};

};

port@3 {

reg = <0x03>;

endpoint {

slave-mode;

remote-endpoint = <0x205>;

phandle = <0x20e>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x203>;

phandle = <0x214>;

};

};

port@4 {

reg = <0x04>;

endpoint {

slave-mode;

remote-endpoint = <0x206>;

phandle = <0x211>;

};

};

port@2 {

reg = <0x02>;

endpoint {

slave-mode;

remote-endpoint = <0x204>;

phandle = <0x208>;

};

};

};

};

tpda@6833000 {

arm,primecell-periphid = <0x3b969>;

qcom,cmb-elem-size = <0x00 0x40>;

clock-names = "apb_pclk";

reg-names = "tpda-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpda-modem-1";

qcom,dsb-elem-size = <0x00 0x20>;

compatible = "arm,primecell";

qcom,tpda-atid = <0x62>;

reg = <0x6833000 0x1000>;

phandle = <0x426>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1ed>;

phandle = <0x1ea>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x1ee>;

phandle = <0x1f0>;

};

};

};

};

cti@6018000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti8";

compatible = "arm,primecell";

reg = <0x6018000 0x1000>;

phandle = <0x47d>;

};

dsi_panel_pwr_supply_labibb_amoled {

#address-cells = <0x01>;

#size-cells = <0x00>;

phandle = <0x521>;

qcom,panel-supply-entry@1 {

qcom,supply-disable-load = <0x50>;

qcom,supply-enable-load = <0x3390>;

qcom,supply-name = "vdda-3p3";

qcom,supply-max-voltage = <0x2dc6c0>;

qcom,supply-pre-off-sleep = <0x0a>;

reg = <0x01>;

qcom,supply-min-voltage = <0x2dc6c0>;

};

qcom,panel-supply-entry@0 {

qcom,supply-disable-load = <0x50>;

qcom,supply-enable-load = <0x7d00>;

qcom,supply-name = "vddio";

qcom,supply-max-voltage = <0x1cfde0>;

qcom,supply-pre-off-sleep = <0x14>;

reg = <0x00>;

qcom,supply-min-voltage = <0x1cfde0>;

};

};

jtagmm@7040000 {

clock-names = "core_clk";

reg-names = "etm-base";

clocks = <0x19 0x00>;

compatible = "qcom,jtagv8-mm";

qcom,coresight-jtagmm-cpu = <0x11>;

reg = <0x7040000 0x1000>;

phandle = <0x2a8>;

};

rpmh-regulator-ldoa13 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa13";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l13 {

regulator-max-microvolt = <0x1d0d80>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x19e100>;

regulator-min-microvolt = <0x19e100>;

regulator-name = "pm6150_l13";

qcom,set = <0x03>;

phandle = <0x408>;

};

};

ufsphy_mem@1d87000 {

clock-names = "ref_clk_src\0ref_clk\0ref_aux_clk";

reg-names = "phy_mem";

lanes-per-direction = <0x01>;

clocks = <0x2f 0x00 0x27 0x7c 0x27 0x84>;

vdda-phy-supply = <0x1a9>;

#phy-cells = <0x00>;

vdda-pll-supply = <0x1a8>;

compatible = "qcom,ufs-phy-qmp-v3";

status = "ok";

vdda-phy-max-microamp = <0xf5b4>;

reg = <0x1d87000 0xddc>;

phandle = <0x9c>;

vdda-phy-always-on;

vdda-pll-max-microamp = <0x477c>;

};

wsa_swr_clk_data_pinctrl {

pinctrl-names = "aud_active\0aud_sleep";

pinctrl-0 = <0x3cd 0x3cf>;

compatible = "qcom,msm-cdc-pinctrl";

pinctrl-1 = <0x3cc 0x3ce>;

status = "disabled";

phandle = <0x4e8>;

};

tpda@78d0000 {

arm,primecell-periphid = <0x3b969>;

qcom,cmb-elem-size = <0x00 0x20>;

clock-names = "apb_pclk";

reg-names = "tpda-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpda-llm-gold";

compatible = "arm,primecell";

qcom,tpda-atid = <0x49>;

reg = <0x78d0000 0x1000>;

phandle = <0x439>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x211>;

phandle = <0x206>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x212>;

phandle = <0x213>;

};

};

};

};

funnel@6005000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-qatb";

compatible = "arm,primecell";

reg = <0x6005000 0x1000>;

phandle = <0x445>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x226>;

phandle = <0x1e1>;

};

};

port@3 {

reg = <0x05>;

endpoint {

slave-mode;

remote-endpoint = <0x229>;

phandle = <0x247>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x227>;

phandle = <0x22e>;

};

};

port@2 {

reg = <0x03>;

endpoint {

slave-mode;

remote-endpoint = <0x228>;

phandle = <0x22a>;

};

};

};

};

tpdm@78a0000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-llm-silver";

compatible = "arm,primecell";

reg = <0x78a0000 0x1000>;

phandle = <0x438>;

port {

endpoint {

remote-endpoint = <0x210>;

phandle = <0x20f>;

};

};

};

qcom,msm-voip-dsp {

compatible = "qcom,msm-voip-dsp";

phandle = <0x261>;

};

cti@6015000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti5";

compatible = "arm,primecell";

reg = <0x6015000 0x1000>;

phandle = <0x47a>;

};

qcom,turing@8300000 {

qcom,smem-state-names = "qcom,force-stop";

qcom,smem-id = <0x259>;

qcom,sysmon-id = <0x07>;

qcom,vdd_mx-uV-uA = <0x181 0x186a0>;

qcom,ssctl-instance-id = <0x17>;

clock-names = "xo";

qcom,proxy-timeout-ms = <0x2710>;

memory-region = <0xad>;

clocks = <0x2f 0x00>;

qcom,signal-aop;

qcom,complete-ramdump;

vdd_mx-supply = <0x1f>;

qcom,pas-id = <0x12>;

interrupts-extended = <0x01 0x00 0x242 0x01 0xae 0x00 0x00 0xae 0x01 0x00 0xae 0x02 0x00 0xae 0x03 0x00>;

compatible = "qcom,pil-tz-generic";

qcom,vdd_cx-uV-uA = <0x181 0x186a0>;

interrupt-names = "qcom,wdog\0qcom,err-fatal\0qcom,err-ready\0qcom,proxy-unvote\0qcom,stop-ack";

reg = <0x8300000 0x100000>;

qcom,smem-states = <0xaf 0x00>;

mboxes = <0x1c 0x00>;

vdd_cx-supply = <0x1d>;

qcom,proxy-clock-names = "xo";

qcom,proxy-reg-names = "vdd_cx\0vdd_mx";

qcom,firmware-name = "cdsp";

mbox-names = "cdsp-pil";

};

qcom,dsi-display@27 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x53b>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_xiaomi_f4_36_02_0b_fhd_cmd_display";

phandle = <0x552>;

};

replicator@6b0a000 {

arm,primecell-periphid = <0x3b909>;

clock-names = "apb_pclk";

reg-names = "replicator-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-replicator-swao";

compatible = "arm,primecell";

reg = <0x6b0a000 0x1000>;

phandle = <0x42a>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x01>;

endpoint {

remote-endpoint = <0x1f3>;

phandle = <0x1f2>;

};

};

port@1 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1f4>;

phandle = <0x1e6>;

};

};

port@2 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x1f5>;

phandle = <0x1f6>;

};

};

};

};

gpio-regulator@3 {

regulator-max-microvolt = <0x2ab980>;

gpio = <0x2ec 0x0b 0x00>;

regulator-enable-ramp-delay = <0x64>;

enable-active-high;

regulator-min-microvolt = <0x2ab980>;

regulator-name = "camera_d_vdda_regulator";

compatible = "regulator-fixed";

reg = <0x03 0x00>;

phandle = <0x56b>;

vin-supply = <0x415>;

};

tpdm@699c000 {

qcom,dummy-source;

coresight-name = "coresight-tpdm-wcss";

compatible = "qcom,coresight-dummy";

phandle = <0x448>;

port {

endpoint {

remote-endpoint = <0x22d>;

phandle = <0x22b>;

};

};

};

qcom,gdsc@10f004 {

qcom,poll-cfg-gdscr;

regulator-name = "usb30_prim_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x10f004 0x04>;

phandle = <0x259>;

};

qcom,mdss_dsi_ctrl0@ae94000 {

clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk";

reg-names = "dsi_ctrl\0disp_cc_base";

cell-index = <0x00>;

interrupts = <0x04 0x00>;

clocks = <0x2a 0x03 0x2a 0x04 0x2a 0x06 0x2a 0x1e 0x2a 0x1f 0x2a 0x16>;

interrupt-parent = <0x1a6>;

label = "dsi-ctrl-0";

vdda-1p2-supply = <0x1a8>;

compatible = "qcom,dsi-ctrl-hw-v2.3";

reg = <0xae94000 0x400 0xaf08000 0x04>;

phandle = <0x372>;

qcom,ctrl-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,ctrl-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x5528>;

qcom,supply-name = "vdda-1p2";

qcom,supply-max-voltage = <0x12cc80>;

reg = <0x00>;

qcom,supply-min-voltage = <0x1174c0>;

};

};

qcom,core-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,core-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x00>;

qcom,supply-name = "refgen";

qcom,supply-max-voltage = <0x00>;

reg = <0x00>;

qcom,supply-min-voltage = <0x00>;

};

};

};

cti@6012000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti2";

compatible = "arm,primecell";

reg = <0x6012000 0x1000>;

phandle = <0x477>;

};

rpmh-regulator-ldoc10 {

qcom,mode-threshold-currents = <0x00 0x2710>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoc10";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150l-l10 {

regulator-max-microvolt = <0x328980>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x30d400>;

regulator-min-microvolt = <0x30d400>;

regulator-name = "pm6150l_l10";

qcom,set = <0x03>;

phandle = <0x33>;

};

};

cti@6c2a000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-dlct_cti1";

compatible = "arm,primecell";

reg = <0x6c2a000 0x1000>;

phandle = <0x469>;

};

funnel_1@6861000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base-dummy\0funnel-base-real";

qcom,duplicate-funnel;

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-turing1";

compatible = "arm,primecell";

reg = <0x6867010 0x10 0x6861000 0x1000>;

phandle = <0x451>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x247>;

phandle = <0x229>;

};

};

port@1 {

reg = <0x01>;

endpoint {

slave-mode;

remote-endpoint = <0x248>;

phandle = <0x249>;

};

};

};

};

funnel@6045000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-merg";

compatible = "arm,primecell";

reg = <0x6045000 0x1000>;

phandle = <0x421>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1da>;

phandle = <0x1d9>;

};

};

port@3 {

reg = <0x02>;

endpoint {

slave-mode;

remote-endpoint = <0x1dd>;

phandle = <0x200>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x1db>;

phandle = <0x1de>;

};

};

port@2 {

reg = <0x01>;

endpoint {

slave-mode;

remote-endpoint = <0x1dc>;

phandle = <0x1e4>;

};

};

};

};

qcom,cpu0-cpu-l3-latmon {

qcom,cachemiss-ev = <0x17>;

qcom,core-dev-table = <0xbb800 0x11e1a300 0xf8700 0x21301800 0x130b00 0x2dc6c000 0x16d7a8 0x38137800 0x1b8a00 0x56f9a000>;

qcom,cpulist = <0x11 0x12 0x13 0x14 0x15 0x16>;

compatible = "qcom,arm-memlat-mon";

phandle = <0x313>;

qcom,target-dev = <0x24>;

};

qcom,msm-pcm-loopback {

compatible = "qcom,msm-pcm-loopback";

phandle = <0x263>;

};

qcom,dsi-display@5 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x527>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_sim_cmd_display";

phandle = <0x544>;

};

msm_cdc_pinctrl@24 {

pinctrl-names = "aud_active\0aud_sleep";

pinctrl-0 = <0x50b>;

compatible = "qcom,msm-cdc-pinctrl";

qcom,lpi-gpios;

pinctrl-1 = <0x50c>;

phandle = <0x4ec>;

};

etm@7540000 {

arm,primecell-periphid = <0xbb95d>;

clock-names = "apb_pclk";

clocks = <0x19 0x00>;

cpu = <0x16>;

qcom,tupwr-disable;

coresight-name = "coresight-etm5";

compatible = "arm,primecell";

reg = <0x7540000 0x1000>;

phandle = <0x441>;

port {

endpoint {

remote-endpoint = <0x222>;

phandle = <0x21a>;

};

};

};

rpmh-regulator-smpc1 {

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "smpc1";

mboxes = <0x1b 0x00>;

regulator-pm6150l-s1 {

regulator-max-microvolt = <0x124f80>;

qcom,init-voltage = <0xf4240>;

regulator-min-microvolt = <0xf4240>;

regulator-name = "pm6150l_s1";

qcom,set = <0x03>;

phandle = <0x3fd>;

};

};

qcom,jpegdma@ac52000 {

clock-names = "jpegdma_clk_src\0jpegdma_clk";

reg-names = "jpegdma_hw";

reg-cam-base = <0x52000>;

cell-index = <0x00>;

camss-vdd-supply = <0x1ae>;

interrupts = <0x00 0x1db 0x00>;

clocks = <0x29 0x4d 0x29 0x4c>;

clock-cntl-level = "nominal";

compatible = "qcom,cam_jpeg_dma";

src-clock-name = "jpegdma_clk_src";

status = "ok";

interrupt-names = "jpegdma";

reg = <0xac52000 0x4000>;

regulator-names = "camss-vdd";

phandle = <0x398>;

clock-rates = <0x23c34600 0x00>;

};

qcom,gcc@100000 {

#reset-cells = <0x01>;

reg-names = "cc_base";

vdd_cx_ao-supply = <0x1e>;

#clock-cells = <0x01>;

compatible = "qcom,gcc-sdmmagpie\0syscon";

reg = <0x100000 0x1f0000>;

phandle = <0x27>;

vdd_cx-supply = <0x1d>;

};

qcom,dsi-display@17 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x532>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_ss_fhd_ea_f10_cmd_display";

phandle = <0x54e>;

};

qcom,vfe1@acb6000 {

camss-supply = <0x1ae>;

clock-control-debugfs = "true";

clock-names = "ife_clk_src\0ife_clk\0ife_axi_clk";

clocks-option = <0x29 0x3d>;

reg-names = "ife";

clock-rates-option = <0x2d4cae00>;

reg-cam-base = <0xb6000>;

cell-index = <0x01>;

ife1-supply = <0x1b8>;

interrupts = <0x00 0x1d3 0x00>;

clocks = <0x29 0x39 0x29 0x38 0x29 0x37>;

clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";

compatible = "qcom,vfe175_130";

src-clock-name = "ife_clk_src";

status = "ok";

clock-names-option = "ife_dsp_clk";

interrupt-names = "ife";

reg = <0xacb6000 0x5200>;

regulator-names = "camss\0ife1";

phandle = <0x390>;

qcom,cam-cx-ipeak = <0x1a3 0x03>;

clock-rates = <0x16a65700 0x00 0x00 0x1e65fb80 0x00 0x00 0x25f7d940 0x00 0x00 0x2d4cae00 0x00 0x00>;

};

i2c@0x88c000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x16d>;

clock-names = "se-clk\0m-ahb\0s-ahb";

interrupts = <0x00 0x25c 0x00>;

clocks = <0x27 0x4a 0x27 0x67 0x27 0x68>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x168>;

dma-names = "tx\0rx";

compatible = "qcom,i2c-geni";

pinctrl-1 = <0x16e>;

status = "disabled";

reg = <0x88c000 0x4000>;

phandle = <0x350>;

dmas = <0x165 0x00 0x03 0x03 0x40 0x00 0x165 0x01 0x03 0x03 0x40 0x00>;

};

qcom,cpu0-cpu-llcc-lat {

qcom,src-dst-ports = <0x01 0x302>;

governor = "performance";

compatible = "qcom,devbw";

phandle = <0xc1>;

qcom,active-only;

operating-points-v2 = <0xbc>;

};

rpmh-regulator-ldoc6 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoc6";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150l-l6 {

regulator-max-microvolt = <0x2f4d60>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x192580>;

regulator-min-microvolt = <0x192580>;

regulator-name = "pm6150l_l6";

qcom,set = <0x03>;

phandle = <0x410>;

};

};

jtagmm@7640000 {

clock-names = "core_clk";

reg-names = "etm-base";

clocks = <0x19 0x00>;

compatible = "qcom,jtagv8-mm";

qcom,coresight-jtagmm-cpu = <0x17>;

reg = <0x7640000 0x1000>;

phandle = <0x2ae>;

};

tpdm@6840000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-vsense";

compatible = "arm,primecell";

reg = <0x6840000 0x1000>;

phandle = <0x457>;

port {

endpoint {

remote-endpoint = <0x252>;

phandle = <0x235>;

};

};

};

qcom,gdsc@9911028 {

clock-names = "ahb_clk";

clocks = <0x27 0x2f>;

regulator-name = "npu_core_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x9911028 0x04>;

phandle = <0x23>;

};

funnel_1@6b53000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-dl-south-1";

compatible = "arm,primecell";

reg = <0x6b58000 0x10 0x6b53000 0x1000>;

phandle = <0x446>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x22a>;

phandle = <0x228>;

};

};

port@1 {

reg = <0x02>;

endpoint {

slave-mode;

remote-endpoint = <0x22b>;

phandle = <0x22d>;

};

};

};

};

cti@69a5000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-wcss_cti1";

compatible = "arm,primecell";

status = "disabled";

reg = <0x69a5000 0x1000>;

phandle = <0x46b>;

};

funnel@6042000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-in1";

compatible = "arm,primecell";

reg = <0x6042000 0x1000>;

phandle = <0x423>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1e4>;

phandle = <0x1dc>;

};

};

port@3 {

reg = <0x05>;

endpoint {

slave-mode;

remote-endpoint = <0x1e7>;

phandle = <0x1e8>;

};

};

port@1 {

reg = <0x03>;

endpoint {

slave-mode;

remote-endpoint = <0x1e5>;

phandle = <0x1f1>;

};

};

port@2 {

reg = <0x04>;

endpoint {

slave-mode;

remote-endpoint = <0x1e6>;

phandle = <0x1f4>;

};

};

};

};

spi@0x880000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x178>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

interrupts = <0x00 0x259 0x00>;

clocks = <0x27 0x44 0x27 0x67 0x27 0x68>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x168>;

spi-max-frequency = <0x2faf080>;

dma-names = "tx\0rx";

compatible = "qcom,spi-geni";

pinctrl-1 = <0x179>;

status = "disabled";

reg = <0x880000 0x4000>;

phandle = <0x354>;

dmas = <0x165 0x00 0x00 0x01 0x40 0x00 0x165 0x01 0x00 0x01 0x40 0x00>;

};

rpmh-regulator-ldof4 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldof4";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm8009-l4 {

regulator-max-microvolt = <0x13e5c0>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x10b940>;

regulator-min-microvolt = <0x10b940>;

regulator-name = "pm8009_l4";

qcom,set = <0x03>;

phandle = <0x419>;

};

};

syscon@17c0000c {

compatible = "syscon";

reg = <0x17c0000c 0x04>;

phandle = <0x99>;

};

qcom,memshare {

compatible = "qcom,memshare";

qcom,client_2 {

qcom,peripheral-size = <0x00>;

qcom,client-id = <0x02>;

label = "modem";

compatible = "qcom,memshare-peripheral";

};

qcom,client_3 {

qcom,peripheral-size = <0x500000>;

qcom,client-id = <0x01>;

qcom,allocate-on-request;

label = "modem";

compatible = "qcom,memshare-peripheral";

phandle = <0x2b0>;

};

qcom,client_1 {

qcom,peripheral-size = <0x00>;

qcom,client-id = <0x00>;

label = "modem";

qcom,allocate-boot-time;

compatible = "qcom,memshare-peripheral";

};

};

tpdm@7830000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-olc";

compatible = "arm,primecell";

reg = <0x7830000 0x1000>;

phandle = <0x434>;

port {

endpoint {

remote-endpoint = <0x20a>;

phandle = <0x209>;

};

};

};

spi@0xa94000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x19f>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

interrupts = <0x00 0x166 0x00>;

clocks = <0x27 0x61 0x27 0x69 0x27 0x6a>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x182>;

spi-max-frequency = <0x2faf080>;

dma-names = "tx\0rx";

compatible = "qcom,spi-geni";

pinctrl-1 = <0x1a0>;

status = "disabled";

reg = <0xa94000 0x4000>;

phandle = <0x367>;

dmas = <0x183 0x00 0x05 0x01 0x40 0x00 0x183 0x01 0x05 0x01 0x40 0x00>;

};

qcom,gdsc@ad09004 {

qcom,poll-cfg-gdscr;

clock-names = "ahb_clk";

qcom,support-hw-trigger;

clocks = <0x27 0x0e>;

regulator-name = "ipe_1_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0xad09004 0x04>;

phandle = <0x1ba>;

};

qcom,vfe0@acaf000 {

camss-supply = <0x1ae>;

clock-control-debugfs = "true";

clock-names = "ife_clk_src\0ife_clk\0ife_axi_clk";

clocks-option = <0x29 0x36>;

reg-names = "ife";

clock-rates-option = <0x2d4cae00>;

reg-cam-base = <0xaf000>;

ife0-supply = <0x1b7>;

cell-index = <0x00>;

interrupts = <0x00 0x1d1 0x00>;

clocks = <0x29 0x32 0x29 0x31 0x29 0x30>;

clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";

compatible = "qcom,vfe175_130";

src-clock-name = "ife_clk_src";

status = "ok";

clock-names-option = "ife_dsp_clk";

interrupt-names = "ife";

reg = <0xacaf000 0x5200>;

regulator-names = "camss\0ife0";

phandle = <0x38e>;

qcom,cam-cx-ipeak = <0x1a3 0x03>;

clock-rates = <0x16a65700 0x00 0x00 0x1e65fb80 0x00 0x00 0x25f7d940 0x00 0x00 0x2d4cae00 0x00 0x00>;

};

qcom,qup_uart@0xa90000 {

pinctrl-names = "default\0sleep";

pinctrl-0 = <0x191 0x192 0x193>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

clocks = <0x27 0x4c 0x27 0x69 0x27 0x6a>;

qcom,wrapper-core = <0x182>;

interrupts-extended = <0x01 0x00 0x165 0x00 0x174 0x71 0x00>;

compatible = "qcom,msm-geni-serial-hs";

pinctrl-1 = <0x191 0x192 0x193>;

status = "disabled";

reg = <0xa90000 0x4000>;

phandle = <0x361>;

qcom,wakeup-byte = <0xfd>;

};

qcom,smp2p_sleepstate {

interrupts = <0x00 0x00>;

interrupt-parent = <0x98>;

compatible = "qcom,smp2p-sleepstate";

interrupt-names = "smp2p-sleepstate-in";

qcom,smem-states = <0x97 0x00>;

};

qcom,a5@ac00000 {

clock-names = "soc_fast_ahb\0icp_ahb_clk\0icp_clk_src\0icp_clk";

fw_name = "CAMERA_ICP.elf";

reg-names = "a5_qgic\0a5_sierra\0a5_csr";

reg-cam-base = <0x00 0x10000 0x18000>;

cell-index = <0x00>;

camss-vdd-supply = <0x1ae>;

interrupts = <0x00 0x1cf 0x00>;

clocks = <0x29 0x28 0x29 0x2d 0x29 0x2f 0x29 0x2e>;

ubwc-cfg = <0x73 0x1cf>;

clock-cntl-level = "svs\0turbo";

compatible = "qcom,cam-a5";

status = "ok";

interrupt-names = "a5";

reg = <0xac00000 0x6000 0xac10000 0x8000 0xac18000 0x3000>;

regulator-names = "camss-vdd";

phandle = <0x393>;

clock-rates = <0xbebc200 0x00 0x17d78400 0x00 0x17d78400 0x00 0x23c34600 0x00>;

};

rpmh-regulator-ldoa11 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa11";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l11 {

regulator-max-microvolt = <0x1e4600>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x19e100>;

regulator-min-microvolt = <0x19e100>;

regulator-name = "pm6150_l11";

qcom,set = <0x03>;

phandle = <0x1cf>;

};

};

rpmh-regulator-cxlvl {

compatible = "qcom,rpmh-arc-regulator";

pm6150l-s2-level_ao-parent-supply = <0x1ce>;

qcom,resource-name = "cx.lvl";

mboxes = <0x1b 0x00>;

pm6150l-s2-level-parent-supply = <0x1f>;

regulator-pm6150l-s2 {

regulator-max-microvolt = <0x10000>;

regulator-min-microvolt = <0x11>;

regulator-name = "pm6150l_s2_level";

qcom,init-voltage-level = <0x11>;

qcom,set = <0x03>;

phandle = <0x1d>;

qcom,min-dropout-voltage-level = <0xffffffff>;

};

regulator-cdev {

qcom,reg-resource-name = "cx";

compatible = "qcom,rpmh-reg-cdev";

phandle = <0x67>;

mboxes = <0x1c 0x00>;

#cooling-cells = <0x02>;

};

regulator-pm6150l-s2-level-ao {

regulator-max-microvolt = <0x10000>;

regulator-min-microvolt = <0x11>;

regulator-name = "pm6150l_s2_level_ao";

qcom,init-voltage-level = <0x11>;

qcom,set = <0x01>;

phandle = <0x1e>;

qcom,min-dropout-voltage-level = <0xffffffff>;

};

};

wsa_core_clk {

qcom,codec-ext-clk-src = <0x03>;

#clock-cells = <0x01>;

compatible = "qcom,audio-ref-clk";

phandle = <0x4e6>;

qcom,codec-lpass-clk-id = <0x309>;

qcom,codec-lpass-ext-clk-freq = <0x124f800>;

};

tpdm@69c0000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-dl-mm";

compatible = "arm,primecell";

reg = <0x69c0000 0x1000>;

phandle = <0x44c>;

port {

endpoint {

remote-endpoint = <0x240>;

phandle = <0x23f>;

};

};

};

qcom,spmi@c440000 {

#address-cells = <0x01>;

reg-names = "core\0chnls\0obsrvr\0intr\0cnfg";

qcom,channel = <0x00>;

cell-index = <0x00>;

interrupts = <0x00 0x1e1 0x00>;

#size-cells = <0x01>;

compatible = "qcom,spmi-pmic-arb";

#interrupt-cells = <0x04>;

interrupt-names = "periph_irq";

reg = <0xc440000 0x1100 0xc600000 0x2000000 0xe600000 0x100000 0xe700000 0xa0000 0xc40a000 0x26000>;

phandle = <0x2e3>;

qcom,ee = <0x00>;

interrupt-controller;

qcom,pm6150@1 {

#address-cells = <0x01>;

#size-cells = <0x01>;

compatible = "qcom,spmi-pmic";

reg = <0x01 0x00>;

qcom,vibrator@5300 {

qcom,disable-overdrive;

compatible = "qcom,qpnp-vibrator-ldo";

reg = <0x5300 0x100>;

phandle = <0x2e9>;

qcom,vib-ldo-volt-uv = <0x2dc6c0>;

};

};

qcom,pm6150l@5 {

#address-cells = <0x01>;

#size-cells = <0x01>;

compatible = "qcom,spmi-pmic";

reg = <0x05 0x00>;

qcom,pwms@bc00 {

qcom,num-lpg-channels = <0x02>;

reg-names = "lpg-base";

#pwm-cells = <0x02>;

compatible = "qcom,pwm-lpg";

status = "disabled";

reg = <0xbc00 0x200>;

phandle = <0x303>;

};

qcom,amoled {

compatible = "qcom,qpnp-amoled-regulator";

status = "disabled";

phandle = <0x308>;

ab@de00 {

regulator-max-microvolt = <0x5d1420>;

reg-names = "ab_base";

regulator-min-microvolt = <0x4630c0>;

regulator-name = "ab";

reg = <0xde00 0x100>;

phandle = <0x30a>;

qcom,swire-control;

};

oledb@e000 {

regulator-max-microvolt = <0x7b98a0>;

reg-names = "oledb_base";

regulator-min-microvolt = <0x4b2648>;

regulator-name = "oledb";

reg = <0xe000 0x100>;

phandle = <0x309>;

qcom,swire-control;

};

ibb@dc00 {

regulator-max-microvolt = <0x5265c0>;

reg-names = "ibb_base";

regulator-min-microvolt = <0xc3500>;

regulator-name = "ibb";

reg = <0xdc00 0x100>;

phandle = <0x30b>;

qcom,swire-control;

};

};

qcom,lcdb@ec00 {

#address-cells = <0x01>;

interrupts = <0x05 0xec 0x01 0x01>;

#size-cells = <0x01>;

compatible = "qcom,qpnp-lcdb-regulator";

status = "disabled";

interrupt-names = "sc-irq";

qcom,pmic-revid = <0xab>;

reg = <0xec00 0x100>;

phandle = <0x2ee>;

bst {

regulator-max-microvolt = <0x5fbfb8>;

label = "bst";

regulator-min-microvolt = <0x47b760>;

regulator-name = "lcdb_bst";

phandle = <0x2f1>;

};

ldo {

regulator-max-microvolt = <0x5b8d80>;

label = "ldo";

regulator-min-microvolt = <0x3d0900>;

regulator-name = "lcdb_ldo";

phandle = <0x2ef>;

};

ncp {

regulator-max-microvolt = <0x5b8d80>;

label = "ncp";

regulator-min-microvolt = <0x3d0900>;

regulator-name = "lcdb_ncp";

phandle = <0x2f0>;

};

};

qcom,leds@d000 {

compatible = "qcom,tri-led";

reg = <0xd000 0x100>;

phandle = <0x304>;

green {

linux,default-trigger = "timer";

label = "green";

led-sources = <0x01>;

phandle = <0x306>;

pwms = <0xac 0x01 0xf4240>;

};

led {

linux,default-trigger = "timer";

label = "red";

led-sources = <0x00>;

phandle = <0x305>;

pwms = <0xac 0x00 0xf4240>;

};

blue {

linux,default-trigger = "timer";

label = "blue";

led-sources = <0x02>;

phandle = <0x307>;

pwms = <0xac 0x02 0xf4240>;

};

};

qcom,leds@d300 {

qcom,hdrm-auto-mode;

qcom,open-circuit-det;

qcom,vph-droop-det;

interrupts = <0x05 0xd3 0x00 0x01 0x05 0xd3 0x03 0x01 0x05 0xd3 0x04 0x01>;

label = "flash";

compatible = "qcom,qpnp-flash-led-v2";

status = "okay";

interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq";

qcom,thermal-derate-en;

qcom,pmic-revid = <0xab>;

reg = <0xd300 0x100>;

phandle = <0x2f2>;

qcom,short-circuit-det;

qcom,thermal-derate-current = <0xc8 0x1f4 0x3e8>;

qcom,isc-delay = <0xc0>;

qcom,flashlight {

qcom,led-name = "flashlight";

qcom,ires-ua = <0x30d4>;

qcom,id = <0x03>;

qcom,current-ma = <0x1f4>;

qcom,duration-ms = <0x500>;

qcom,hdrm-vol-hi-lo-win-mv = <0x64>;

label = "flash";

qcom,hdrm-voltage-mv = <0x145>;

phandle = <0x2fc>;

qcom,max-current = <0x2ee>;

qcom,default-led-trigger = "flashlight_trigger";

};

qcom,torch_2 {

qcom,led-name = "led:torch_2";

qcom,ires-ua = <0x30d4>;

qcom,id = <0x02>;

qcom,current-ma = <0x12c>;

qcom,hdrm-vol-hi-lo-win-mv = <0x64>;

label = "torch";

status = "disabled";

qcom,hdrm-voltage-mv = <0x145>;

phandle = <0x2f8>;

qcom,max-current = <0x1f4>;

qcom,default-led-trigger = "torch2_trigger";

};

qcom,flash_1 {

qcom,led-name = "led:flash_1";

qcom,ires-ua = <0x30d4>;

qcom,id = <0x01>;

qcom,current-ma = <0x3e8>;

qcom,duration-ms = <0x500>;

qcom,hdrm-vol-hi-lo-win-mv = <0x64>;

label = "flash";

qcom,hdrm-voltage-mv = <0x145>;

phandle = <0x2f4>;

qcom,max-current = <0x5dc>;

qcom,default-led-trigger = "flash1_trigger";

};

qcom,torch_0 {

qcom,led-name = "led:torch_0";

qcom,ires-ua = <0x30d4>;

qcom,id = <0x00>;

qcom,current-ma = <0x12c>;

qcom,hdrm-vol-hi-lo-win-mv = <0x64>;

label = "torch";

qcom,hdrm-voltage-mv = <0x145>;

phandle = <0x2f6>;

qcom,max-current = <0x1f4>;

qcom,default-led-trigger = "torch0_trigger";

};

qcom,led_switch_1 {

qcom,led-name = "led:switch_1";

qcom,led-mask = <0x02>;

label = "switch";

phandle = <0x2fa>;

qcom,default-led-trigger = "switch1_trigger";

};

qcom,flash_2 {

qcom,led-name = "led:flash_2";

qcom,ires-ua = <0x30d4>;

qcom,id = <0x02>;

qcom,current-ma = <0x1f4>;

qcom,duration-ms = <0x500>;

qcom,hdrm-vol-hi-lo-win-mv = <0x64>;

label = "flash";

status = "disabled";

qcom,hdrm-voltage-mv = <0x145>;

phandle = <0x2f5>;

qcom,max-current = <0x2ee>;

qcom,default-led-trigger = "flash2_trigger";

};

qcom,torch_1 {

qcom,led-name = "led:torch_1";

qcom,ires-ua = <0x30d4>;

qcom,id = <0x01>;

qcom,current-ma = <0x12c>;

qcom,hdrm-vol-hi-lo-win-mv = <0x64>;

label = "torch";

qcom,hdrm-voltage-mv = <0x145>;

phandle = <0x2f7>;

qcom,max-current = <0x1f4>;

qcom,default-led-trigger = "torch1_trigger";

};

qcom,flash_0 {

qcom,led-name = "led:flash_0";

qcom,ires-ua = <0x30d4>;

qcom,id = <0x00>;

qcom,current-ma = <0x3e8>;

qcom,duration-ms = <0x500>;

qcom,hdrm-vol-hi-lo-win-mv = <0x64>;

label = "flash";

qcom,hdrm-voltage-mv = <0x145>;

phandle = <0x2f3>;

qcom,max-current = <0x5dc>;

qcom,default-led-trigger = "flash0_trigger";

};

qcom,led_switch_2 {

qcom,led-name = "led:switch_2";

qcom,led-mask = <0x03>;

label = "switch";

phandle = <0x2fb>;

qcom,default-led-trigger = "switch2_trigger";

};

qcom,led_switch_0 {

qcom,led-name = "led:switch_0";

qcom,led-mask = <0x01>;

label = "switch";

phandle = <0x2f9>;

qcom,default-led-trigger = "switch0_trigger";

};

};

qcom,pwms@b100 {

qcom,num-lpg-channels = <0x03>;

reg-names = "lpg-base\0lut-base";

#pwm-cells = <0x02>;

compatible = "qcom,pwm-lpg";

qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>;

reg = <0xb100 0x300 0xb000 0x100>;

phandle = <0xac>;

lpg3 {

qcom,ramp-pattern-repeat;

qcom,ramp-pause-hi-count = <0x02>;

qcom,ramp-step-ms = <0x64>;

qcom,ramp-from-low-to-high;

qcom,ramp-low-index = <0x00>;

qcom,ramp-high-index = <0x14>;

phandle = <0x302>;

qcom,lpg-chan-id = <0x03>;

qcom,ramp-pause-lo-count = <0x02>;

};

lpg1 {

qcom,ramp-pattern-repeat;

qcom,ramp-pause-hi-count = <0x02>;

qcom,ramp-step-ms = <0x64>;

qcom,ramp-from-low-to-high;

qcom,ramp-low-index = <0x00>;

qcom,ramp-high-index = <0x14>;

qcom,lpg-chan-id = <0x01>;

qcom,ramp-pause-lo-count = <0x02>;

};

lpg2 {

qcom,ramp-pattern-repeat;

qcom,ramp-pause-hi-count = <0x02>;

qcom,ramp-step-ms = <0x64>;

qcom,ramp-from-low-to-high;

qcom,ramp-low-index = <0x00>;

qcom,ramp-high-index = <0x14>;

phandle = <0x301>;

qcom,lpg-chan-id = <0x02>;

qcom,ramp-pause-lo-count = <0x02>;

};

};

qcom,wled@d800 {

reg-names = "wled-ctrl-base\0wled-sink-base";

interrupts = <0x05 0xd8 0x01 0x01 0x05 0xd8 0x04 0x03 0x05 0xd8 0x05 0x03>;

label = "backlight";

qcom,auto-calibration;

compatible = "qcom,pm6150l-spmi-wled";

status = "disabled";

interrupt-names = "ovp-irq\0pre-flash-irq\0flash-irq";

qcom,pmic-revid = <0xab>;

reg = <0xd800 0x100 0xd900 0x100>;

phandle = <0x2fd>;

qcom,wled-torch {

label = "torch";

phandle = <0x2ff>;

qcom,wled-torch-timer = <0x4b0>;

qcom,default-led-trigger = "wled_torch";

};

qcom,wled-switch {

label = "switch";

phandle = <0x300>;

qcom,default-led-trigger = "wled_switch";

};

qcom,wled-flash {

label = "flash";

phandle = <0x2fe>;

qcom,default-led-trigger = "wled_flash";

};

};

};

qcom,pm8009@a {

#address-cells = <0x01>;

#size-cells = <0x01>;

compatible = "qcom,spmi-pmic";

reg = <0x0a 0x00>;

pinctrl@c000 {

qcom,gpios-disallowed = <0x03>;

gpio-controller;

interrupts = <0x00 0xc0 0x00 0x00 0x00 0xc1 0x00 0x00 0x00 0xc3 0x00 0x00>;

compatible = "qcom,spmi-gpio";

interrupt-names = "pm8009_gpio1\0pm8009_gpio2\0pm8009_gpio4";

reg = <0xc000 0x400>;

phandle = <0x30c>;

#gpio-cells = <0x02>;

};

qcom,revid@100 {

compatible = "qcom,qpnp-revid";

reg = <0x100 0x100>;

};

};

qcom,pm6150@0 {

#address-cells = <0x01>;

#size-cells = <0x01>;

compatible = "qcom,spmi-pmic";

reg = <0x00 0x00>;

qcom,power-on@800 {

interrupts = <0x00 0x08 0x00 0x00 0x00 0x08 0x01 0x00 0x00 0x08 0x04 0x00 0x00 0x08 0x05 0x00>;

qcom,pon-dbc-delay = <0xf424>;

compatible = "qcom,qpnp-power-on";

qcom,system-reset;

interrupt-names = "kpdpwr\0resin\0resin-bark\0kpdpwr-resin-bark";

reg = <0x800 0x100>;

qcom,kpdpwr-sw-debounce;

qcom,store-hard-reset-reason;

qcom,pon_3 {

qcom,s2-type = <0x01>;

qcom,pull-up = <0x01>;

qcom,pon-type = <0x03>;

qcom,s1-timer = <0x548>;

qcom,support-reset = <0x01>;

qcom,use-bark;

qcom,s2-timer = <0x7d0>;

};

qcom,pon_1 {

qcom,s2-type = <0x07>;

qcom,pull-up = <0x01>;

qcom,pon-type = <0x00>;

qcom,s1-timer = <0x1180>;

qcom,support-reset = <0x01>;

qcom,s2-timer = <0x7d0>;

linux,code = <0x74>;

};

qcom,pon_2 {

qcom,pull-up;

qcom,pon-type = <0x01>;

linux,code = <0x72>;

};

};

qcom,qpnp-smb5 {

qcom,thermal-mitigation-icl = <0x2dc6c0 0x2dc6c0 0x2dc6c0 0x249f00 0x2191c0 0x200b20 0x1e8480 0x1e8480 0x1e8480 0x1cfde0 0x1b7740 0x186a00 0x16e360 0x13d620 0x13d620 0xb71b0>;

mi,ffc-low-tbat = <0x96>;

mi,support-qc3p5-without-smb;

qcom,thermal-mitigation-pd-base = <0x5b8d80 0x4c4b40 0x44aa20 0x3d0900 0x33e140 0x325aa0 0x30d400 0x2f4d60 0x2dc6c0 0x2ab980 0x27ac40 0x249f00 0x2191c0 0x1e8480 0xf4240 0xaae60>;

#address-cells = <0x01>;

mi,fcc-batt-unverify-ua = <0x1e8480>;

qcom,reg-dump-enable;

qcom,thermal-fcc-qc3-normal = <0x5b8d80 0x4c4b40 0x44aa20 0x3d0900 0x3567e0 0x2dc6c0 0x2c4020 0x2ab980 0x2932e0 0x27ac40 0x249f00 0x2191c0 0x1e8480 0x1e8480 0xb71b0 0xaae60>;

mi,ffc-high-tbat = <0x1e0>;

qcom,disable-suspend-on-collapse;

qcom,fv-max-uv = <0x4434f0>;

qcom,chg-term-current-ma = <0xffffff38>;

qcom,sec-charger-config = <0x00>;

io-channels = <0xa8 0x08 0xa8 0x07 0xa8 0x09 0xa8 0x06 0x2ea 0x4d 0xa8 0x99 0xa8 0x83>;

mi,early-status-report;

qcom,fcc-max-ua = <0x5b8d80>;

mi,use-bq-pump;

#size-cells = <0x01>;

dpdm-supply = <0x25a>;

mi,support-ffc;

qcom,usbpd-phandle = <0x25b>;

qcom,thermal-fcc-pps-cp = <0x5b8d80 0x53ec60 0x4c4b40 0x44aa20 0x3e8fa0 0x3b8260 0x3567e0 0x30d400 0x2f4d60 0x2ab980 0x27ac40 0x249f00 0x2191c0 0x1e8480 0xf4240 0xaae60>;

qcom,battery-data = <0x58e>;

qcom,distinguish-qc-class-ab;

qcom,usb-icl-ua = <0x2dc6c0>;

qcom,thermal-mitigation = <0x5b8d80 0x4c4b40 0x44aa20 0x3d0900 0x3567e0 0x2dc6c0 0x2c4020 0x2ab980 0x27ac40 0x249f00 0x2191c0 0x1e8480 0x1b7740 0x16e360 0xf4240 0x7a120>;

compatible = "qcom,qpnp-smb5";

qcom,step-charging-enable;

qcom,chg-term-src = <0x01>;

qcom,sw-jeita-enable;

qcom,pmic-revid = <0xa4>;

qcom,thermal-mitigation-dcp = <0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x19f0a0 0x186a00 0x155cc0 0x124f80 0x10c8e0 0x10c8e0 0xf4240>;

qcom,auto-recharge-soc = <0x63>;

phandle = <0x8a>;

qcom,thermal-fcc-qc3-cp = <0x5b8d80 0x4c4b40 0x44aa20 0x3d0900 0x3567e0 0x325aa0 0x30d400 0x2f4d60 0x2dc6c0 0x2ab980 0x27ac40 0x249f00 0x2191c0 0x1e8480 0x1e8480 0x30d40>;

qcom,lpd-disable;

qcom,thermal-mitigation-qc2 = <0x16e360 0x16e360 0x16e360 0x16e360 0x162010 0x155cc0 0x149970 0x13d620 0x118c30 0x10c8e0 0xf4240 0xdbba0 0xcf850 0xb71b0 0x9eb10 0x7a120>;

io-channel-names = "usb_in_voltage\0usb_in_current\0chg_temp\0die_temp\0conn_temp\0sbux_res\0vph_voltage";

#cooling-cells = <0x02>;

qcom,chgr@1000 {

interrupts = <0x00 0x10 0x00 0x01 0x00 0x10 0x01 0x01 0x00 0x10 0x02 0x01 0x00 0x10 0x03 0x01 0x00 0x10 0x04 0x01 0x00 0x10 0x05 0x01 0x00 0x10 0x06 0x01 0x00 0x10 0x07 0x01>;

interrupt-names = "chgr-error\0chg-state-change\0step-chg-state-change\0step-chg-soc-update-fail\0step-chg-soc-update-req\0fg-fvcal-qualified\0vph-alarm\0vph-drop-prechg";

reg = <0x1000 0x100>;

};

qcom,batif@1200 {

interrupts = <0x00 0x12 0x00 0x01 0x00 0x12 0x02 0x03 0x00 0x12 0x03 0x03 0x00 0x12 0x04 0x03 0x00 0x12 0x05 0x03 0x00 0x12 0x06 0x03 0x00 0x12 0x07 0x03>;

interrupt-names = "bat-temp\0bat-ov\0bat-low\0bat-therm-or-id-missing\0bat-terminal-missing\0buck-oc\0vph-ov";

reg = <0x1200 0x100>;

};

qcom,typec@1500 {

interrupts = <0x00 0x15 0x00 0x01 0x00 0x15 0x01 0x01 0x00 0x15 0x02 0x01 0x00 0x15 0x03 0x01 0x00 0x15 0x04 0x01 0x00 0x15 0x05 0x01 0x00 0x15 0x06 0x01 0x00 0x15 0x07 0x01>;

interrupt-names = "typec-or-rid-detect-change\0typec-vpd-detect\0typec-cc-state-change\0typec-vconn-oc\0typec-vbus-change\0typec-attach-detach\0typec-legacy-cable-detect\0typec-try-snk-src-detect";

reg = <0x1500 0x100>;

};

qcom,dc@1400 {

interrupts = <0x00 0x14 0x01 0x03 0x00 0x14 0x02 0x03 0x00 0x14 0x03 0x03 0x00 0x14 0x04 0x03 0x00 0x14 0x05 0x01 0x00 0x14 0x06 0x01 0x00 0x14 0x07 0x01>;

interrupt-names = "dcin-vashdn\0dcin-uv\0dcin-ov\0dcin-plugin\0dcin-revi\0dcin-pon\0dcin-en";

reg = <0x1400 0x100>;

};

qcom,misc@1600 {

interrupts = <0x00 0x16 0x00 0x01 0x00 0x16 0x01 0x01 0x00 0x16 0x02 0x01 0x00 0x16 0x03 0x01 0x00 0x16 0x04 0x03 0x00 0x16 0x05 0x01 0x00 0x16 0x06 0x01 0x00 0x16 0x07 0x01>;

interrupt-names = "wdog-snarl\0wdog-bark\0aicl-fail\0aicl-done\0smb-en\0imp-trigger\0temp-change\0temp-change-smb";

reg = <0x1600 0x100>;

};

qcom,dcdc@1100 {

interrupts = <0x00 0x11 0x00 0x01 0x00 0x11 0x01 0x01 0x00 0x11 0x02 0x01 0x00 0x11 0x03 0x03 0x00 0x11 0x04 0x03 0x00 0x11 0x05 0x03 0x00 0x11 0x06 0x01 0x00 0x11 0x07 0x03>;

interrupt-names = "otg-fail\0otg-oc-disable-sw\0otg-oc-hiccup\0bsm-active\0high-duty-cycle\0input-current-limiting\0concurrent-mode-disable\0switcher-power-ok";

reg = <0x1100 0x100>;

};

qcom,usb@1300 {

interrupts = <0x00 0x13 0x00 0x03 0x00 0x13 0x01 0x03 0x00 0x13 0x02 0x03 0x00 0x13 0x03 0x03 0x00 0x13 0x04 0x03 0x00 0x13 0x05 0x01 0x00 0x13 0x06 0x01 0x00 0x13 0x07 0x01>;

interrupt-names = "usbin-collapse\0usbin-vashdn\0usbin-uv\0usbin-ov\0usbin-plugin\0usbin-revi-change\0usbin-src-change\0usbin-icl-change";

reg = <0x1300 0x100>;

};

qcom,sdam@b100 {

interrupts = <0x00 0xb1 0x01 0x01>;

interrupt-names = "sdam-sts";

reg = <0xb100 0x100>;

};

qcom,smb5-vbus {

regulator-name = "smb5-vbus";

phandle = <0xa6>;

};

qcom,smb5-vconn {

regulator-name = "smb5-vconn";

phandle = <0xa7>;

};

};

qcom,misc@900 {

compatible = "qcom,qpnp-misc";

reg = <0x900 0x100>;

phandle = <0x2e4>;

};

vadc@3100 {

io-channel-ranges;

#address-cells = <0x01>;

reg-names = "adc5-usr-base\0adc5-cal-base";

interrupts = <0x00 0x31 0x00 0x01>;

#io-channel-cells = <0x01>;

#size-cells = <0x00>;

compatible = "qcom,spmi-adc5";

qcom,adc-vdd-reference = <0x753>;

interrupt-names = "eoc-int-en-set";

qcom,pmic-revid = <0xa4>;

reg = <0x3100 0x100 0x3700 0x100>;

phandle = <0xa8>;

xo_therm {

label = "xo_therm";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x4c>;

qcom,hw-settle-time = <0xc8>;

};

ref_gnd {

label = "ref_gnd";

qcom,pre-scaling = <0x01 0x01>;

reg = <0x00>;

};

chg_temp {

label = "chg_temp";

qcom,pre-scaling = <0x01 0x01>;

reg = <0x09>;

};

v_i_int_ext {

label = "v_i_int_vbat_vdata";

qcom,pre-scaling = <0x01 0x01>;

reg = <0xb0>;

};

vph_pwr {

label = "vph_pwr";

qcom,pre-scaling = <0x01 0x03>;

reg = <0x83>;

};

chg_sbux {

label = "chg_sbux";

qcom,pre-scaling = <0x01 0x03>;

reg = <0x99>;

};

vcoin {

label = "vcoin";

qcom,pre-scaling = <0x01 0x03>;

reg = <0x85>;

};

bat_therm {

label = "bat_therm";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x4a>;

qcom,hw-settle-time = <0xc8>;

};

bat_therm_400k {

label = "bat_therm_400k";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x6a>;

qcom,hw-settle-time = <0xc8>;

};

cpu_therm {

label = "cpu_therm";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x4f>;

qcom,hw-settle-time = <0xc8>;

};

vref_1p25 {

label = "vref_1p25";

qcom,pre-scaling = <0x01 0x01>;

reg = <0x01>;

};

v_i_parallel {

label = "v_i_parallel_vbat_vdata";

qcom,pre-scaling = <0x01 0x01>;

reg = <0xb4>;

};

die_temp {

label = "die_temp";

qcom,pre-scaling = <0x01 0x01>;

reg = <0x06>;

};

pa_therm0 {

label = "pa_therm0";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x4e>;

qcom,hw-settle-time = <0xc8>;

};

usb_in_i_uv {

label = "usb_in_i_uv";

qcom,pre-scaling = <0x01 0x01>;

reg = <0x07>;

};

mid_chg_div6 {

label = "chg_mid";

qcom,pre-scaling = <0x01 0x06>;

reg = <0x1e>;

};

usb_in_v_div_16 {

label = "usb_in_v_div_16";

qcom,pre-scaling = <0x01 0x10>;

reg = <0x08>;

};

vbat_sns {

label = "vbat_sns";

qcom,pre-scaling = <0x01 0x03>;

reg = <0x84>;

};

bat_therm_30k {

label = "bat_therm_30k";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x2a>;

qcom,hw-settle-time = <0xc8>;

};

quiet_therm {

label = "quiet_therm";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x50>;

qcom,hw-settle-time = <0xc8>;

};

bat_id {

label = "bat_id";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x4b>;

qcom,hw-settle-time = <0xc8>;

};

};

qpnp,qg {

qcom,bass-enable;

qcom,cl-feedback-on;

mi,software-optimize-ffc-qg-iterm;

#address-cells = <0x01>;

qcom,vbatt-empty-mv = <0xc1c>;

qcom,vbatt-empty-cold-mv = <0xbb8>;

qcom,vbatt-cutoff-mv = <0xd48>;

io-channels = <0xa8 0x4a 0xa8 0x4b>;

qcom,qg-iterm-ma = <0x15e>;

qcom,s3-entry-fifo-length = <0x02>;

#size-cells = <0x01>;

qcom,vbatt-low-mv = <0xdac>;

qcom,vbatt-low-cold-mv = <0xed8>;

qcom,s3-entry-ibat-ua = <0x61a8>;

qcom,tcss-enable;

qcom,hold-soc-while-full;

qcom,battery-data = <0x58e>;

qcom,linearize-soc;

qcom,tcss-entry-soc = <0x5a>;

compatible = "qcom,qpnp-qg";

qcom,soc_decimal_rate = <0x00 0x20 0x0a 0x1e 0x14 0x1c 0x1e 0x1c 0x28 0x1c 0x32 0x1c 0x3c 0x1c 0x46 0x1c 0x50 0x1c 0x5a 0x1a 0x5f 0x0a 0x63 0x05>;

qcom,pmic-revid = <0xa4>;

qcom,qg-ext-sns;

phandle = <0x2e5>;

qcom,shutdown-delay-enable;

qcom,shutdown-soc-threshold = <0x0a>;

qcom,s3-exit-ibat-ua = <0xafc8>;

io-channel-names = "batt-therm\0batt-id";

qcom,qg-sdam@b600 {

status = "okay";

reg = <0xb600 0x100>;

};

qcom,qgauge@4800 {

interrupts = <0x00 0x48 0x00 0x03 0x00 0x48 0x01 0x03 0x00 0x48 0x02 0x01 0x00 0x48 0x03 0x01 0x00 0x48 0x04 0x01>;

status = "okay";

interrupt-names = "qg-batt-missing\0qg-vbat-low\0qg-vbat-empty\0qg-fifo-done\0qg-good-ocv";

reg = <0x4800 0x100>;

};

};

pinctrl@c000 {

qcom,gpios-disallowed = <0x05 0x06 0x09 0x0a>;

gpio-controller;

interrupts = <0x00 0xc0 0x00 0x00 0x00 0xc1 0x00 0x00 0x00 0xc2 0x00 0x00 0x00 0xc3 0x00 0x00 0x00 0xc6 0x00 0x00 0x00 0xc7 0x00 0x00>;

compatible = "qcom,spmi-gpio";

interrupt-names = "pm6150_gpio1\0pm6150_gpio2\0pm6150_gpio3\0pm6150_gpio4\0pm6150_gpio7\0pm6150_gpio8";

reg = <0xc000 0xa00>;

phandle = <0x2e6>;

#gpio-cells = <0x02>;

smb_stat {

smb_stat_default {

function = "normal";

pins = "gpio3";

qcom,pull-up-strength = <0x00>;

phandle = <0x5b3>;

bias-pull-up;

power-source = <0x00>;

input-enable;

};

};

wcd934x_mclk {

wcd934x_mclk_default {

function = "func1";

pins = "gpio8";

qcom,drive-strength = <0x02>;

bias-disable;

phandle = <0x2e7>;

power-source = <0x00>;

output-low;

};

};

};

qcom,usb-pdphy@1700 {

mi,limit_pd_unverified_pps_vbus = <0x01>;

vdd-pdphy-supply = <0xa5>;

mi,non-qcom-pps-ctrl;

interrupts = <0x00 0x17 0x00 0x01 0x00 0x17 0x01 0x01 0x00 0x17 0x02 0x01 0x00 0x17 0x03 0x01 0x00 0x17 0x04 0x01 0x00 0x17 0x05 0x01 0x00 0x17 0x06 0x01 0x00 0x17 0x07 0x01>;

vconn-supply = <0xa7>;

vbus-supply = <0xa6>;

mi,pd_unverified_pps_max_vbus_limit = <0x90f560>;

qcom,default-sink-caps = <0x1388 0xbb8 0x2328 0xbb8 0x2ee0 0x8ca>;

compatible = "qcom,qpnp-pdphy";

interrupt-names = "sig-tx\0sig-rx\0msg-tx\0msg-rx\0msg-tx-failed\0msg-tx-discarded\0msg-rx-discarded\0fr-swap";

mi,pd_max_curr_limit = <0x3d0900>;

reg = <0x1700 0x100>;

phandle = <0x25b>;

mi,pd_curr_limit = <0x01>;

};

clock-controller@5b00 {

clock-output-names = "pm6150_div_clk1";

clock-names = "xo";

assigned-clocks = <0xa9 0x01>;

assigned-clock-rates = <0x124f800>;

clocks = <0x2f 0x00>;

#clock-cells = <0x01>;

compatible = "qcom,spmi-clkdiv";

qcom,num-clkdivs = <0x01>;

reg = <0x5b00 0x100>;

phandle = <0xa9>;

};

adc_tm@3500 {

#address-cells = <0x01>;

interrupts = <0x00 0x35 0x00 0x01>;

io-channels = <0xa8 0x4c 0xa8 0x4e 0xa8 0x4f 0xa8 0x50>;

#size-cells = <0x00>;

#thermal-sensor-cells = <0x01>;

compatible = "qcom,adc-tm5";

interrupt-names = "thr-int-en";

reg = <0x3500 0x100>;

phandle = <0x7f>;

xo_therm {

qcom,ratiometric;

reg = <0x4c>;

qcom,hw-settle-time = <0xc8>;

};

cpu_therm {

qcom,ratiometric;

reg = <0x4f>;

qcom,hw-settle-time = <0xc8>;

};

pa_therm0 {

qcom,ratiometric;

reg = <0x4e>;

qcom,hw-settle-time = <0xc8>;

};

quiet_therm {

qcom,ratiometric;

reg = <0x50>;

qcom,hw-settle-time = <0xc8>;

};

};

bcl@1d00 {

interrupts = <0x00 0x1d 0x00 0x00 0x00 0x1d 0x01 0x00 0x00 0x1d 0x02 0x00>;

#thermal-sensor-cells = <0x01>;

compatible = "qcom,bcl-v5";

interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2";

reg = <0x1d00 0x100>;

phandle = <0x55>;

};

qcom,pm6150_rtc {

#address-cells = <0x01>;

#size-cells = <0x01>;

qcom,qpnp-rtc-alarm-pwrup = <0x00>;

compatible = "qcom,qpnp-rtc";

phandle = <0x2e8>;

qcom,qpnp-rtc-write = <0x00>;

qcom,pm6150_rtc_rw@6000 {

reg = <0x6000 0x100>;

};

qcom,pm6150_rtc_alarm@6100 {

interrupts = <0x00 0x61 0x01 0x00>;

reg = <0x6100 0x100>;

};

};

qcom,revid@100 {

compatible = "qcom,qpnp-revid";

reg = <0x100 0x100>;

phandle = <0xa4>;

};

qcom,temp-alarm@2400 {

qcom,temperature-threshold-set = <0x01>;

interrupts = <0x00 0x24 0x00 0x01>;

#thermal-sensor-cells = <0x00>;

compatible = "qcom,spmi-temp-alarm";

reg = <0x2400 0x100>;

phandle = <0x54>;

};

bcl-soc {

#thermal-sensor-cells = <0x00>;

compatible = "qcom,msm-bcl-soc";

phandle = <0x56>;

};

};

qcom,pm6150l@4 {

#address-cells = <0x01>;

#size-cells = <0x01>;

compatible = "qcom,spmi-pmic";

reg = <0x04 0x00>;

qcom,power-on@800 {

compatible = "qcom,qpnp-power-on";

reg = <0x800 0x100>;

};

bcl@3d00 {

interrupts = <0x04 0x3d 0x00 0x00 0x04 0x3d 0x01 0x00 0x04 0x3d 0x02 0x00>;

#thermal-sensor-cells = <0x01>;

compatible = "qcom,bcl-v5";

interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2";

reg = <0x3d00 0x100>;

phandle = <0x58>;

};

vadc@3100 {

io-channel-ranges;

#address-cells = <0x01>;

interrupts = <0x04 0x31 0x00 0x01>;

#io-channel-cells = <0x01>;

#size-cells = <0x00>;

compatible = "qcom,spmi-adc5";

qcom,adc-vdd-reference = <0x753>;

interrupt-names = "eoc-int-en-set";

reg = <0x3100 0x100>;

phandle = <0x2ea>;

ref_gnd {

label = "ref_gnd";

qcom,pre-scaling = <0x01 0x01>;

reg = <0x00>;

};

smb_therm {

label = "smb_therm";

qcom,pre-scaling = <0x01 0x01>;

reg = <0x0e>;

qcom,hw-settle-time = <0xc8>;

};

vph_pwr {

label = "vph_pwr";

qcom,pre-scaling = <0x01 0x03>;

reg = <0x83>;

};

charger_therm0 {

label = "charger_therm0";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x4e>;

qcom,hw-settle-time = <0xc8>;

};

vref_1p25 {

label = "vref_1p25";

qcom,pre-scaling = <0x01 0x01>;

reg = <0x01>;

};

conn_therm {

label = "conn_therm";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x4d>;

qcom,hw-settle-time = <0xc8>;

};

wifi_therm {

label = "wifi_therm";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x4f>;

qcom,hw-settle-time = <0xc8>;

};

die_temp {

label = "die_temp";

qcom,pre-scaling = <0x01 0x01>;

reg = <0x06>;

};

nvm_therm {

label = "nvm_therm";

qcom,pre-scaling = <0x01 0x01>;

qcom,ratiometric;

reg = <0x55>;

qcom,hw-settle-time = <0xc8>;

};

};

pinctrl@c000 {

gpio-controller;

interrupts = <0x04 0xc0 0x00 0x00 0x04 0xc1 0x00 0x00 0x04 0xc2 0x00 0x00 0x04 0xc3 0x00 0x00 0x04 0xc4 0x00 0x00 0x04 0xc5 0x00 0x00 0x04 0xc6 0x00 0x00 0x04 0xc7 0x00 0x00 0x04 0xc8 0x00 0x00 0x04 0xc9 0x00 0x00 0x04 0xca 0x00 0x00 0x04 0xcb 0x00 0x00>;

compatible = "qcom,spmi-gpio";

interrupt-names = "pm6150l_gpio1\0pm6150l_gpio2\0pm6150l_gpio3\0pm6150l_gpio4\0pm6150l_gpio5\0pm6150l_gpio6\0pm6150l_gpio7\0pm6150l_gpio8\0pm6150l_gpio9\0pm6150l_gpio10\0pm6150l_gpio11\0pm6150l_gpio12";

reg = <0xc000 0xc00>;

phandle = <0x2ec>;

#gpio-cells = <0x02>;

disp_pins {

disp_pins_default {

function = "func1";

pins = "gpio9";

qcom,drive-strength = <0x02>;

bias-disable;

phandle = <0x2ed>;

power-source = <0x01>;

output-low;

};

};

cam_sensor_w_vdda_vddd_disable {

function = "normal";

pins = "gpio3";

phandle = <0x5a8>;

power-source = <0x00>;

output-low;

};

key_vol_up {

key_vol_up_default {

function = "normal";

pins = "gpio2";

phandle = <0x561>;

bias-pull-up;

power-source = <0x00>;

input-enable;

};

};

aw3644_pwm_default {

function = "normal";

pins = "gpio4";

phandle = <0x5af>;

power-source = <0x00>;

output-low;

};

cam_sensor_w_vdda_vddd_enable {

function = "normal";

pins = "gpio3";

phandle = <0x5a7>;

power-source = <0x00>;

output-low;

};

cam_sensor_u_vdda_vddd_enable {

function = "normal";

pins = "gpio11";

phandle = <0x5ab>;

power-source = <0x01>;

output-low;

};

cam_sensor_u_vdda_vddd_disable {

function = "normal";

pins = "gpio11";

phandle = <0x5ac>;

power-source = <0x01>;

output-low;

};

cam_sensor_d_vdda_vddd_disable {

function = "normal";

pins = "gpio8";

phandle = <0x5aa>;

power-source = <0x01>;

output-low;

};

aw8624_interrupt_pin {

aw8624_interrupt_pin {

function = "normal";

pins = "gpio10";

qcom,pull-up-strength = <0x02>;

phandle = <0x58d>;

bias-pull-up;

power-source = <0x01>;

input-enable;

};

};

aw3644_led_hwen_suspend {

function = "normal";

pins = "gpio12";

phandle = <0x5ae>;

power-source = <0x00>;

output-low;

};

aw3644_led_hwen_active {

function = "normal";

pins = "gpio12";

phandle = <0x5ad>;

power-source = <0x00>;

output-low;

};

cam_sensor_d_vdda_vddd_enable {

function = "normal";

pins = "gpio8";

phandle = <0x5a9>;

power-source = <0x01>;

output-low;

};

};

clock-controller@5b00 {

clock-output-names = "pm6150l_div_clk1";

clock-names = "xo";

assigned-clocks = <0xaa 0x01>;

assigned-clock-rates = <0x927c00>;

clocks = <0x2f 0x00>;

#clock-cells = <0x01>;

compatible = "qcom,spmi-clkdiv";

qcom,num-clkdivs = <0x01>;

reg = <0x5b00 0x100>;

phandle = <0xaa>;

};

adc_tm@3500 {

#address-cells = <0x01>;

interrupts = <0x04 0x35 0x00 0x01>;

io-channels = <0x2ea 0x4d 0x2ea 0x4e 0x2ea 0x4f 0x2ea 0x55>;

#size-cells = <0x00>;

#thermal-sensor-cells = <0x01>;

compatible = "qcom,adc-tm5";

interrupt-names = "thr-int-en";

reg = <0x3500 0x100>;

phandle = <0x2eb>;

charger_therm0 {

qcom,ratiometric;

reg = <0x4e>;

qcom,hw-settle-time = <0xc8>;

};

conn_therm {

qcom,ratiometric;

reg = <0x4d>;

qcom,hw-settle-time = <0xc8>;

};

wifi_therm {

qcom,ratiometric;

reg = <0x4f>;

qcom,hw-settle-time = <0xc8>;

};

nvm_therm {

qcom,ratiometric;

reg = <0x55>;

qcom,hw-settle-time = <0xc8>;

};

};

qcom,revid@100 {

compatible = "qcom,qpnp-revid";

reg = <0x100 0x100>;

phandle = <0xab>;

};

qcom,temp-alarm@2400 {

qcom,temperature-threshold-set = <0x01>;

interrupts = <0x04 0x24 0x00 0x01>;

#thermal-sensor-cells = <0x00>;

compatible = "qcom,spmi-temp-alarm";

reg = <0x2400 0x100>;

phandle = <0x57>;

};

};

qcom,pm8009@b {

#address-cells = <0x01>;

#size-cells = <0x01>;

compatible = "qcom,spmi-pmic";

reg = <0x0b 0x00>;

};

};

qcom,msm-ultra-low-latency {

qcom,msm-pcm-dsp-id = <0x02>;

qcom,latency-level = "ultra";

compatible = "qcom,msm-pcm-dsp";

phandle = <0x260>;

qcom,msm-pcm-low-latency;

};

qcom,mss@4080000 {

qcom,smem-state-names = "qcom,force-stop";

qcom,smem-id = <0x1a5>;

qcom,sysmon-id = <0x00>;

qcom,ssctl-instance-id = <0x12>;

clock-names = "xo";

qcom,msm-bus,name = "pil-modem";

qcom,proxy-timeout-ms = <0x2710>;

memory-region = <0xb1>;

clocks = <0x2f 0x00>;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,vdd_mss-uV-uA = <0x181 0x186a0>;

qcom,signal-aop;

qcom,complete-ramdump;

qcom,pas-id = <0x04>;

qcom,minidump-id = <0x03>;

qcom,aux-minidump-ids = <0x04>;

interrupts-extended = <0x01 0x00 0x10a 0x01 0xb2 0x00 0x00 0xb2 0x01 0x00 0xb2 0x02 0x00 0xb2 0x03 0x00 0xb2 0x07 0x00>;

compatible = "qcom,pil-tz-generic";

qcom,vdd_cx-uV-uA = <0x181 0x186a0>;

interrupt-names = "qcom,wdog\0qcom,err-fatal\0qcom,err-ready\0qcom,proxy-unvote\0qcom,stop-ack\0qcom,shutdown-ack";

reg = <0x4080000 0x100>;

vdd_mss-supply = <0xb0>;

phandle = <0x30d>;

qcom,smem-states = <0xb3 0x00>;

qcom,msm-bus,vectors-KBps = <0x81 0x200 0x00 0x00 0x81 0x200 0x00 0x6acfc0>;

mboxes = <0x1c 0x00>;

vdd_cx-supply = <0x1d>;

qcom,proxy-clock-names = "xo";

qcom,proxy-reg-names = "vdd_cx\0vdd_mss";

qcom,firmware-name = "modem";

mbox-names = "mss-pil";

};

qcom,qup_uart@0xa88000 {

pinctrl-names = "default\0sleep";

pinctrl-0 = <0x180>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

interrupts = <0x00 0x163 0x00>;

clocks = <0x27 0x5b 0x27 0x69 0x27 0x6a>;

qcom,wrapper-core = <0x182>;

compatible = "qcom,msm-geni-console";

pinctrl-1 = <0x181>;

status = "disabled";

reg = <0xa88000 0x4000>;

phandle = <0x359>;

};

rpmh-regulator-ldoa6 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa6";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l6 {

regulator-max-microvolt = <0x13e5c0>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x10b940>;

regulator-min-microvolt = <0x100590>;

regulator-name = "pm6150_l6";

qcom,set = <0x03>;

phandle = <0x406>;

};

};

qcom,msm-dai-q6 {

compatible = "qcom,msm-dai-q6";

qcom,msm-dai-q6-int-fm-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x3004>;

phandle = <0x4aa>;

};

qcom,msm-dai-q6-usb-audio-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x7000>;

phandle = <0x284>;

};

qcom,msm-dai-q6-sb-8-tx {

qcom,msm-dai-q6-slim-dev-id = <0x00>;

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4011>;

phandle = <0x280>;

};

qcom,msm-dai-q6-sb-5-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x400b>;

phandle = <0x4a3>;

};

qcom,msm-dai-q6-sb-2-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4005>;

phandle = <0x49e>;

};

qcom,msm-dai-q6-sb-8-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4010>;

phandle = <0x281>;

};

qcom,msm-dai-q6-sb-5-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x400a>;

phandle = <0x4a4>;

};

qcom,msm-dai-q6-sb-2-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4004>;

phandle = <0x49d>;

};

qcom,msm-dai-q6-incall-record-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x8004>;

phandle = <0x27b>;

};

qcom,msm-dai-q6-incall-record-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x8003>;

phandle = <0x27a>;

};

qcom,msm-dai-q6-incall-music-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x8005>;

phandle = <0x27c>;

};

qcom,msm-dai-q6-incall-music-2-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x8002>;

phandle = <0x27d>;

};

qcom,msm-dai-q6-proxy-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x2003>;

phandle = <0x283>;

};

qcom,msm-dai-q6-sb-7-tx {

qcom,msm-dai-q6-slim-dev-id = <0x00>;

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x400f>;

phandle = <0x27f>;

};

qcom,msm-dai-q6-sb-4-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4009>;

phandle = <0x4a2>;

};

qcom,msm-dai-q6-proxy-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x2002>;

phandle = <0x282>;

};

qcom,msm-dai-q6-sb-1-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4003>;

phandle = <0x49c>;

};

qcom,msm-dai-q6-sb-7-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x400e>;

phandle = <0x27e>;

};

qcom,msm-dai-q6-sb-4-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4008>;

phandle = <0x4a1>;

};

qcom,msm-dai-q6-sb-1-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4002>;

phandle = <0x49b>;

};

qcom,msm-dai-q6-be-afe-pcm-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0xe1>;

phandle = <0x277>;

};

qcom,msm-dai-q6-be-afe-pcm-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0xe0>;

phandle = <0x276>;

};

qcom,msm-dai-q6-sb-9-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4013>;

phandle = <0x4a7>;

};

qcom,msm-dai-q6-sb-3-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4007>;

phandle = <0x4a0>;

};

qcom,msm-dai-q6-sb-9-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4012>;

phandle = <0x4a6>;

};

qcom,msm-dai-q6-sb-0-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4001>;

phandle = <0x49a>;

};

qcom,msm-dai-q6-sb-6-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x400c>;

phandle = <0x4a5>;

};

qcom,msm-dai-q6-sb-3-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4006>;

phandle = <0x49f>;

};

qcom,msm-dai-q6-bt-sco-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x3001>;

phandle = <0x4a9>;

};

qcom,msm-dai-q6-sb-0-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x4000>;

phandle = <0x499>;

};

qcom,msm-dai-q6-bt-sco-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x3000>;

phandle = <0x4a8>;

};

qcom,msm-dai-q6-afe-proxy-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0xf0>;

phandle = <0x279>;

};

qcom,msm-dai-q6-int-fm-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x3005>;

phandle = <0x4ab>;

};

qcom,msm-dai-q6-afe-proxy-rx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0xf1>;

phandle = <0x278>;

};

qcom,msm-dai-q6-usb-audio-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x7001>;

phandle = <0x285>;

};

};

qcom,avtimer@62CF7000 {

reg-names = "avtimer_lsb_addr\0avtimer_msb_addr";

qcom,clk-div = <0xc0>;

compatible = "qcom,avtimer";

qcom,clk-mult = <0x0a>;

reg = <0x62cf700c 0x04 0x62cf7010 0x04>;

};

dummy_source {

qcom,dummy-source;

coresight-name = "coresight-tpdm-lpass";

compatible = "qcom,coresight-dummy";

phandle = <0x447>;

port {

endpoint {

remote-endpoint = <0x22c>;

phandle = <0x1df>;

};

};

};

qcom,dsi-display@25 {

qcom,dsi-phy-num = <0x00 0x01>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x539>;

qcom,dsi-ctrl-num = <0x00 0x01>;

qcom,display-type = "primary";

label = "dsi_sharp_qsync_fhd_cmd_display";

phandle = <0x55a>;

};

cti@6b06000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-swao_cti2";

compatible = "arm,primecell";

reg = <0x6b06000 0x1000>;

phandle = <0x471>;

};

qcom,rmtfs_sharedmem@0 {

reg-names = "rmtfs";

qcom,client-id = <0x01>;

qcom,guard-memory;

compatible = "qcom,sharedmem-uio";

reg = <0x00 0x200000>;

};

sdhci@7c4000 {

pinctrl-names = "active\0sleep";

qcom,large-address-bus;

qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;

qcom,pm-qos-cmdq-latency-us = <0x43 0x43 0x43 0x43>;

pinctrl-0 = <0x3dd 0x3df 0x3e1 0x3e3>;

clock-names = "iface_clk\0core_clk\0ice_core_clk";

qcom,bus-width = <0x08>;

reg-names = "hc_mem\0cmdq_mem\0cmdq_ice";

qcom,msm-bus,name = "sdhc1";

qcom,pm-qos-irq-latency = <0x43 0x43>;

qcom,pm-qos-legacy-latency-us = <0x43 0x43 0x43 0x43>;

interrupts = <0x00 0x281 0x00 0x00 0x284 0x00>;

qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xb71b000 0x16e36000>;

clocks = <0x27 0x6b 0x27 0x6c 0x27 0x6e>;

qcom,msm-bus,num-paths = <0x02>;

qcom,msm-bus,num-cases = <0x09>;

qcom,vdd-io-current-level = <0x00 0x4f588>;

qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x60152b0 0xbebc200 0x17d78400 0xffffffff>;

qcom,pm-qos-cpu-groups = <0x3f 0xc0>;

qcom,pm-qos-irq-type = "affine_irq";

qcom,ice-clk-rates = <0x11e1a300 0x47868c0>;

vdd-supply = <0x40d>;

compatible = "qcom,sdhci-msm-v5";

qcom,devfreq,freq-table = <0x2faf080 0xbebc200>;

qcom,vdd-io-lpm-sup;

vdd-io-supply = <0x407>;

pinctrl-1 = <0x3de 0x3e0 0x3e2 0x3e4>;

qcom,vdd-current-level = <0x00 0x8b290>;

status = "ok";

qcom,dll-hsr-list = <0xf642c 0x00 0x00 0x10800 0x80040868>;

interrupt-names = "hc_irq\0pwr_irq";

reg = <0x7c4000 0x1000 0x7c5000 0x1000 0x7c8000 0x8000>;

phandle = <0x2d8>;

qcom,msm-bus,vectors-KBps = <0x96 0x200 0x00 0x00 0x01 0x326 0x00 0x00 0x96 0x200 0x3e8 0x7d0 0x01 0x326 0x7d0 0xfa0 0x96 0x200 0x61a8 0xc350 0x01 0x326 0x4e20 0x9c40 0x96 0x200 0xc350 0x186a0 0x01 0x326 0x7530 0xea60 0x96 0x200 0x13880 0x249f0 0x01 0x326 0x9c40 0x13880 0x96 0x200 0x186a0 0x30d40 0x01 0x326 0xc350 0x186a0 0x96 0x200 0x249f0 0x3d090 0x01 0x326 0x13880 0x1d4c0 0x96 0x200 0x3fd3e 0x297c66 0x01 0x326 0x493e0 0x14be33 0x96 0x200 0x146cc2 0x3e8000 0x01 0x326 0x146cc2 0x3e8000>;

qcom,vdd-io-always-on;

qcom,bus-speed-mode = "HS400_1p8v\0HS200_1p8v\0DDR_1p8v";

qcom,scaling-lower-bus-speed-mode = "DDR52";

qcom,vdd-io-voltage-level = <0x1b7740 0x1b7740>;

qcom,nonremovable;

};

wsa_spkr_en2_pinctrl {

pinctrl-names = "aud_active\0aud_sleep";

pinctrl-0 = <0x3d3>;

compatible = "qcom,msm-cdc-pinctrl";

pinctrl-1 = <0x3d2>;

status = "disabled";

phandle = <0x4ea>;

};

va_core_clk {

qcom,codec-ext-clk-src = <0x02>;

#clock-cells = <0x01>;

compatible = "qcom,audio-ref-clk";

phandle = <0x4eb>;

qcom,codec-lpass-clk-id = <0x30b>;

qcom,codec-lpass-ext-clk-freq = <0x124f800>;

};

gpio-regulator@1 {

regulator-max-microvolt = <0x1b7740>;

gpio = <0x2ec 0x08 0x00>;

regulator-enable-ramp-delay = <0x64>;

enable-active-high;

regulator-min-microvolt = <0x1b7740>;

regulator-name = "camera_vddio_depth_regulator";

compatible = "regulator-fixed";

reg = <0x01 0x00>;

phandle = <0x579>;

vin-supply = <0x3fe>;

};

qcom,gdsc@509100c {

qcom,poll-cfg-gdscr;

clock-names = "core_root_clk";

parent-supply = <0x20>;

clocks = <0x2b 0x12>;

domain-addr = <0xcd>;

regulator-name = "gpu_gx_gdsc";

qcom,reset-aon-logic;

compatible = "qcom,gdsc";

qcom,force-enable-root-clk;

status = "ok";

reg = <0x509100c 0x04>;

sw-reset = <0xce>;

phandle = <0x24e>;

};

apps-smmu@0x15000000 {

#global-interrupts = <0x01>;

#address-cells = <0x01>;

reg-names = "base\0tcu-base";

qcom,msm-bus,name = "apps_smmu";

qcom,msm-bus,active-only;

interrupts = <0x00 0x41 0x04 0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0xb5 0x04 0x00 0xb6 0x04 0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x13e 0x04 0x00 0x13f 0x04 0x00 0x140 0x04 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04 0x00 0x18e 0x04 0x00 0x18f 0x04 0x00 0x190 0x04 0x00 0x191 0x04 0x00 0x192 0x04 0x00 0x193 0x04 0x00 0x194 0x04 0x00 0x195 0x04 0x00 0x196 0x04 0x00 0x197 0x04 0x00 0x198 0x04 0x00 0x199 0x04 0x00 0x19a 0x04 0x00 0x19b 0x04 0x00 0x19c 0x04 0x00 0x19d 0x04>;

qcom,actlr = <0x800 0x7ff 0x103 0x1000 0x3ff 0x103 0x1460 0x1f 0x303>;

qcom,msm-bus,num-paths = <0x01>;

#size-cells = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,skip-init;

qcom,use-3-lvl-tables;

#iommu-cells = <0x02>;

compatible = "qcom,qsmmu-v500";

ranges;

reg = <0x15000000 0x100000 0x15182000 0x20>;

phandle = <0x30>;

qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>;

anoc_1_tbu@0x15185000 {

reg-names = "base\0status-reg";

qcom,msm-bus,name = "apps_smmu";

qcom,msm-bus,active-only;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,stream-id-range = <0x00 0x400>;

qcom,regulator-names = "vdd";

vdd-supply = <0x1c6>;

compatible = "qcom,qsmmuv500-tbu";

reg = <0x15185000 0x1000 0x15182200 0x08>;

phandle = <0x39c>;

qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>;

};

mnoc_sf_0_tbu@0x15195000 {

reg-names = "base\0status-reg";

qcom,msm-bus,name = "mnoc_sf_0_tbu";

qcom,msm-bus,active-only;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,stream-id-range = <0x1000 0x400>;

qcom,regulator-names = "vdd";

vdd-supply = <0x1ca>;

compatible = "qcom,qsmmuv500-tbu";

reg = <0x15195000 0x1000 0x15182220 0x08>;

phandle = <0x3a0>;

qcom,msm-bus,vectors-KBps = <0x89 0x304 0x00 0x00 0x89 0x304 0x00 0x3e8>;

};

mnoc_hf_0_tbu@0x1518d000 {

reg-names = "base\0status-reg";

qcom,msm-bus,name = "mnoc_hf_0_tbu";

qcom,msm-bus,active-only;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,stream-id-range = <0x800 0x400>;

qcom,regulator-names = "vdd";

vdd-supply = <0x1c8>;

compatible = "qcom,qsmmuv500-tbu";

reg = <0x1518d000 0x1000 0x15182210 0x08>;

phandle = <0x39e>;

qcom,msm-bus,vectors-KBps = <0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8>;

};

mnoc_hf_1_tbu@0x15191000 {

reg-names = "base\0status-reg";

qcom,msm-bus,name = "mnoc_hf_1_tbu";

qcom,msm-bus,active-only;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,stream-id-range = <0xc00 0x400>;

qcom,regulator-names = "vdd";

vdd-supply = <0x1c9>;

compatible = "qcom,qsmmuv500-tbu";

reg = <0x15191000 0x1000 0x15182218 0x08>;

phandle = <0x39f>;

qcom,msm-bus,vectors-KBps = <0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8>;

};

compute_dsp_0_tbu@0x15199000 {

reg-names = "base\0status-reg";

qcom,msm-bus,name = "apps_smmu";

qcom,msm-bus,active-only;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,stream-id-range = <0x1400 0x400>;

compatible = "qcom,qsmmuv500-tbu";

reg = <0x15199000 0x1000 0x15182228 0x08>;

phandle = <0x3a1>;

qcom,msm-bus,vectors-KBps = <0x9a 0x275c 0x00 0x00 0x9a 0x275c 0x00 0x3e8>;

};

anoc_2_tbu@0x15189000 {

reg-names = "base\0status-reg";

qcom,msm-bus,name = "apps_smmu";

qcom,msm-bus,active-only;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,stream-id-range = <0x400 0x400>;

qcom,regulator-names = "vdd";

vdd-supply = <0x1c7>;

compatible = "qcom,qsmmuv500-tbu";

reg = <0x15189000 0x1000 0x15182208 0x08>;

phandle = <0x39d>;

qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>;

};

adsp_tbu@0x1519d000 {

reg-names = "base\0status-reg";

qcom,msm-bus,name = "apps_smmu";

qcom,msm-bus,active-only;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,stream-id-range = <0x1800 0x400>;

qcom,regulator-names = "vdd";

vdd-supply = <0x1cb>;

compatible = "qcom,qsmmuv500-tbu";

reg = <0x1519d000 0x1000 0x15182230 0x08>;

phandle = <0x3a2>;

qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>;

};

anoc_1_pcie_tbu@0x151a1000 {

clock-names = "gcc_aggre_noc_pcie_tbu_clk";

reg-names = "base\0status-reg";

qcom,msm-bus,name = "apps_smmu";

qcom,msm-bus,active-only;

clocks = <0x27 0x08>;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,stream-id-range = <0x1c00 0x400>;

qcom,regulator-names = "vdd";

vdd-supply = <0x1cc>;

compatible = "qcom,qsmmuv500-tbu";

reg = <0x151a1000 0x1000 0x15182238 0x08>;

phandle = <0x3a3>;

qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>;

};

};

cpu-pmu {

interrupts = <0x01 0x05 0x04>;

qcom,irq-is-percpu;

compatible = "arm,armv8-pmuv3";

phandle = <0x2b3>;

};

tpda@6004000 {

arm,primecell-periphid = <0x3b969>;

qcom,cmb-elem-size = <0x03 0x40 0x07 0x40 0x0d 0x40>;

clock-names = "apb_pclk";

reg-names = "tpda-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpda";

qcom,dsb-elem-size = <0x00 0x20 0x02 0x20 0x03 0x20 0x05 0x20 0x06 0x20 0x0a 0x20 0x0b 0x20 0x0d 0x20>;

qcom,tc-elem-size = <0x0d 0x20>;

compatible = "arm,primecell";

qcom,tpda-atid = <0x41>;

qcom,bc-elem-size = <0x0a 0x20 0x0d 0x20>;

reg = <0x6004000 0x1000>;

phandle = <0x449>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x22e>;

phandle = <0x227>;

};

};

port@14 {

reg = <0x11>;

endpoint {

slave-mode;

remote-endpoint = <0x23c>;

phandle = <0x23d>;

};

};

port@9 {

reg = <0x0b>;

endpoint {

slave-mode;

remote-endpoint = <0x237>;

phandle = <0x254>;

};

};

port@12 {

reg = <0x0e>;

endpoint {

slave-mode;

remote-endpoint = <0x23a>;

phandle = <0x258>;

};

};

port@7 {

reg = <0x08>;

endpoint {

slave-mode;

remote-endpoint = <0x235>;

phandle = <0x252>;

};

};

port@10 {

reg = <0x0c>;

endpoint {

slave-mode;

remote-endpoint = <0x238>;

phandle = <0x255>;

};

};

port@5 {

reg = <0x06>;

endpoint {

slave-mode;

remote-endpoint = <0x233>;

phandle = <0x24b>;

};

};

port@3 {

reg = <0x03>;

endpoint {

slave-mode;

remote-endpoint = <0x231>;

phandle = <0x242>;

};

};

port@1 {

reg = <0x01>;

endpoint {

slave-mode;

remote-endpoint = <0x22f>;

phandle = <0x23e>;

};

};

port@13 {

reg = <0x0f>;

endpoint {

slave-mode;

remote-endpoint = <0x23b>;

phandle = <0x257>;

};

};

port@8 {

reg = <0x0a>;

endpoint {

slave-mode;

remote-endpoint = <0x236>;

phandle = <0x253>;

};

};

port@11 {

reg = <0x0d>;

endpoint {

slave-mode;

remote-endpoint = <0x239>;

phandle = <0x256>;

};

};

port@6 {

reg = <0x07>;

endpoint {

slave-mode;

remote-endpoint = <0x234>;

phandle = <0x24f>;

};

};

port@4 {

reg = <0x05>;

endpoint {

slave-mode;

remote-endpoint = <0x232>;

phandle = <0x245>;

};

};

port@2 {

reg = <0x02>;

endpoint {

slave-mode;

remote-endpoint = <0x230>;

phandle = <0x241>;

};

};

};

};

tpdm@6a00000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-ddr";

compatible = "arm,primecell";

reg = <0x6a00000 0x1000>;

phandle = <0x454>;

qcom,msr-fix-req;

port {

endpoint {

remote-endpoint = <0x24d>;

phandle = <0x24c>;

};

};

};

qcom,msm-quin-auxpcm {

qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;

qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;

qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;

qcom,msm-auxpcm-interface = "quinary";

qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;

qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;

qcom,msm-cpudai-afe-clk-ver = <0x02>;

qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;

compatible = "qcom,msm-auxpcm-dev";

qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;

phandle = <0x275>;

qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;

};

qcom,dsi-display@3 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x525>;

qcom,dsi-ctrl-num = <0x00>;

qcom,dsi-display-active;

qcom,display-type = "primary";

label = "dsi_sim_vid_display";

phandle = <0x542>;

};

ufshc@1d84000 {

vcc-max-microamp = <0x927c0>;

pinctrl-names = "dev-reset-assert\0dev-reset-deassert";

freq-table-hz = <0x2faf080 0xbebc200 0x00 0x00 0x00 0x00 0x23c3460 0x8f0d180 0x47868c0 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00>;

qcom,pm-qos-cpu-group-latency-us = <0x43 0x43>;

spm-level = <0x03>;

phy-names = "ufsphy";

pinctrl-0 = <0x9d>;

clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk";

reg-names = "ufs_mem\0ufs_ice";

qcom,bus-vector-names = "MIN\0PWM_G1_L1\0PWM_G2_L1\0PWM_G3_L1\0PWM_G4_L1\0HS_RA_G1_L1\0HS_RA_G2_L1\0HS_RA_G3_L1\0HS_RB_G1_L1\0HS_RB_G2_L1\0HS_RB_G3_L1\0MAX";

vcc-voltage-level = <0x2d0370 0x2d2a80>;

qcom,msm-bus,name = "ufshc_mem";

non-removable;

lanes-per-direction = <0x01>;

qcom,vddp-ref-clk-max-microamp = <0x64>;

resets = <0x27 0x03>;

interrupts = <0x00 0x109 0x00>;

clocks = <0x27 0x7e 0x27 0x09 0x27 0x7d 0x27 0x89 0x27 0x81 0x2f 0x00 0x27 0x88 0x27 0x87>;

dev-ref-clk-freq = <0x00>;

vccq2-supply = <0x407>;

qcom,msm-bus,num-paths = <0x02>;

qcom,msm-bus,num-cases = <0x0c>;

vdd-hba-fixed-regulator;

qcom,pm-qos-cpu-groups = <0x3f 0xc0>;

rpm-level = <0x03>;

compatible = "qcom,ufshc";

pinctrl-1 = <0x9e>;

status = "ok";

phys = <0x9c>;

vdd-hba-supply = <0x9b>;

reg = <0x1d84000 0x3000 0x1d90000 0x8000>;

phandle = <0x2de>;

vccq2-voltage-level = <0x1b7740 0x1dc130>;

qcom,msm-bus,vectors-KBps = <0x7b 0x200 0x00 0x00 0x01 0x2f5 0x00 0x00 0x7b 0x200 0x39a 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x734 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0xe68 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1cd0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1f334 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x3e667 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x247ae 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x48ccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x74a000 0x00 0x01 0x2f5 0x4b000 0x00>;

vccq2-max-microamp = <0x927c0>;

reset-names = "core_reset";

vcc-supply = <0x40d>;

qcom,pm-qos-default-cpu = <0x00>;

qcom,vddp-ref-clk-supply = <0x1a8>;

};

wsa_npl_clk {

qcom,codec-ext-clk-src = <0x04>;

#clock-cells = <0x01>;

compatible = "qcom,audio-ref-clk";

phandle = <0x4e7>;

qcom,codec-lpass-clk-id = <0x30a>;

qcom,codec-lpass-ext-clk-freq = <0x124f800>;

};

qcom,smp2p-adsp {

qcom,local-pid = <0x00>;

interrupts = <0x00 0xac 0x01>;

qcom,remote-pid = <0x02>;

compatible = "qcom,smp2p";

qcom,smem = <0x1bb 0x1ad>;

qcom,ipc = <0x99 0x00 0x1a>;

qcom,smp2p-rdbg2-out {

qcom,entry-name = "rdbg";

#qcom,smem-state-cells = <0x01>;

phandle = <0x1bc>;

};

slave-kernel {

qcom,entry-name = "slave-kernel";

#interrupt-cells = <0x02>;

phandle = <0xa2>;

interrupt-controller;

};

qcom,sleepstate-in {

qcom,entry-name = "sleepstate_see";

#interrupt-cells = <0x02>;

phandle = <0x98>;

interrupt-controller;

};

sleepstate-out {

qcom,entry-name = "sleepstate";

#qcom,smem-state-cells = <0x01>;

phandle = <0x97>;

};

master-kernel {

qcom,entry-name = "master-kernel";

#qcom,smem-state-cells = <0x01>;

phandle = <0xa3>;

};

qcom,smp2p-rdbg2-in {

qcom,entry-name = "rdbg";

#interrupt-cells = <0x02>;

phandle = <0x1bd>;

interrupt-controller;

};

};

qcom,dsi-display@15 {

qcom,dsi-phy-num = <0x01>;

qcom,dsi-select-clocks = "mux_byte_clk1\0mux_pixel_clk1";

qcom,dsi-panel = <0x52f>;

qcom,dsi-ctrl-num = <0x01>;

qcom,display-type = "secondary";

label = "dsi_nt35695b_truly_fhd_video_sec_display";

phandle = <0x55c>;

};

cdc_dmic01_pinctrl {

pinctrl-names = "aud_active\0aud_sleep";

pinctrl-0 = <0x4f7 0x4f8>;

compatible = "qcom,msm-cdc-pinctrl";

qcom,lpi-gpios;

pinctrl-1 = <0x4f9 0x4fa>;

phandle = <0x4ef>;

};

qcom,mdss_dsi_phy1@ae96400 {

qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00];

reg-names = "dsi_phy\0dyn_refresh_base";

cell-index = <0x01>;

label = "dsi-phy-1";

qcom,platform-lane-config = <0x00 0x00 0x00 0x00 0x80>;

compatible = "qcom,dsi-phy-v3.0";

vdda-0p9-supply = <0x1a9>;

qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];

reg = <0xae96400 0x7c0 0xae96200 0x100>;

phandle = <0x375>;

qcom,phy-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,phy-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x8ca0>;

qcom,supply-name = "vdda-0p9";

qcom,supply-max-voltage = <0xe09c0>;

reg = <0x00>;

qcom,supply-min-voltage = <0xc92c0>;

};

};

};

qcom,kgsl-hyp {

qcom,pas-id = <0x0d>;

compatible = "qcom,pil-tz-generic";

phandle = <0x4ce>;

qcom,firmware-name = "a615_zap";

};

tsens@c222000 {

reg-names = "tsens_srot_physical\0tsens_tm_physical";

interrupts = <0x00 0x1fa 0x00 0x00 0x1fc 0x00>;

#thermal-sensor-cells = <0x01>;

compatible = "qcom,tsens24xx";

interrupt-names = "tsens-upper-lower\0tsens-critical";

reg = <0xc222000 0x08 0xc263000 0x1ff>;

phandle = <0x59>;

tsens-reinit-wa;

};

qcom,cpu6-cpu-l3-lat {

clock-names = "devfreq_clk";

clocks = <0xc0 0x01>;

governor = "performance";

compatible = "devfreq-simple-dev";

phandle = <0x25>;

};

rpmh-regulator-ldoc4 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoc4";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150l-l4 {

regulator-max-microvolt = <0x2d0370>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x192580>;

regulator-min-microvolt = <0x192580>;

regulator-name = "pm6150l_l4";

qcom,set = <0x03>;

phandle = <0x40e>;

};

};

usb_audio_qmi_dev {

iommus = <0x30 0x1b2f 0x00>;

qcom,usb-audio-intr-num = <0x02>;

compatible = "qcom,usb-audio-qmi-dev";

qcom,usb-audio-stream-id = <0x0f>;

};

qcom,msm-adsprpc-mem {

restrict-access;

memory-region = <0x92>;

compatible = "qcom,msm-adsprpc-mem-region";

};

qcom,msm_hdcp {

compatible = "qcom,msm-hdcp";

phandle = <0x2e0>;

};

ad-hoc-bus {

reg-names = "aggre1_noc-base\0aggre2_noc-base\0config_noc-base\0dc_noc-base\0gem_noc-base\0mc_virt-base\0mmss_noc-base\0system_noc-base\0ipa_virt-base\0camnoc_virt-base\0compute_noc-base";

compatible = "qcom,msm-bus-device";

reg = <0x16e0000 0x11080 0x1700000 0x1f080 0x1500000 0x28000 0x9160000 0x3200 0x9680000 0x3e200 0x1380000 0x40000 0x1740000 0x1c100 0x1620000 0x18080 0x1620000 0x40000 0x1620000 0x40000 0x80a8000 0x1400>;

phandle = <0x322>;

mboxes = <0x1b 0x00 0xcf 0x00>;

mbox-names = "apps_rsc\0disp_rsc";

mas-qhm-gemnoc-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x9d>;

qcom,buswidth = <0x04>;

label = "mas-qhm-gemnoc-cfg";

qcom,connections = <0x11b 0x11c>;

phandle = <0x14b>;

qcom,bus-dev = <0x118>;

};

slv-qns-gemnoc-gc {

qcom,agg-ports = <0x01>;

cell-id = <0x2758>;

qcom,buswidth = <0x08>;

label = "slv-qns-gemnoc-gc";

qcom,connections = <0x157>;

phandle = <0x133>;

qcom,bcms = <0x158>;

qcom,bus-dev = <0x128>;

};

mas-qhm-mnoc-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x67>;

qcom,buswidth = <0x04>;

label = "mas-qhm-mnoc-cfg";

qcom,connections = <0x121>;

phandle = <0x148>;

qcom,bus-dev = <0x122>;

};

bcm-mm3_display {

qcom,rscs = <0xd1>;

cell-id = <0x697d>;

label = "MM3_DISPLAY";

qcom,bcm-name = "MM3";

phandle = <0x13e>;

qcom,bcm-dev;

};

mas-qnm-gemnoc {

qcom,agg-ports = <0x01>;

cell-id = <0xa1>;

qcom,buswidth = <0x08>;

label = "mas-qnm-gemnoc";

qcom,connections = <0x12a 0x12b 0x12c 0x12d 0x130 0x12e>;

phandle = <0x14c>;

qcom,bcms = <0x132>;

qcom,bus-dev = <0x128>;

};

mas-qhm-tsif {

qcom,agg-ports = <0x01>;

cell-id = <0x52>;

qcom,buswidth = <0x04>;

label = "mas-qhm-tsif";

qcom,connections = <0xd4>;

phandle = <0x325>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xd3>;

};

bcm-alc {

qcom,rscs = <0xd0>;

cell-id = <0x1b7f>;

label = "ALC";

qcom,bcm-name = "ALC";

phandle = <0x135>;

qcom,bcm-dev;

};

slv-qhs-snoc-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x282>;

qcom,buswidth = <0x04>;

label = "slv-qhs-snoc-cfg";

qcom,connections = <0x149>;

phandle = <0xf8>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

bcm-sn12 {

qcom,rscs = <0xd0>;

cell-id = <0x1b76>;

label = "SN12";

qcom,bcm-name = "SN12";

phandle = <0x134>;

qcom,bcm-dev;

};

bcm-sn0 {

qcom,rscs = <0xd0>;

cell-id = <0x1b6a>;

label = "SN0";

qcom,bcm-name = "SN0";

phandle = <0x15a>;

qcom,bcm-dev;

};

slv-qns2-mem-noc_display {

qcom,agg-ports = <0x01>;

cell-id = <0x5022>;

qcom,buswidth = <0x20>;

label = "slv-qns2-mem-noc_display";

qcom,connections = <0x161>;

phandle = <0x13d>;

qcom,bcms = <0x162>;

qcom,bus-dev = <0x13b>;

};

bcm-acv_display {

qcom,rscs = <0xd1>;

cell-id = <0x697e>;

label = "ACV_DISPLAY";

qcom,bcm-name = "ACV";

phandle = <0x160>;

qcom,bcm-dev;

};

slv-qns-a2noc-snoc {

qcom,agg-ports = <0x01>;

cell-id = <0x2751>;

qcom,buswidth = <0x10>;

label = "slv-qns-a2noc-snoc";

qcom,connections = <0x140>;

phandle = <0xd9>;

qcom,bcms = <0x131>;

qcom,bus-dev = <0xd8>;

};

mas-qnm-mnoc-sf {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0x85>;

qcom,buswidth = <0x20>;

label = "mas-qnm-mnoc-sf";

qcom,forwarding;

qcom,connections = <0x116 0x117>;

qcom,qport = <0x140>;

phandle = <0x153>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x118>;

};

slv-srvc-cnoc {

qcom,agg-ports = <0x01>;

cell-id = <0x286>;

qcom,buswidth = <0x04>;

label = "slv-srvc-cnoc";

phandle = <0x101>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qhs-venus-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x254>;

qcom,buswidth = <0x04>;

label = "slv-qhs-venus-cfg";

phandle = <0xfa>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

qcom,disable-ports = <0x4b 0x4c>;

};

slv-qhs-pdm {

qcom,agg-ports = <0x01>;

cell-id = <0x267>;

qcom,buswidth = <0x04>;

label = "slv-qhs-pdm";

phandle = <0xec>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

bcm-mm0 {

qcom,rscs = <0xd0>;

cell-id = <0x1b63>;

label = "MM0";

qcom,bcm-name = "MM0";

phandle = <0x155>;

qcom,bcm-dev;

};

slv-qns-llcc {

qcom,agg-ports = <0x02>;

cell-id = <0x302>;

qcom,buswidth = <0x10>;

label = "slv-qns-llcc";

qcom,connections = <0x14e>;

phandle = <0x116>;

qcom,bcms = <0x14f>;

qcom,bus-dev = <0x118>;

};

slv-qhs-ipa {

qcom,agg-ports = <0x01>;

cell-id = <0x2a4>;

qcom,buswidth = <0x04>;

label = "slv-qhs-ipa";

phandle = <0x105>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qhs-ahb2phy-north {

qcom,agg-ports = <0x01>;

cell-id = <0x327>;

qcom,buswidth = <0x04>;

label = "slv-qhs-ahb2phy-north";

phandle = <0xf7>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

bcm-cn0 {

qcom,rscs = <0xd0>;

cell-id = <0x1b7c>;

label = "CN0";

qcom,bcm-name = "CN0";

phandle = <0xd6>;

qcom,bcm-dev;

};

slv-qhs-camera-nrt-thrott-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x328>;

qcom,buswidth = <0x04>;

label = "slv-qhs-camera-nrt-throttle-cfg";

phandle = <0xed>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

bcm-sn9 {

qcom,rscs = <0xd0>;

cell-id = <0x1b73>;

label = "SN9";

qcom,bcm-name = "SN9";

phandle = <0x12f>;

qcom,bcm-dev;

};

bcm-sh2 {

qcom,rscs = <0xd0>;

cell-id = <0x1b5d>;

label = "SH2";

qcom,bcm-name = "SH2";

phandle = <0x14d>;

qcom,bcm-dev;

};

slv-qhs-ufs-mem-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x2f5>;

qcom,buswidth = <0x04>;

label = "slv-qhs-ufs-mem-cfg";

phandle = <0xe9>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qhs-tlmm-west {

qcom,agg-ports = <0x01>;

cell-id = <0x2dc>;

qcom,buswidth = <0x04>;

label = "slv-qhs-tlmm-west";

phandle = <0x107>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

fab-mc_virt {

qcom,base-name = "mc_virt-base";

qcom,sbm-offset = <0x00>;

cell-id = <0x1807>;

qcom,bypass-qos-prg;

clocks;

label = "fab-mc_virt";

qcom,base-offset = <0x00>;

qcom,fab-dev;

phandle = <0x120>;

qcom,qos-off = <0x00>;

};

slv-qhs-camera-rt-throttle-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x329>;

qcom,buswidth = <0x04>;

label = "slv-qhs-camera-rt-throttle-cfg";

phandle = <0xf0>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

bcm-mc0_display {

qcom,rscs = <0xd1>;

cell-id = <0x6978>;

label = "MC0_DISPLAY";

qcom,bcm-name = "MC0";

phandle = <0x15f>;

qcom,bcm-dev;

};

mas-qxm-mdp0_display {

qcom,agg-ports = <0x01>;

cell-id = <0x4e23>;

qcom,buswidth = <0x20>;

label = "mas-qxm-mdp0_display";

qcom,connections = <0x13a>;

qcom,qport = <0x60>;

phandle = <0x349>;

qcom,bcms = <0x13c>;

qcom,bus-dev = <0x13b>;

};

slv-qhs-usb3-0 {

qcom,agg-ports = <0x01>;

cell-id = <0x247>;

qcom,buswidth = <0x04>;

label = "slv-qhs-usb3-0";

phandle = <0x103>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-qhm-qup-north {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x98>;

qcom,buswidth = <0x04>;

label = "mas-qhm-qup-north";

qcom,connections = <0xd9>;

qcom,qport = <0x00>;

phandle = <0x32b>;

qcom,bcms = <0xd5>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd8>;

};

slv-qns-mem-noc-hf {

qcom,agg-ports = <0x02>;

cell-id = <0x305>;

qcom,buswidth = <0x20>;

label = "slv-qns-mem-noc-hf";

qcom,connections = <0x154>;

phandle = <0x123>;

qcom,bcms = <0x155>;

qcom,bus-dev = <0x122>;

};

slv-qns2-mem-noc {

qcom,agg-ports = <0x01>;

cell-id = <0x304>;

qcom,buswidth = <0x20>;

label = "slv-qns2-mem-noc";

qcom,connections = <0x153>;

phandle = <0x124>;

qcom,bcms = <0x125>;

qcom,bus-dev = <0x122>;

};

mas-qxm-camnoc-rt {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0xac>;

qcom,buswidth = <0x20>;

label = "mas-qxm-camnoc-rt";

qcom,forwarding;

qcom,connections = <0x123>;

qcom,qport = <0x101>;

phandle = <0x33e>;

qcom,bcms = <0xde>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x122>;

};

fab-ipa_virt {

qcom,base-name = "ipa_virt-base";

qcom,sbm-offset = <0x00>;

cell-id = <0x1809>;

qcom,bypass-qos-prg;

clocks;

label = "fab-ipa_virt";

qcom,base-offset = <0x00>;

qcom,fab-dev;

phandle = <0x11e>;

qcom,qos-off = <0x00>;

};

slv-qns-cnoc-a2noc {

qcom,agg-ports = <0x01>;

cell-id = <0x2d5>;

qcom,buswidth = <0x08>;

label = "slv-qns-cnoc-a2noc";

qcom,connections = <0x14a>;

phandle = <0xe2>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-xm-ufs-mem {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x7b>;

qcom,buswidth = <0x08>;

label = "mas-xm-ufs-mem";

qcom,connections = <0xd4>;

qcom,qport = <0x04>;

phandle = <0x329>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd3>;

qcom,node-qos-clks {

clock-names = "clk-aggre-ufs-phy-axi-no-rate";

clocks = <0x27 0x09>;

};

};

mas-xm-qdss-dap {

qcom,agg-ports = <0x01>;

cell-id = <0x4c>;

qcom,buswidth = <0x08>;

label = "mas-xm-qdss-dap";

qcom,connections = <0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xe2 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109 0x10a 0x10b 0x10c 0x10d 0x10e 0x10f 0x110 0x111 0x112>;

phandle = <0x337>;

qcom,bus-dev = <0xe3>;

};

fab-gem_noc {

qcom,base-name = "gem_noc-base";

qcom,sbm-offset = <0x00>;

qcom,bus-type = <0x01>;

cell-id = <0x180c>;

clocks;

label = "fab-gem_noc";

qcom,base-offset = <0x2b000>;

qcom,fab-dev;

phandle = <0x118>;

qcom,qos-off = <0x80>;

};

bcm-sh0 {

qcom,rscs = <0xd0>;

cell-id = <0x1b5b>;

label = "SH0";

qcom,bcm-name = "SH0";

phandle = <0x14f>;

qcom,bcm-dev;

};

mas-qnm-snoc-gc {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x86>;

qcom,buswidth = <0x08>;

label = "mas-qnm-snoc-gc";

qcom,forwarding;

qcom,connections = <0x116>;

qcom,qport = <0xc0>;

phandle = <0x157>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x118>;

};

slv-qhs-qupv3-center {

qcom,agg-ports = <0x01>;

cell-id = <0x313>;

qcom,buswidth = <0x04>;

label = "slv-qhs-qupv3-center";

phandle = <0xea>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qns-cnoc {

qcom,agg-ports = <0x01>;

cell-id = <0x2734>;

qcom,buswidth = <0x08>;

label = "slv-qns-cnoc";

qcom,connections = <0x156>;

phandle = <0x12d>;

qcom,bus-dev = <0x128>;

};

slv-qhs-mnoc-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x280>;

qcom,buswidth = <0x04>;

label = "slv-qhs-mnoc-cfg";

qcom,connections = <0x148>;

phandle = <0xe8>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-srvc-gemnoc {

qcom,agg-ports = <0x01>;

cell-id = <0x316>;

qcom,buswidth = <0x04>;

label = "slv-srvc-gemnoc";

phandle = <0x11b>;

qcom,bus-dev = <0x118>;

};

slv-qhs-a2-noc-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x2b0>;

qcom,buswidth = <0x04>;

label = "slv-qhs-a2-noc-cfg";

qcom,connections = <0x146>;

phandle = <0xee>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-qnm-snoc {

qcom,agg-ports = <0x01>;

cell-id = <0x2733>;

qcom,buswidth = <0x08>;

label = "mas-qnm-snoc";

qcom,connections = <0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109 0x10a 0x10b 0x10c 0x10d 0x10e 0x10f 0x110 0x111 0x112>;

phandle = <0x156>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

fab-camnoc_virt {

qcom,base-name = "camnoc_virt-base";

qcom,sbm-offset = <0x00>;

cell-id = <0x180a>;

qcom,bypass-qos-prg;

clocks;

label = "fab-camnoc_virt";

qcom,base-offset = <0x00>;

qcom,fab-dev;

phandle = <0xdd>;

qcom,qos-off = <0x00>;

};

mas-qnm-npu {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x9a>;

qcom,buswidth = <0x20>;

label = "mas-qnm-npu";

qcom,connections = <0xdf>;

qcom,qport = <0x01>;

phandle = <0x335>;

qcom,bcms = <0xe1>;

qcom,prio = <0x00>;

qcom,bus-dev = <0xe0>;

};

mas-xm-gic {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x95>;

qcom,buswidth = <0x08>;

label = "mas-xm-gic";

qcom,forwarding;

qcom,connections = <0x133 0x12b>;

qcom,qport = <0x00>;

phandle = <0x347>;

qcom,bcms = <0x134>;

qcom,prio = <0x02>;

qcom,bus-dev = <0x128>;

};

bcm-acv {

qcom,rscs = <0xd0>;

cell-id = <0x1b7e>;

label = "ACV";

qcom,bcm-name = "ACV";

phandle = <0x152>;

qcom,bcm-dev;

};

fab-system_noc {

qcom,base-name = "system_noc-base";

qcom,sbm-offset = <0x00>;

qcom,bus-type = <0x01>;

cell-id = <0x400>;

clocks;

label = "fab-system_noc";

qcom,base-offset = <0xa000>;

qcom,fab-dev;

phandle = <0x128>;

qcom,qos-off = <0x1000>;

};

slv-qhs-prng {

qcom,agg-ports = <0x01>;

cell-id = <0x26a>;

qcom,buswidth = <0x04>;

label = "slv-qhs-prng";

phandle = <0x10a>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-qxm-camnoc-hf {

qcom,ap-owned;

qcom,agg-ports = <0x02>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0x88>;

qcom,buswidth = <0x20>;

label = "mas-qxm-camnoc-hf";

qcom,forwarding;

qcom,connections = <0x123>;

qcom,qport = <0x20 0x40>;

phandle = <0x33c>;

qcom,bcms = <0xde>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x122>;

};

slv-qhs-pcie-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x28d>;

qcom,buswidth = <0x04>;

label = "slv-qhs-pcie-cfg";

phandle = <0xf2>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qns-gem-noc-snoc {

qcom,agg-ports = <0x01>;

cell-id = <0x2757>;

qcom,buswidth = <0x08>;

label = "slv-qns-gem-noc-snoc";

qcom,connections = <0x14c>;

phandle = <0x117>;

qcom,bcms = <0x14d>;

qcom,bus-dev = <0x118>;

};

slv-qhs-tsif {

qcom,agg-ports = <0x01>;

cell-id = <0x23f>;

qcom,buswidth = <0x04>;

label = "slv-qhs-tsif";

phandle = <0xfb>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qhs-aop {

qcom,agg-ports = <0x01>;

cell-id = <0x2eb>;

qcom,buswidth = <0x04>;

label = "slv-qhs-aop";

phandle = <0xfe>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-ebi_display {

qcom,agg-ports = <0x02>;

cell-id = <0x5020>;

qcom,buswidth = <0x04>;

label = "slv-ebi_display";

phandle = <0x138>;

qcom,bcms = <0x15f 0x160>;

qcom,bus-dev = <0x139>;

};

mas-qxm-camnoc-sf-uncomp {

qcom,agg-ports = <0x01>;

cell-id = <0x94>;

qcom,buswidth = <0x20>;

label = "mas-qxm-camnoc-sf-uncomp";

qcom,connections = <0xdc>;

phandle = <0x333>;

qcom,bcms = <0xde>;

qcom,bus-dev = <0xdd>;

};

bcm-mm0_display {

qcom,rscs = <0xd1>;

cell-id = <0x697a>;

label = "MM0_DISPLAY";

qcom,bcm-name = "MM0";

phandle = <0x164>;

qcom,bcm-dev;

};

slv-qhs-gpuss-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x256>;

qcom,buswidth = <0x08>;

label = "slv-qhs-gpuss-cfg";

phandle = <0xf9>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-qnm-mnoc-hf_display {

qcom,agg-ports = <0x02>;

cell-id = <0x4e21>;

qcom,buswidth = <0x20>;

label = "mas-qnm-mnoc-hf_display";

qcom,connections = <0x136>;

qcom,qport = <0x80 0x81>;

phandle = <0x163>;

qcom,bus-dev = <0x137>;

};

slv-srvc-snoc {

qcom,agg-ports = <0x01>;

cell-id = <0x24b>;

qcom,buswidth = <0x04>;

label = "slv-srvc-snoc";

phandle = <0x127>;

qcom,bus-dev = <0x128>;

};

slv-qns-cdsp-gemnoc {

qcom,agg-ports = <0x01>;

cell-id = <0x275c>;

qcom,buswidth = <0x20>;

label = "slv-qns-cdsp-gemnoc";

qcom,connections = <0x143>;

phandle = <0xdf>;

qcom,bcms = <0x144>;

qcom,bus-dev = <0xe0>;

};

bcm-ce0 {

qcom,rscs = <0xd0>;

cell-id = <0x1b7a>;

label = "CE0";

qcom,bcm-name = "CE0";

phandle = <0xda>;

qcom,bcm-dev;

};

fab-mmss_noc_display {

qcom,base-name = "mmss_noc-base";

qcom,sbm-offset = <0x00>;

qcom,bus-type = <0x01>;

cell-id = <0x6592>;

qcom,bypass-qos-prg;

clocks;

label = "fab-mmss_noc_display";

qcom,base-offset = <0x9000>;

qcom,fab-dev;

phandle = <0x13b>;

qcom,qos-off = <0x80>;

};

slv-qhs-tcsr {

qcom,agg-ports = <0x01>;

cell-id = <0x26f>;

qcom,buswidth = <0x04>;

label = "slv-qhs-tcsr";

phandle = <0xf4>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qhs-tlmm-north {

qcom,agg-ports = <0x01>;

cell-id = <0x2db>;

qcom,buswidth = <0x04>;

label = "slv-qhs-tlmm-north";

phandle = <0x110>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qhs-pimem-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x2a9>;

qcom,buswidth = <0x04>;

label = "slv-qhs-pimem-cfg";

phandle = <0x10f>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

bcm-mc0 {

qcom,rscs = <0xd0>;

cell-id = <0x1b58>;

label = "MC0";

qcom,bcm-name = "MC0";

phandle = <0x151>;

qcom,bcm-dev;

};

slv-qhs-apss {

qcom,agg-ports = <0x01>;

cell-id = <0x2a1>;

qcom,buswidth = <0x08>;

label = "slv-qhs-apss";

phandle = <0x12c>;

qcom,bus-dev = <0x128>;

};

slv-qhs-vsense-ctrl-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x2f6>;

qcom,buswidth = <0x04>;

label = "slv-qhs-vsense-ctrl-cfg";

phandle = <0x10b>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

bcm-sn15 {

qcom,rscs = <0xd0>;

cell-id = <0x1b79>;

label = "SN15";

qcom,bcm-name = "SN15";

phandle = <0x132>;

qcom,bcm-dev;

};

slv-ebi {

qcom,agg-ports = <0x02>;

cell-id = <0x200>;

qcom,buswidth = <0x04>;

label = "slv-ebi";

phandle = <0x11f>;

qcom,bcms = <0x151 0x152>;

qcom,bus-dev = <0x120>;

};

mas-qxm-camnoc-sf {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0x89>;

qcom,buswidth = <0x20>;

label = "mas-qxm-camnoc-sf";

qcom,forwarding;

qcom,connections = <0x124>;

qcom,qport = <0x00>;

phandle = <0x33f>;

qcom,bcms = <0x126>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x122>;

};

bcm-sh0_display {

qcom,rscs = <0xd1>;

cell-id = <0x6979>;

label = "SH0_DISPLAY";

qcom,bcm-name = "SH0";

phandle = <0x15e>;

qcom,bcm-dev;

};

mas-qnm-cmpnoc {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x9e>;

qcom,buswidth = <0x20>;

label = "mas-qnm-cmpnoc";

qcom,connections = <0x116 0x117>;

qcom,qport = <0x40>;

phandle = <0x143>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x118>;

};

mas-qxm-venus-arm9 {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0x8a>;

qcom,buswidth = <0x08>;

label = "mas-qxm-venus-arm9";

qcom,forwarding;

qcom,connections = <0x124>;

qcom,qport = <0x100>;

phandle = <0x345>;

qcom,bcms = <0x126>;

qcom,prio = <0x05>;

qcom,bus-dev = <0x122>;

};

slv-qhs-llcc {

qcom,agg-ports = <0x01>;

cell-id = <0x2f8>;

qcom,buswidth = <0x04>;

label = "slv-qhs-llcc";

phandle = <0x113>;

qcom,bus-dev = <0x115>;

};

mas-qxm-camnoc-nrt {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0xab>;

qcom,buswidth = <0x08>;

label = "mas-qxm-camnoc-nrt";

qcom,forwarding;

qcom,connections = <0x124>;

qcom,qport = <0x102>;

phandle = <0x33d>;

qcom,bcms = <0x125>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x122>;

};

mas-qxm-venus0 {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0x3f>;

qcom,buswidth = <0x20>;

label = "mas-qxm-venus0";

qcom,forwarding;

qcom,connections = <0x124>;

qcom,qport = <0xc0>;

phandle = <0x343>;

qcom,bcms = <0x126>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x122>;

};

slv-qhs-gemnoc {

qcom,agg-ports = <0x01>;

cell-id = <0x314>;

qcom,buswidth = <0x04>;

label = "slv-qhs-gemnoc";

qcom,connections = <0x14b>;

phandle = <0x114>;

qcom,bus-dev = <0x115>;

};

slv-qns-mem-noc-hf_display {

qcom,agg-ports = <0x02>;

cell-id = <0x5023>;

qcom,buswidth = <0x20>;

label = "slv-qns-mem-noc-hf_display";

qcom,connections = <0x163>;

phandle = <0x13a>;

qcom,bcms = <0x164>;

qcom,bus-dev = <0x13b>;

};

bcm-mm3 {

qcom,rscs = <0xd0>;

cell-id = <0x1b66>;

label = "MM3";

qcom,bcm-name = "MM3";

phandle = <0x126>;

qcom,bcm-dev;

};

slv-xs-sys-tcu-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x2a0>;

qcom,buswidth = <0x08>;

label = "slv-xs-sys-tcu-cfg";

phandle = <0x130>;

qcom,bus-dev = <0x128>;

};

bcm-mm2_display {

qcom,rscs = <0xd1>;

cell-id = <0x697c>;

label = "MM2_DISPLAY";

qcom,bcm-name = "MM2";

phandle = <0x162>;

qcom,bcm-dev;

};

mas-qxm-mdp0 {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0x16>;

qcom,buswidth = <0x20>;

label = "mas-qxm-mdp0";

qcom,forwarding;

qcom,connections = <0x123>;

qcom,qport = <0x60>;

phandle = <0x340>;

qcom,bcms = <0xde>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x122>;

};

bcm-sh5 {

qcom,rscs = <0xd0>;

cell-id = <0x1b60>;

label = "SH5";

qcom,bcm-name = "SH5";

phandle = <0x119>;

qcom,bcm-dev;

};

slv-qhs-cpr-mx {

qcom,agg-ports = <0x01>;

cell-id = <0x28c>;

qcom,buswidth = <0x04>;

label = "slv-qhs-cpr-mx";

phandle = <0x111>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qns-gemnoc-sf {

qcom,agg-ports = <0x01>;

cell-id = <0x2759>;

qcom,buswidth = <0x10>;

label = "slv-qns-gemnoc-sf";

qcom,connections = <0x159>;

phandle = <0x129>;

qcom,bcms = <0x15a>;

qcom,bus-dev = <0x128>;

};

slv-qns-a1noc-snoc {

qcom,agg-ports = <0x01>;

cell-id = <0x274e>;

qcom,buswidth = <0x10>;

label = "slv-qns-a1noc-snoc";

qcom,connections = <0x13f>;

phandle = <0xd4>;

qcom,bcms = <0x12f>;

qcom,bus-dev = <0xd3>;

};

mas-acm-apps {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x01>;

qcom,buswidth = <0x10>;

label = "mas-acm-apps";

qcom,forwarding;

qcom,connections = <0x116 0x117>;

qcom,qport = <0x60 0x62>;

phandle = <0x338>;

qcom,bcms = <0x119>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x118>;

};

bcm-qup0 {

qcom,rscs = <0xd0>;

cell-id = <0x1b80>;

label = "QUP0";

qcom,bcm-name = "QUP0";

phandle = <0xd5>;

qcom,bcm-dev;

};

bcm-sn1 {

qcom,rscs = <0xd0>;

cell-id = <0x1b6b>;

label = "SN1";

qcom,bcm-name = "SN1";

phandle = <0x15b>;

qcom,bcm-dev;

};

slv-qhs-ahb2phy-south {

qcom,agg-ports = <0x01>;

cell-id = <0x30b>;

qcom,buswidth = <0x04>;

label = "slv-qhs-ahb2phy-south";

phandle = <0x100>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

fab-mc_virt_display {

qcom,base-name = "mc_virt-base";

qcom,sbm-offset = <0x00>;

cell-id = <0x6590>;

qcom,bypass-qos-prg;

clocks;

label = "fab-mc_virt_display";

qcom,base-offset = <0x00>;

qcom,fab-dev;

phandle = <0x139>;

qcom,qos-off = <0x00>;

};

fab-aggre1_noc {

qcom,base-name = "aggre1_noc-base";

qcom,sbm-offset = <0x00>;

qcom,bus-type = <0x01>;

cell-id = <0x1802>;

clocks;

label = "fab-aggre1_noc";

qcom,base-offset = <0x4000>;

qcom,fab-dev;

phandle = <0xd3>;

qcom,qos-off = <0x1000>;

};

slv-srvc-aggre1-noc {

qcom,agg-ports = <0x01>;

cell-id = <0x2e8>;

qcom,buswidth = <0x04>;

label = "slv-srvc-aggre1-noc";

phandle = <0xd2>;

qcom,bus-dev = <0xd3>;

};

slv-qhs-crypto0-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x271>;

qcom,buswidth = <0x04>;

label = "slv-qhs-crypto0-cfg";

phandle = <0x10e>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-qxm-camnoc-hf0-uncomp {

qcom,agg-ports = <0x02>;

cell-id = <0x92>;

qcom,buswidth = <0x20>;

label = "mas-qxm-camnoc-hf0-uncomp";

qcom,connections = <0xdc>;

phandle = <0x331>;

qcom,bcms = <0xde>;

qcom,bus-dev = <0xdd>;

};

mas-xm-sdc4 {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x50>;

qcom,buswidth = <0x08>;

label = "mas-xm-sdc4";

qcom,connections = <0xd4>;

qcom,qport = <0x02>;

phandle = <0x328>;

qcom,bcms = <0xd6>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd3>;

};

slv-qhs-compute-dsp-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x2ed>;

qcom,buswidth = <0x04>;

label = "slv-qhs-compute-dsp-cfg";

phandle = <0xfc>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-qxm-rot_display {

qcom,agg-ports = <0x01>;

cell-id = <0x4e25>;

qcom,buswidth = <0x20>;

label = "mas-qxm-rot_display";

qcom,connections = <0x13d>;

qcom,qport = <0xa0>;

phandle = <0x34b>;

qcom,bcms = <0x13e>;

qcom,bus-dev = <0x13b>;

};

bcm-mm1 {

qcom,rscs = <0xd0>;

cell-id = <0x1b64>;

label = "MM1";

qcom,bcm-name = "MM1";

phandle = <0xde>;

qcom,bcm-dev;

};

fab-mmss_noc {

qcom,base-name = "mmss_noc-base";

qcom,sbm-offset = <0x00>;

qcom,bus-type = <0x01>;

cell-id = <0x800>;

clocks;

label = "fab-mmss_noc";

qcom,base-offset = <0x9000>;

qcom,fab-dev;

phandle = <0x122>;

qcom,qos-off = <0x80>;

};

bcm-sh3 {

qcom,rscs = <0xd0>;

cell-id = <0x1b5e>;

label = "SH3";

qcom,bcm-name = "SH3";

phandle = <0x11a>;

qcom,bcm-dev;

};

slv-qhs-ahb2phy-west {

qcom,agg-ports = <0x01>;

cell-id = <0x319>;

qcom,buswidth = <0x04>;

label = "slv-qhs-ahb2phy-west";

phandle = <0x102>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-qxm-rot {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0x19>;

qcom,buswidth = <0x20>;

label = "mas-qxm-rot";

qcom,forwarding;

qcom,connections = <0x124>;

qcom,qport = <0xa0>;

phandle = <0x342>;

qcom,bcms = <0x126>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x122>;

};

mas-qhm-spdm {

qcom,agg-ports = <0x01>;

cell-id = <0x24>;

qcom,buswidth = <0x04>;

label = "mas-qhm-spdm";

qcom,connections = <0xe2>;

phandle = <0x336>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

bcm-sn11 {

qcom,rscs = <0xd0>;

cell-id = <0x1b75>;

label = "SN11";

qcom,bcm-name = "SN11";

phandle = <0x131>;

qcom,bcm-dev;

};

slv-qns-camnoc-uncomp {

qcom,agg-ports = <0x01>;

cell-id = <0x30a>;

qcom,buswidth = <0x20>;

label = "slv-qns-camnoc-uncomp";

phandle = <0xdc>;

qcom,bus-dev = <0xdd>;

};

slv-qxs-pimem {

qcom,agg-ports = <0x01>;

cell-id = <0x2c8>;

qcom,buswidth = <0x08>;

label = "slv-qxs-pimem";

phandle = <0x12a>;

qcom,bcms = <0x15c>;

qcom,bus-dev = <0x128>;

};

fab-dc_noc {

qcom,base-name = "dc_noc-base";

qcom,sbm-offset = <0x00>;

qcom,bus-type = <0x01>;

cell-id = <0x1806>;

qcom,bypass-qos-prg;

clocks;

label = "fab-dc_noc";

qcom,base-offset = <0x00>;

qcom,fab-dev;

phandle = <0x115>;

qcom,qos-off = <0x00>;

};

mas-qxm-pimem {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x8d>;

qcom,buswidth = <0x08>;

label = "mas-qxm-pimem";

qcom,forwarding;

qcom,connections = <0x133 0x12b>;

qcom,qport = <0x03>;

phandle = <0x346>;

qcom,bcms = <0x134>;

qcom,prio = <0x02>;

qcom,bus-dev = <0x128>;

};

mas-qnm-mnoc-sf_display {

qcom,agg-ports = <0x01>;

cell-id = <0x4e22>;

qcom,buswidth = <0x20>;

label = "mas-qnm-mnoc-sf_display";

qcom,connections = <0x136>;

qcom,qport = <0x140>;

phandle = <0x161>;

qcom,bus-dev = <0x137>;

};

mas-xm-sdc2 {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x51>;

qcom,buswidth = <0x08>;

label = "mas-xm-sdc2";

qcom,connections = <0xd4>;

qcom,qport = <0x01>;

phandle = <0x327>;

qcom,bcms = <0xd6>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd3>;

};

slv-qhs-display-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x24e>;

qcom,buswidth = <0x04>;

label = "slv-qhs-display-cfg";

phandle = <0xf1>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

qcom,disable-ports = <0x48 0x49>;

};

mas-acm-sys-tcu {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x9c>;

qcom,buswidth = <0x08>;

label = "mas-acm-sys-tcu";

qcom,connections = <0x116 0x117>;

qcom,qport = <0x180>;

phandle = <0x339>;

qcom,bcms = <0x11a>;

qcom,prio = <0x06>;

qcom,bus-dev = <0x118>;

};

slv-srvc-mnoc {

qcom,agg-ports = <0x01>;

cell-id = <0x25b>;

qcom,buswidth = <0x04>;

label = "slv-srvc-mnoc";

phandle = <0x121>;

qcom,bus-dev = <0x122>;

};

mas-qxm-camnoc-nrt-uncomp {

qcom,agg-ports = <0x01>;

cell-id = <0xb3>;

qcom,buswidth = <0x20>;

label = "mas-qxm-camnoc-nrt-uncomp";

qcom,connections = <0xdc>;

phandle = <0x334>;

qcom,bcms = <0xde>;

qcom,bus-dev = <0xdd>;

};

slv-qhs-a1-noc-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x2af>;

qcom,buswidth = <0x04>;

label = "slv-qhs-a1-noc-cfg";

qcom,connections = <0x145>;

phandle = <0x108>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

bcm-ip0 {

qcom,rscs = <0xd0>;

cell-id = <0x1b7b>;

label = "IP0";

qcom,bcm-name = "IP0";

phandle = <0x150>;

qcom,bcm-dev;

};

mas-qnm-pcie {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x9f>;

qcom,buswidth = <0x08>;

label = "mas-qnm-pcie";

qcom,connections = <0x116 0x117>;

qcom,qport = <0xe0>;

phandle = <0x141>;

qcom,prio = <0x02>;

qcom,bus-dev = <0x118>;

};

mas-qhm-cnoc-dc-noc {

qcom,agg-ports = <0x01>;

cell-id = <0x7e>;

qcom,buswidth = <0x04>;

label = "mas-qhm-cnoc-dc-noc";

qcom,connections = <0x113 0x114>;

phandle = <0x147>;

qcom,bus-dev = <0x115>;

};

mas-qnm-snoc-sf {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x87>;

qcom,buswidth = <0x10>;

label = "mas-qnm-snoc-sf";

qcom,forwarding;

qcom,connections = <0x116>;

qcom,qport = <0xa0>;

phandle = <0x159>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x118>;

};

slv-qhs-ddrss-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x2ee>;

qcom,buswidth = <0x04>;

label = "slv-qhs-ddrss-cfg";

qcom,connections = <0x147>;

phandle = <0xf6>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-xs-qdss-stm {

qcom,agg-ports = <0x01>;

cell-id = <0x24c>;

qcom,buswidth = <0x04>;

label = "slv-xs-qdss-stm";

phandle = <0x12e>;

qcom,bus-dev = <0x128>;

};

mas-qnm-aggre1-noc {

qcom,agg-ports = <0x01>;

cell-id = <0x274f>;

qcom,buswidth = <0x10>;

label = "mas-qnm-aggre1-noc";

qcom,connections = <0x129 0x12a 0x12b 0x12c 0x12d 0x12e>;

phandle = <0x13f>;

qcom,bcms = <0x12f>;

qcom,bus-dev = <0x128>;

};

mas-xm-qdss-etr {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x3c>;

qcom,buswidth = <0x08>;

label = "mas-xm-qdss-etr";

qcom,connections = <0xd9>;

qcom,qport = <0x09>;

phandle = <0x32f>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd8>;

};

slv-qhs-mdsp-ms-mpu-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x2fd>;

qcom,buswidth = <0x04>;

label = "slv-qhs-mdsp-ms-mpu-cfg";

phandle = <0x11c>;

qcom,bus-dev = <0x118>;

};

mas-qxm-mdp1_display {

qcom,agg-ports = <0x01>;

cell-id = <0x4e24>;

qcom,buswidth = <0x20>;

label = "mas-qxm-mdp1_display";

qcom,connections = <0x13a>;

qcom,qport = <0x80>;

phandle = <0x34a>;

qcom,bcms = <0x13c>;

qcom,bus-dev = <0x13b>;

};

mas-qhm-qup-center {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x97>;

qcom,buswidth = <0x04>;

label = "mas-qhm-qup-center";

qcom,connections = <0xd4>;

qcom,qport = <0x05>;

phandle = <0x324>;

qcom,bcms = <0xd5>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd3>;

};

slv-qhs-display-throttle-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x2bc>;

qcom,buswidth = <0x04>;

label = "slv-qhs-display-throttle-cfg";

phandle = <0xf3>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

bcm-alc_display {

qcom,rscs = <0xd1>;

cell-id = <0x697f>;

label = "ALC_DISPLAY";

qcom,bcm-name = "ALC";

phandle = <0x323>;

qcom,bcm-dev;

};

slv-qhs-cpr-cx {

qcom,agg-ports = <0x01>;

cell-id = <0x28b>;

qcom,buswidth = <0x04>;

label = "slv-qhs-cpr-cx";

phandle = <0x106>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qhs-tlmm-south {

qcom,agg-ports = <0x01>;

cell-id = <0x2f3>;

qcom,buswidth = <0x04>;

label = "slv-qhs-tlmm-south";

phandle = <0xe4>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qhs-sdc4 {

qcom,agg-ports = <0x01>;

cell-id = <0x261>;

qcom,buswidth = <0x04>;

label = "slv-qhs-sdc4";

phandle = <0xe6>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

fab-aggre2_noc {

qcom,base-name = "aggre2_noc-base";

qcom,sbm-offset = <0x00>;

qcom,bus-type = <0x01>;

cell-id = <0x1803>;

clocks;

label = "fab-aggre2_noc";

qcom,base-offset = <0x5000>;

qcom,fab-dev;

phandle = <0xd8>;

qcom,qos-off = <0x1000>;

};

rsc-disp {

qcom,req_state = <0x02>;

cell-id = <0x1f41>;

label = "disp_rsc";

qcom,rsc-dev;

phandle = <0xd1>;

};

mas-qxm-crypto {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x7d>;

qcom,buswidth = <0x08>;

label = "mas-qxm-crypto";

qcom,forwarding;

qcom,connections = <0xd9>;

qcom,qport = <0x01>;

phandle = <0x32c>;

qcom,bcms = <0xda>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd8>;

};

slv-srvc-aggre2-noc {

qcom,agg-ports = <0x01>;

cell-id = <0x2ea>;

qcom,buswidth = <0x04>;

label = "slv-srvc-aggre2-noc";

phandle = <0xd7>;

qcom,bus-dev = <0xd8>;

};

mas-xm-pcie3-0 {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x2d>;

qcom,buswidth = <0x08>;

label = "mas-xm-pcie3-0";

qcom,connections = <0xdb>;

qcom,qport = <0x0b>;

phandle = <0x32e>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd8>;

};

mas-llcc-mc_display {

qcom,agg-ports = <0x02>;

cell-id = <0x4e20>;

qcom,buswidth = <0x04>;

label = "mas-llcc-mc_display";

qcom,connections = <0x138>;

phandle = <0x15d>;

qcom,bus-dev = <0x139>;

};

slv-qhs-glm {

qcom,agg-ports = <0x01>;

cell-id = <0x2d6>;

qcom,buswidth = <0x04>;

label = "slv-qhs-glm";

phandle = <0xeb>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-qhm-qdss-bam {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x35>;

qcom,buswidth = <0x04>;

label = "mas-qhm-qdss-bam";

qcom,connections = <0xd9>;

qcom,qport = <0x08>;

phandle = <0x32a>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd8>;

};

bcm-sh8 {

qcom,rscs = <0xd0>;

cell-id = <0x1b8c>;

label = "SH8";

qcom,bcm-name = "SH8";

phandle = <0x144>;

qcom,bcm-dev;

};

mas-qhm-snoc-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x36>;

qcom,buswidth = <0x04>;

label = "mas-qhm-snoc-cfg";

qcom,connections = <0x127>;

phandle = <0x149>;

qcom,bus-dev = <0x128>;

};

slv-qhs-camera-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x24d>;

qcom,buswidth = <0x04>;

label = "slv-qhs-camera-cfg";

phandle = <0xe5>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

qcom,disable-ports = <0x46 0x47>;

};

slv-qhs-qupv3-north {

qcom,agg-ports = <0x01>;

cell-id = <0x312>;

qcom,buswidth = <0x04>;

label = "slv-qhs-qupv3-north";

phandle = <0xff>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-llcc-mc {

qcom,agg-ports = <0x02>;

cell-id = <0x81>;

qcom,buswidth = <0x04>;

label = "mas-llcc-mc";

qcom,connections = <0x11f>;

phandle = <0x14e>;

qcom,bus-dev = <0x120>;

};

bcm-sn4 {

qcom,rscs = <0xd0>;

cell-id = <0x1b6e>;

label = "SN4";

qcom,bcm-name = "SN4";

phandle = <0x15c>;

qcom,bcm-dev;

};

slv-qhs-emmc-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x326>;

qcom,buswidth = <0x04>;

label = "slv-qhs-emmc-cfg";

phandle = <0x10c>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qns-pcie-gemnoc {

qcom,agg-ports = <0x01>;

cell-id = <0x2755>;

qcom,buswidth = <0x08>;

label = "slv-qns-pcie-gemnoc";

qcom,connections = <0x141>;

phandle = <0xdb>;

qcom,bcms = <0x142>;

qcom,bus-dev = <0xd8>;

};

slv-qhs-sdc2 {

qcom,agg-ports = <0x01>;

cell-id = <0x260>;

qcom,buswidth = <0x04>;

label = "slv-qhs-sdc2";

phandle = <0xe7>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qhs-spdm {

qcom,agg-ports = <0x01>;

cell-id = <0x279>;

qcom,buswidth = <0x04>;

label = "slv-qhs-spdm";

phandle = <0x10d>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qhs-qdss-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x27b>;

qcom,buswidth = <0x04>;

label = "slv-qhs-qdss-cfg";

phandle = <0xef>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-qhm-a1noc-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x79>;

qcom,buswidth = <0x04>;

label = "mas-qhm-a1noc-cfg";

qcom,connections = <0xd2>;

phandle = <0x145>;

qcom,bus-dev = <0xd3>;

};

mas-qxm-venus1 {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0x40>;

qcom,buswidth = <0x20>;

label = "mas-qxm-venus1";

qcom,forwarding;

qcom,connections = <0x124>;

qcom,qport = <0xe0>;

phandle = <0x344>;

qcom,bcms = <0x126>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x122>;

};

slv-qhs-imem-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x273>;

qcom,buswidth = <0x04>;

label = "slv-qhs-imem-cfg";

phandle = <0x112>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

slv-qns-llcc_display {

qcom,agg-ports = <0x02>;

cell-id = <0x5021>;

qcom,buswidth = <0x10>;

label = "slv-qns-llcc_display";

qcom,connections = <0x15d>;

phandle = <0x136>;

qcom,bcms = <0x15e>;

qcom,bus-dev = <0x137>;

};

bcm-mm1_display {

qcom,rscs = <0xd1>;

cell-id = <0x697b>;

label = "MM1_DISPLAY";

qcom,bcm-name = "MM1";

phandle = <0x13c>;

qcom,bcm-dev;

};

slv-qhs-aoss {

qcom,agg-ports = <0x01>;

cell-id = <0x2ec>;

qcom,buswidth = <0x04>;

label = "slv-qhs-aoss";

phandle = <0x109>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

rsc-apps {

qcom,req_state = <0x02>;

cell-id = <0x1f40>;

label = "apps_rsc";

qcom,rsc-dev;

phandle = <0xd0>;

};

mas-qxm-mdp1 {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0x17>;

qcom,buswidth = <0x20>;

label = "mas-qxm-mdp1";

qcom,forwarding;

qcom,connections = <0x123>;

qcom,qport = <0x80>;

phandle = <0x341>;

qcom,bcms = <0xde>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x122>;

};

mas-qnm-mnoc-hf {

qcom,ap-owned;

qcom,agg-ports = <0x02>;

qcom,node-qos-bcms = <0x1b64 0x00 0x01>;

cell-id = <0x84>;

qcom,buswidth = <0x20>;

label = "mas-qnm-mnoc-hf";

qcom,forwarding;

qcom,connections = <0x116>;

qcom,qport = <0x80 0x81>;

phandle = <0x154>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x118>;

};

mas-qxm-ipa {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

qcom,node-qos-bcms = <0x1b7b 0x00 0x01>;

cell-id = <0x5a>;

qcom,buswidth = <0x08>;

label = "mas-qxm-ipa";

qcom,forwarding;

qcom,connections = <0xd9>;

qcom,defer-init-qos;

qcom,qport = <0x02>;

phandle = <0x32d>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd8>;

};

fab-config_noc {

qcom,base-name = "config_noc-base";

qcom,sbm-offset = <0x00>;

qcom,bus-type = <0x01>;

cell-id = <0x1400>;

qcom,bypass-qos-prg;

clocks;

label = "fab-config_noc";

qcom,base-offset = <0x00>;

qcom,fab-dev;

phandle = <0xe3>;

qcom,qos-off = <0x00>;

};

mas-qhm-a2noc-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x7c>;

qcom,buswidth = <0x04>;

label = "mas-qhm-a2noc-cfg";

qcom,connections = <0xd7>;

phandle = <0x146>;

qcom,bus-dev = <0xd8>;

};

bcm-sn14 {

qcom,rscs = <0xd0>;

cell-id = <0x1b78>;

label = "SN14";

qcom,bcm-name = "SN14";

phandle = <0x142>;

qcom,bcm-dev;

};

fab-gem_noc_display {

qcom,base-name = "gem_noc-base";

qcom,sbm-offset = <0x00>;

qcom,bus-type = <0x01>;

cell-id = <0x6593>;

qcom,bypass-qos-prg;

clocks;

label = "fab-gem_noc_display";

qcom,base-offset = <0x2b000>;

qcom,fab-dev;

phandle = <0x137>;

qcom,qos-off = <0x80>;

};

bcm-sn2 {

qcom,rscs = <0xd0>;

cell-id = <0x1b6c>;

label = "SN2";

qcom,bcm-name = "SN2";

phandle = <0x158>;

qcom,bcm-dev;

};

mas-ipa-core-master {

qcom,agg-ports = <0x01>;

cell-id = <0x8f>;

qcom,buswidth = <0x08>;

label = "mas-ipa-core-master";

qcom,connections = <0x11d>;

phandle = <0x33b>;

qcom,bus-dev = <0x11e>;

};

mas-qnm-aggre2-noc {

qcom,agg-ports = <0x01>;

cell-id = <0x2750>;

qcom,buswidth = <0x10>;

label = "mas-qnm-aggre2-noc";

qcom,connections = <0x129 0x12a 0x12b 0x12c 0x12d 0x130 0x12e>;

phandle = <0x140>;

qcom,bcms = <0x131>;

qcom,bus-dev = <0x128>;

};

mas-qnm-cnoc {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x76>;

qcom,buswidth = <0x08>;

label = "mas-qnm-cnoc";

qcom,forwarding;

qcom,connections = <0xd9>;

qcom,qport = <0x03>;

phandle = <0x14a>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd8>;

};

slv-qhs-venus-throttle-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x2b8>;

qcom,buswidth = <0x04>;

label = "slv-qhs-venus-throttle-cfg";

phandle = <0x104>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

mas-xm-usb3-0 {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x3d>;

qcom,buswidth = <0x08>;

label = "mas-xm-usb3-0";

qcom,connections = <0xd9>;

qcom,qport = <0x0c>;

phandle = <0x330>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd8>;

qcom,node-qos-clks {

clock-names = "clk-aggre-usb3-prim-axi-no-rate";

clocks = <0x27 0x0b>;

};

};

bcm-sh10 {

qcom,rscs = <0xd0>;

cell-id = <0x1b8e>;

label = "SH10";

qcom,bcm-name = "SH10";

phandle = <0xe1>;

qcom,bcm-dev;

};

mas-alc {

qcom,agg-ports = <0x01>;

cell-id = <0x90>;

qcom,buswidth = <0x01>;

label = "mas-alc";

phandle = <0x348>;

qcom,bcms = <0x135>;

qcom,bus-dev = <0x120>;

};

slv-ipa-core-slave {

qcom,agg-ports = <0x01>;

cell-id = <0x309>;

qcom,buswidth = <0x08>;

label = "slv-ipa-core-slave";

phandle = <0x11d>;

qcom,bcms = <0x150>;

qcom,bus-dev = <0x11e>;

};

mas-qxm-gpu {

qcom,ap-owned;

qcom,agg-ports = <0x02>;

cell-id = <0x1a>;

qcom,buswidth = <0x20>;

label = "mas-qxm-gpu";

qcom,forwarding;

qcom,connections = <0x116 0x117>;

qcom,qport = <0x120 0x121>;

phandle = <0x33a>;

qcom,prio = <0x00>;

qcom,bus-dev = <0x118>;

};

mas-qxm-camnoc-rt-uncomp {

qcom,agg-ports = <0x01>;

cell-id = <0xb2>;

qcom,buswidth = <0x20>;

label = "mas-qxm-camnoc-rt-uncomp";

qcom,connections = <0xdc>;

phandle = <0x332>;

qcom,bcms = <0xde>;

qcom,bus-dev = <0xdd>;

};

slv-qhs-clk-ctl {

qcom,agg-ports = <0x01>;

cell-id = <0x26c>;

qcom,buswidth = <0x04>;

label = "slv-qhs-clk-ctl";

phandle = <0xfd>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

bcm-mm2 {

qcom,rscs = <0xd0>;

cell-id = <0x1b65>;

label = "MM2";

qcom,bcm-name = "MM2";

phandle = <0x125>;

qcom,bcm-dev;

};

slv-qhs-venus-cvp-throttle-cfg {

qcom,agg-ports = <0x01>;

cell-id = <0x32a>;

qcom,buswidth = <0x04>;

label = "slv-qhs-venus-cvp-throttle-cfg";

phandle = <0xf5>;

qcom,bcms = <0xd6>;

qcom,bus-dev = <0xe3>;

};

fab-compute_noc {

qcom,base-name = "compute_noc-base";

qcom,sbm-offset = <0x00>;

qcom,bus-type = <0x01>;

cell-id = <0x180b>;

qcom,bypass-qos-prg;

clocks;

label = "fab-compute_noc";

qcom,base-offset = <0x00>;

qcom,fab-dev;

phandle = <0xe0>;

qcom,qos-off = <0x1000>;

};

slv-qxs-imem {

qcom,agg-ports = <0x01>;

cell-id = <0x249>;

qcom,buswidth = <0x08>;

label = "slv-qxs-imem";

phandle = <0x12b>;

qcom,bcms = <0x15b>;

qcom,bus-dev = <0x128>;

};

mas-xm-emmc {

qcom,ap-owned;

qcom,agg-ports = <0x01>;

cell-id = <0x96>;

qcom,buswidth = <0x08>;

label = "mas-xm-emmc";

qcom,connections = <0xd4>;

qcom,qport = <0x03>;

phandle = <0x326>;

qcom,bcms = <0xd6>;

qcom,prio = <0x02>;

qcom,bus-dev = <0xd3>;

};

};

qcom,smp2p_interrupt_rdbg_2_out {

qcom,smem-state-names = "rdbg-smp2p-out";

compatible = "qcom,smp2p-interrupt-rdbg-2-out";

qcom,smem-states = <0x1bc 0x00>;

};

cti@683b000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-mss-q6";

compatible = "arm,primecell";

reg = <0x683b000 0x1000>;

phandle = <0x46d>;

};

qseecom@86d00000 {

qcom,hlos-num-ce-hw-instances = <0x01>;

reg-names = "secapp-region";

memory-region = <0x9a>;

qcom,qsee-reentrancy-support = <0x02>;

compatible = "qcom,qseecom";

qcom,no-clock-support;

qcom,disk-encrypt-pipe-pair = <0x02>;

qcom,support-fde;

qcom,appsbl-qseecom-support;

qcom,qsee-ce-hw-instance = <0x00>;

reg = <0x86d00000 0x3e00000>;

phandle = <0x2da>;

qcom,commonlib64-loaded-by-uefi;

qcom,hlos-ce-hw-instance = <0x00>;

qcom,fde-key-size;

};

qcom,msm-dai-tdm-sen-tx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9051>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9151>;

phandle = <0x4c6>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-sen-tx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9051>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x4c7>;

};

};

rpmh-regulator-ldof2 {

compatible = "qcom,rpmh-xob-regulator";

qcom,resource-name = "ldof2";

mboxes = <0x1b 0x00>;

regulator-pm8009-l2 {

regulator-max-microvolt = <0x100590>;

regulator-min-microvolt = <0x100590>;

regulator-name = "pm8009_l2";

qcom,set = <0x03>;

phandle = <0x418>;

};

};

i2c@0xa8c000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x18a>;

clock-names = "se-clk\0m-ahb\0s-ahb";

interrupts = <0x00 0x164 0x00>;

clocks = <0x27 0x5d 0x27 0x69 0x27 0x6a>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x182>;

qcom,clk-freq-in = <0x61a80>;

dma-names = "tx\0rx";

compatible = "qcom,i2c-geni";

pinctrl-1 = <0x18b>;

status = "ok";

reg = <0xa8c000 0x4000>;

phandle = <0x35d>;

dmas = <0x183 0x00 0x03 0x03 0x40 0x00 0x183 0x01 0x03 0x03 0x40 0x00>;

qcom,clk-freq-out = <0x61a80>;

fsa4480@43 {

pinctrl-names = "default";

pinctrl-0 = <0x18c>;

compatible = "qcom,fsa4480-i2c";

status = "disabled";

reg = <0x43>;

phandle = <0x35e>;

};

wl2866d@28 {

vin1-supply = <0x3ff>;

vin2-supply = <0x415>;

vin2-voltage-level = <0x325aa0 0x325aa0>;

en-gpio = <0x174 0x1e 0x00>;

compatible = "xiaomi,wl2866d";

status = "ok";

reg = <0x28>;

vin1-voltage-level = <0x149970 0x149970>;

};

aw8624_haptic@5A {

vib_f0_cali_percen = <0x07>;

pinctrl-names = "aw8624_reset_reset\0aw8624_reset_active\0aw8624_interrupt_active";

pinctrl-2 = <0x58d>;

vib_brake_cont_config = <0x01 0x01 0x5a 0x2a 0x14 0x05 0x02 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;

vib_f0_pre = <0x802>;

irq-gpio = <0x2ec 0x0a 0x00>;

vib_tset = <0x11>;

pinctrl-0 = <0x58b>;

vib_bstdbg = <0x30 0xeb 0xd4 0x00 0x00 0x00>;

vib_effect_max = <0xaa>;

vib_bemf_config = <0x00 0x08 0x03 0xf8>;

vib_td_brake = <0xa6e0 0xa6e0 0xa6e0>;

vib_duration_time = <0x0f 0x3c 0x00 0x00 0x00>;

vib_cont_num_brk = <0x03>;

vib_rtp_time = <0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x6e 0x78 0x82 0x8c 0x96 0xa0 0xaa 0xb4 0xbe 0xc8 0xd2 0xdc 0xe6 0xf0 0xfa 0x104 0x10e 0x118 0x122 0x12c 0x136 0x140 0x14a 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14>;

vib_r_spare = <0x68>;

vib_func_parameter1 = <0x01>;

vib_cont_zc_thr = <0x8f8>;

vib_effect_id_boundary = <0x0a>;

vib_cont_drv_lvl_ov = <0x9b>;

reset-gpio = <0x174 0x04 0x00>;

vib_sw_brake = <0x2c>;

vib_cont_td = <0xf06c>;

compatible = "awinic,aw8624_haptic";

vib_brake_ram_config = <0x01 0x01 0x5a 0x3c 0x14 0x03 0x01 0x03 0x01 0x01 0x5a 0x3c 0x1e 0x05 0x01 0x03 0x00 0x00 0x32 0x28 0x19 0x00 0x05 0x03>;

pinctrl-1 = <0x58c>;

vib_cont_drv_lev = <0x6a>;

vib_f0_trace_parameter = <0x09 0x05 0x01 0x0f>;

reg = <0x5a>;

vib_f0_coeff = <0x104>;

vib_gain_flag = <0x01>;

vib_wavseq = <0x00 0x01 0x01 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;

vib_wavloop = <0x00 0x06 0x01 0x0f 0x00 0x00 0x00 0x00 0x00 0x00>;

wf_7 {

qcom,wf-play-rate-us = <0x4e20>;

qcom,wf-brake-pattern = <0x2010000>;

qcom,effect-id = <0x07>;

qcom,wf-pattern = [3e 3e];

qcom,wf-vmax-mv = <0xe10>;

};

wf_5 {

qcom,wf-play-rate-us = <0x4e20>;

qcom,wf-brake-pattern = <0x3030100>;

qcom,effect-id = <0x05>;

qcom,wf-pattern = [7e 7e 7e];

qcom,wf-vmax-mv = <0xe10>;

};

wf_3 {

qcom,wf-play-rate-us = <0x4e20>;

qcom,wf-brake-pattern = <0x2010000>;

qcom,effect-id = <0x03>;

qcom,wf-pattern = [3e 3e];

qcom,wf-vmax-mv = <0xe10>;

};

wf_1 {

qcom,wf-play-rate-us = <0x4e20>;

qcom,wf-brake-pattern = <0x3010000>;

qcom,effect-id = <0x01>;

qcom,wf-pattern = [7e 3e];

qcom,wf-vmax-mv = <0xe10>;

};

wf_8 {

qcom,wf-play-rate-us = <0x4e20>;

qcom,wf-brake-pattern = <0x2010000>;

qcom,effect-id = <0x08>;

qcom,wf-pattern = [3e 3e];

qcom,wf-vmax-mv = <0xe10>;

};

wf_6 {

qcom,wf-play-rate-us = <0x4e20>;

qcom,wf-brake-pattern = <0x2010000>;

qcom,effect-id = <0x06>;

qcom,wf-pattern = [3e 3e];

qcom,wf-vmax-mv = <0xe10>;

};

wf_4 {

qcom,wf-play-rate-us = <0x6d60>;

qcom,wf-brake-pattern = <0x2010000>;

qcom,effect-id = <0x04>;

qcom,wf-pattern = [3e 3e];

qcom,wf-vmax-mv = <0xe10>;

};

wf_2 {

qcom,wf-play-rate-us = <0x4e20>;

qcom,wf-brake-pattern = <0x2010000>;

qcom,effect-id = <0x02>;

qcom,wf-pattern = [7e 3e];

qcom,wf-vmax-mv = <0xe10>;

};

wf_0 {

qcom,wf-play-rate-us = <0x4e20>;

qcom,wf-brake-pattern = <0x2010000>;

qcom,effect-id = <0x00>;

qcom,wf-pattern = [3e 3e];

qcom,wf-vmax-mv = <0xe10>;

};

wf_9 {

qcom,wf-play-rate-us = <0x4e20>;

qcom,wf-brake-pattern = <0x2010000>;

qcom,effect-id = <0x09>;

qcom,wf-pattern = [3e 3e];

qcom,wf-vmax-mv = <0xe10>;

};

};

bq25970-standalone@66 {

ti,bq2597x,bat-ovp-alarm-threshold = <0x11ad>;

ti,bq2597x,bus-ocp-threshold = <0xea6>;

pinctrl-names = "default";

ti,bq2597x,bat-ocp-alarm-disable;

ti,bq2597x,die-therm-threshold = <0x91>;

ti,bq2597x,bat-therm-threshold = <0x15>;

ti,bq2597x,bat-ovp-threshold = <0x11c6>;

pinctrl-0 = <0x589 0x58a>;

ti,bq2597x,bat-therm-disable;

ti,bq2597x,bus-ovp-threshold = <0x2ee0>;

ti,bq2597x,bus-therm-disable;

interrupts = <0x37 0x2002>;

interrupt-parent = <0x174>;

ti,bq2597x,die-therm-disable;

ti,bq2597x,bus-therm-threshold = <0x15>;

ti,bq2597x,bus-ovp-alarm-threshold = <0x2af8>;

ti,bq2597x,ac-ovp-threshold = <0x0e>;

compatible = "ti,bq2597x-standalone";

ti,bq2597x,bat-ocp-disable;

reg = <0x66>;

ti,bq2597x,bus-ocp-alarm-threshold = <0xdac>;

ti,bq2597x,bat-ovp-alarm-disable;

ti,bq2597x,bat-ucp-disable;

ti,bq2597x,bat-ucp-alarm-disable;

};

};

qcom,cmd-db@c3f000c {

compatible = "qcom,cmd-db";

reg = <0xc3f000c 0x08>;

phandle = <0x2d3>;

};

qcom,mdss_dsi_ss_fhd_eb_f10_cmd {

qcom,mdss-dsi-bl-dcs-type-ss-eb;

qcom,ulps-enabled;

qcom,disp-doze-backlight-threshold = <0x08>;

qcom,mdss-pan-physical-width-dimension = <0x44>;

qcom,mdss-dsi-panel-name = "ss eb fhd cmd dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x93>;

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-t-clk-post = <0x0f>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-panel-id = <0x00>;

qcom,mdss-dsi-panel-fod-dimlayer-enabled;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,bl-update-flag = "delay_until_first_frame";

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,disp-fod-off-dimming-delay = <0x55>;

qcom,dispparam-enabled;

qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x00 0x01 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x37>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,mdss-dsi-panel-model = "SS FHD EB CMD PANEL";

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x533>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-panel-sleepwrmod = <0x00>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-brightness-remap;

qcom,esd-err-irq-gpio = <0x174 0x20 0x2002>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-brightness-max-level = <0x7ff>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode";

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x00 0x01>;

qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x14>;

qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00];

qcom,mdss-dsi-panel-jitter = <0x05 0x01>;

qcom,mdss-dsi-nolp-command = <0x39010000 0x351 0x1003901 0x00 0x2b00039 0x1000000 0x4f0bb 0x2a403901 0x100 0x2532039 0x1000000 0x28800>;

qcom,mdss-dsi-lp1-command = [39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 88 01];

qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode";

qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode";

qcom,mdss-dsi-doze-lbm-command = [39 01 00 00 00 00 03 51 00 40 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 04 f0 bb 2a 40 39 01 00 00 00 00 02 53 20];

qcom,mdss-dsi-dispparam-hbm-fod-on-command = [39 01 00 00 03 00 02 88 00 39 01 00 00 00 00 02 53 e0];

qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 e8];

qcom,mdss-dsi-dispparam-hbm-fod-off-command = [39 01 00 00 00 00 02 53 20];

qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 ff 00 02 53 28 39 01 00 00 00 00 02 53 20];

qcom,mdss-dsi-panel-height = <0x924>;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 00 00 00 00 00 2c bb 59 ff ff ff ef cf ab 87 63 3f 4a 48 46 44 42 40 3e 3c 3a 64 00 ff ff ff ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00 02 02 42 00 39 00 00 00 00 00 03 d4 00 8d 39 00 00 00 00 00 02 fa 0f 39 01 00 00 00 00 02 b0 80 39 00 00 00 00 00 02 e6 00 39 00 00 00 00 00 02 35 00 39 00 00 00 00 00 05 2a 00 00 04 37 39 00 00 00 00 00 05 2b 00 00 09 23 39 00 00 00 00 00 03 51 01 00 05 01 00 00 6e 00 02 11 00 05 01 00 00 10 00 02 29 00 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 04 f0 cf c3 00 39 01 00 00 00 00 04 f0 cf c4 00];

qcom,mdss-dsi-h-front-porch = <0x40>;

qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];

qcom,mdss-dsi-h-back-porch = <0x40>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-lp1-command-state = "dsi_lp_mode";

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];

qcom,mdss-dsi-panel-clockrate = <0x4190ab00>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode";

qcom,mdss-dsi-v-pulse-width = <0x14>;

qcom,mdss-dsi-doze-hbm-command = [39 01 00 00 00 00 03 51 00 ff 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 04 f0 bb 2a 40 39 01 00 00 00 00 02 53 20];

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x240a0a 0x2625090a 0x6020400>;

qcom,mdss-dsi-v-back-porch = <0x40>;

qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode";

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode";

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsi-v-front-porch = <0x40>;

qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

};

};

qcom,fd@ac5a000 {

clock-control-debugfs = "true";

clock-names = "fd_core_clk_src\0fd_core_clk\0fd_core_uar_clk";

reg-names = "fd_core\0fd_wrapper";

reg-cam-base = <0x5a000 0x5b000>;

cell-index = <0x00>;

camss-vdd-supply = <0x1ae>;

interrupts = <0x00 0x1ce 0x00>;

clocks = <0x29 0x2a 0x29 0x29 0x29 0x2b>;

clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";

compatible = "qcom,fd501";

src-clock-name = "fd_core_clk_src";

status = "ok";

interrupt-names = "fd";

reg = <0xac5a000 0x1000 0xac5b000 0x400>;

regulator-names = "camss-vdd";

phandle = <0x399>;

clock-rates = <0x23c34600 0x00 0x00 0x23c34600 0x00 0x00 0x23c34600 0x00 0x00 0x23c34600 0x00 0x00>;

};

xiaomi_touch {

touch,name = "xiaomi-touch";

compatible = "xiaomi-touch";

status = "ok";

};

qcom,msm-dai-q6-hdmi {

compatible = "qcom,msm-dai-q6-hdmi";

qcom,msm-dai-q6-dev-id = <0x08>;

phandle = <0x48d>;

};

onewire_gpio {

pinctrl-names = "onewire_active\0onewire_sleep";

mi,onewire-gpio-cfg-addr = <0x395b000 0x04>;

pinctrl-0 = <0x587>;

label = "xm_onewire";

xiaomi,version = <0x01>;

compatible = "xiaomi,onewire_gpio";

pinctrl-1 = <0x588>;

status = "ok";

xiaomi,ow_gpio = <0x174 0x5b 0x00>;

phandle = <0x5b1>;

};

tgu@6b0c000 {

arm,primecell-periphid = <0x3b999>;

clock-names = "apb_pclk";

reg-names = "tgu-base";

clocks = <0x19 0x00>;

tgu-regs = <0x04>;

tgu-steps = <0x03>;

coresight-name = "coresight-tgu-ipcb";

tgu-conditions = <0x04>;

compatible = "arm,primecell";

reg = <0x6b0c000 0x1000>;

phandle = <0x485>;

tgu-timer-counters = <0x08>;

};

spi@0xa80000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x197>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

interrupts = <0x00 0x161 0x00>;

clocks = <0x27 0x57 0x27 0x69 0x27 0x6a>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x182>;

spi-max-frequency = <0x2faf080>;

dma-names = "tx\0rx";

compatible = "qcom,spi-geni";

pinctrl-1 = <0x198>;

status = "disabled";

reg = <0xa80000 0x4000>;

phandle = <0x363>;

dmas = <0x183 0x00 0x00 0x01 0x40 0x00 0x183 0x01 0x00 0x01 0x40 0x00>;

};

qrng@793000 {

qcom,msm-rng-iface-clk;

clock-names = "iface_clk";

qcom,no-qrng-config;

qcom,msm-bus,name = "msm-rng-noc";

clocks = <0x27 0x41>;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

compatible = "qcom,msm-rng";

reg = <0x793000 0x1000>;

phandle = <0x2dc>;

qcom,msm-bus,vectors-KBps = <0x01 0x26a 0x00 0x00 0x01 0x26a 0x00 0x493e0>;

};

wcd-dsp-mgr@2 {

compatible = "qcom,wcd-dsp-mgr";

status = "disabled";

qcom,wdsp-components = <0x50d 0x00 0x50e 0x01 0x2d6 0x02>;

phandle = <0x59a>;

qcom,img-filename = "cpe_9340";

};

qcom,glinkpkt {

compatible = "qcom,glinkpkt";

qcom,glinkpkt-apr-apps2 {

qcom,glinkpkt-edge = "adsp";

qcom,glinkpkt-dev-name = "apr_apps2";

qcom,glinkpkt-ch-name = "apr_apps2";

};

qcom,glinkpkt-data11 {

qcom,glinkpkt-edge = "mpss";

qcom,glinkpkt-dev-name = "smd11";

qcom,glinkpkt-ch-name = "DATA11";

};

qcom,glinkpkt-data1 {

qcom,glinkpkt-edge = "mpss";

qcom,glinkpkt-dev-name = "smd7";

qcom,glinkpkt-ch-name = "DATA1";

};

qcom,glinkpkt-data40-cntl {

qcom,glinkpkt-edge = "mpss";

qcom,glinkpkt-dev-name = "smdcntl8";

qcom,glinkpkt-ch-name = "DATA40_CNTL";

};

qcom,glinkpkt-data4 {

qcom,glinkpkt-edge = "mpss";

qcom,glinkpkt-dev-name = "smd8";

qcom,glinkpkt-ch-name = "DATA4";

};

qcom,glinkpkt-at-mdm0 {

qcom,glinkpkt-edge = "mpss";

qcom,glinkpkt-dev-name = "at_mdm0";

qcom,glinkpkt-ch-name = "DS";

};

};

qcom,mdss_dsi_xiaomi_f4_36_02_0b_fhd_cmd {

qcom,ulps-enabled;

qcom,disp-doze-backlight-threshold = <0x08>;

qcom,mdss-dsi-bl-min-level = <0x02>;

qcom,mdss-dsi-bl-xiaomi-f4-36-flag;

qcom,mdss-pan-physical-width-dimension = <0x45>;

qcom,mdss-dsi-panel-name = "xiaomi f4 36 02 0b fhd cmd dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x95>;

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-panel-hbm-off-51-index = <0x01>;

qcom,mdss-dsi-t-clk-post = <0x09>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-panel-id = <0x00>;

qcom,mdss-dsi-panel-fod-dimlayer-enabled;

qcom,mdss-dsi-mode-sel-gpio-state = "single_port";

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-bl-max-level = <0x7ff>;

qcom,bl-update-flag = "delay_until_first_frame";

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,mdss-dsi-panel-fod-off-51-index = <0x01>;

qcom,disp-fod-off-dimming-delay = <0x55>;

qcom,dispparam-enabled;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-bl-default-level = <0x218>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-bl-dcs-type-ss-ea;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,dispparam-f4-51-ctrl-flag;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-panel-on-dimming-delay = <0xc8>;

qcom,mdss-dsi-t-clk-pre = <0x1a>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x53b>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-panel-sleepwrmod = <0x00>;

qcom,panel-supply-entries = <0x521>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,disp-backlight-pulse-threshold = <0x40e>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,platform-te-gpio = <0x174 0x0a 0x00>;

qcom,esd-err-irq-gpio = <0x174 0x20 0x2002>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-brightness-max-level = <0x7ff>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-dispparam-one-pluse-command = [39 00 00 00 00 00 06 f0 55 aa 52 08 00 39 00 00 00 00 00 02 6f 09 39 01 00 00 00 00 02 b2 00];

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,mdss-dsc-encoders = <0x02>;

qcom,display-topology = <0x02 0x02 0x01>;

qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-dispparam-one-pluse-command-state = "dsi_lp_mode";

qcom,mdss-dsi-h-pulse-width = <0x04>;

qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-jitter = <0x08 0x0a>;

qcom,mdss-dsi-nolp-command = [39 00 00 00 00 00 02 65 00 39 00 00 00 00 00 02 38 00 15 01 00 00 00 00 02 2c 00];

qcom,compression-mode = "dsc";

qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode";

qcom,mdss-dsi-dispparam-dc-off-command-state = "dsi_hs_mode";

qcom,mdss-dsi-dispparam-dc-on-command-state = "dsi_hs_mode";

qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode";

qcom,mdss-dsi-doze-lbm-command = [39 00 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 1f 39 00 00 00 00 00 02 6f 02 39 00 00 00 00 00 03 51 00 0a 39 00 00 00 00 00 02 39 00 39 00 00 00 00 00 02 65 01 15 01 00 00 00 00 02 2c 00];

qcom,mdss-dsi-dispparam-hbm-fod-on-command = [39 00 00 00 00 00 02 65 00 39 00 00 00 00 00 02 38 00 15 01 00 00 00 00 02 2c 00 39 00 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 0f ff];

qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 28 39 01 00 00 00 00 03 51 0f ff];

qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-hbm-fod-off-command = [39 00 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 07 ff];

qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28 39 01 00 00 00 00 03 51 07 ff];

qcom,mdss-dsi-dispparam-four-pluse-command = [39 00 00 00 00 00 06 f0 55 aa 52 08 00 39 00 00 00 00 00 02 6f 09 39 01 00 00 00 00 02 b2 20];

qcom,lm-split = <0x21c 0x21c>;

qcom,mdss-dsi-dispparam-dc-on-command = [39 00 00 00 00 00 06 f0 55 aa 52 08 00 39 00 00 00 00 00 0b b2 c9 00 10 10 00 08 08 00 00 00 39 01 00 00 00 00 25 b3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 07 ff 0b ff 0b ff 0f ff 39 00 00 00 00 00 06 f0 55 aa 52 08 04 39 00 00 00 00 00 15 d0 00 1f 00 00 85 0b 17 20 40 80 00 b6 00 f8 01 5c 01 e6 07 ff 39 01 00 00 00 00 4c d2 08 08 08 08 08 20 20 20 20 20 2a 2a 2a 2a 2a 40 40 40 40 40 40 40 40 40 40 08 08 08 08 08 20 20 20 20 20 2a 2a 2a 2a 2a 40 40 40 40 40 40 40 40 40 40 08 08 08 08 08 20 20 20 20 20 2a 2a 2a 2a 2a 40 40 40 40 40 40 40 40 40 40];

qcom,mdss-dsi-dispparam-dc-off-command = [39 00 00 00 00 00 06 f0 55 aa 52 08 00 39 00 00 00 00 00 0b b2 59 00 10 10 00 08 08 00 00 20 39 01 00 00 00 00 25 b3 00 02 00 0a 00 0a 00 24 00 24 00 5e 00 5e 00 ee 00 ee 01 e6 01 e6 03 b8 03 b8 07 ff 07 ff 0b ff 0b ff 0f ff 39 00 00 00 00 00 06 f0 55 aa 52 08 04 39 00 00 00 00 00 15 d0 00 1f 00 00 85 0b 17 20 40 80 00 0a 00 5e 00 ee 01 e6 07 ff 39 01 00 00 00 00 4c d2 00 08 00 08 08 10 50 40 3c 20 60 60 50 40 2a 60 60 50 50 40 60 60 54 50 40 00 08 00 08 08 10 50 40 3c 20 60 60 50 40 2a 60 60 50 50 40 60 60 54 50 40 00 08 00 08 08 10 50 40 3c 20 60 60 50 40 2a 60 60 50 50 40 60 60 54 50 40];

qcom,mdss-dsi-panel-height = <0x924>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [39 00 00 00 00 00 05 ff aa 55 a5 80 39 00 00 00 00 00 02 6f 0a 39 01 00 00 00 00 02 fc 02 39 01 00 00 00 00 06 f0 55 aa 52 08 00 39 01 00 00 00 00 05 b2 19 00 10 10 39 00 00 00 00 00 02 6f 09 39 01 00 00 00 00 02 b2 20 15 01 00 00 00 00 02 6f 13 39 01 00 00 00 00 03 b2 03 b8 39 00 00 00 00 00 02 c0 56 39 00 00 00 00 00 02 6f 06 39 00 00 00 00 00 0b b5 2b 1c 00 00 00 2b 1c 00 00 00 39 00 00 00 00 00 03 be 0e 0b 39 00 00 00 00 00 02 6f 05 39 01 00 00 00 00 02 be 8a 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 00 00 00 00 00 02 6f 03 39 00 00 00 00 00 02 cf 09 39 00 00 00 00 00 02 6f 02 39 00 00 00 00 00 02 d2 22 39 00 00 00 00 00 07 b6 00 98 00 98 00 98 39 00 00 00 00 00 05 ff aa 55 a5 81 39 00 00 00 00 00 02 6f 04 39 01 00 00 00 00 02 f5 08 39 01 00 00 00 00 06 f0 55 aa 52 08 00 39 00 00 00 00 00 02 df 81 39 00 00 00 00 00 02 6f 01 39 00 00 00 00 00 04 df 80 80 00 39 00 00 00 00 00 02 6f 04 39 00 00 00 00 00 02 df 02 39 00 00 00 00 00 02 6f 22 39 01 00 00 00 00 06 df 35 80 7f 15 50 39 00 00 00 00 00 03 89 00 0f 39 01 00 00 00 00 05 88 02 1b 07 11 39 00 00 00 00 00 05 ff aa 55 a5 81 39 00 00 00 00 00 02 6f 05 39 01 00 00 00 00 03 fd 00 db 39 00 00 00 00 00 05 ff aa 55 a5 81 39 00 00 00 00 00 02 6f 0d 39 00 00 00 00 00 02 f3 a7 39 01 00 00 00 00 05 3b 00 10 00 0c 39 00 00 00 00 00 02 90 01 39 00 00 00 00 00 13 93 89 28 00 0c 02 00 02 0e 01 1f 00 07 08 bb 08 7a 10 f0 39 00 00 00 00 00 02 03 11 39 01 00 00 00 00 02 2c 00 39 00 00 00 00 00 05 51 00 00 00 00 39 00 00 00 00 00 02 53 20 39 01 00 00 00 00 02 35 00 39 00 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 80 00 02 11 00 05 01 00 00 00 00 02 29 00];

qcom,mdss-dsi-h-front-porch = <0x08>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x08>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x0c>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x04>;

qcom,mdss-dsi-doze-hbm-command = [39 00 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 1f 39 00 00 00 00 00 02 6f 02 39 00 00 00 00 00 03 51 00 ee 39 00 00 00 00 00 02 39 00 39 00 00 00 00 00 02 65 01 15 01 00 00 00 00 02 2c 00];

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20];

qcom,mdss-dsi-panel-phy-timings = <0xe0303 0x1e1d0403 0x2020400>;

qcom,mdss-dsi-v-back-porch = <0x0c>;

qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode";

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode";

qcom,mdss-dsc-slice-per-pkt = <0x02>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsc-scr-version = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 66 00 02 10 00];

qcom,mdss-dsi-dispparam-four-pluse-command-state = "dsi_lp_mode";

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28];

qcom,mdss-dsi-v-front-porch = <0x0c>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

qcom,mdss-dsc-version = <0x11>;

};

};

};

keepalive-opp-table {

compatible = "operating-points-v2";

phandle = <0xca>;

opp-1 {

opp-hz = <0x00 0x01>;

};

};

qcom,msm-dai-tdm-quat-tx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9031>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9131>;

phandle = <0x4c1>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-quat-tx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9031>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x28d>;

};

};

thermal-zones {

phandle = <0x2bc>;

xo_therm {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x7f 0x4c>;

thermal-governor = "user_space";

trips {

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

mdm-dsp-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x07>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

mdm-dsp-lowf-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x75>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x75>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x75>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x75>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x75>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x75>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x75>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x75>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x75>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

cpu-0-2-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x03>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpuss-0-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x07>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

nvm-therm-adc {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x2eb 0x55>;

thermal-governor = "user_space";

trips {

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpu-1-1-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x0a>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpu-0-4-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x05>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

cpu4-config {

temperature = <0x1adb0>;

hysteresis = <0x2710>;

type = "passive";

phandle = <0x60>;

};

};

cooling-maps {

cpu4_cdev {

trip = <0x60>;

cooling-device = <0x15 0xfffffffe 0xfffffffe>;

};

};

};

cpu-0-0-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x01>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

cpu-0-0-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x6c>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x6c>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x6c>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x6c>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x6c>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x6c>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x6c>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x6c>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x6c>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

pm6150-ibat-lvl0 {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x55 0x00>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

ibat-lvl0 {

temperature = <0x157c>;

hysteresis = <0xc8>;

type = "passive";

phandle = <0x2c0>;

};

};

};

pm6150l-vph-lvl1 {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x58 0x03>;

thermal-governor = "low_limits_cap";

wake-capable-sensor;

trips {

vph-lvl1 {

temperature = <0xabe>;

hysteresis = <0xc8>;

type = "passive";

phandle = <0x2cd>;

};

};

};

cpu-1-0-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x09>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

cpu-1-0-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x6d>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x6d>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x6d>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x6d>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x6d>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x6d>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x6d>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x6d>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x6d>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

q6-hvx-step {

polling-delay = <0x00>;

polling-delay-passive = <0x0a>;

thermal-sensors = <0x5a 0x04>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

q6-hvx-trip2 {

temperature = <0x19a28>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x7e>;

};

q6-hvx-trip0 {

temperature = <0x17318>;

hysteresis = <0x4e20>;

type = "passive";

phandle = <0x7a>;

};

q6-hvx-trip1 {

temperature = <0x17318>;

hysteresis = <0x00>;

type = "passive";

phandle = <0x7c>;

};

};

cooling-maps {

cdsp-cdev0 {

trip = <0x7c>;

cooling-device = <0x7d 0xffffffff 0x04>;

};

cxip-cdev {

trip = <0x7a>;

cooling-device = <0x7b 0x01 0x01>;

};

cdsp-cdev1 {

trip = <0x7e>;

cooling-device = <0x7d 0x04 0x04>;

};

};

};

q6-hvx-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x04>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpu-0-3-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x04>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

cpu3-config {

temperature = <0x1adb0>;

hysteresis = <0x2710>;

type = "passive";

phandle = <0x5f>;

};

};

cooling-maps {

cpu3_cdev {

trip = <0x5f>;

cooling-device = <0x14 0xfffffffe 0xfffffffe>;

};

};

};

mdm-core-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x06>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

mdm-core-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x74>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x74>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x74>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x74>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x74>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x74>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x74>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x74>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x74>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

lmh-dcvs-01 {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x0f>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

active-config {

temperature = <0x17318>;

hysteresis = <0x7530>;

type = "passive";

};

};

};

charger_therm0 {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x2eb 0x4e>;

thermal-governor = "user_space";

trips {

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpu-1-3-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x0c>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

cpu7-1-config {

temperature = <0x1adb0>;

hysteresis = <0x2710>;

type = "passive";

phandle = <0x65>;

};

};

cooling-maps {

cpu7_cdev {

trip = <0x65>;

cooling-device = <0x18 0xfffffffe 0xfffffffe>;

};

};

};

pm6150l-tz {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x57>;

thermal-governor = "step_wise";

phandle = <0x2c9>;

wake-capable-sensor;

trips {

trip2 {

temperature = <0x23668>;

hysteresis = <0x00>;

type = "passive";

};

trip0 {

temperature = <0x17318>;

hysteresis = <0x00>;

type = "passive";

phandle = <0x2ca>;

};

trip1 {

temperature = <0x1c138>;

hysteresis = <0x00>;

type = "passive";

phandle = <0x2cb>;

};

};

cooling-maps {

trip1_cpu6 {

trip = <0x2cb>;

cooling-device = <0x17 0xfffffffe 0xfffffffe>;

};

trip1_cpu4 {

trip = <0x2cb>;

cooling-device = <0x15 0xfffffffe 0xfffffffe>;

};

trip0_cpu6 {

trip = <0x2ca>;

cooling-device = <0x17 0xfffffffd 0xfffffffd>;

};

trip1_cpu2 {

trip = <0x2cb>;

cooling-device = <0x13 0xfffffffe 0xfffffffe>;

};

trip0_cpu4 {

trip = <0x2ca>;

cooling-device = <0x15 0xfffffffd 0xfffffffd>;

};

trip0_cpu2 {

trip = <0x2ca>;

cooling-device = <0x13 0xfffffffd 0xfffffffd>;

};

trip0_cpu0 {

trip = <0x2ca>;

cooling-device = <0x11 0xfffffffd 0xfffffffd>;

};

trip1_cpu7 {

trip = <0x2cb>;

cooling-device = <0x18 0xfffffffe 0xfffffffe>;

};

trip1_cpu5 {

trip = <0x2cb>;

cooling-device = <0x16 0xfffffffe 0xfffffffe>;

};

trip0_cpu7 {

trip = <0x2ca>;

cooling-device = <0x18 0xfffffffd 0xfffffffd>;

};

trip1_cpu3 {

trip = <0x2cb>;

cooling-device = <0x14 0xfffffffe 0xfffffffe>;

};

trip0_cpu5 {

trip = <0x2ca>;

cooling-device = <0x16 0xfffffffd 0xfffffffd>;

};

trip1_cpu1 {

trip = <0x2cb>;

cooling-device = <0x12 0xfffffffe 0xfffffffe>;

};

trip0_cpu3 {

trip = <0x2ca>;

cooling-device = <0x14 0xfffffffd 0xfffffffd>;

};

trip0_cpu1 {

trip = <0x2ca>;

cooling-device = <0x12 0xfffffffd 0xfffffffd>;

};

};

};

cpu-0-3-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x04>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpuss-1-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x08>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cwlan-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x01>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

aoss-0-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x00>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

aoss0-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x66>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x66>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x66>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x66>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x66>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x66>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x66>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x66>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x66>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

camera-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x05>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpu-1-2-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x0b>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

pm6150-bcl-lvl2 {

polling-delay = <0x00>;

polling-delay-passive = <0x64>;

thermal-sensors = <0x55 0x07>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

bcl-lvl2 {

temperature = <0x01>;

hysteresis = <0x01>;

type = "passive";

phandle = <0x2c7>;

};

};

cooling-maps {

ibat_cpu7 {

trip = <0x2c7>;

cooling-device = <0x18 0xfffffffe 0xfffffffe>;

};

ibat_cpu6 {

trip = <0x2c7>;

cooling-device = <0x17 0xfffffffe 0xfffffffe>;

};

};

};

soc {

polling-delay = <0x00>;

tracks-low;

disable-thermal-zone;

polling-delay-passive = <0x64>;

thermal-sensors = <0x56>;

thermal-governor = "low_limits_cap";

wake-capable-sensor;

trips {

soc-trip {

temperature = <0x0a>;

hysteresis = <0x00>;

type = "passive";

phandle = <0x2c8>;

};

};

cooling-maps {

soc_cpu7 {

trip = <0x2c8>;

cooling-device = <0x18 0xfffffffe 0xfffffffe>;

};

soc_cpu6 {

trip = <0x2c8>;

cooling-device = <0x17 0xfffffffe 0xfffffffe>;

};

};

};

cpu_therm {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x7f 0x4f>;

thermal-governor = "user_space";

trips {

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpu-0-2-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x03>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

cpu2-config {

temperature = <0x1adb0>;

hysteresis = <0x2710>;

type = "passive";

phandle = <0x5e>;

};

};

cooling-maps {

cpu2_cdev {

trip = <0x5e>;

cooling-device = <0x13 0xfffffffe 0xfffffffe>;

};

};

};

pm6150l-bcl-lvl1 {

polling-delay = <0x00>;

polling-delay-passive = <0x64>;

thermal-sensors = <0x58 0x06>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

l-bcl-lvl1 {

temperature = <0x01>;

hysteresis = <0x01>;

type = "passive";

phandle = <0x2d0>;

};

};

};

gpuss-0-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x0d>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

gpuss-0-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x6e>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x6e>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x6e>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x6e>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x6e>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x6e>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x6e>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x6e>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x6e>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

pm6150-bcl-lvl0 {

polling-delay = <0x00>;

polling-delay-passive = <0x64>;

thermal-sensors = <0x55 0x05>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

bcl-lvl0 {

temperature = <0x01>;

hysteresis = <0x01>;

type = "passive";

phandle = <0x2c5>;

};

};

cooling-maps {

vbat_cpu6 {

trip = <0x2c5>;

cooling-device = <0x17 0xfffffffe 0xfffffffe>;

};

vbat_cpu7 {

trip = <0x2c5>;

cooling-device = <0x18 0xfffffffe 0xfffffffe>;

};

};

};

pm6150-vbat-lvl1 {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x55 0x03>;

thermal-governor = "low_limits_cap";

wake-capable-sensor;

trips {

vbat-lvl1 {

temperature = <0xaf0>;

hysteresis = <0xc8>;

type = "passive";

phandle = <0x2c3>;

};

};

};

cpu-1-2-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x0b>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

cpu7-0-config {

temperature = <0x1adb0>;

hysteresis = <0x2710>;

type = "passive";

phandle = <0x64>;

};

};

cooling-maps {

cpu7_cdev {

trip = <0x64>;

cooling-device = <0x18 0xfffffffe 0xfffffffe>;

};

};

};

cpu-0-max-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

silver-trip {

temperature = <0x1d4c0>;

hysteresis = <0x00>;

type = "passive";

};

};

};

cpu-0-0-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x01>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

q6-hvx-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x04>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

q6-hvx-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x72>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x72>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x72>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x72>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x72>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x72>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x72>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x72>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x72>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

quiet-therm-step {

polling-delay = <0x00>;

disable-thermal-zone;

polling-delay-passive = <0x3e8>;

thermal-sensors = <0x7f 0x50>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

batt-trip1 {

temperature = <0xafc8>;

hysteresis = <0x7d0>;

type = "passive";

phandle = <0x8b>;

};

modem-trip1-hvx-trip {

temperature = <0xc350>;

hysteresis = <0x7d0>;

type = "passive";

phandle = <0x83>;

};

silver-trip {

temperature = <0xd2f0>;

hysteresis = <0x00>;

type = "passive";

phandle = <0x81>;

};

modem-trip2 {

temperature = <0xcb20>;

hysteresis = <0x7d0>;

type = "passive";

phandle = <0x85>;

};

modem-trip0 {

temperature = <0xbb80>;

hysteresis = <0xfa0>;

type = "passive";

phandle = <0x87>;

};

batt-trip4 {

temperature = <0xc738>;

hysteresis = <0x7d0>;

type = "passive";

phandle = <0x8e>;

};

batt-trip2 {

temperature = <0xb798>;

hysteresis = <0x7d0>;

type = "passive";

phandle = <0x8c>;

};

batt-trip0 {

temperature = <0xa7f8>;

hysteresis = <0xfa0>;

type = "passive";

phandle = <0x89>;

};

modem-trip3 {

temperature = <0xe290>;

hysteresis = <0xfa0>;

type = "passive";

phandle = <0x86>;

};

gold-trip {

temperature = <0xc350>;

hysteresis = <0x00>;

type = "passive";

phandle = <0x80>;

};

skin-gpu-trip {

temperature = <0xcb20>;

hysteresis = <0xfa0>;

type = "passive";

phandle = <0x82>;

};

batt-trip3 {

temperature = <0xbf68>;

hysteresis = <0x7d0>;

type = "passive";

phandle = <0x8d>;

};

};

cooling-maps {

skin_cpu1 {

trip = <0x81>;

cooling-device = <0x12 0xffffffff 0xfffffff7>;

};

cdsp_cdev1 {

trip = <0x83>;

cooling-device = <0x7d 0x04 0x04>;

};

battery_lvl3 {

trip = <0x8d>;

cooling-device = <0x8a 0x05 0x05>;

};

battery_lvl1 {

trip = <0x8b>;

cooling-device = <0x8a 0x02 0x02>;

};

skin_cpu6 {

trip = <0x80>;

cooling-device = <0x17 0xffffffff 0xfffffff5>;

};

skin_cpu4 {

trip = <0x81>;

cooling-device = <0x15 0xffffffff 0xfffffff7>;

};

modem_proc_lvl3 {

trip = <0x86>;

cooling-device = <0x88 0x03 0x03>;

};

modem_lvl2 {

trip = <0x85>;

cooling-device = <0x84 0x02 0x02>;

};

skin_gpu {

trip = <0x82>;

cooling-device = <0x21 0xfffffff9 0xfffffff9>;

};

skin_cpu2 {

trip = <0x81>;

cooling-device = <0x13 0xffffffff 0xfffffff7>;

};

modem_proc_lvl1 {

trip = <0x87>;

cooling-device = <0x88 0x01 0x01>;

};

skin_cpu0 {

trip = <0x81>;

cooling-device = <0x11 0xffffffff 0xfffffff7>;

};

battery_lvl4 {

trip = <0x8e>;

cooling-device = <0x8a 0x06 0x06>;

};

battery_lvl2 {

trip = <0x8c>;

cooling-device = <0x8a 0x04 0x04>;

};

skin_cpu7 {

trip = <0x80>;

cooling-device = <0x18 0xffffffff 0xfffffff5>;

};

battery_lvl0 {

trip = <0x89>;

cooling-device = <0x8a 0x01 0x01>;

};

skin_cpu5 {

trip = <0x81>;

cooling-device = <0x16 0xffffffff 0xfffffff7>;

};

modem_lvl3 {

trip = <0x86>;

cooling-device = <0x84 0x03 0x03>;

};

skin_cpu3 {

trip = <0x81>;

cooling-device = <0x14 0xffffffff 0xfffffff7>;

};

modem_lvl1 {

trip = <0x83>;

cooling-device = <0x84 0x01 0x01>;

};

};

};

cpu-0-1-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x02>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

cpu1-config {

temperature = <0x1adb0>;

hysteresis = <0x2710>;

type = "passive";

phandle = <0x5d>;

};

};

cooling-maps {

cpu1_cdev {

trip = <0x5d>;

cooling-device = <0x12 0xfffffffe 0xfffffffe>;

};

};

};

mdm-core-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x06>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

pm6150-ibat-lvl1 {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x55 0x01>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

ibat-lvl1 {

temperature = <0x1770>;

hysteresis = <0xc8>;

type = "passive";

phandle = <0x2c1>;

};

};

};

cpu-0-4-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x05>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpu-1-3-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x0c>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpu-1-1-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x0a>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

cpu6-1-config {

temperature = <0x1adb0>;

hysteresis = <0x2710>;

type = "passive";

phandle = <0x63>;

};

};

cooling-maps {

cpu6_cdev {

trip = <0x63>;

cooling-device = <0x17 0xfffffffe 0xfffffffe>;

};

};

};

pm6150l-vph-lvl2 {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x58 0x04>;

thermal-governor = "low_limits_cap";

wake-capable-sensor;

trips {

vph-lvl2 {

temperature = <0x9c4>;

hysteresis = <0xc8>;

type = "passive";

phandle = <0x2ce>;

};

};

};

npu-step {

polling-delay = <0x00>;

polling-delay-passive = <0x0a>;

thermal-sensors = <0x5a 0x08>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

npu-trip0 {

temperature = <0x17318>;

hysteresis = <0x00>;

type = "passive";

phandle = <0x78>;

};

};

cooling-maps {

npu_cdev {

trip = <0x78>;

cooling-device = <0x79 0xffffffff 0xffffffff>;

};

};

};

conn_therm {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x2eb 0x4d>;

thermal-governor = "user_space";

trips {

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

aoss-0-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x00>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cwlan-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x01>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

cwlan-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x6f>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x6f>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x6f>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x6f>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x6f>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x6f>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x6f>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x6f>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x6f>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

gpuss-0-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x0d>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

ddr-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x03>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

ddr-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x71>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x71>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x71>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x71>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x71>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x71>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x71>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x71>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x71>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

wifi_therm {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x2eb 0x4f>;

thermal-governor = "user_space";

trips {

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

camera-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x05>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

camera-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x73>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x73>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x73>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x73>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x73>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x73>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x73>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x73>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x73>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

pm6150l-vph-lvl0 {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x58 0x02>;

thermal-governor = "low_limits_cap";

wake-capable-sensor;

trips {

vph-lvl0 {

temperature = <0xbb8>;

hysteresis = <0xc8>;

type = "passive";

phandle = <0x2cc>;

};

};

};

cpu-0-0-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x01>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

cpu0-config {

temperature = <0x1adb0>;

hysteresis = <0x2710>;

type = "passive";

phandle = <0x5c>;

};

};

cooling-maps {

cpu0_cdev {

trip = <0x5c>;

cooling-device = <0x11 0xfffffffe 0xfffffffe>;

};

};

};

npu-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x08>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

pa_therm0 {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x7f 0x4e>;

thermal-governor = "user_space";

trips {

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

pm6150-tz {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x54>;

thermal-governor = "step_wise";

phandle = <0x2bd>;

wake-capable-sensor;

trips {

trip2 {

temperature = <0x23668>;

hysteresis = <0x00>;

type = "passive";

};

trip0 {

temperature = <0x17318>;

hysteresis = <0x00>;

type = "passive";

phandle = <0x2be>;

};

trip1 {

temperature = <0x1c138>;

hysteresis = <0x00>;

type = "passive";

phandle = <0x2bf>;

};

};

cooling-maps {

trip0_bat {

trip = <0x2be>;

cooling-device = <0x8a 0xfffffffd 0xfffffffd>;

};

trip1_bat {

trip = <0x2bf>;

cooling-device = <0x8a 0xfffffffe 0xfffffffe>;

};

};

};

audio-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x02>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

audio-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x70>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x70>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x70>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x70>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x70>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x70>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x70>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x70>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x70>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

cpu-1-max-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

gold-trip {

temperature = <0x1d4c0>;

hysteresis = <0x00>;

type = "passive";

};

};

};

cpu-1-0-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x09>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

cpu6-0-config {

temperature = <0x1adb0>;

hysteresis = <0x2710>;

type = "passive";

phandle = <0x62>;

};

};

cooling-maps {

cpu6_cdev {

trip = <0x62>;

cooling-device = <0x17 0xfffffffe 0xfffffffe>;

};

};

};

video-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x09>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

video-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x77>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x77>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x77>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x77>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x77>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x77>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x77>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x77>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x77>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

video-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x09>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpu-0-1-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x02>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

mdm-dsp-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x07>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

lmh-dcvs-00 {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x05>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

active-config {

temperature = <0x17318>;

hysteresis = <0x7530>;

type = "passive";

};

};

};

cpu-1-0-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x09>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpu-0-5-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x06>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

ddr-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x03>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

audio-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x02>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

gpuss-max-step {

polling-delay = <0x64>;

polling-delay-passive = <0x0a>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

gpu-trip {

temperature = <0x17318>;

hysteresis = <0x00>;

type = "passive";

phandle = <0x5b>;

};

};

cooling-maps {

gpu_cdev {

trip = <0x5b>;

cooling-device = <0x21 0xffffffff 0xffffffff>;

};

};

};

pm6150l-bcl-lvl2 {

polling-delay = <0x00>;

polling-delay-passive = <0x64>;

thermal-sensors = <0x58 0x07>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

l-bcl-lvl2 {

temperature = <0x01>;

hysteresis = <0x01>;

type = "passive";

phandle = <0x2d1>;

};

};

};

pm6150-bcl-lvl1 {

polling-delay = <0x00>;

polling-delay-passive = <0x64>;

thermal-sensors = <0x55 0x06>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

bcl-lvl1 {

temperature = <0x01>;

hysteresis = <0x01>;

type = "passive";

phandle = <0x2c6>;

};

};

cooling-maps {

ibat_cpu7 {

trip = <0x2c6>;

cooling-device = <0x18 0xfffffffe 0xfffffffe>;

};

ibat_cpu6 {

trip = <0x2c6>;

cooling-device = <0x17 0xfffffffe 0xfffffffe>;

};

};

};

quiet_therm {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x7f 0x50>;

thermal-governor = "user_space";

trips {

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

pm6150-vbat-lvl2 {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x55 0x04>;

thermal-governor = "low_limits_cap";

wake-capable-sensor;

trips {

vbat-lvl2 {

temperature = <0xa28>;

hysteresis = <0xc8>;

type = "passive";

phandle = <0x2c4>;

};

};

};

aoss-1-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x00>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

gpuss-1-usr {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x0e>;

thermal-governor = "user_space";

wake-capable-sensor;

trips {

reset-mon-cfg {

temperature = <0x1c138>;

hysteresis = <0x1388>;

type = "passive";

};

active-config0 {

temperature = <0x1e848>;

hysteresis = <0x3e8>;

type = "passive";

};

};

};

cpu-0-5-step {

polling-delay = <0x00>;

polling-delay-passive = <0x00>;

thermal-sensors = <0x59 0x06>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

cpu5-config {

temperature = <0x1adb0>;

hysteresis = <0x2710>;

type = "passive";

phandle = <0x61>;

};

};

cooling-maps {

cpu5_cdev {

trip = <0x61>;

cooling-device = <0x16 0xfffffffe 0xfffffffe>;

};

};

};

pm6150l-bcl-lvl0 {

polling-delay = <0x00>;

polling-delay-passive = <0x64>;

thermal-sensors = <0x58 0x05>;

thermal-governor = "step_wise";

wake-capable-sensor;

trips {

l-bcl-lvl0 {

temperature = <0x01>;

hysteresis = <0x01>;

type = "passive";

phandle = <0x2cf>;

};

};

};

pm6150-vbat-lvl0 {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x55 0x02>;

thermal-governor = "low_limits_cap";

wake-capable-sensor;

trips {

vbat-lvl0 {

temperature = <0xbb8>;

hysteresis = <0xc8>;

type = "passive";

phandle = <0x2c2>;

};

};

};

npu-lowf {

polling-delay = <0x00>;

tracks-low;

polling-delay-passive = <0x00>;

thermal-sensors = <0x5a 0x08>;

thermal-governor = "low_limits_floor";

wake-capable-sensor;

trips {

npu-trip {

temperature = <0x1388>;

hysteresis = <0x1388>;

type = "passive";

phandle = <0x76>;

};

};

cooling-maps {

cdsp_vdd_cdev {

trip = <0x76>;

cooling-device = <0x6b 0x00 0x00>;

};

adsp_vdd_cdev {

trip = <0x76>;

cooling-device = <0x6a 0x00 0x00>;

};

cpu1_cdev {

trip = <0x76>;

cooling-device = <0x17 0x04 0x04>;

};

cx_vdd_cdev {

trip = <0x76>;

cooling-device = <0x67 0x00 0x00>;

};

mx_vdd_cdev {

trip = <0x76>;

cooling-device = <0x68 0x00 0x00>;

};

cpu0_cdev {

trip = <0x76>;

cooling-device = <0x11 0x02 0x02>;

};

modem_vdd_cdev {

trip = <0x76>;

cooling-device = <0x69 0x00 0x00>;

};

gpu_vdd_cdev {

trip = <0x76>;

cooling-device = <0x21 0xfffffffb 0xfffffffb>;

};

};

};

};

qcom,cpu6-computemon {

qcom,core-dev-table = <0x10b170 0x478 0x1433e0 0x826 0x17af48 0xb71 0x1a0fe0 0xf27 0x253500 0x1ae1>;

qcom,cpulist = <0x17 0x18>;

compatible = "qcom,arm-cpu-mon";

phandle = <0x31a>;

qcom,target-dev = <0xc6>;

};

qcom,cpas-cdm0@ac48000 {

camss-supply = <0x1ae>;

clock-names = "cam_cc_cpas_slow_ahb_clk\0cam_cc_cpas_ahb_clk";

reg-names = "cpas-cdm";

reg-cam-base = <0x48000>;

cdm-client-names = "ife";

cell-index = <0x00>;

interrupts = <0x00 0x1d4 0x00>;

clocks = <0x29 0x5a 0x29 0x1a>;

label = "cpas-cdm";

clock-cntl-level = "svs";

compatible = "qcom,cam170-cpas-cdm0";

status = "ok";

interrupt-names = "cpas-cdm";

reg = <0xac48000 0x1000>;

regulator-names = "camss";

clock-rates = <0x00 0x00>;

};

pinctrl@3400000 {

reg-names = "pinctrl\0spi_cfg";

gpio-controller;

interrupts = <0x00 0xd0 0x00>;

compatible = "qcom,sdmmagpie-pinctrl";

#interrupt-cells = <0x02>;

reg = <0x3400000 0xdc2000 0x17c000f0 0x60>;

phandle = <0x174>;

#gpio-cells = <0x02>;

interrupt-controller;

sdc1_cmd_on {

phandle = <0x3df>;

config {

pins = "sdc1_cmd";

drive-strength = <0x0a>;

bias-pull-up;

};

};

qupv3_se11_4uart_pins {

phandle = <0x3c4>;

qupv3_se11_rts {

phandle = <0x195>;

mux {

function = "qup15";

pins = "gpio102";

};

config {

pins = "gpio102";

drive-strength = <0x02>;

bias-pull-down;

};

};

qupv3_se11_tx {

phandle = <0x196>;

mux {

function = "qup15";

pins = "gpio103";

};

config {

pins = "gpio103";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se11_ctsrx {

phandle = <0x194>;

mux {

function = "qup15";

pins = "gpio101\0gpio92";

};

config {

pins = "gpio101\0gpio92";

drive-strength = <0x02>;

bias-no-pull;

};

};

};

pmx_ts_int_suspend {

ts_int_suspend {

phandle = <0x590>;

mux {

function = "gpio";

pins = "gpio9";

};

config {

pins = "gpio9";

drive-strength = <0x02>;

bias-disable;

bias-pull-down;

};

};

tp_int_suspend {

phandle = <0x59c>;

mux {

function = "gpio";

pins = "gpio9";

};

config {

pins = "gpio9";

drive-strength = <0x10>;

slew-rate = <0x00>;

bias-pull-up = <0x00>;

input-enable;

};

};

};

cam_sensor_wide_active {

phandle = <0x564>;

mux {

function = "gpio";

pins = "gpio26";

};

config {

pins = "gpio26";

drive-strength = <0x02>;

bias-disable;

};

};

aw8624_gpio_reset_output_high {

phandle = <0x58c>;

mux {

function = "gpio";

pins = "gpio4";

};

config {

pins = "gpio4";

drive-strength = <0x02>;

bias-disable;

output-high;

};

};

sdc2_cmd_on {

phandle = <0x3e7>;

config {

pins = "sdc2_cmd";

drive-strength = <0x0a>;

bias-pull-up;

};

};

cam_sensor_ultra_active {

phandle = <0x581>;

mux {

function = "gpio";

pins = "gpio25";

};

config {

pins = "gpio25";

drive-strength = <0x02>;

bias-disable;

};

};

onewire_gpio_active {

phandle = <0x587>;

mux {

function = "gpio";

pins = "gpio91";

};

config {

pins = "gpio91";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se6_spi_pins {

phandle = <0x3b9>;

qupv3_se6_spi_sleep {

phandle = <0x198>;

mux {

function = "gpio";

pins = "gpio59\0gpio60\0gpio61\0gpio62";

};

config {

pins = "gpio59\0gpio60\0gpio61\0gpio62";

drive-strength = <0x06>;

bias-disable;

};

};

qupv3_se6_spi_active {

phandle = <0x197>;

mux {

function = "qup10";

pins = "gpio59\0gpio60\0gpio61\0gpio62";

};

config {

pins = "gpio59\0gpio60\0gpio61\0gpio62";

drive-strength = <0x06>;

bias-disable;

};

};

};

qupv3_se3_4uart_pins {

phandle = <0x3b0>;

qupv3_se3_rts {

phandle = <0x172>;

mux {

function = "qup03";

pins = "gpio39";

};

config {

pins = "gpio39";

drive-strength = <0x02>;

bias-pull-down;

};

};

qupv3_se3_tx {

phandle = <0x173>;

mux {

function = "qup03";

pins = "gpio40";

};

config {

pins = "gpio40";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se3_ctsrx {

phandle = <0x171>;

mux {

function = "qup03";

pins = "gpio38\0gpio41";

};

config {

pins = "gpio38\0gpio41";

drive-strength = <0x02>;

bias-no-pull;

};

};

};

qupv3_se11_i2c_pins {

phandle = <0x3c3>;

qupv3_se11_i2c_active {

phandle = <0x18f>;

mux {

function = "qup15";

pins = "gpio101\0gpio102";

};

config {

pins = "gpio101\0gpio102";

drive-strength = <0x02>;

bias-disable;

};

};

qupv3_se11_i2c_sleep {

phandle = <0x190>;

mux {

function = "gpio";

pins = "gpio101\0gpio102";

};

config {

pins = "gpio101\0gpio102";

drive-strength = <0x02>;

bias-pull-up;

};

};

};

qupv3_se2_i2c_pins {

phandle = <0x3a8>;

qupv3_se2_i2c_sleep {

phandle = <0x16c>;

mux {

function = "gpio";

pins = "gpio34\0gpio35";

};

config {

pins = "gpio34\0gpio35";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se2_i2c_active {

phandle = <0x16b>;

mux {

function = "qup02";

pins = "gpio34\0gpio35";

};

config {

pins = "gpio34\0gpio35";

drive-strength = <0x02>;

bias-disable;

};

};

};

sdc2_data_on {

phandle = <0x3e9>;

config {

pins = "sdc2_data";

drive-strength = <0x0a>;

bias-pull-up;

};

};

onewire_gpio_sleep {

phandle = <0x588>;

mux {

function = "gpio";

pins = "gpio91";

};

config {

pins = "gpio91";

drive-strength = <0x02>;

bias-pull-up;

};

};

fpc_reset_int {

int_low {

phandle = <0x3b4>;

mux {

function = "gpio";

pins = "gpio90";

};

config {

pins = "gpio90";

drive-strength = <0x02>;

bias-pull-down;

input-enable;

};

};

reset_high {

phandle = <0x3b3>;

mux {

function = "gpio";

pins = "gpio91";

};

config {

pins = "gpio91";

drive-strength = <0x02>;

bias-disable;

output-high;

};

};

reset_low {

phandle = <0x3b2>;

mux {

function = "gpio";

pins = "gpio91";

};

config {

pins = "gpio91";

drive-strength = <0x02>;

bias-disable;

output-low;

};

};

};

ufs_dev_reset_assert {

phandle = <0x9d>;

config {

pins = "ufs_reset";

drive-strength = <0x08>;

bias-pull-down;

output-low;

};

};

sdc1_rclk_off {

phandle = <0x3e4>;

config {

pins = "sdc1_rclk";

bias-pull-down;

};

};

qupv3_se11_spi_pins {

phandle = <0x3c5>;

qupv3_se11_spi_sleep {

phandle = <0x1a0>;

mux {

function = "gpio";

pins = "gpio101\0gpio102\0gpio103\0gpio92";

};

config {

pins = "gpio101\0gpio102\0gpio103\0gpio92";

drive-strength = <0x06>;

bias-disable;

};

};

qupv3_se11_spi_active {

phandle = <0x19f>;

mux {

function = "qup15";

pins = "gpio101\0gpio102\0gpio103\0gpio92";

};

config {

pins = "gpio101\0gpio102\0gpio103\0gpio92";

drive-strength = <0x06>;

bias-disable;

};

};

};

qupv3_se7_i2c_pins {

phandle = <0x3ba>;

qupv3_se7_i2c_sleep {

phandle = <0x187>;

mux {

function = "gpio";

pins = "gpio6\0gpio7";

};

config {

pins = "gpio6\0gpio7";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se7_i2c_active {

phandle = <0x186>;

mux {

function = "qup11";

pins = "gpio6\0gpio7";

};

config {

pins = "gpio6\0gpio7";

drive-strength = <0x02>;

bias-disable;

};

};

};

aw8624_gpio_reset {

phandle = <0x58b>;

mux {

function = "gpio";

pins = "gpio4";

};

config {

pins = "gpio4";

drive-strength = <0x02>;

bias-disable;

output-low;

};

};

cam_sensor_vddio_disable {

phandle = <0x5a2>;

mux {

function = "gpio";

pins = "gpio5";

};

config {

pins = "gpio5";

drive-strength = <0x02>;

bias-pull-down;

output-low;

};

};

msm_gpio_58 {

phandle = <0x584>;

mux {

function = "gpio";

pins = "gpio58";

};

config {

pins = "gpio58";

driver-strength = <0x02>;

bias-disable;

output-low;

};

};

cd_off {

phandle = <0x3ec>;

mux {

function = "gpio";

pins = "gpio69";

};

config {

pins = "gpio69";

drive-strength = <0x02>;

bias-disable;

};

};

bot_smartpa_int_active {

phandle = <0x51e>;

mux {

function = "gpio";

pins = "gpio56";

};

config {

pins = "gpio56";

drive-strength = <0x02>;

bias-pull-up;

input-enable;

};

};

cam_sensor_f_vdda_f_vddd_enable {

phandle = <0x5a3>;

mux {

function = "gpio";

pins = "gpio57";

};

config {

pins = "gpio57";

drive-strength = <0x02>;

bias-disable;

};

};

smartpa_int_active {

phandle = <0x3f9>;

mux {

function = "gpio";

pins = "gpio56";

};

config {

pins = "gpio56";

drive-strength = <0x02>;

bias-pull-up;

input-enable;

};

};

smartpa_enable_active {

phandle = <0x3fb>;

mux {

function = "gpio";

pins = "gpio67";

};

config {

pins = "gpio67";

drive-strength = <0x02>;

bias-disable;

bias-pull-down;

output-low;

};

};

cam_sensor_mipi_switch_sel_high {

phandle = <0x575>;

mux {

function = "gpio";

pins = "gpio88";

};

config {

pins = "gpio88";

drive-strength = <0x02>;

bias-disable;

output-low;

};

};

sdc2_clk_off {

phandle = <0x3e6>;

config {

pins = "sdc2_clk";

drive-strength = <0x02>;

bias-disable;

};

};

qupv3_se7_spi_pins {

phandle = <0x3bb>;

qupv3_se7_spi_sleep {

phandle = <0x19a>;

mux {

function = "gpio";

pins = "gpio6\0gpio7\0gpio8\0gpio9";

};

config {

pins = "gpio6\0gpio7\0gpio8\0gpio9";

drive-strength = <0x06>;

bias-disable;

};

};

qupv3_se7_spi_active {

phandle = <0x199>;

mux {

function = "qup11";

pins = "gpio6\0gpio7\0gpio8\0gpio9";

};

config {

pins = "gpio6\0gpio7\0gpio8\0gpio9";

drive-strength = <0x06>;

bias-disable;

};

};

};

cam_sensor_mclk1_suspend {

phandle = <0x582>;

mux {

function = "cam_mclk";

pins = "gpio14";

};

config {

pins = "gpio14";

drive-strength = <0x04>;

bias-pull-down;

};

};

cam_sensor_front_active {

phandle = <0x56d>;

mux {

function = "gpio";

pins = "gpio23";

};

config {

pins = "gpio23";

drive-strength = <0x02>;

bias-disable;

};

};

sdc2_cmd_off {

phandle = <0x3e8>;

config {

pins = "sdc2_cmd";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se3_i2c_pins {

phandle = <0x3af>;

qupv3_se3_i2c_active {

phandle = <0x16d>;

mux {

function = "qup03";

pins = "gpio38\0gpio39";

};

config {

pins = "gpio38\0gpio39";

drive-strength = <0x02>;

bias-disable;

};

};

qupv3_se3_i2c_sleep {

phandle = <0x16e>;

mux {

function = "gpio";

pins = "gpio38\0gpio39";

};

config {

pins = "gpio38\0gpio39";

drive-strength = <0x02>;

bias-pull-up;

};

};

};

nfc {

nfc_int_suspend {

phandle = <0x3aa>;

mux {

function = "gpio";

pins = "gpio37";

};

config {

pins = "gpio37";

drive-strength = <0x02>;

bias-pull-up;

};

};

nfc_enable_active {

phandle = <0x3ab>;

mux {

function = "gpio";

pins = "gpio66\0gpio36";

};

config {

pins = "gpio66\0gpio36";

drive-strength = <0x02>;

bias-pull-up;

};

};

nfc_int_active {

phandle = <0x3a9>;

mux {

function = "gpio";

pins = "gpio37";

};

config {

pins = "gpio37";

drive-strength = <0x02>;

bias-pull-up;

};

};

nfc_enable_suspend {

phandle = <0x3ac>;

mux {

function = "gpio";

pins = "gpio66\0gpio36";

};

config {

pins = "gpio66\0gpio36";

drive-strength = <0x02>;

bias-disable;

};

};

nfc_clk_req_active {

phandle = <0x3ad>;

mux {

function = "gpio";

pins = "gpio31";

};

config {

pins = "gpio31";

drive-strength = <0x02>;

bias-pull-up;

};

};

nfc_clk_req_suspend {

phandle = <0x3ae>;

mux {

function = "gpio";

pins = "gpio31";

};

config {

pins = "gpio31";

drive-strength = <0x02>;

bias-disable;

};

};

};

pri_i2s_data0 {

pri_i2s_data0_sleep {

phandle = <0x51a>;

mux {

function = "pri_mi2s";

pins = "gpio52";

};

config {

pins = "gpio52";

drive-strength = <0x02>;

};

};

pri_i2s_data0_active {

phandle = <0x516>;

mux {

function = "pri_mi2s";

pins = "gpio52";

};

config {

pins = "gpio52";

drive-strength = <0x08>;

bias-disable;

input-enable;

};

};

};

cam_sensor_wide_suspend {

phandle = <0x566>;

mux {

function = "gpio";

pins = "gpio26";

};

config {

pins = "gpio26";

drive-strength = <0x02>;

bias-pull-down;

output-low;

};

};

sdc1_clk_on {

phandle = <0x3dd>;

config {

pins = "sdc1_clk";

drive-strength = <0x10>;

bias-disable;

};

};

wsa_swr_data_pin {

wsa_swr_data_active {

phandle = <0x3cf>;

mux {

function = "wsa_data";

pins = "gpio50";

};

config {

pins = "gpio50";

drive-strength = <0x04>;

bias-bus-hold;

};

};

wsa_swr_data_sleep {

phandle = <0x3ce>;

mux {

function = "wsa_data";

pins = "gpio50";

};

config {

pins = "gpio50";

drive-strength = <0x04>;

bias-bus-hold;

};

};

};

pmx_ts_reset_suspend {

ts_reset_suspend {

phandle = <0x591>;

mux {

function = "gpio";

pins = "gpio8";

};

config {

pins = "gpio8";

drive-strength = <0x02>;

bias-disable;

bias-pull-down;

};

};

tp_reset_suspend {

phandle = <0x59d>;

mux {

function = "gpio";

pins = "gpio8";

};

config {

pins = "gpio8";

drive-strength = <0x10>;

bias-disable;

output-high;

slew-rate = <0x01>;

};

};

};

qupv3_se8_i2c_pins {

phandle = <0x3bc>;

qupv3_se8_i2c_active {

phandle = <0x188>;

mux {

function = "qup12";

pins = "gpio42\0gpio43";

};

config {

pins = "gpio42\0gpio43";

drive-strength = <0x02>;

bias-disable;

};

};

qupv3_se8_i2c_sleep {

phandle = <0x189>;

mux {

function = "gpio";

pins = "gpio42\0gpio43";

};

config {

pins = "gpio42\0gpio43";

drive-strength = <0x02>;

bias-pull-up;

};

};

};

sdc2_clk_on {

phandle = <0x3e5>;

config {

pins = "sdc2_clk";

drive-strength = <0x10>;

bias-disable;

};

};

cam_sensor_depth_active {

phandle = <0x57b>;

mux {

function = "gpio";

pins = "gpio21";

};

config {

pins = "gpio21";

drive-strength = <0x02>;

bias-disable;

};

};

cci1_suspend {

phandle = <0x1b3>;

mux {

function = "cci_i2c";

pins = "gpio19\0gpio20";

};

config {

pins = "gpio19\0gpio20";

drive-strength = <0x02>;

bias-pull-down;

};

};

qupv3_se3_spi_pins {

phandle = <0x3b1>;

qupv3_se3_spi_sleep {

phandle = <0x17d>;

mux {

function = "gpio";

pins = "gpio38\0gpio39\0gpio40\0gpio41";

};

config {

pins = "gpio38\0gpio39\0gpio40\0gpio41";

drive-strength = <0x06>;

bias-disable;

};

};

qupv3_se3_spi_active {

phandle = <0x17c>;

mux {

function = "qup03";

pins = "gpio38\0gpio39\0gpio40\0gpio41";

};

config {

pins = "gpio38\0gpio39\0gpio40\0gpio41";

drive-strength = <0x06>;

bias-disable;

};

};

};

cam_sensor_mipi_switch_sel_low {

phandle = <0x578>;

mux {

function = "gpio";

pins = "gpio88";

};

config {

pins = "gpio88";

drive-strength = <0x02>;

bias-disable;

};

};

sde_dp_aux_suspend {

phandle = <0x3cb>;

mux {

function = "gpio";

pins = "gpio42\0gpio33";

};

config {

pins = "gpio42\0gpio33";

drive-strength = <0x02>;

bias-pull-down;

};

};

cam_sensor_mclk3_suspend {

phandle = <0x576>;

mux {

function = "cam_mclk";

pins = "gpio16";

};

config {

pins = "gpio16";

drive-strength = <0x04>;

bias-pull-down;

};

};

cam_sensor_front_suspend {

phandle = <0x56f>;

mux {

function = "gpio";

pins = "gpio23";

};

config {

pins = "gpio23";

drive-strength = <0x02>;

bias-pull-down;

output-low;

};

};

wcd9xxx_intr {

wcd_intr_default {

phandle = <0x3d4>;

mux {

function = "gpio";

pins = "gpio58";

};

config {

pins = "gpio58";

drive-strength = <0x02>;

bias-pull-down;

input-enable;

};

};

};

pmx_ts_release {

ts_release {

phandle = <0x3f0>;

mux {

function = "gpio";

pins = "gpio9\0gpio8";

};

config {

pins = "gpio9\0gpio8";

drive-strength = <0x02>;

bias-disable;

};

};

};

qupv3_se4_4uart_pins {

phandle = <0x3b6>;

qupv3_se4_ctsrx {

phandle = <0x175>;

mux {

function = "qup04";

pins = "gpio53\0gpio56";

};

config {

pins = "gpio53\0gpio56";

drive-strength = <0x02>;

bias-no-pull;

};

};

qupv3_se4_tx {

phandle = <0x177>;

mux {

function = "qup04";

pins = "gpio55";

};

config {

pins = "gpio55";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se4_rts {

phandle = <0x176>;

mux {

function = "qup04";

pins = "gpio54";

};

config {

pins = "gpio54";

drive-strength = <0x02>;

bias-pull-down;

};

};

};

qupv3_se8_spi_pins {

phandle = <0x3be>;

qupv3_se8_spi_sleep {

phandle = <0x19c>;

mux {

function = "gpio";

pins = "gpio42\0gpio43\0gpio44\0gpio45";

};

config {

pins = "gpio42\0gpio43\0gpio44\0gpio45";

drive-strength = <0x06>;

bias-disable;

};

};

qupv3_se8_spi_active {

phandle = <0x19b>;

mux {

function = "qup12";

pins = "gpio42\0gpio43\0gpio44\0gpio45";

};

config {

pins = "gpio42\0gpio43\0gpio44\0gpio45";

drive-strength = <0x06>;

bias-disable;

};

};

};

cam_sensor_mclk0_active {

phandle = <0x56c>;

mux {

function = "cam_mclk";

pins = "gpio13";

};

config {

pins = "gpio13";

drive-strength = <0x06>;

bias-disable;

};

};

fsa_usbc_ana_en_n@42 {

fsa_usbc_ana_en {

phandle = <0x18c>;

mux {

function = "gpio";

pins = "gpio42";

};

config {

pins = "gpio42";

drive-strength = <0x02>;

bias-disable;

output-low;

};

};

};

bq2597x {

bq2597x_int_suspend {

phandle = <0x58a>;

mux {

function = "gpio";

pins = "gpio55";

};

config {

pins = "gpio55";

drive-strength = <0x02>;

bias-pull-up;

input-enable;

};

};

bq2597x_int_default {

phandle = <0x589>;

mux {

function = "gpio";

pins = "gpio55";

};

config {

pins = "gpio55";

drive-strength = <0x02>;

bias-pull-up;

input-enable;

};

};

};

qupv3_se4_i2c_pins {

phandle = <0x3b5>;

qupv3_se4_i2c_active {

phandle = <0x16f>;

mux {

function = "qup04";

pins = "gpio53\0gpio54";

};

config {

pins = "gpio53\0gpio54";

drive-strength = <0x02>;

bias-disable;

};

};

qupv3_se4_i2c_sleep {

phandle = <0x170>;

mux {

function = "gpio";

pins = "gpio53\0gpio54";

};

config {

pins = "gpio53\0gpio54";

drive-strength = <0x02>;

bias-pull-up;

};

};

};

top_smartpa_int_suspend {

phandle = <0x51d>;

mux {

function = "gpio";

pins = "gpio93";

};

config {

pins = "gpio93";

drive-strength = <0x02>;

bias-pull-up;

input-enable;

};

};

sdc1_data_on {

phandle = <0x3e1>;

config {

pins = "sdc1_data";

drive-strength = <0x0a>;

bias-pull-up;

};

};

pmx_sde_te {

sde_te_suspend {

phandle = <0x3c7>;

mux {

function = "mdp_vsync";

pins = "gpio10";

};

config {

pins = "gpio10";

drive-strength = <0x02>;

bias-pull-down;

};

};

sde_te1_active {

phandle = <0x3c8>;

mux {

function = "mdp_vsync";

pins = "gpio11";

};

config {

pins = "gpio11";

drive-strength = <0x02>;

bias-pull-down;

};

};

sde_te1_suspend {

phandle = <0x3c9>;

mux {

function = "mdp_vsync";

pins = "gpio11";

};

config {

pins = "gpio11";

drive-strength = <0x02>;

bias-pull-down;

};

};

sde_te_active {

phandle = <0x3c6>;

mux {

function = "mdp_vsync";

pins = "gpio10";

};

config {

pins = "gpio10";

drive-strength = <0x02>;

bias-pull-down;

};

};

};

cam_sensor_mclk1_active {

phandle = <0x580>;

mux {

function = "cam_mclk";

pins = "gpio14";

};

config {

pins = "gpio14";

drive-strength = <0x04>;

bias-disable;

};

};

sde_dp_aux_active {

phandle = <0x3ca>;

mux {

function = "gpio";

pins = "gpio42\0gpio33";

};

config {

pins = "gpio42\0gpio33";

drive-strength = <0x08>;

bias-disable = <0x00>;

};

};

sdc1_rclk_on {

phandle = <0x3e3>;

config {

pins = "sdc1_rclk";

bias-pull-down;

};

};

qupv3_se10_4uart_pins {

phandle = <0x3c1>;

qupv3_se10_ctsrx {

phandle = <0x191>;

mux {

function = "qup14";

pins = "gpio110\0gpio113";

};

config {

pins = "gpio110\0gpio113";

drive-strength = <0x02>;

bias-no-pull;

};

};

qupv3_se10_tx {

phandle = <0x193>;

mux {

function = "qup14";

pins = "gpio112";

};

config {

pins = "gpio112";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se10_rts {

phandle = <0x192>;

mux {

function = "qup14";

pins = "gpio111";

};

config {

pins = "gpio111";

drive-strength = <0x02>;

bias-pull-down;

};

};

};

bot_smartpa_int_suspend {

phandle = <0x51f>;

mux {

function = "gpio";

pins = "gpio56";

};

config {

pins = "gpio56";

drive-strength = <0x02>;

bias-pull-up;

input-enable;

};

};

cam_sensor_mclk2_active {

phandle = <0x563>;

mux {

function = "cam_mclk";

pins = "gpio15";

};

config {

pins = "gpio15";

drive-strength = <0x04>;

bias-disable;

};

};

qupv3_se9_i2c_pins {

phandle = <0x3bf>;

qupv3_se9_i2c_active {

phandle = <0x18a>;

mux {

function = "qup13";

pins = "gpio46\0gpio47";

};

config {

pins = "gpio46\0gpio47";

drive-strength = <0x02>;

bias-disable;

};

};

qupv3_se9_i2c_sleep {

phandle = <0x18b>;

mux {

function = "gpio";

pins = "gpio46\0gpio47";

};

config {

pins = "gpio6\0gpio7";

drive-strength = <0x02>;

bias-pull-up;

};

};

};

qupv3_se4_spi_pins {

phandle = <0x3b7>;

qupv3_se4_spi_active {

phandle = <0x17e>;

mux {

function = "qup04";

pins = "gpio53\0gpio54\0gpio55\0gpio56";

};

config {

pins = "gpio53\0gpio54\0gpio55\0gpio56";

drive-strength = <0x06>;

bias-disable;

};

};

qupv3_se4_spi_sleep {

phandle = <0x17f>;

mux {

function = "gpio";

pins = "gpio53\0gpio54\0gpio55\0gpio56";

};

config {

pins = "gpio53\0gpio54\0gpio55\0gpio56";

drive-strength = <0x06>;

bias-disable;

};

};

};

pmx_ts_active {

tp_active {

phandle = <0x59b>;

mux {

function = "gpio";

pins = "gpio9\0gpio8";

};

config {

pins = "gpio9\0gpio8";

drive-strength = <0x10>;

bias-pull-up;

};

};

ts_active {

phandle = <0x58f>;

mux {

function = "gpio";

pins = "gpio8\0gpio9";

};

config {

pins = "gpio8\0gpio9";

drive-strength = <0x08>;

bias-pull-up;

};

};

};

cam_sensor_mclk3_active {

phandle = <0x573>;

mux {

function = "cam_mclk";

pins = "gpio16";

};

config {

pins = "gpio16";

drive-strength = <0x04>;

bias-disable;

};

};

qupv3_se0_i2c_pins {

phandle = <0x3a4>;

qupv3_se0_i2c_sleep {

phandle = <0x167>;

mux {

function = "gpio";

pins = "gpio49\0gpio50";

};

config {

pins = "gpio49\0gpio50";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se0_i2c_active {

phandle = <0x166>;

mux {

function = "qup00";

pins = "gpio49\0gpio50";

};

config {

pins = "gpio49\0gpio50";

drive-strength = <0x02>;

bias-disable;

};

};

};

top_smartpa_int_active {

phandle = <0x51c>;

mux {

function = "gpio";

pins = "gpio93";

};

config {

pins = "gpio93";

drive-strength = <0x02>;

bias-pull-up;

input-enable;

};

};

qupv3_se8_2uart_pins {

phandle = <0x3bd>;

qupv3_se8_2uart_sleep {

phandle = <0x181>;

mux {

function = "gpio";

pins = "gpio44\0gpio45";

};

config {

pins = "gpio44\0gpio45";

drive-strength = <0x02>;

bias-disable;

};

};

qupv3_se8_2uart_active {

phandle = <0x180>;

mux {

function = "qup12";

pins = "gpio44\0gpio45";

};

config {

pins = "gpio44\0gpio45";

drive-strength = <0x02>;

bias-disable;

};

};

};

sde_dp_usbplug_cc_suspend {

phandle = <0x1ad>;

mux {

function = "gpio";

pins = "gpio104";

};

config {

pins = "gpio104";

drive-strength = <0x02>;

bias-pull-down;

};

};

cam_sensor_depth_suspend {

phandle = <0x57c>;

mux {

function = "gpio";

pins = "gpio21";

};

config {

pins = "gpio21";

drive-strength = <0x02>;

bias-pull-down;

output-low;

};

};

sdc1_clk_off {

phandle = <0x3de>;

config {

pins = "sdc1_clk";

drive-strength = <0x02>;

bias-disable;

};

};

sdc1_data_off {

phandle = <0x3e2>;

config {

pins = "sdc1_data";

drive-strength = <0x02>;

bias-pull-up;

};

};

cam_sensor_mclk0_suspend {

phandle = <0x56e>;

mux {

function = "cam_mclk";

pins = "gpio13";

};

config {

pins = "gpio13";

drive-strength = <0x06>;

bias-pull-down;

};

};

ufs_dev_reset_deassert {

phandle = <0x9e>;

config {

pins = "ufs_reset";

drive-strength = <0x08>;

output-high;

bias-pull-down;

};

};

smartpa_int_suspend {

phandle = <0x3fa>;

mux {

function = "gpio";

pins = "gpio56";

};

config {

pins = "gpio56";

drive-strength = <0x02>;

bias-pull-up;

input-enable;

};

};

cam_sensor_ultra_suspend {

phandle = <0x583>;

mux {

function = "gpio";

pins = "gpio25";

};

config {

pins = "gpio25";

drive-strength = <0x02>;

bias-pull-down;

output-low;

};

};

pri_i2s_sck_ws {

pri_i2s_sck_sleep {

phandle = <0x518>;

mux {

function = "pri_mi2s";

pins = "gpio49";

};

config {

pins = "gpio49";

drive-strength = <0x02>;

};

};

pri_i2s_ws_active {

phandle = <0x515>;

mux {

function = "pri_mi2s_ws";

pins = "gpio50";

};

config {

pins = "gpio50";

drive-strength = <0x08>;

bias-disable;

output-high;

};

};

pri_i2s_sck_active {

phandle = <0x514>;

mux {

function = "pri_mi2s";

pins = "gpio49";

};

config {

pins = "gpio49";

drive-strength = <0x08>;

bias-disable;

output-high;

};

};

pri_i2s_ws_sleep {

phandle = <0x519>;

mux {

function = "pri_mi2s_ws";

pins = "gpio50";

};

config {

pins = "gpio50";

drive-strength = <0x02>;

};

};

};

cam_sensor_mipi_switch1_sel_high {

phandle = <0x5a6>;

mux {

function = "gpio";

pins = "gpio90";

};

config {

pins = "gpio90";

drive-strength = <0x02>;

bias-disable;

output-low;

};

};

sdc1_cmd_off {

phandle = <0x3e0>;

config {

num-grp-pins = <0x01>;

pins = "sdc1_cmd";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se0_spi_pins {

phandle = <0x3a5>;

qupv3_se0_spi_sleep {

phandle = <0x179>;

mux {

function = "gpio";

pins = "gpio49\0gpio50\0gpio51\0gpio52";

};

config {

pins = "gpio49\0gpio50\0gpio51\0gpio52";

drive-strength = <0x06>;

bias-disable;

};

};

qupv3_se0_spi_active {

phandle = <0x178>;

mux {

function = "qup00";

pins = "gpio49\0gpio50\0gpio51\0gpio52";

};

config {

pins = "gpio49\0gpio50\0gpio51\0gpio52";

drive-strength = <0x06>;

bias-disable;

};

};

};

msm_gpio_57 {

phandle = <0x586>;

mux {

function = "gpio";

pins = "gpio57";

};

config {

pins = "gpio57";

drive-strength = <0x02>;

bias-pull-down;

};

};

pri_i2s_data1 {

pri_i2s_data1_sleep {

phandle = <0x51b>;

mux {

function = "pri_mi2s";

pins = "gpio51";

};

config {

pins = "gpio51";

drive-strength = <0x02>;

};

};

pri_i2s_data1_active {

phandle = <0x517>;

mux {

function = "pri_mi2s";

pins = "gpio51";

};

config {

pins = "gpio51";

drive-strength = <0x08>;

bias-disable;

output-high;

};

};

};

spkr_2_sd_n {

spkr_2_sd_n_active {

phandle = <0x3d3>;

mux {

function = "gpio";

pins = "gpio52";

};

config {

pins = "gpio52";

drive-strength = <0x10>;

bias-disable;

output-high;

};

};

spkr_2_sd_n_sleep {

phandle = <0x3d2>;

mux {

function = "gpio";

pins = "gpio52";

};

config {

pins = "gpio52";

drive-strength = <0x02>;

bias-pull-down;

input-enable;

};

};

};

wsa_swr_clk_pin {

wsa_swr_clk_active {

phandle = <0x3cd>;

mux {

function = "wsa_clk";

pins = "gpio49";

};

config {

pins = "gpio49";

drive-strength = <0x02>;

bias-bus-hold;

};

};

wsa_swr_clk_sleep {

phandle = <0x3cc>;

mux {

function = "wsa_clk";

pins = "gpio49";

};

config {

pins = "gpio49";

drive-strength = <0x02>;

bias-bus-hold;

};

};

};

smartpa_enable_suspend {

phandle = <0x3fc>;

mux {

function = "gpio";

pins = "gpio67";

};

config {

pins = "gpio67";

drive-strength = <0x02>;

bias-disable;

bias-pull-down;

output-low;

};

};

cam_sensor_mipi_switch1_sel_low {

phandle = <0x5a5>;

mux {

function = "gpio";

pins = "gpio90";

};

config {

pins = "gpio90";

drive-strength = <0x02>;

bias-disable;

};

};

cci0_suspend {

phandle = <0x1b2>;

mux {

function = "cci_i2c";

pins = "gpio17\0gpio18";

};

config {

pins = "gpio17\0gpio18";

drive-strength = <0x02>;

bias-pull-down;

};

};

cam_sensor_mclk2_suspend {

phandle = <0x565>;

mux {

function = "cam_mclk";

pins = "gpio15";

};

config {

pins = "gpio15";

drive-strength = <0x04>;

bias-pull-down;

};

};

cd_on {

phandle = <0x3eb>;

mux {

function = "gpio";

pins = "gpio69";

};

config {

pins = "gpio69";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se10_i2c_pins {

phandle = <0x3c0>;

qupv3_se10_i2c_sleep {

phandle = <0x18e>;

mux {

function = "gpio";

pins = "gpio110\0gpio111";

};

config {

pins = "gpio110\0gpio111";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se10_i2c_active {

phandle = <0x18d>;

mux {

function = "qup14";

pins = "gpio110\0gpio111";

};

config {

pins = "gpio110\0gpio111";

drive-strength = <0x02>;

bias-disable;

};

};

};

cci0_active {

phandle = <0x1b0>;

mux {

function = "cci_i2c";

pins = "gpio17\0gpio18";

};

config {

pins = "gpio17\0gpio18";

drive-strength = <0x02>;

bias-pull-up;

};

};

qupv3_se1_i2c_pins {

phandle = <0x3a6>;

qupv3_se1_i2c_active {

phandle = <0x169>;

mux {

function = "qup01";

pins = "gpio0\0gpio1";

};

config {

pins = "gpio0\0gpio1";

drive-strength = <0x02>;

bias-disable;

};

};

qupv3_se1_i2c_sleep {

phandle = <0x16a>;

mux {

function = "gpio";

pins = "gpio0\0gpio1";

};

config {

pins = "gpio0\0gpio1";

drive-strength = <0x02>;

bias-pull-up;

};

};

};

cam_sensor_vddio_enable {

phandle = <0x5a1>;

mux {

function = "gpio";

pins = "gpio5";

};

config {

pins = "gpio5";

drive-strength = <0x02>;

bias-disable;

};

};

msm_gpio_24_output_high {

phandle = <0x585>;

mux {

function = "gpio";

pins = "gpio58";

};

config {

pins = "gpio58";

drive-strength = <0x02>;

bias-disable;

output-high;

};

};

cci1_active {

phandle = <0x1b1>;

mux {

function = "cci_i2c";

pins = "gpio19\0gpio20";

};

config {

pins = "gpio19\0gpio20";

drive-strength = <0x02>;

bias-pull-up;

};

};

sdc2_data_off {

phandle = <0x3ea>;

config {

pins = "sdc2_data";

drive-strength = <0x02>;

bias-pull-up;

};

};

cam_sensor_macro_suspend {

phandle = <0x577>;

mux {

function = "gpio";

pins = "gpio24";

};

config {

pins = "gpio24";

drive-strength = <0x02>;

bias-pull-down;

output-low;

};

};

spkr_1_sd_n {

spkr_1_sd_n_active {

phandle = <0x3d1>;

mux {

function = "gpio";

pins = "gpio51";

};

config {

pins = "gpio51";

drive-strength = <0x10>;

bias-disable;

output-high;

};

};

spkr_1_sd_n_sleep {

phandle = <0x3d0>;

mux {

function = "gpio";

pins = "gpio51";

};

config {

pins = "gpio51";

drive-strength = <0x02>;

bias-pull-down;

input-enable;

};

};

};

sde_dp_usbplug_cc_active {

phandle = <0x1ac>;

mux {

function = "gpio";

pins = "gpio104";

};

config {

pins = "gpio104";

drive-strength = <0x10>;

bias-disable;

};

};

qupv3_se10_spi_pins {

phandle = <0x3c2>;

qupv3_se10_spi_active {

phandle = <0x19d>;

mux {

function = "qup14";

pins = "gpio110\0gpio111\0gpio112\0gpio113";

};

config {

pins = "gpio110\0gpio111\0gpio112\0gpio113";

drive-strength = <0x06>;

bias-disable;

};

};

qupv3_se10_spi_sleep {

phandle = <0x19e>;

mux {

function = "gpio";

pins = "gpio110\0gpio111\0gpio112\0gpio113";

};

config {

pins = "gpio110\0gpio111\0gpio112\0gpio113";

drive-strength = <0x06>;

bias-disable;

};

};

};

qupv3_se6_i2c_pins {

phandle = <0x3b8>;

qupv3_se6_i2c_active {

phandle = <0x184>;

mux {

function = "qup10";

pins = "gpio59\0gpio60";

};

config {

pins = "gpio59\0gpio60";

drive-strength = <0x02>;

bias-disable;

};

};

qupv3_se6_i2c_sleep {

phandle = <0x185>;

mux {

function = "gpio";

pins = "gpio59\0gpio60";

};

config {

pins = "gpio59\0gpio60";

drive-strength = <0x02>;

bias-pull-up;

};

};

};

cam_sensor_f_vdda_f_vddd_disable {

phandle = <0x5a4>;

mux {

function = "gpio";

pins = "gpio57";

};

config {

pins = "gpio57";

drive-strength = <0x02>;

bias-pull-down;

output-low;

};

};

qupv3_se1_spi_pins {

phandle = <0x3a7>;

qupv3_se1_spi_sleep {

phandle = <0x17b>;

mux {

function = "gpio";

pins = "gpio0\0gpio1\0gpio2\0gpio3";

};

config {

pins = "gpio0\0gpio1\0gpio2\0gpio3";

drive-strength = <0x06>;

bias-disable;

};

};

qupv3_se1_spi_active {

phandle = <0x17a>;

mux {

function = "qup01";

pins = "gpio0\0gpio1\0gpio2\0gpio3";

};

config {

pins = "gpio0\0gpio1\0gpio2\0gpio3";

drive-strength = <0x06>;

bias-disable;

};

};

};

cci2_suspend {

phandle = <0x1b5>;

mux {

function = "cci_i2c";

pins = "gpio27\0gpio28";

};

config {

pins = "gpio27\0gpio28";

drive-strength = <0x02>;

bias-pull-down;

};

};

cam_sensor_macro_active {

phandle = <0x574>;

mux {

function = "gpio";

pins = "gpio24";

};

config {

pins = "gpio24";

drive-strength = <0x02>;

bias-disable;

};

};

cci2_active {

phandle = <0x1b4>;

mux {

function = "cci_i2c";

pins = "gpio27\0gpio28";

};

config {

pins = "gpio27\0gpio28";

drive-strength = <0x02>;

bias-pull-up;

};

};

};

dcc_v2@10a2000 {

dcc-ram-offset = <0x6000>;

reg-names = "dcc-base\0dcc-ram-base";

compatible = "qcom,dcc-v2";

reg = <0x10a2000 0x1000 0x10ae000 0x2000>;

phandle = <0x2d2>;

};

qcom,cam-cpas@ac40000 {

camnoc-bus-width = <0x20>;

client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0cci0\0cci1\0csid0\0csid1\0csid2\0iferdi0\0ifenrdi0\0iferdi1\0ifenrdi1\0iferdi2\0ifenrdi2\0ipe0\0ipe1\0cam-cdm-intf0\0cpas-cdm0\0bps0\0icp0\0jpeg-dma0\0jpeg-enc0\0fd0\0lrmecpas0";

vdd-corners = <0x01 0x11 0x31 0x41 0x81 0xc1 0x101 0x141 0x151 0x181 0x1a1>;

clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0slow_ahb_clk_src\0cpas_ahb_clk\0camnoc_axi_clk_src\0camnoc_axi_clk";

client-axi-port-names = "cam_hf_0\0cam_hf_0\0cam_hf_0\0cam_hf_0\0cam_sf_0\0cam_sf_0\0cam_hf_0\0cam_hf_0\0cam_hf_0\0cam_hf_1\0cam_hf_0\0cam_hf_1\0cam_hf_0\0cam_hf_1\0cam_hf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_1\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0";

reg-names = "cam_cpas_top\0cam_camnoc";

qcom,msm-bus,name = "cam_ahb";

reg-cam-base = <0x40000 0x42000>;

cell-index = <0x00>;

vdd-corner-ahb-mapping = "suspend\0suspend\0minsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo";

control-camnoc-axi-clk;

camss-vdd-supply = <0x1ae>;

interrupts = <0x00 0x1cb 0x00>;

clocks = <0x27 0x0e 0x27 0x0f 0x27 0x10 0x29 0x5a 0x29 0x1a 0x29 0x13 0x29 0x12>;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x06>;

label = "cpas";

client-id-based;

clock-cntl-level = "suspend\0lowsvs\0svs\0svs_l1\0nominal\0turbo";

client-bus-camnoc-based;

compatible = "qcom,cam-cpas";

src-clock-name = "camnoc_axi_clk_src";

status = "ok";

camnoc-axi-clk-bw-margin-perc = <0x14>;

interrupt-names = "cpas_camnoc";

reg = <0xac40000 0x1000 0xac42000 0x6000>;

regulator-names = "camss-vdd";

qcom,msm-bus,vectors-KBps = <0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x1d4c0 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x493e0 0x01 0x24d 0x00 0x493e0>;

qcom,cam-cx-ipeak = <0x1a3 0x03>;

clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x8f0d180 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0xe4e1c00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x1312d000 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x1c9c3800 0x00>;

arch-compat = "cpas_top";

camnoc-axi-min-ib-bw = <0xb2d05e00>;

qcom,axi-port-list {

qcom,axi-port4 {

qcom,axi-port-name = "cam_sf_1";

qcom,axi-port-mnoc {

qcom,msm-bus,name = "cam_sf_1_mnoc";

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,msm-bus,vectors-KBps = <0xab 0x200 0x00 0x00 0xab 0x200 0x00 0x00>;

qcom,msm-bus-vector-dyn-vote;

};

qcom,axi-port-camnoc {

qcom,msm-bus,name = "cam_sf_1_camnoc";

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,msm-bus,vectors-KBps = <0xb3 0x30a 0x00 0x00 0xb3 0x30a 0x00 0x00>;

qcom,msm-bus-vector-dyn-vote;

};

};

qcom,axi-port2 {

ib-bw-voting-needed;

qcom,axi-port-name = "cam_hf_1";

qcom,axi-port-mnoc {

qcom,msm-bus,name = "cam_hf_1_mnoc";

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,msm-bus,vectors-KBps = <0xac 0x200 0x00 0x00 0xac 0x200 0x00 0x00>;

qcom,msm-bus-vector-dyn-vote;

};

qcom,axi-port-camnoc {

qcom,msm-bus,name = "cam_hf_1_camnoc";

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,msm-bus,vectors-KBps = <0xb2 0x30a 0x00 0x00 0xb2 0x30a 0x00 0x00>;

qcom,msm-bus-vector-dyn-vote;

};

};

qcom,axi-port3 {

qcom,axi-port-name = "cam_sf_0";

qcom,axi-port-mnoc {

qcom,msm-bus,name = "cam_sf_0_mnoc";

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,msm-bus,vectors-KBps = <0x89 0x200 0x00 0x00 0x89 0x200 0x00 0x00>;

qcom,msm-bus-vector-dyn-vote;

};

qcom,axi-port-camnoc {

qcom,msm-bus,name = "cam_sf_0_camnoc";

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,msm-bus,vectors-KBps = <0x94 0x30a 0x00 0x00 0x94 0x30a 0x00 0x00>;

qcom,msm-bus-vector-dyn-vote;

};

};

qcom,axi-port1 {

ib-bw-voting-needed;

qcom,axi-port-name = "cam_hf_0";

qcom,axi-port-mnoc {

qcom,msm-bus,name = "cam_hf_0_mnoc";

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,msm-bus,vectors-KBps = <0x88 0x200 0x00 0x00 0x88 0x200 0x00 0x00>;

qcom,msm-bus-vector-dyn-vote;

};

qcom,axi-port-camnoc {

qcom,msm-bus,name = "cam_hf_0_camnoc";

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,msm-bus,vectors-KBps = <0x92 0x30a 0x00 0x00 0x92 0x30a 0x00 0x00>;

qcom,msm-bus-vector-dyn-vote;

};

};

};

};

etm@7440000 {

arm,primecell-periphid = <0xbb95d>;

clock-names = "apb_pclk";

clocks = <0x19 0x00>;

cpu = <0x15>;

qcom,tupwr-disable;

coresight-name = "coresight-etm4";

compatible = "arm,primecell";

reg = <0x7440000 0x1000>;

phandle = <0x440>;

port {

endpoint {

remote-endpoint = <0x221>;

phandle = <0x219>;

};

};

};

rpmh-regulator-ldoa4 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa4";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l4 {

regulator-max-microvolt = <0xe09c0>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0xc92c0>;

regulator-min-microvolt = <0xc92c0>;

regulator-name = "pm6150_l4";

qcom,set = <0x03>;

phandle = <0x1a9>;

};

};

funnel@69C3000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-dl-mm";

compatible = "arm,primecell";

reg = <0x69c3000 0x1000>;

phandle = <0x44b>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x23e>;

phandle = <0x22f>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x23f>;

phandle = <0x240>;

};

};

};

};

qcom,mdss_mdp@ae00000 {

iommus = <0x30 0x800 0x440>;

qcom,sde-safe-lut-macrotile-qseed = <0x00 0xf000>;

qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0>;

qcom,sde-qseed-type = "qseedv3lite";

qcom,sde-max-per-pipe-bw-kbps = <0x3567e0 0x3567e0 0x3567e0 0x3567e0 0x3567e0>;

qcom,sde-smart-dma-rev = "smart_dma_v2p5";

qcom,sde-mixer-cwb-pref = "none\0none\0cwb\0cwb\0none\0none";

qcom,sde-vbif-off = <0x00>;

qcom,sde-panic-per-pipe;

qcom,sde-danger-lut = <0x0f 0xffff 0x00 0x00 0xffff>;

qcom,sde-te2-off = <0x2000 0x2000 0x00 0x00>;

qcom,sde-sspp-smart-dma-priority = <0x04 0x05 0x01 0x02 0x03>;

qcom,sde-sspp-qseed-off = <0xa00>;

qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none";

qcom,sde-dspp-size = <0x1800>;

qcom,sde-sspp-src-size = <0x1f0>;

clock-max-rate = <0x00 0x00 0x00 0x00 0x19a14780 0x124f800 0x19a14780 0x19a14780>;

#address-cells = <0x01>;

qcom,sde-sspp-excl-rect = <0x01 0x01 0x01 0x01 0x01>;

qcom,sde-wb-id = <0x02>;

qcom,sde-safe-lut-macrotile = <0x00 0xf000>;

qcom,sde-wb-size = <0x2c8>;

qcom,sde-qos-lut-nrt = <0x00 0x00 0x00>;

qcom,sde-axi-bus-width = <0x20>;

connectors = <0x36d 0x55e 0x55f 0x560>;

qcom,sde-safe-lut-cwb = <0x00 0xffff>;

qcom,sde-pp-size = <0xd4>;

qcom,sde-dest-scaler-top-off = <0x61000>;

clock-names = "gcc_iface\0gcc_bus\0gcc_nrt_bus\0iface_clk\0core_clk\0vsync_clk\0lut_clk\0rot_clk";

reg-names = "mdp_phys\0vbif_phys\0regdma_phys";

qcom,sde-qos-lut-macrotile-qseed = <0x00 0x112233 0x66777777>;

qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>;

qcom,sde-max-dest-scaler-output-linewidth = <0xa00>;

qcom,sde-qos-cpu-mask = <0x03>;

qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600 0x2800 0x2a00>;

qcom,sde-dest-scaler-size = <0xa0>;

qcom,sde-vbif-qos-nrt-remap = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>;

qcom,sde-num-mnoc-ports = <0x02>;

qcom,sde-cdp-setting = <0x01 0x01 0x01 0x00>;

qcom,sde-dspp-ad-version = <0x40000>;

qcom,sde-reg-dma-trigger-off = <0x119c>;

qcom,sde-dram-channels = <0x02>;

qcom,sde-ctl-size = <0x1e0>;

qcom,sde-csc-type = "csc-10bit";

interrupts = <0x00 0x53 0x00>;

clocks = <0x27 0x1c 0x27 0x1f 0x27 0x20 0x2a 0x01 0x2a 0x1a 0x2a 0x26 0x2a 0x1c 0x2a 0x22>;

qcom,sde-merge-3d-size = <0x100>;

qcom,sde-dsc-off = <0x81000 0x81400>;

qcom,sde-mixer-pair-mask = <0x02 0x01 0x04 0x03 0x00 0x00>;

qcom,sde-dither-version = <0x10000>;

qcom,sde-min-core-ib-kbps = <0x249f00>;

#size-cells = <0x00>;

qcom,sde-pp-merge-3d-id = <0x00 0x00 0x01 0x01>;

qcom,sde-off = <0x1000>;

qcom,sde-vbif-memtype-0 = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>;

qcom,sde-sspp-clk-ctrl = <0x2ac 0x00 0x2b4 0x00 0x2ac 0x08 0x2b4 0x08 0x2bc 0x08>;

qcom,sde-dspp-top-off = <0x1300>;

qcom,dss-cx-ipeak = <0x1a3 0x04>;

#power-domain-cells = <0x00>;

qcom,sde-dspp-top-size = <0x80>;

qcom,sde-qos-cpu-dma-latency = <0x12c>;

qcom,sde-mixer-blendstages = <0x0b>;

qcom,sde-safe-lut-linear = <0x00 0xfff8>;

qcom,sde-qos-lut-linear = <0x00 0x112222 0x22223357>;

qcom,sde-dsc-size = <0x140>;

qcom,sde-dither-size = <0x20>;

qcom,sde-intf-type = "dp\0dsi\0dsi\0dp";

qcom,sde-safe-lut-nrt = <0x00 0xffff>;

qcom,sde-mixer-linewidth = <0xa00>;

qcom,sde-dest-scaler-top-size = <0x1c>;

qcom,sde-wb-xin-id = <0x06>;

qcom,sde-dspp-ad-off = <0x28000 0x27000>;

qcom,sde-qos-lut-macrotile = <0x00 0x112233 0x44556677>;

qcom,sde-min-llcc-ib-kbps = <0xc3500>;

qcom,sde-max-dest-scaler-input-linewidth = <0x800>;

qcom,sde-has-src-split;

qcom,sde-sspp-csc-off = <0x1a00>;

qcom,sde-has-dest-scaler;

compatible = "qcom,sde-kms";

qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>;

qcom,sde-dest-scaler-off = <0x800 0x1000>;

qcom,sde-ubwc-version = <0x200>;

#interrupt-cells = <0x01>;

clock-rate = <0x00 0x00 0x00 0x00 0x14810600 0x124f800 0xbebc200 0xbebc200>;

qcom,sde-intf-size = <0x2b8>;

qcom,sde-intf-off = <0x6b000 0x6b800 0x6c000 0x6c800>;

qcom,sde-mixer-size = <0x320>;

qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none";

qcom,sde-has-idle-pc;

qcom,sde-wb-clk-ctrl = <0x3b8 0x18>;

qcom,sde-merge-3d-off = <0x84000 0x84100>;

qcom,sde-min-dram-ib-kbps = <0xc3500>;

reg = <0xae00000 0x84208 0xaeb0000 0x2008 0xaeac000 0x214>;

qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x00 0x00>;

qcom,sde-max-bw-low-kbps = <0x6c5660>;

qcom,sde-pipe-order-version = <0x01>;

qcom,sde-highest-bank-bit = <0x01>;

qcom,sde-vbif-id = <0x00>;

phandle = <0x1a6>;

qcom,sde-cdm-size = <0x224>;

qcom,sde-vbif-qos-rt-remap = <0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06>;

qcom,sde-qos-lut-cwb = <0x00 0x75300000 0x00>;

qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>;

qcom,sde-num-nrt-paths = <0x00>;

qcom,sde-reg-dma-off = <0x00>;

qcom,sde-cdm-off = <0x7a200>;

qcom,sde-reg-dma-version = <0x10001>;

qcom,sde-vbif-memtype-1 = <0x03 0x03 0x03 0x03 0x03 0x03>;

qcom,sde-wb-off = <0x66000>;

qcom,sde-has-cdp;

qcom,sde-sspp-xin-id = <0x00 0x04 0x01 0x05 0x09>;

qcom,sde-vbif-size = <0x1040>;

qcom,sde-sspp-linewidth = <0xb40>;

qcom,sde-pp-slave = <0x00 0x00 0x00 0x00>;

qcom,sde-wb-linewidth = <0x1000>;

qcom,sde-secure-sid-mask = <0x4400801>;

interrupt-controller;

qcom,sde-dspp-off = <0x55000 0x57000>;

qcom,sde-sspp-type = "vig\0vig\0dma\0dma\0dma";

#cooling-cells = <0x02>;

qcom,sde-len = <0x45c>;

qcom,sde-has-dim-layer;

qcom,sde-max-bw-high-kbps = <0x6c5660>;

qcom,mdss_dsi_sw43404_amoled_wqhd_cmd {

qcom,ulps-enabled;

qcom,mdss-dsi-bl-min-level = <0x01>;

qcom,mdss-dsi-panel-status-check-mode = "reg_read";

qcom,mdss-dsi-panel-status-read-length = <0x01>;

qcom,mdss-dsi-panel-name = "sw43404 amoled cmd mode dsi boe panel with DSC";

qcom,mdss-dsi-te-using-te-pin;

qcom,esd-check-enabled;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-panel-status-value = <0x9c>;

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-t-clk-post = <0x0a>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-bl-max-level = <0x3ff>;

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-panel-peak-brightness = <0x401640>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-physical-type = "oled";

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x21>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

qcom,mdss-dsi-te-pin-select = <0x01>;

qcom,mdss-dsi-panel-on-check-value = <0x9c>;

phandle = <0x523>;

qcom,mdss-dsi-bllp-power-mode;

qcom,panel-supply-entries = <0x521>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-lane-map = "lane_map_0123";

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,platform-te-gpio = <0x174 0x0a 0x00>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 5a 00];

qcom,partial-update-enabled = "single_roi";

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x02 0x02 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x0c>;

qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-jitter = <0x07 0x01>;

qcom,mdss-dsi-nolp-command = [05 01 00 00 00 00 02 38 00];

qcom,mdss-dsi-lp1-command = [05 01 00 00 00 00 02 39 00];

qcom,compression-mode = "dsc";

qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 5a 01];

qcom,mdss-dsi-panel-height = <0xb40>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = <0x39010000 0x3b0 0xa5003901 0x00 0x35c4200 0x7010000 0x201 0xa0100 0x80 0x11000089 0x30800b40 0x5a005a0 0x2d002d0 0x2000268 0x209adb 0xa000c 0x12000e 0x180010f0 0x30c2000 0x60b0b33 0xe1c2a38 0x46546269 0x7077797b 0x7d7e0102 0x1000940 0x9be19fc 0x19fa19f8 0x1a381a78 0x1ab62af6 0x2b342b74 0x3b746bf4 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x39010000 0x3b0 0xa5003901 0x00 0x9f80008 0x10082d00 0x2d1501 0x00 0x2550805 0x100001e 0x21100 0x39010000 0x3b0 0xa5001501 0x00 0x2e01839 0x1000000 0xcc000 0x536f5150 0x51344f5a 0x33190501 0x7800 0x2350005 0x100003c 0x22900>;

qcom,mdss-dsi-h-front-porch = <0x3c>;

qcom,mdss-dsc-slice-width = <0x2d0>;

qcom,mdss-dsi-h-back-porch = <0x1e>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-lp1-command-state = "dsi_lp_mode";

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0xb4>;

qcom,mdss-dsi-qsync-off-commands-state = "dsi_lp_mode";

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x5a0>;

qcom,mdss-dsi-v-pulse-width = <0x01>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x130504 0x1f1e0505 0x3020400>;

qcom,mdss-dsi-v-back-porch = <0x08>;

qcom,default-topology-index = <0x00>;

qcom,panel-roi-alignment = <0x2d0 0xb4 0xb4 0xb4 0x5a0 0xb4>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsi-qsync-on-commands-state = "dsi_lp_mode";

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-mdp-transfer-time-us = <0x32c8>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,mdss_dsi_rm69298_truly_amoled_video {

qcom,mdss-dsi-panel-name = "rm69298 amoled fhd+ video mode dsi truly panel";

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-t-clk-post = <0x0d>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";

qcom,mdss-dsi-pan-enable-dynamic-fps;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,mdss-dsi-lane-0-state;

qcom,dsi-supported-dfps-list = <0x3c 0x39 0x35>;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x30>;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x52d>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-lane-map = "lane_map_0123";

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,display-topology = <0x01 0x00 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x0a>;

qcom,mdss-dsi-panel-height = <0x870>;

qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 fe 40 15 01 00 00 00 00 02 0a 15 15 01 00 00 00 00 02 0b cc 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 80 15 01 00 00 00 00 02 0f 87 15 01 00 00 00 00 02 05 08 15 01 00 00 00 00 02 06 08 15 01 00 00 00 00 02 08 08 15 01 00 00 00 00 02 09 08 15 01 00 00 00 00 02 16 15 15 01 00 00 00 00 02 20 8d 15 01 00 00 00 00 02 21 8d 15 01 00 00 00 00 02 24 55 15 01 00 00 00 00 02 26 55 15 01 00 00 00 00 02 28 55 15 01 00 00 00 00 02 2a 55 15 01 00 00 00 00 02 2d 28 15 01 00 00 00 00 02 2f 28 15 01 00 00 00 00 02 30 1e 15 01 00 00 00 00 02 31 1e 15 01 00 00 00 00 02 37 80 15 01 00 00 00 00 02 38 40 15 01 00 00 00 00 02 39 90 15 01 00 00 00 00 02 46 43 15 01 00 00 00 00 02 47 43 15 01 00 00 00 00 02 64 02 15 01 00 00 00 00 02 6f 02 15 01 00 00 00 00 02 74 2f 15 01 00 00 00 00 02 80 16 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 fe a0 15 01 00 00 00 00 02 2b 22 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 2f 35 15 01 00 00 00 00 02 fe 60 15 01 00 00 00 00 02 00 ac 15 01 00 00 00 00 02 01 0f 15 01 00 00 00 00 02 02 ff 15 01 00 00 00 00 02 03 05 15 01 00 00 00 00 02 04 00 15 01 00 00 00 00 02 05 06 15 01 00 00 00 00 02 06 00 15 01 00 00 00 00 02 07 00 15 01 00 00 00 00 02 09 c0 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 02 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0e 00 15 01 00 00 00 00 02 0e 04 15 01 00 00 00 00 02 0f 0e 15 01 00 00 00 00 02 10 a2 15 01 00 00 00 00 02 12 c0 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 14 02 15 01 00 00 00 00 02 15 00 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 17 05 15 01 00 00 00 00 02 18 0e 15 01 00 00 00 00 02 19 a2 15 01 00 00 00 00 02 1b c0 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 04 15 01 00 00 00 00 02 1e 01 15 01 00 00 00 00 02 1f 00 15 01 00 00 00 00 02 20 04 15 01 00 00 00 00 02 21 24 15 01 00 00 00 00 02 22 99 15 01 00 00 00 00 02 24 c0 15 01 00 00 00 00 02 25 00 15 01 00 00 00 00 02 26 04 15 01 00 00 00 00 02 27 01 15 01 00 00 00 00 02 28 00 15 01 00 00 00 00 02 29 06 15 01 00 00 00 00 02 2a 24 15 01 00 00 00 00 02 2b 99 15 01 00 00 00 00 02 83 ca 15 01 00 00 00 00 02 84 0f 15 01 00 00 00 00 02 85 ff 15 01 00 00 00 00 02 86 0a 15 01 00 00 00 00 02 87 00 15 01 00 00 00 00 02 88 08 15 01 00 00 00 00 02 89 00 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 8b 80 15 01 00 00 00 00 02 c7 1f 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 c9 01 15 01 00 00 00 00 02 ca 1f 15 01 00 00 00 00 02 cb 02 15 01 00 00 00 00 02 cc 1f 15 01 00 00 00 00 02 cd 1f 15 01 00 00 00 00 02 ce 1f 15 01 00 00 00 00 02 cf 1f 15 01 00 00 00 00 02 d0 1f 15 01 00 00 00 00 02 d1 1f 15 01 00 00 00 00 02 d2 1f 15 01 00 00 00 00 02 d3 1f 15 01 00 00 00 00 02 d4 1f 15 01 00 00 00 00 02 d5 1f 15 01 00 00 00 00 02 d6 1f 15 01 00 00 00 00 02 d7 1f 15 01 00 00 00 00 02 d8 1f 15 01 00 00 00 00 02 d9 1f 15 01 00 00 00 00 02 da 1f 15 01 00 00 00 00 02 db 1f 15 01 00 00 00 00 02 dc 00 15 01 00 00 00 00 02 dd 0e 15 01 00 00 00 00 02 de 1f 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 04 15 01 00 00 00 00 02 e1 1f 15 01 00 00 00 00 02 e2 01 15 01 00 00 00 00 02 e3 02 15 01 00 00 00 00 02 e4 1f 15 01 00 00 00 00 02 e5 1f 15 01 00 00 00 00 02 e6 1f 15 01 00 00 00 00 02 e7 1f 15 01 00 00 00 00 02 e8 1f 15 01 00 00 00 00 02 e9 1f 15 01 00 00 00 00 02 ea 1f 15 01 00 00 00 00 02 eb 1f 15 01 00 00 00 00 02 ec 1f 15 01 00 00 00 00 02 ed 1f 15 01 00 00 00 00 02 ee 1f 15 01 00 00 00 00 02 ef 03 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 c6 15 15 01 00 00 00 00 02 c9 9e 15 01 00 00 00 00 02 cb 3f 15 01 00 00 00 00 02 d1 0f 15 01 00 00 00 00 02 d3 15 15 01 00 00 00 00 02 d4 15 15 01 00 00 00 00 02 d5 00 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 a9 40 15 01 00 00 00 00 02 cb 05 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 5a ff 15 01 00 00 00 00 02 5c ff 15 01 00 00 00 00 02 5d 0a 15 01 00 00 00 00 02 7d 31 15 01 00 00 00 00 02 7e 4a 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 49 05 15 01 00 00 00 00 02 4a 2e 15 01 00 00 00 00 02 4b 58 15 01 00 00 00 00 02 4c 77 15 01 00 00 00 00 02 4d a1 15 01 00 00 00 00 02 4e de 15 01 00 00 00 00 02 4f 2c 15 01 00 00 00 00 02 50 97 15 01 00 00 00 00 02 51 2a 15 01 00 00 00 00 02 ad ec 15 01 00 00 00 00 02 ae 80 15 01 00 00 00 00 02 af 00 15 01 00 00 00 00 02 b0 50 15 01 00 00 00 00 02 b1 3a 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 56 91 15 01 00 00 00 00 02 58 04 15 01 00 00 00 00 02 59 24 15 01 00 00 00 00 02 5a 05 15 01 00 00 00 00 02 5b c6 15 01 00 00 00 00 02 5c 05 15 01 00 00 00 00 02 5d 66 15 01 00 00 00 00 02 5e 06 15 01 00 00 00 00 02 5f 17 15 01 00 00 00 00 02 60 07 15 01 00 00 00 00 02 61 cf 15 01 00 00 00 00 02 62 07 15 01 00 00 00 00 02 63 98 15 01 00 00 00 00 02 64 08 15 01 00 00 00 00 02 65 65 15 01 00 00 00 00 02 66 09 15 01 00 00 00 00 02 67 37 15 01 00 00 00 00 02 68 0a 15 01 00 00 00 00 02 6b 02 15 01 00 00 00 00 02 6c 0c 15 01 00 00 00 00 02 71 02 15 01 00 00 00 00 02 72 0f 15 01 00 00 00 00 02 73 93 15 01 00 00 00 00 02 74 0f 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 98 cf 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 b4 31 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 aa 03 15 01 00 00 00 00 02 09 13 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 01 41 15 01 00 00 00 00 02 02 00 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 04 ff 15 01 00 00 00 00 02 05 00 15 01 00 00 00 00 02 06 c0 15 01 00 00 00 00 02 07 40 15 01 00 00 00 00 02 08 20 15 01 00 00 00 00 02 19 e0 15 01 00 00 00 00 02 1a 40 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 80 15 01 00 00 00 00 02 60 40 15 01 00 00 00 00 02 61 40 15 01 00 00 00 00 02 62 40 15 01 00 00 00 00 02 63 40 15 01 00 00 00 00 02 64 40 15 01 00 00 00 00 02 65 40 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 02 15 01 00 00 00 00 02 75 10 15 01 00 00 00 00 02 76 14 15 01 00 00 00 00 02 77 1c 15 01 00 00 00 00 02 78 20 15 01 00 00 00 00 02 79 0a 15 01 00 00 00 00 02 7a 00 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c 00 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e 00 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 81 00 15 01 00 00 00 00 02 82 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 84 00 15 01 00 00 00 00 02 85 00 15 01 00 00 00 00 02 86 20 15 01 00 00 00 00 02 87 0a 15 01 00 00 00 00 02 88 02 15 01 00 00 00 00 02 89 2b 15 01 00 00 00 00 02 8a 14 15 01 00 00 00 00 02 8b 01 15 01 00 00 00 00 02 8c 00 15 01 00 00 00 00 02 8d 00 15 01 00 00 00 00 02 8e 00 15 01 00 00 00 00 02 8f 00 15 01 00 00 00 00 02 90 00 15 01 00 00 00 00 02 91 00 15 01 00 00 00 00 02 92 00 15 01 00 00 00 00 02 93 00 15 01 00 00 00 00 02 94 00 15 01 00 00 00 00 02 95 00 15 01 00 00 00 00 02 96 00 15 01 00 00 00 00 02 b2 40 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 b8 d0 15 01 00 00 00 00 02 b9 06 15 01 00 00 00 00 02 ba 00 15 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 05 51 00 00 ff ff 15 01 00 00 00 00 02 c2 09 05 01 00 00 96 00 01 11 05 01 00 00 32 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x1e>;

qcom,mdss-dsi-h-back-porch = <0x28>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x04>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x1f0808 0x24220808 0x5020400>;

qcom,mdss-dsi-v-back-porch = <0x10>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00];

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,mdss_dsi_sharp_wqhd_video {

qcom,adjust-timer-wakeup-ms = <0x01>;

qcom,mdss-dsi-panel-status-check-mode = "reg_read";

qcom,mdss-pan-physical-width-dimension = <0x44>;

qcom,mdss-dsi-panel-status-read-length = <0x01>;

qcom,mdss-dsi-panel-name = "Dual Sharp wqhd video mode dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x79>;

qcom,esd-check-enabled;

qcom,mdss-dsi-panel-status-value = <0x9c>;

qcom,mdss-dsi-t-clk-post = <0x0c>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";

qcom,mdss-dsi-pan-enable-dynamic-fps;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,dsi-dyn-clk-enable;

qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x14>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,dsi-dyn-clk-list = <0x1fdf1000 0x1fbd1100 0x1f9b1200 0x1f571400 0x1f791300>;

qcom,mdss-dsi-lane-0-state;

qcom,dsi-supported-dfps-list = <0x3c 0x39 0x37>;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x21>;

qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

qcom,mdss-dsi-panel-on-check-value = <0x9c>;

phandle = <0x52b>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,display-topology = <0x02 0x00 0x02>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x04>;

qcom,mdss-dsi-panel-height = <0xa00>;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 10 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 15 01 00 00 00 00 02 90 01 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 58 01 15 01 00 00 00 00 02 c9 00 15 01 00 00 00 00 02 c0 15 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x1e>;

qcom,mdss-dsi-h-back-porch = <0x64>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x2d0>;

qcom,mdss-dsi-v-pulse-width = <0x01>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x2e080a 0x1218080b 0x9030400>;

qcom,mdss-dsi-v-back-porch = <0x08>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,smmu_sde_sec_cb {

iommus = <0x30 0x801 0x440>;

compatible = "qcom,smmu_sde_sec";

phandle = <0x36c>;

};

qcom,mdss_dsi_nt35695b_truly_fhd_cmd {

qcom,ulps-enabled;

qcom,mdss-dsi-panel-status-check-mode = "reg_read";

qcom,mdss-dsi-panel-status-read-length = <0x01>;

qcom,mdss-dsi-panel-name = "nt35695b truly fhd command mode dsi panel";

qcom,mdss-dsi-te-using-te-pin;

qcom,esd-check-enabled;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-panel-status-value = <0x9c>;

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-t-clk-post = <0x07>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-post-init-delay = <0x01>;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x1c>;

qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

qcom,mdss-dsi-te-pin-select = <0x01>;

qcom,mdss-dsi-panel-on-check-value = <0x9c>;

phandle = <0x530>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x00 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x0c>;

qcom,mdss-dsi-panel-height = <0x780>;

qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00];

qcom,mdss-dsi-h-front-porch = <0x78>;

qcom,mdss-dsi-h-back-porch = <0x3c>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x130504 0x1f1e0505 0x3020400>;

qcom,mdss-dsi-v-back-porch = <0x02>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsi-v-front-porch = <0x0c>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

};

};

qcom,mdss_dsi_sim_dsc_375_cmd {

qcom,ulps-enabled;

qcom,adjust-timer-wakeup-ms = <0x01>;

qcom,mdss-dsi-panel-name = "Simulator cmd mode DSC 3.75:1 dsi panel";

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,panel-ack-disabled;

qcom,mdss-dsi-t-clk-post = <0x0d>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-bl-max-level = <0xfff>;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-te-using-wd;

qcom,mdss-dsi-t-clk-pre = <0x2d>;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x529>;

qcom,mdss-dsi-bllp-power-mode;

qcom,panel-supply-entries = <0x520>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@1 {

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x00>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0x780>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>;

qcom,mdss-dsi-h-front-porch = <0x00>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x00>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x10>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x00>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x150505 0x201f0505 0x3020400>;

qcom,mdss-dsi-v-back-porch = <0x00>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x02>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>;

qcom,mdss-dsc-bit-per-component = <0x0a>;

qcom,mdss-dsi-v-front-porch = <0x00>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

timing@0 {

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x01 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x10>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0xa00>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2723115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00315 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>;

qcom,mdss-dsi-h-front-porch = <0x64>;

qcom,mdss-dsc-slice-width = <0x2d0>;

qcom,mdss-dsi-h-back-porch = <0x20>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x10>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x5a0>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_hs_mode";

qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4020400>;

qcom,mdss-dsi-v-back-porch = <0x08>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x02>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsc-bit-per-component = <0x0a>;

qcom,mdss-dsi-v-front-porch = <0x0a>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,mdss_dsi_sim_cmd {

qcom,ulps-enabled;

qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel";

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,panel-ack-disabled;

qcom,mdss-dsi-t-clk-post = <0x0c>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-bl-max-level = <0xfff>;

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-panel-peak-brightness = <0x401640>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-te-using-wd;

qcom,mdss-dsi-t-clk-pre = <0x29>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x527>;

qcom,mdss-dsi-bllp-power-mode;

qcom,panel-supply-entries = <0x520>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@1 {

qcom,partial-update-enabled = "single_roi";

qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>;

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x28>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0x780>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>;

qcom,mdss-dsi-h-front-porch = <0x78>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x1cc>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x28>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x28>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4020400>;

qcom,mdss-dsi-v-back-porch = <0x64>;

qcom,default-topology-index = <0x01>;

qcom,panel-roi-alignment = <0x21c 0x28 0x21c 0x28 0x21c 0x28>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x2e4>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

timing@2 {

qcom,partial-update-enabled = "single_roi";

qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>;

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x28>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0x500>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>;

qcom,mdss-dsi-h-front-porch = <0x64>;

qcom,mdss-dsc-slice-width = <0x168>;

qcom,mdss-dsi-h-back-porch = <0x348>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x28>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x2d0>;

qcom,mdss-dsi-v-pulse-width = <0x28>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4020400>;

qcom,mdss-dsi-v-back-porch = <0x64>;

qcom,default-topology-index = <0x01>;

qcom,panel-roi-alignment = <0x168 0x28 0x168 0x28 0x168 0x28>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x564>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

timing@0 {

qcom,partial-update-enabled = "single_roi";

qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>;

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x28>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0xa00>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>;

qcom,mdss-dsi-h-front-porch = <0x78>;

qcom,mdss-dsc-slice-width = <0x2d0>;

qcom,mdss-dsi-h-back-porch = <0x64>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x28>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x5a0>;

qcom,mdss-dsi-v-pulse-width = <0x28>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4020400>;

qcom,mdss-dsi-v-back-porch = <0x64>;

qcom,default-topology-index = <0x01>;

qcom,panel-roi-alignment = <0x2d0 0x28 0x2d0 0x28 0x2d0 0x28>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x64>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,mdss_dsi_sw43404_amoled_wqhd_video {

qcom,adjust-timer-wakeup-ms = <0x01>;

qcom,mdss-dsi-bl-min-level = <0x01>;

qcom,mdss-dsi-panel-name = "sw43404 amoled video mode dsi boe panel with DSC";

qcom,mdss-dsi-t-clk-post = <0x0a>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-bl-max-level = <0x3ff>;

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-panel-peak-brightness = <0x401640>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-pan-enable-dynamic-fps;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-physical-type = "oled";

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,mdss-dsi-lane-0-state;

qcom,dsi-supported-dfps-list = <0x3c 0x39 0x37>;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x21>;

qcom,mdss-dsi-panel-hdr-enabled;

phandle = <0x522>;

qcom,mdss-dsi-bllp-power-mode;

qcom,panel-supply-entries = <0x521>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,platform-te-gpio = <0x174 0x0a 0x00>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-brightness-max-level = <0x7ff>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,display-topology = <0x02 0x02 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x0c>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0xb40>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 03 b0 a5 00 07 01 00 00 00 00 02 01 00 39 01 00 00 00 00 06 b2 00 5d 04 80 49 15 01 00 00 00 00 02 3d 10 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 55 08 39 01 00 00 00 00 09 f8 00 08 10 08 2d 00 00 2d 39 01 00 00 3c 00 03 51 00 00 05 01 00 00 50 00 02 11 00 39 01 00 00 00 00 03 b0 34 04 39 01 00 00 00 00 05 c1 00 00 00 46 39 01 00 00 00 00 03 b0 a5 00 0a 01 00 00 00 00 80 11 00 00 89 30 80 0b 40 05 a0 02 d0 02 d0 02 d0 02 00 02 68 00 20 4e a8 00 0a 00 0c 00 23 00 1c 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05 01 00 00 78 00 02 29 00];

qcom,mdss-dsi-h-front-porch = <0x0a>;

qcom,mdss-dsc-slice-width = <0x2d0>;

qcom,mdss-dsi-h-back-porch = <0x0a>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x2d0>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x5a0>;

qcom,mdss-dsi-v-pulse-width = <0x01>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x130504 0x1f1e0505 0x3020400>;

qcom,mdss-dsi-v-back-porch = <0x0a>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x02>;

qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x0a>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,mdss_dsi_sharp_qsync_fhd_cmd {

qcom,adjust-timer-wakeup-ms = <0x01>;

qcom,mdss-pan-physical-width-dimension = <0x4a>;

qcom,mdss-dsi-panel-name = "Sharp fhd cmd mode qsync dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x86>;

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-t-clk-post = <0x09>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-panel-blackness-level = <0x1361>;

qcom,mdss-dsi-panel-peak-brightness = <0x626b50>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x12>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x539>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@1 {

qcom,display-topology = <0x02 0x02 0x02>;

qcom,mdss-dsi-panel-framerate = <0x5a>;

qcom,mdss-dsi-h-pulse-width = <0x08>;

qcom,mdss-dsi-panel-jitter = <0x03 0x01>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0x780>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x14>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x0c>;

qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 02];

qcom,mdss-dsc-slice-height = <0x08>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x21c>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0xc0202 0x1d1c0303 0x1020400>;

qcom,mdss-dsi-v-back-porch = <0x0e>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x10>;

qcom,mdss-mdp-transfer-time-us = <0x2134>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

timing@2 {

qcom,display-topology = <0x02 0x02 0x02>;

qcom,mdss-dsi-panel-framerate = <0x78>;

qcom,mdss-dsi-h-pulse-width = <0x08>;

qcom,mdss-dsi-panel-jitter = <0x03 0x01>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0x780>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x14>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x0c>;

qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 03];

qcom,mdss-dsc-slice-height = <0x08>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x21c>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0xf0303 0x1e1d0404 0x2020400>;

qcom,mdss-dsi-v-back-porch = <0x0e>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x10>;

qcom,mdss-mdp-transfer-time-us = <0x16a8>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

timing@0 {

qcom,display-topology = <0x02 0x02 0x02>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x08>;

qcom,mdss-dsi-panel-jitter = <0x03 0x01>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0x780>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x14>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x0c>;

qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01];

qcom,mdss-dsc-slice-height = <0x08>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x21c>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0xa0102 0x1b1b0202 0x20400>;

qcom,mdss-dsi-v-back-porch = <0x0e>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x10>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

};

};

qcom,mdss_dsi_sharp_qsync_wqhd_video {

qcom,adjust-timer-wakeup-ms = <0x01>;

qcom,dsi-phy-num = <0x00 0x01>;

qcom,mdss-pan-physical-width-dimension = <0x4a>;

qcom,mdss-dsi-panel-name = "Sharp 2k video mode qsync dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x86>;

qcom,dsi-select-clocks = "src_byte_clk0\0src_pixel_clk0";

qcom,mdss-dsi-t-clk-post = <0x0a>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,dsi-ctrl-num = <0x00 0x01>;

qcom,mdss-dsi-panel-blackness-level = <0x1361>;

qcom,mdss-dsi-panel-peak-brightness = <0x626b50>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x1e>;

qcom,mdss-dsi-panel-hdr-enabled;

phandle = <0x537>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,display-topology = <0x02 0x02 0x02>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x08>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0xa00>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = <0x39010000 0x2ff 0xd0390100 0x02 0x75403901 0x1000 0x2f14039 0x1000000 0x2ff10 0x39010000 0x1000062c 0x1020408 0x10390100 0x02 0xffd03901 0x00 0x2750039 0x1000010 0x2f100 0x39010000 0x2ff 0x10390100 0x02 0xfb013901 0x00 0x2ba0339 0x1000000 0x2bc08 0x39010000 0x2c0 0x83390100 0x11 0xc1892800 0x8020002 0x6800d500 0xa0db709 0x89390100 0x03 0xc210f039 0x1000000 0x2d500 0x39010000 0x2d6 0x390100 0x02 0xde003901 0x00 0x2e10039 0x1000000 0x2e501 0x39010000 0x2bb 0x3390100 0x02 0xf6703901 0x00 0x2f78039 0x1000000 0x5be00 0x10001039 0x1000000 0x23500 0x39010000 0x244 0x390100 0x02 0xff203901 0x00 0x2fb0139 0x1000000 0x28702 0x39010000 0x25d 0x390100 0x02 0x5e143901 0x00 0x25feb39 0x1000000 0x2ff26 0x39010000 0x2fb 0x1390100 0x02 0x60003901 0x00 0x2620139 0x1000000 0x24000 0x39010000 0x2ff 0x28390100 0x02 0xfb013901 0x00 0x2910239 0x1000000 0x2ffe0 0x39010000 0x2fb 0x1390100 0x02 0x48813901 0x00 0x28e0939 0x1000000 0x2fff0 0x39010000 0x2fb 0x1390100 0x02 0x33203901 0x00 0x2343539 0x1000000 0x2ff10 0x5010000 0x78000111 0x5010000 0x78000129>;

qcom,mdss-dsi-h-front-porch = <0x14>;

qcom,mdss-dsc-slice-width = <0x2d0>;

qcom,mdss-dsi-h-back-porch = <0x0c>;

qcom,mdss-dsc-slice-height = <0x08>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x2d0>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x120404 0x1e1e0404 0x2020400>;

qcom,mdss-dsi-v-back-porch = <0x0e>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x7d8>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

};

};

qcom,mdss_dsi_sharp_wqhd_cmd {

qcom,ulps-enabled;

qcom,adjust-timer-wakeup-ms = <0x01>;

qcom,mdss-dsi-panel-status-check-mode = "reg_read";

qcom,mdss-pan-physical-width-dimension = <0x44>;

qcom,mdss-dsi-panel-status-read-length = <0x01>;

qcom,mdss-dsi-panel-name = "Dual Sharp WQHD cmd mode dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x79>;

qcom,mdss-dsi-te-using-te-pin;

qcom,esd-check-enabled;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-panel-status-value = <0x9c>;

qcom,mdss-dsi-t-clk-post = <0x0c>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x14>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x21>;

qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

qcom,mdss-dsi-te-pin-select = <0x01>;

qcom,mdss-dsi-panel-on-check-value = <0x9c>;

phandle = <0x52c>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,dcs-cmd-by-left;

qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,partial-update-enabled = "single_roi";

qcom,display-topology = <0x02 0x00 0x02>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x04>;

qcom,mdss-dsi-panel-height = <0xa00>;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 15 01 00 00 00 00 02 90 01 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 58 01 15 01 00 00 00 00 02 c9 00 15 01 00 00 00 00 02 c0 15 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x1e>;

qcom,mdss-dsi-h-back-porch = <0x64>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x2d0>;

qcom,mdss-dsi-v-pulse-width = <0x01>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x2e080a 0x1218080b 0x9030400>;

qcom,mdss-dsi-v-back-porch = <0x08>;

qcom,default-topology-index = <0x00>;

qcom,panel-roi-alignment = <0x2d0 0xa0 0xa0 0xa0 0x5a0 0xa0>;

qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,mdss_dsi_dual_sim_dsc_375_cmd {

qcom,ulps-enabled;

qcom,mdss-dsi-panel-name = "Sim dual cmd mode DSC 3.75:1 dsi panel";

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,panel-ack-disabled;

qcom,mdss-dsi-t-clk-post = <0x0d>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-bl-max-level = <0xfff>;

qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,cmd-sync-wait-broadcast;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-te-using-wd;

qcom,mdss-dsi-t-clk-pre = <0x2d>;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x52a>;

qcom,mdss-dsi-bllp-power-mode;

qcom,panel-supply-entries = <0x520>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@1 {

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x02 0x02 0x02>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x10>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0xa00>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00];

qcom,mdss-dsi-h-front-porch = <0x64>;

qcom,mdss-dsc-slice-width = <0x2d0>;

qcom,mdss-dsi-h-back-porch = <0x20>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x10>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x2d0>;

qcom,mdss-dsi-v-pulse-width = <0x01>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4020400>;

qcom,mdss-dsi-v-back-porch = <0x07>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsc-bit-per-component = <0x0a>;

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

timing@0 {

qcom,display-topology = <0x02 0x02 0x02>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x04>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0xf00>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x1e>;

qcom,mdss-dsc-slice-width = <0x438>;

qcom,mdss-dsi-h-back-porch = <0x64>;

qcom,mdss-dsc-slice-height = <0x20>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x01>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5020400>;

qcom,mdss-dsi-v-back-porch = <0x07>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsc-bit-per-component = <0x0a>;

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,mdss_dsi_sw43404_fhd_plus_cmd {

qcom,ulps-enabled;

qcom,mdss-dsi-bl-min-level = <0x01>;

qcom,mdss-dsi-panel-status-check-mode = "reg_read";

qcom,mdss-pan-physical-width-dimension = <0x44>;

qcom,mdss-dsi-panel-status-read-length = <0x01>;

qcom,mdss-dsi-panel-name = "sw43404 amoled boe fhd+ panel with DSC";

qcom,mdss-pan-physical-height-dimension = <0x8a>;

qcom,mdss-dsi-te-using-te-pin;

qcom,esd-check-enabled;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-panel-status-value = <0x9c>;

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-t-clk-post = <0x09>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-bl-max-level = <0x3ff>;

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-panel-peak-brightness = <0x401640>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-physical-type = "oled";

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x1b>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

qcom,mdss-dsi-te-pin-select = <0x01>;

qcom,mdss-dsi-panel-on-check-value = <0x9c>;

phandle = <0x524>;

qcom,mdss-dsi-bllp-power-mode;

qcom,panel-supply-entries = <0x521>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-lane-map = "lane_map_0123";

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,platform-te-gpio = <0x174 0x0a 0x00>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,partial-update-enabled = "single_roi";

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x01 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x10>;

qcom,mdss-dsi-panel-jitter = <0x03 0x01>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0x870>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 03 b0 a5 00 07 01 00 00 00 00 02 01 00 0a 01 00 00 00 00 80 11 00 00 89 30 80 08 70 04 38 02 1c 02 1c 02 1c 02 00 02 0e 00 20 34 29 00 07 00 0c 00 2e 00 31 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 03 b0 a5 00 15 01 00 00 00 00 02 5e 10 39 01 00 00 00 00 06 b9 bf 11 40 00 30 39 01 00 00 00 00 09 f8 00 08 10 08 2d 00 00 2d 15 01 00 00 00 00 02 55 08 05 01 00 00 1e 00 02 11 00 15 01 00 00 78 00 02 3d 01 39 01 00 00 00 00 03 b0 a5 00 05 01 00 00 78 00 02 35 00 05 01 00 00 3c 00 02 29 00];

qcom,mdss-dsi-h-front-porch = <0xa0>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x48>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x10e>;

qcom,mdss-dsi-panel-clockrate = <0x15228c00>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x01>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0xf0303 0x1e1d0404 0x2030400>;

qcom,mdss-dsi-v-back-porch = <0x08>;

qcom,default-topology-index = <0x00>;

qcom,panel-roi-alignment = <0x21c 0x10e 0x10e 0x10e 0x438 0x10e>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,mdss_dsi_sim_video {

qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel";

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-panel-mode-switch;

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,panel-ack-disabled;

qcom,mdss-dsi-t-clk-post = <0x0d>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-panel-peak-brightness = <0x401640>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-te-using-wd;

qcom,mdss-dsi-t-clk-pre = <0x2d>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x525>;

qcom,mdss-dsi-bllp-power-mode;

qcom,panel-supply-entries = <0x520>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@1 {

qcom,mdss-dsi-panel-timings = <0x00 0x00 0x00>;

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,video-to-cmd-mode-post-switch-commands-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x08>;

qcom,mdss-dsi-panel-height = <0x1e0>;

qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00];

qcom,mdss-dsi-h-front-porch = <0x08>;

qcom,mdss-dsi-h-back-porch = <0x08>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x280>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-v-back-porch = <0x06>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsi-cmd-mode;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00];

qcom,video-to-cmd-mode-post-switch-commands = [32 01 00 00 00 00 02 00 00];

qcom,mdss-dsi-v-front-porch = <0x06>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

timing@0 {

qcom,mdss-dsi-panel-timings = <0x00 0x00 0x00>;

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x00 0x01 0x02 0x00 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,cmd-to-video-mode-post-switch-commands-state = "dsi_lp_mode";

qcom,mdss-dsi-h-pulse-width = <0x08>;

qcom,mdss-dsi-video-mode;

qcom,mdss-dsi-panel-height = <0x1e0>;

qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00];

qcom,mdss-dsi-h-front-porch = <0x08>;

qcom,mdss-dsi-h-back-porch = <0x08>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x280>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5020400>;

qcom,mdss-dsi-v-back-porch = <0x06>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,cmd-to-video-mode-post-switch-commands = [32 01 00 00 00 00 02 00 00];

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00];

qcom,mdss-dsi-v-front-porch = <0x06>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

};

};

qcom,sde-reg-bus {

qcom,msm-bus,name = "mdss_reg";

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x04>;

qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00 0x01 0x24e 0x00 0x249f0 0x01 0x24e 0x00 0x493e0>;

};

qcom,mdss_dsi_dual_sim_cmd {

qcom,ulps-enabled;

qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel";

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,panel-ack-disabled;

qcom,mdss-dsi-t-clk-post = <0x0d>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-bl-max-level = <0xfff>;

qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>;

qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,cmd-sync-wait-broadcast;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-te-using-wd;

qcom,mdss-dsi-t-clk-pre = <0x2d>;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x528>;

qcom,mdss-dsi-bllp-power-mode;

qcom,panel-supply-entries = <0x520>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@1 {

qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x10>;

qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];

qcom,mdss-dsi-panel-height = <0x5a0>;

qcom,mdss-dsi-on-command = <0x5010000 0x129>;

qcom,mdss-dsi-h-front-porch = <0x78>;

qcom,mdss-dsi-h-back-porch = <0x2c>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode";

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x500>;

qcom,mdss-dsi-v-pulse-width = <0x04>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5020400>;

qcom,mdss-dsi-v-back-porch = <0x04>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00];

qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode";

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

timing@2 {

qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];

qcom,display-topology = <0x02 0x00 0x02>;

qcom,mdss-dsi-panel-framerate = <0x28>;

qcom,mdss-dsi-h-pulse-width = <0x04>;

qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];

qcom,mdss-dsi-panel-height = <0xf00>;

qcom,mdss-dsi-on-command = <0x5010000 0x129>;

qcom,mdss-dsi-h-front-porch = <0x1e>;

qcom,mdss-dsi-h-back-porch = <0x64>;

qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode";

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x01>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4020400>;

qcom,mdss-dsi-v-back-porch = <0x07>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00];

qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode";

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

timing@0 {

qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x02 0x00 0x02>;

qcom,mdss-dsi-panel-framerate = <0x78>;

qcom,mdss-dsi-h-pulse-width = <0x04>;

qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];

qcom,mdss-dsi-panel-height = <0x780>;

qcom,mdss-dsi-on-command = <0x5010000 0x129>;

qcom,mdss-dsi-h-front-porch = <0x1c>;

qcom,mdss-dsi-h-back-porch = <0x04>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode";

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x21c>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x240909 0x26240909 0x6020400>;

qcom,mdss-dsi-v-back-porch = <0x0c>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00];

qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode";

qcom,mdss-dsi-v-front-porch = <0x0c>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,mdss_dsi_sharp_qsync_wqhd_cmd {

qcom,adjust-timer-wakeup-ms = <0x01>;

qcom,mdss-pan-physical-width-dimension = <0x4a>;

qcom,mdss-dsi-panel-name = "Sharp 2k cmd mode qsync dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x86>;

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-t-clk-post = <0x0b>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-panel-blackness-level = <0x1361>;

qcom,mdss-dsi-panel-peak-brightness = <0x626b50>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x24>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x536>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@3 {

qcom,display-topology = <0x02 0x02 0x02>;

qcom,mdss-dsi-panel-framerate = <0x78>;

qcom,mdss-dsi-h-pulse-width = <0x08>;

qcom,mdss-dsi-panel-jitter = <0x03 0x01>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0xa00>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x14>;

qcom,mdss-dsc-slice-width = <0x2d0>;

qcom,mdss-dsi-h-back-porch = <0x0c>;

qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 03];

qcom,mdss-dsc-slice-height = <0x08>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x2d0>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x160605 0x201f0606 0x3020400>;

qcom,mdss-dsi-v-back-porch = <0x0e>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x10>;

qcom,mdss-mdp-transfer-time-us = <0x16a8>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

timing@1 {

qcom,display-topology = <0x02 0x02 0x02>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x08>;

qcom,mdss-dsi-panel-jitter = <0x03 0x01>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0x780>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x14>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x0c>;

qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01];

qcom,mdss-dsc-slice-height = <0x08>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x21c>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0xa0102 0x1b1b0202 0x20400>;

qcom,mdss-dsi-v-back-porch = <0x0e>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x10>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

timing@2 {

qcom,display-topology = <0x02 0x02 0x02>;

qcom,mdss-dsi-panel-framerate = <0x5a>;

qcom,mdss-dsi-h-pulse-width = <0x08>;

qcom,mdss-dsi-panel-jitter = <0x03 0x01>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0xa00>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x14>;

qcom,mdss-dsc-slice-width = <0x2d0>;

qcom,mdss-dsi-h-back-porch = <0x0c>;

qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 02];

qcom,mdss-dsc-slice-height = <0x08>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x2d0>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x110404 0x1e1e0404 0x2020400>;

qcom,mdss-dsi-v-back-porch = <0x0e>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x10>;

qcom,mdss-mdp-transfer-time-us = <0x2134>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

timing@0 {

qcom,display-topology = <0x02 0x02 0x02>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x08>;

qcom,mdss-dsi-panel-jitter = <0x03 0x01>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0xa00>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x14>;

qcom,mdss-dsc-slice-width = <0x2d0>;

qcom,mdss-dsi-h-back-porch = <0x0c>;

qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01];

qcom,mdss-dsc-slice-height = <0x08>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x2d0>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0xb0302 0x1d1c0303 0x1020400>;

qcom,mdss-dsi-v-back-porch = <0x0e>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x10>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

};

};

qcom,mdss_dsi_nt35695b_truly_fhd_video {

qcom,mdss-dsi-panel-status-check-mode = "reg_read";

qcom,mdss-dsi-panel-status-read-length = <0x01>;

qcom,mdss-dsi-panel-name = "nt35695b truly fhd video mode dsi panel";

qcom,esd-check-enabled;

qcom,mdss-dsi-panel-status-value = <0x9c>;

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-t-clk-post = <0x07>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-post-init-delay = <0x01>;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";

qcom,mdss-dsi-pan-enable-dynamic-fps;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,mdss-dsi-lane-0-state;

qcom,dsi-supported-dfps-list = <0x3c 0x37 0x30>;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x1c>;

qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

qcom,mdss-dsi-panel-on-check-value = <0x9c>;

phandle = <0x52f>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x00 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x0c>;

qcom,mdss-dsi-panel-height = <0x780>;

qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 03 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00];

qcom,mdss-dsi-h-front-porch = <0x78>;

qcom,mdss-dsi-h-back-porch = <0x3c>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x130504 0x1f1e0505 0x3020400>;

qcom,mdss-dsi-v-back-porch = <0x02>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsi-v-front-porch = <0x0c>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

};

};

qcom,sde-sspp-vig-blocks {

qcom,sde-vig-igc = <0x1d00 0x50000>;

qcom,sde-vig-gamut = <0x1d00 0x50000>;

qcom,sde-vig-qseed-size = <0xa0>;

qcom,sde-vig-csc-off = <0x1a00>;

qcom,sde-vig-inverse-pma;

qcom,sde-vig-qseed-off = <0xa00>;

};

qcom,mdss_dsi_rm69299_visionox_amoled_video {

qcom,mdss-dsi-panel-name = "rm69299 amoled fhd+ video mode dsi visionox panel";

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-t-clk-post = <0x0e>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x31>;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x531>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-lane-map = "lane_map_0123";

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,display-topology = <0x01 0x00 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x02>;

qcom,mdss-dsi-panel-height = <0x8c8>;

qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 c2 08 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 51 ff 05 01 00 00 96 00 02 11 00 05 01 00 00 32 00 02 29 00];

qcom,mdss-dsi-h-front-porch = <0x1a>;

qcom,mdss-dsi-h-back-porch = <0x24>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x04>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x200808 0x24230808 0x5020400>;

qcom,mdss-dsi-v-back-porch = <0x04>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00];

qcom,mdss-dsi-v-front-porch = <0x38>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,mdss_dsi_dual_sim_video {

qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel";

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,panel-ack-disabled;

qcom,mdss-dsi-t-clk-post = <0x0d>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-bl-max-level = <0xfff>;

qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-panel-broadcast-mode;

qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0xc8 0x01 0x14>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x2d>;

phandle = <0x526>;

qcom,mdss-dsi-bllp-power-mode;

qcom,panel-supply-entries = <0x520>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x10>;

qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];

qcom,mdss-dsi-panel-height = <0x5a0>;

qcom,mdss-dsi-h-front-porch = <0x78>;

qcom,mdss-dsi-h-back-porch = <0x2c>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode";

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x500>;

qcom,mdss-dsi-v-pulse-width = <0x04>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5020400>;

qcom,mdss-dsi-v-back-porch = <0x04>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode";

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

qcom,sde-dspp-blocks {

qcom,sde-dspp-memcolor = <0x880 0x10007>;

qcom,sde-dspp-gc = <0x17c0 0x10008>;

qcom,sde-dspp-pcc = <0x1700 0x40000>;

qcom,sde-dspp-igc = <0x00 0x30001>;

qcom,sde-dspp-hist = <0x800 0x10007>;

qcom,sde-dspp-vlut = <0xa00 0x10008>;

qcom,sde-dspp-dither = <0x82c 0x10007>;

qcom,sde-dspp-gamut = <0x1000 0x40001>;

qcom,sde-dspp-sixzone = <0x900 0x10007>;

qcom,sde-dspp-hsic = <0x800 0x10007>;

};

qcom,sde-data-bus {

qcom,msm-bus,name = "mdss_sde";

qcom,msm-bus,num-paths = <0x02>;

qcom,msm-bus,num-cases = <0x03>;

qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x17 0x200 0x00 0x00 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800>;

};

qcom,sde-sspp-dma-blocks {

dgm@1 {

qcom,sde-dma-igc = <0x1400 0x50000>;

qcom,sde-dma-gc = <0x600 0x50000>;

qcom,sde-dma-csc-off = <0x1200>;

qcom,sde-dma-inverse-pma;

};

dgm@0 {

qcom,sde-dma-igc = <0x400 0x50000>;

qcom,sde-dma-gc = <0x600 0x50000>;

qcom,sde-dma-csc-off = <0x200>;

qcom,sde-dma-inverse-pma;

};

};

qcom,mdss_dsi_sharp_qsync_fhd_video {

qcom,adjust-timer-wakeup-ms = <0x01>;

qcom,mdss-pan-physical-width-dimension = <0x4a>;

qcom,mdss-dsi-panel-name = "Sharp fhd video mode qsync dsi panel";

qcom,mdss-dsi-min-refresh-rate = <0x3c>;

qcom,mdss-pan-physical-height-dimension = <0x86>;

qcom,mdss-dsi-t-clk-post = <0x0a>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-max-refresh-rate = <0x78>;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-panel-blackness-level = <0x1361>;

qcom,mdss-dsi-panel-peak-brightness = <0x626b50>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";

qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>;

qcom,mdss-dsi-pan-enable-dynamic-fps;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,mdss-dsi-lane-0-state;

qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x20>;

qcom,mdss-dsi-panel-hdr-enabled;

phandle = <0x538>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,display-topology = <0x02 0x02 0x02>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x14>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-panel-height = <0x780>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = <0x39010000 0x2ff 0xd0390100 0x02 0x75403901 0x1000 0x2f14039 0x1000000 0x2ff10 0x39010000 0x1000062c 0x1020408 0x10390100 0x02 0xffd03901 0x00 0x2750039 0x1000010 0x2f100 0x39010000 0x2ff 0x10390100 0x02 0xfb013901 0x00 0x2ba0339 0x1000000 0x2bc08 0x39010000 0x2c0 0x85390100 0x11 0xc1892800 0x8020002 0xe00bb00 0x70db70c 0xb7390100 0x03 0xc210f039 0x1000000 0x2d500 0x39010000 0x2d6 0x390100 0x02 0xde003901 0x00 0x2e10039 0x1000000 0x2e501 0x39010000 0x2bb 0x3390100 0x02 0xf6703901 0x00 0x2f78039 0x1000000 0x5be00 0x10001039 0x1000000 0x23500 0x39010000 0x244 0x390100 0x02 0xff203901 0x00 0x2fb0139 0x1000000 0x28702 0x39010000 0x25d 0x390100 0x02 0x5e143901 0x00 0x25feb39 0x1000000 0x2ff26 0x39010000 0x2fb 0x1390100 0x02 0x60003901 0x00 0x2620139 0x1000000 0x24000 0x39010000 0x2ff 0x28390100 0x02 0xfb013901 0x00 0x2910239 0x1000000 0x2ffe0 0x39010000 0x2fb 0x1390100 0x02 0x48813901 0x00 0x28e0939 0x1000000 0x2fff0 0x39010000 0x2fb 0x1390100 0x02 0x33203901 0x00 0x2343539 0x1000000 0x2ff10 0x5010000 0x78000111 0x5010000 0x78000129>;

qcom,mdss-dsi-h-front-porch = <0x7c>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x14>;

qcom,mdss-dsc-slice-height = <0x08>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x21c>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x130404 0x1f1f0405 0x3020400>;

qcom,mdss-dsi-v-back-porch = <0x0e>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x01>;

qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x7b0>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

};

};

qcom,mdss_dsi_rm69298_truly_amoled_cmd {

qcom,mdss-dsi-panel-name = "rm69298 amoled fhd+ cmd mode dsi truly panel";

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-t-clk-post = <0x0d>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x30>;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x52e>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-lane-map = "lane_map_0123";

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,display-topology = <0x01 0x00 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x0a>;

qcom,mdss-dsi-panel-height = <0x870>;

qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 fe 40 15 01 00 00 00 00 02 0a 15 15 01 00 00 00 00 02 0b cc 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 80 15 01 00 00 00 00 02 0f 87 15 01 00 00 00 00 02 05 08 15 01 00 00 00 00 02 06 08 15 01 00 00 00 00 02 08 08 15 01 00 00 00 00 02 09 08 15 01 00 00 00 00 02 16 15 15 01 00 00 00 00 02 20 8d 15 01 00 00 00 00 02 21 8d 15 01 00 00 00 00 02 24 55 15 01 00 00 00 00 02 26 55 15 01 00 00 00 00 02 28 55 15 01 00 00 00 00 02 2a 55 15 01 00 00 00 00 02 2d 28 15 01 00 00 00 00 02 2f 28 15 01 00 00 00 00 02 30 1e 15 01 00 00 00 00 02 31 1e 15 01 00 00 00 00 02 37 80 15 01 00 00 00 00 02 38 40 15 01 00 00 00 00 02 39 90 15 01 00 00 00 00 02 46 43 15 01 00 00 00 00 02 47 43 15 01 00 00 00 00 02 64 02 15 01 00 00 00 00 02 6f 02 15 01 00 00 00 00 02 74 2f 15 01 00 00 00 00 02 80 16 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 fe a0 15 01 00 00 00 00 02 2b 22 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 2f 35 15 01 00 00 00 00 02 fe 60 15 01 00 00 00 00 02 00 ac 15 01 00 00 00 00 02 01 0f 15 01 00 00 00 00 02 02 ff 15 01 00 00 00 00 02 03 05 15 01 00 00 00 00 02 04 00 15 01 00 00 00 00 02 05 06 15 01 00 00 00 00 02 06 00 15 01 00 00 00 00 02 07 00 15 01 00 00 00 00 02 09 c0 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 02 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0e 00 15 01 00 00 00 00 02 0e 04 15 01 00 00 00 00 02 0f 0e 15 01 00 00 00 00 02 10 a2 15 01 00 00 00 00 02 12 c0 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 14 02 15 01 00 00 00 00 02 15 00 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 17 05 15 01 00 00 00 00 02 18 0e 15 01 00 00 00 00 02 19 a2 15 01 00 00 00 00 02 1b c0 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 04 15 01 00 00 00 00 02 1e 01 15 01 00 00 00 00 02 1f 00 15 01 00 00 00 00 02 20 04 15 01 00 00 00 00 02 21 24 15 01 00 00 00 00 02 22 99 15 01 00 00 00 00 02 24 c0 15 01 00 00 00 00 02 25 00 15 01 00 00 00 00 02 26 04 15 01 00 00 00 00 02 27 01 15 01 00 00 00 00 02 28 00 15 01 00 00 00 00 02 29 06 15 01 00 00 00 00 02 2a 24 15 01 00 00 00 00 02 2b 99 15 01 00 00 00 00 02 83 ca 15 01 00 00 00 00 02 84 0f 15 01 00 00 00 00 02 85 ff 15 01 00 00 00 00 02 86 0a 15 01 00 00 00 00 02 87 00 15 01 00 00 00 00 02 88 08 15 01 00 00 00 00 02 89 00 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 8b 80 15 01 00 00 00 00 02 c7 1f 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 c9 01 15 01 00 00 00 00 02 ca 1f 15 01 00 00 00 00 02 cb 02 15 01 00 00 00 00 02 cc 1f 15 01 00 00 00 00 02 cd 1f 15 01 00 00 00 00 02 ce 1f 15 01 00 00 00 00 02 cf 1f 15 01 00 00 00 00 02 d0 1f 15 01 00 00 00 00 02 d1 1f 15 01 00 00 00 00 02 d2 1f 15 01 00 00 00 00 02 d3 1f 15 01 00 00 00 00 02 d4 1f 15 01 00 00 00 00 02 d5 1f 15 01 00 00 00 00 02 d6 1f 15 01 00 00 00 00 02 d7 1f 15 01 00 00 00 00 02 d8 1f 15 01 00 00 00 00 02 d9 1f 15 01 00 00 00 00 02 da 1f 15 01 00 00 00 00 02 db 1f 15 01 00 00 00 00 02 dc 00 15 01 00 00 00 00 02 dd 0e 15 01 00 00 00 00 02 de 1f 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 04 15 01 00 00 00 00 02 e1 1f 15 01 00 00 00 00 02 e2 01 15 01 00 00 00 00 02 e3 02 15 01 00 00 00 00 02 e4 1f 15 01 00 00 00 00 02 e5 1f 15 01 00 00 00 00 02 e6 1f 15 01 00 00 00 00 02 e7 1f 15 01 00 00 00 00 02 e8 1f 15 01 00 00 00 00 02 e9 1f 15 01 00 00 00 00 02 ea 1f 15 01 00 00 00 00 02 eb 1f 15 01 00 00 00 00 02 ec 1f 15 01 00 00 00 00 02 ed 1f 15 01 00 00 00 00 02 ee 1f 15 01 00 00 00 00 02 ef 03 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 c6 15 15 01 00 00 00 00 02 c9 9e 15 01 00 00 00 00 02 cb 3f 15 01 00 00 00 00 02 d1 0f 15 01 00 00 00 00 02 d3 15 15 01 00 00 00 00 02 d4 15 15 01 00 00 00 00 02 d5 00 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 a9 40 15 01 00 00 00 00 02 cb 05 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 5a ff 15 01 00 00 00 00 02 5c ff 15 01 00 00 00 00 02 5d 0a 15 01 00 00 00 00 02 7d 31 15 01 00 00 00 00 02 7e 4a 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 49 05 15 01 00 00 00 00 02 4a 2e 15 01 00 00 00 00 02 4b 58 15 01 00 00 00 00 02 4c 77 15 01 00 00 00 00 02 4d a1 15 01 00 00 00 00 02 4e de 15 01 00 00 00 00 02 4f 2c 15 01 00 00 00 00 02 50 97 15 01 00 00 00 00 02 51 2a 15 01 00 00 00 00 02 ad ec 15 01 00 00 00 00 02 ae 80 15 01 00 00 00 00 02 af 00 15 01 00 00 00 00 02 b0 50 15 01 00 00 00 00 02 b1 3a 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 56 91 15 01 00 00 00 00 02 58 04 15 01 00 00 00 00 02 59 24 15 01 00 00 00 00 02 5a 05 15 01 00 00 00 00 02 5b c6 15 01 00 00 00 00 02 5c 05 15 01 00 00 00 00 02 5d 66 15 01 00 00 00 00 02 5e 06 15 01 00 00 00 00 02 5f 17 15 01 00 00 00 00 02 60 07 15 01 00 00 00 00 02 61 cf 15 01 00 00 00 00 02 62 07 15 01 00 00 00 00 02 63 98 15 01 00 00 00 00 02 64 08 15 01 00 00 00 00 02 65 65 15 01 00 00 00 00 02 66 09 15 01 00 00 00 00 02 67 37 15 01 00 00 00 00 02 68 0a 15 01 00 00 00 00 02 6b 02 15 01 00 00 00 00 02 6c 0c 15 01 00 00 00 00 02 71 02 15 01 00 00 00 00 02 72 0f 15 01 00 00 00 00 02 73 93 15 01 00 00 00 00 02 74 0f 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 98 cf 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 b4 31 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 aa 03 15 01 00 00 00 00 02 09 13 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 01 41 15 01 00 00 00 00 02 02 00 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 04 ff 15 01 00 00 00 00 02 05 00 15 01 00 00 00 00 02 06 c0 15 01 00 00 00 00 02 07 40 15 01 00 00 00 00 02 08 20 15 01 00 00 00 00 02 19 e0 15 01 00 00 00 00 02 1a 40 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 80 15 01 00 00 00 00 02 60 40 15 01 00 00 00 00 02 61 40 15 01 00 00 00 00 02 62 40 15 01 00 00 00 00 02 63 40 15 01 00 00 00 00 02 64 40 15 01 00 00 00 00 02 65 40 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 02 15 01 00 00 00 00 02 75 10 15 01 00 00 00 00 02 76 14 15 01 00 00 00 00 02 77 1c 15 01 00 00 00 00 02 78 20 15 01 00 00 00 00 02 79 0a 15 01 00 00 00 00 02 7a 00 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c 00 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e 00 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 81 00 15 01 00 00 00 00 02 82 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 84 00 15 01 00 00 00 00 02 85 00 15 01 00 00 00 00 02 86 20 15 01 00 00 00 00 02 87 0a 15 01 00 00 00 00 02 88 02 15 01 00 00 00 00 02 89 2b 15 01 00 00 00 00 02 8a 14 15 01 00 00 00 00 02 8b 01 15 01 00 00 00 00 02 8c 00 15 01 00 00 00 00 02 8d 00 15 01 00 00 00 00 02 8e 00 15 01 00 00 00 00 02 8f 00 15 01 00 00 00 00 02 90 00 15 01 00 00 00 00 02 91 00 15 01 00 00 00 00 02 92 00 15 01 00 00 00 00 02 93 00 15 01 00 00 00 00 02 94 00 15 01 00 00 00 00 02 95 00 15 01 00 00 00 00 02 96 00 15 01 00 00 00 00 02 b2 40 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 b8 d0 15 01 00 00 00 00 02 b9 06 15 01 00 00 00 00 02 ba 00 15 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 05 51 00 00 ff ff 15 01 00 00 00 00 02 c2 08 15 01 00 00 00 00 02 35 00 05 01 00 00 96 00 01 11 05 01 00 00 32 00 01 29];

qcom,mdss-dsi-h-front-porch = <0x1e>;

qcom,mdss-dsi-h-back-porch = <0x28>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x04>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x1f0808 0x24220808 0x5020400>;

qcom,mdss-dsi-v-back-porch = <0x10>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00];

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

};

};

};

};

jtagmm@7540000 {

clock-names = "core_clk";

reg-names = "etm-base";

clocks = <0x19 0x00>;

compatible = "qcom,jtagv8-mm";

qcom,coresight-jtagmm-cpu = <0x16>;

reg = <0x7540000 0x1000>;

phandle = <0x2ad>;

};

qcom,msm-cdsp-loader {

compatible = "qcom,cdsp-loader";

qcom,proc-img-to-load = "cdsp";

};

rpmh-regulator-smpc8 {

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "smpc8";

mboxes = <0x1b 0x00>;

regulator-pm6150l-s8 {

regulator-max-microvolt = <0x157c00>;

qcom,init-voltage = <0x111700>;

regulator-min-microvolt = <0x111700>;

regulator-name = "pm6150l_s8";

qcom,set = <0x03>;

phandle = <0x3ff>;

};

};

i2c@0x880000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x166>;

clock-names = "se-clk\0m-ahb\0s-ahb";

interrupts = <0x00 0x259 0x00>;

clocks = <0x27 0x44 0x27 0x67 0x27 0x68>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x168>;

dma-names = "tx\0rx";

compatible = "qcom,i2c-geni";

pinctrl-1 = <0x167>;

status = "disabled";

reg = <0x880000 0x4000>;

phandle = <0x34d>;

dmas = <0x165 0x00 0x00 0x03 0x40 0x00 0x165 0x01 0x00 0x03 0x40 0x00>;

};

qcom,dsi-display@23 {

qcom,dsi-phy-num = <0x00 0x01>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x537>;

qcom,dsi-ctrl-num = <0x00 0x01>;

qcom,display-type = "primary";

label = "dsi_sharp_qsync_wqhd_video_display";

phandle = <0x558>;

};

cti@601d000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti13";

compatible = "arm,primecell";

reg = <0x601d000 0x1000>;

phandle = <0x482>;

};

lpass_core_hw_vote {

qcom,codec-ext-clk-src = <0x09>;

#clock-cells = <0x01>;

compatible = "qcom,audio-ref-clk";

phandle = <0x4cd>;

};

qcom,msm-dai-tdm-sen-rx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9050>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9150>;

phandle = <0x4c4>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-sen-rx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9050>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x4c5>;

};

};

qcom,gdsc@17d048 {

qcom,no-status-check-on-disable;

qcom,gds-timeout = <0x1f4>;

regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x17d048 0x04>;

phandle = <0x1c9>;

};

qcom,msm-compr-dsp {

compatible = "qcom,msm-compr-dsp";

phandle = <0x269>;

};

dsi_panel_pwr_supply_no_labibb {

#address-cells = <0x01>;

#size-cells = <0x00>;

phandle = <0x59e>;

qcom,panel-supply-entry@0 {

qcom,supply-disable-load = <0x50>;

qcom,supply-enable-load = <0x7d00>;

qcom,supply-name = "vddio";

qcom,supply-max-voltage = <0x1d0d80>;

reg = <0x00>;

qcom,supply-min-voltage = <0x1b7740>;

};

};

clocks {

sleep-clk {

clock-output-names = "chip_sleep_clk";

#clock-cells = <0x01>;

clock-frequency = <0x7d00>;

compatible = "fixed-clock";

phandle = <0x2b1>;

};

};

stm@6002000 {

arm,primecell-periphid = <0x3b962>;

clock-names = "apb_pclk";

reg-names = "stm-base\0stm-stimulus-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-stm";

compatible = "arm,primecell";

reg = <0x6002000 0x1000 0x16280000 0x180000>;

phandle = <0x444>;

port {

endpoint {

remote-endpoint = <0x225>;

phandle = <0x1e2>;

};

};

};

i2c@0xa94000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x18f>;

clock-names = "se-clk\0m-ahb\0s-ahb";

interrupts = <0x00 0x166 0x00>;

clocks = <0x27 0x61 0x27 0x69 0x27 0x6a>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x182>;

dma-names = "tx\0rx";

compatible = "qcom,i2c-geni";

pinctrl-1 = <0x190>;

status = "disabled";

reg = <0xa94000 0x4000>;

phandle = <0x360>;

dmas = <0x183 0x00 0x05 0x03 0x40 0x00 0x183 0x01 0x05 0x03 0x40 0x00>;

};

qcom,msm-dai-cdc-dma {

compatible = "qcom,msm-dai-cdc-dma";

phandle = <0x495>;

qcom,msm-dai-va-cdc-dma-0-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb021>;

phandle = <0x496>;

};

qcom,msm-dai-rx-cdc-dma-6-rx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb03c>;

phandle = <0x2a1>;

};

qcom,msm-dai-rx-cdc-dma-3-rx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb036>;

phandle = <0x29b>;

};

qcom,msm-dai-rx-cdc-dma-0-rx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb030>;

phandle = <0x295>;

};

qcom,msm-dai-wsa-cdc-dma-0-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb001>;

phandle = <0x291>;

};

qcom,msm-dai-wsa-cdc-dma-0-rx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb000>;

phandle = <0x290>;

};

qcom,msm-dai-tx-cdc-dma-5-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb03b>;

phandle = <0x2a0>;

};

qcom,msm-dai-tx-cdc-dma-2-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb035>;

phandle = <0x29a>;

};

qcom,msm-dai-va-cdc-dma-2-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb025>;

phandle = <0x498>;

};

qcom,msm-dai-rx-cdc-dma-5-rx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb03a>;

phandle = <0x29f>;

};

qcom,msm-dai-rx-cdc-dma-2-rx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb034>;

phandle = <0x299>;

};

qcom,msm-dai-wsa-cdc-dma-2-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb005>;

phandle = <0x294>;

};

qcom,msm-dai-tx-cdc-dma-4-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb039>;

phandle = <0x29e>;

};

qcom,msm-dai-tx-cdc-dma-1-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb033>;

phandle = <0x298>;

};

qcom,msm-dai-va-cdc-dma-1-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb023>;

phandle = <0x497>;

};

qcom,msm-dai-rx-cdc-dma-7-rx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb03e>;

phandle = <0x2a2>;

};

qcom,msm-dai-rx-cdc-dma-4-rx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb038>;

phandle = <0x29d>;

};

qcom,msm-dai-rx-cdc-dma-1-rx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb032>;

phandle = <0x297>;

};

qcom,msm-dai-wsa-cdc-dma-1-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb003>;

phandle = <0x293>;

};

qcom,msm-dai-wsa-cdc-dma-1-rx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb002>;

phandle = <0x292>;

};

qcom,msm-dai-tx-cdc-dma-3-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb037>;

phandle = <0x29c>;

};

qcom,msm-dai-tx-cdc-dma-0-tx {

compatible = "qcom,msm-dai-cdc-dma-dev";

qcom,msm-dai-cdc-dma-dev-id = <0xb031>;

phandle = <0x296>;

};

};

qcom,msm-pcm-routing {

compatible = "qcom,msm-pcm-routing";

phandle = <0x268>;

};

tx_core_clk {

qcom,codec-ext-clk-src = <0x07>;

#clock-cells = <0x01>;

compatible = "qcom,audio-ref-clk";

phandle = <0x4e0>;

qcom,codec-lpass-clk-id = <0x30c>;

qcom,codec-lpass-ext-clk-freq = <0x124f800>;

};

cti@78e0000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-apss_cti0";

compatible = "arm,primecell";

reg = <0x78e0000 0x1000>;

phandle = <0x45e>;

};

qcom,sps {

qcom,pipe-attr-ee;

compatible = "qcom,msm-sps-4k";

};

tpdm@6006000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-qdss";

compatible = "arm,primecell";

reg = <0x6006000 0x1000>;

phandle = <0x44a>;

port {

endpoint {

remote-endpoint = <0x23d>;

phandle = <0x23c>;

};

};

};

cti@601a000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti10";

compatible = "arm,primecell";

reg = <0x601a000 0x1000>;

phandle = <0x47f>;

};

cti@6a11000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-ddr_dl_1_cti1";

compatible = "arm,primecell";

reg = <0x6a11000 0x1000>;

phandle = <0x464>;

};

qcom,dsi-display@1 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x523>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_sw43404_amoled_cmd_display";

phandle = <0x540>;

};

smcinvoke@86d00000 {

reg-names = "secapp-region";

compatible = "qcom,smcinvoke";

reg = <0x86d00000 0x3e00000>;

phandle = <0x2db>;

};

qcom,npu@0x9800000 {

memory-region = <0xb6>;

qcom,pas-id = <0x17>;

compatible = "qcom,pil-tz-generic";

status = "ok";

reg = <0x9800000 0x800000>;

qcom,firmware-name = "npu";

};

cti@6c13000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-titan";

compatible = "arm,primecell";

status = "disabled";

reg = <0x6c13000 0x1000>;

phandle = <0x474>;

};

qcom,dsi-display@13 {

qcom,dsi-phy-num = <0x01>;

qcom,dsi-select-clocks = "mux_byte_clk1\0mux_pixel_clk1";

qcom,dsi-panel = <0x52f>;

qcom,dsi-ctrl-num = <0x01>;

qcom,display-type = "primary";

label = "dsi_nt35695b_truly_fhd_video_display";

phandle = <0x54c>;

};

qcom,msm-dai-tdm-quat-rx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9030>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9130>;

phandle = <0x4c0>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-quat-rx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9030>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x28c>;

};

};

rpmh-regulator-ldoc2 {

qcom,mode-threshold-currents = <0x00 0x2710>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoc2";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150l-l2 {

regulator-max-microvolt = <0x14a140>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x124f80>;

regulator-min-microvolt = <0x124f80>;

regulator-name = "pm6150l_l2";

qcom,set = <0x03>;

phandle = <0x32>;

};

};

qcom,cam-lrme {

compatible = "qcom,cam-lrme";

status = "ok";

arch-compat = "lrme";

};

qcom,gdsc@17d038 {

qcom,no-status-check-on-disable;

qcom,gds-timeout = <0x1f4>;

regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x17d038 0x04>;

phandle = <0x1c7>;

};

qcom,msm-eud@88e0000 {

clock-names = "eud_ahb2phy_clk";

reg-names = "eud_base\0eud_mode_mgr2";

interrupts = <0x00 0x1ec 0x04>;

clocks = <0x27 0x97>;

qcom,secure-eud-en;

compatible = "qcom,msm-eud";

status = "ok";

interrupt-names = "eud_irq";

reg = <0x88e0000 0x2000 0x88e4000 0x1000>;

phandle = <0x25c>;

qcom,eud-clock-vote-req;

};

qcom,mdss_dsi_g7b_37_02_0b_dsc_video {

qcom,mdss-pan-physical-width-dimension = <0x46>;

qcom,mdss-dsi-panel-name = "xiaomi 37 02 0b video mode dsc dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x9a>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-underflow-color = <0x00>;

qcom,mdss-dsi-t-clk-post = <0x0e>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-panel-id = <0x00>;

qcom,mdss-dsi-pan-enable-smart-fps;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-panel-max-luminance = <0x0f 0x20>;

qcom,bl-update-flag = "delay_until_first_frame";

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,mdss-dsi-panel-xy-coordinate = <0x0f 0x18>;

qcom,mdss-dsi-qsync-min-refresh-rate = <0x3c>;

qcom,mdss-dsi-panel-max-luminance-valid = <0x01 0x01>;

qcom,dispparam-enabled;

qcom,mdss-dsi-panel-peak-brightness = <0x401640>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-pan-enable-dynamic-fps;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x05 0x00 0x01 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,is-tddi-flag;

qcom,mdss-dsi-lane-0-state;

qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c 0x32 0x1e>;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-panel-on-dimming-delay = <0xc8>;

qcom,mdss-dsi-t-clk-pre = <0x34>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,cont-splash-enabled;

qcom,mdss-dsi-panel-model = "xiaomi 37 02 0a VIDEO PANEL";

phandle = <0x53d>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,esd-err-irq-gpio = <0x174 0x20 0x2002>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,disp-panel-offon-mode-enabled;

qcom,mdss-brightness-max-level = <0xfff>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_hs_mode";

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x01 0x01>;

qcom,mdss-dsi-panel-framerate = <0x78>;

qcom,mdss-dsi-h-pulse-width = <0x0c>;

qcom,mdss-dsi-dispparam-xy-coordinate-command = [15 01 00 00 00 00 02 ff 10 06 01 00 01 05 00 02 a1 00];

qcom,mdss-dsi-read-lockdown-info-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command = [39 01 00 00 00 00 03 51 0d b5];

qcom,mdss-dsi-dispparam-xy-coordinate-command-state = "dsi_hs_mode";

qcom,compression-mode = "dsc";

qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_hs_mode";

qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode";

qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-lcd-hbm-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-cabcmovieon-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 03];

qcom,mdss-dsi-panel-height = <0x960>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsi-panel-xy-coordinate = <0x0f 0x18>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 23 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 00 80 15 00 00 00 00 00 02 01 84 15 00 00 00 00 00 02 05 2d 15 00 00 00 00 00 02 06 00 15 00 00 00 00 00 02 07 00 15 00 00 00 00 00 02 08 01 15 00 00 00 00 00 02 09 45 15 00 00 00 00 00 02 11 01 15 00 00 00 00 00 02 12 95 15 00 00 00 00 00 02 15 68 15 00 00 00 00 00 02 16 0b 15 00 00 00 00 00 02 29 0a 15 00 00 00 00 00 02 30 ff 15 00 00 00 00 00 02 31 fe 15 00 00 00 00 00 02 32 fd 15 00 00 00 00 00 02 33 fb 15 00 00 00 00 00 02 34 f8 15 00 00 00 00 00 02 35 f5 15 00 00 00 00 00 02 36 f3 15 00 00 00 00 00 02 37 f2 15 00 00 00 00 00 02 38 f2 15 00 00 00 00 00 02 39 f2 15 00 00 00 00 00 02 3a ef 15 00 00 00 00 00 02 3b ec 15 00 00 00 00 00 02 3d e9 15 00 00 00 00 00 02 3f e5 15 00 00 00 00 00 02 40 e5 15 00 00 00 00 00 02 41 e5 15 00 00 00 00 00 02 2a 13 15 00 00 00 00 00 02 45 ff 15 00 00 00 00 00 02 46 f4 15 00 00 00 00 00 02 47 e7 15 00 00 00 00 00 02 48 da 15 00 00 00 00 00 02 49 cd 15 00 00 00 00 00 02 4a c0 15 00 00 00 00 00 02 4b b3 15 00 00 00 00 00 02 4c b2 15 00 00 00 00 00 02 4d b2 15 00 00 00 00 00 02 4e b2 15 00 00 00 00 00 02 4f 99 15 00 00 00 00 00 02 50 80 15 00 00 00 00 00 02 51 68 15 00 00 00 00 00 02 52 66 15 00 00 00 00 00 02 53 66 15 00 00 00 00 00 02 54 66 15 00 00 00 00 00 02 2b 0e 15 00 00 00 00 00 02 58 ff 15 00 00 00 00 00 02 59 fb 15 00 00 00 00 00 02 5a f7 15 00 00 00 00 00 02 5b f3 15 00 00 00 00 00 02 5c ef 15 00 00 00 00 00 02 5d e3 15 00 00 00 00 00 02 5e da 15 00 00 00 00 00 02 5f d8 15 00 00 00 00 00 02 60 d8 15 00 00 00 00 00 02 61 d8 15 00 00 00 00 00 02 62 cb 15 00 00 00 00 00 02 63 bf 15 00 00 00 00 00 02 64 b3 15 00 00 00 00 00 02 65 b2 15 00 00 00 00 00 02 66 b2 15 01 00 00 00 00 02 67 b2 15 01 00 00 00 00 02 ff 26 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 81 0e 15 01 00 00 00 00 02 88 0c 15 01 00 00 00 00 02 ff e0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 35 82 15 00 00 00 00 00 02 4e 02 15 01 00 00 00 00 02 ff f0 15 00 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 ff d0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 09 af 15 01 00 00 00 00 02 ff c0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 9c 11 15 00 00 00 00 00 02 9d 11 15 01 00 00 00 00 02 ff f0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 9c 00 15 01 00 00 00 00 02 ff 10 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 b0 00 39 00 00 00 00 00 03 51 0b 6c 15 01 00 00 00 00 02 53 24 15 01 00 00 46 00 02 11 00 15 01 00 00 00 00 02 29 00 15 01 00 00 00 00 02 ff 27 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 3f 01 15 00 00 00 00 00 02 43 08 15 00 00 00 00 00 02 40 25 15 01 00 00 00 00 02 ff 10];

qcom,mdss-dsi-h-front-porch = <0x28>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x28>;

qcom,mdss-dsi-dispparam-cabcstillon-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 02];

qcom,mdss-dsi-dispparam-cabcuion-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 01];

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command = [39 01 00 00 00 00 03 51 0e 8c];

qcom,mdss-dsi-dispparam-lcd-hbm-off-command = [39 01 00 00 00 00 03 51 0b 6c];

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x14>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-dispparam-cabcoff-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00];

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 24];

qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5020400>;

qcom,mdss-dsi-v-back-porch = <0x1e>;

qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command-state = "dsi_lp_mode";

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x02>;

qcom,mdss-dsi-h-sync-pulse = <0x01>;

qcom,mdss-dsc-scr-version = <0x00>;

qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 27 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 3f 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 28 00 15 01 00 00 46 00 02 10 00];

qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode";

qcom,mdss-dsi-dispparam-cabcuion-command-state = "dsi_hs_mode";

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c];

qcom,mdss-dsi-v-front-porch = <0x20>;

qcom,mdss-dsi-displayoff-command = [15 01 00 00 20 00 02 28 00];

qcom,mdss-dsi-displayon-command = [15 01 00 00 14 00 02 29 00];

qcom,mdss-dsi-read-lockdown-info-command = [15 01 00 00 00 00 02 ff 21 06 01 00 00 00 00 01 f1];

qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_hs_mode";

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

qcom,mdss-dsc-version = <0x11>;

};

};

};

qcom,camera-flash@2 {

cell-index = <0x02>;

torch-source = <0x2f6>;

switch-source = <0x2fb>;

compatible = "qcom,camera-flash";

status = "ok";

reg = <0x02 0x00>;

phandle = <0x567>;

flash-source = <0x2f3>;

};

qcom,cam-isp {

compatible = "qcom,cam-isp";

status = "ok";

arch-compat = "ife";

};

rpmh-regulator-ldoa18 {

compatible = "qcom,rpmh-xob-regulator";

qcom,resource-name = "ldoa18";

mboxes = <0x1b 0x00>;

regulator-pm6150-l18 {

regulator-max-microvolt = <0x2dc6c0>;

regulator-min-microvolt = <0x2dc6c0>;

regulator-name = "pm6150_l18";

qcom,set = <0x03>;

phandle = <0x40c>;

};

};

qcom,mdss_dsi_phy0@ae94400 {

qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00];

reg-names = "dsi_phy\0dyn_refresh_base";

cell-index = <0x00>;

label = "dsi-phy-0";

qcom,platform-lane-config = <0x00 0x00 0x00 0x00 0x80>;

compatible = "qcom,dsi-phy-v3.0";

vdda-0p9-supply = <0x1a9>;

qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];

reg = <0xae94400 0x7c0 0xae94200 0x100>;

phandle = <0x374>;

qcom,phy-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,phy-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x8ca0>;

qcom,supply-name = "vdda-0p9";

qcom,supply-max-voltage = <0xe09c0>;

reg = <0x00>;

qcom,supply-min-voltage = <0xc92c0>;

};

};

};

qcom,cam-icp {

icp_pc_en;

num-bps = <0x01>;

num-ipe = <0x02>;

num-a5 = <0x01>;

compat-hw-name = "qcom,a5\0qcom,ipe0\0qcom,ipe1\0qcom,bps";

compatible = "qcom,cam-icp";

status = "ok";

};

qcom,csiphy@ace2000 {

clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk";

reg-names = "csiphy";

reg-cam-base = <0xe2000>;

csi-vdd-voltage = <0x124f80>;

cell-index = <0x01>;

interrupts = <0x00 0x1de 0x00>;

clocks = <0x29 0x1b 0x29 0x24 0x29 0x25 0x29 0x1f 0x29 0x1e>;

gdscr-supply = <0x1ae>;

clock-cntl-level = "svs\0svs_l1\0turbo";

compatible = "qcom,csiphy-v1.2\0qcom,csiphy";

src-clock-name = "csi1phytimer_clk_src";

mipi-csi-vdd-supply = <0x1a8>;

status = "ok";

interrupt-names = "csiphy";

reg = <0xace2000 0x2000>;

regulator-names = "gdscr\0refgen";

phandle = <0x379>;

refgen-supply = <0x1af>;

clock-rates = <0x16e36000 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00>;

};

tpdm@78b0000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-llm-gold";

compatible = "arm,primecell";

reg = <0x78b0000 0x1000>;

phandle = <0x43a>;

port {

endpoint {

remote-endpoint = <0x213>;

phandle = <0x212>;

};

};

};

tpdm@69e1000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk\0npu_core_apb_clk\0npu_core_atb_clk\0npu_core_clk\0npu_core_clk_src\0npu_core_cti_clk";

reg-names = "tpdm-base";

clocks = <0x19 0x00 0x2c 0x0c 0x2c 0x0d 0x2c 0x0e 0x2c 0x0f 0x2c 0x10>;

coresight-name = "coresight-tpdm-npu";

vdd-supply = <0x23>;

compatible = "arm,primecell";

qcom,tpdm-regs = "vdd\0vdd_cx";

reg = <0x69e1000 0x1000>;

phandle = <0x486>;

vdd_cx-supply = <0x1d>;

qcom,tpdm-clks = "npu_core_apb_clk\0npu_core_atb_clk\0npu_core_clk\0npu_core_clk_src\0npu_core_cti_clk";

port {

endpoint {

remote-endpoint = <0x258>;

phandle = <0x23a>;

};

};

};

qcom,cpu0-llcc-ddr-latmon {

qcom,cachemiss-ev = <0x1000>;

qcom,core-dev-table = <0xbb800 0x478 0xf8700 0x6b8 0x130b00 0x826 0x16d7a8 0xb71 0x1b8a00 0xf27>;

qcom,cpulist = <0x11 0x12 0x13 0x14 0x15 0x16>;

compatible = "qcom,arm-memlat-mon";

phandle = <0x317>;

qcom,target-dev = <0xc3>;

};

tpdm@6b48000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-north";

compatible = "arm,primecell";

reg = <0x6b48000 0x1000>;

phandle = <0x459>;

port {

endpoint {

remote-endpoint = <0x254>;

phandle = <0x237>;

};

};

};

system_pm {

compatible = "qcom,system-pm";

mboxes = <0x1b 0x00>;

};

cpuss_dump {

compatible = "qcom,cpuss-dump";

qcom,l2_tlb_dump400 {

qcom,dump-node = <0x4d>;

qcom,dump-id = <0x124>;

};

qcom,l2_tlb_dump0 {

qcom,dump-node = <0x49>;

qcom,dump-id = <0x120>;

};

qcom,l1_d_cache100 {

qcom,dump-node = <0x3e>;

qcom,dump-id = <0x81>;

};

qcom,l2_tlb_dump700 {

qcom,dump-node = <0x50>;

qcom,dump-id = <0x127>;

};

qcom,llcc2_d_cache {

qcom,dump-node = <0x52>;

qcom,dump-id = <0x141>;

};

qcom,l1_d_cache400 {

qcom,dump-node = <0x41>;

qcom,dump-id = <0x84>;

};

qcom,l1_i_cache100 {

qcom,dump-node = <0x36>;

qcom,dump-id = <0x61>;

};

qcom,l1_d_tlb_dump600 {

qcom,dump-node = <0x47>;

qcom,dump-id = <0x46>;

};

qcom,l1_d_cache700 {

qcom,dump-node = <0x44>;

qcom,dump-id = <0x87>;

};

qcom,l1_i_cache400 {

qcom,dump-node = <0x39>;

qcom,dump-id = <0x64>;

};

qcom,l2_tlb_dump300 {

qcom,dump-node = <0x4c>;

qcom,dump-id = <0x123>;

};

qcom,l1_i_tlb_dump700 {

qcom,dump-node = <0x46>;

qcom,dump-id = <0x27>;

};

qcom,l1_i_cache700 {

qcom,dump-node = <0x3c>;

qcom,dump-id = <0x67>;

};

qcom,l2_tlb_dump600 {

qcom,dump-node = <0x4f>;

qcom,dump-id = <0x126>;

};

qcom,l1_d_cache0 {

qcom,dump-node = <0x3d>;

qcom,dump-id = <0x80>;

};

qcom,l2_cache_dump700 {

qcom,dump-node = <0x10>;

qcom,dump-id = <0xc7>;

};

qcom,l1_d_cache300 {

qcom,dump-node = <0x40>;

qcom,dump-id = <0x83>;

};

qcom,llcc1_d_cache {

qcom,dump-node = <0x51>;

qcom,dump-id = <0x140>;

};

qcom,l1_d_cache600 {

qcom,dump-node = <0x43>;

qcom,dump-id = <0x86>;

};

qcom,l1_i_cache300 {

qcom,dump-node = <0x38>;

qcom,dump-id = <0x63>;

};

qcom,l2_tlb_dump200 {

qcom,dump-node = <0x4b>;

qcom,dump-id = <0x122>;

};

qcom,l1_i_tlb_dump600 {

qcom,dump-node = <0x45>;

qcom,dump-id = <0x26>;

};

qcom,l1_i_cache600 {

qcom,dump-node = <0x3b>;

qcom,dump-id = <0x66>;

};

qcom,l2_tlb_dump500 {

qcom,dump-node = <0x4e>;

qcom,dump-id = <0x125>;

};

qcom,l1_i_cache0 {

qcom,dump-node = <0x35>;

qcom,dump-id = <0x60>;

};

qcom,l2_cache_dump600 {

qcom,dump-node = <0x0e>;

qcom,dump-id = <0xc6>;

};

qcom,l1_d_cache200 {

qcom,dump-node = <0x3f>;

qcom,dump-id = <0x82>;

};

qcom,l1_d_cache500 {

qcom,dump-node = <0x42>;

qcom,dump-id = <0x85>;

};

qcom,l1_i_cache200 {

qcom,dump-node = <0x37>;

qcom,dump-id = <0x62>;

};

qcom,l2_tlb_dump100 {

qcom,dump-node = <0x4a>;

qcom,dump-id = <0x121>;

};

qcom,l1_d_tlb_dump700 {

qcom,dump-node = <0x48>;

qcom,dump-id = <0x47>;

};

qcom,l1_i_cache500 {

qcom,dump-node = <0x3a>;

qcom,dump-id = <0x65>;

};

};

cti@69C2000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-dlmm_cti1";

compatible = "arm,primecell";

reg = <0x69c2000 0x1000>;

phandle = <0x467>;

};

cti@6a03000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-ddr_dl_0_cti1";

compatible = "arm,primecell";

reg = <0x6a03000 0x1000>;

phandle = <0x462>;

};

tpdm@6b02000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-swao-0";

compatible = "arm,primecell";

reg = <0x6b02000 0x1000>;

phandle = <0x42f>;

port {

endpoint {

remote-endpoint = <0x1fe>;

phandle = <0x1fc>;

};

};

};

llcc-bw-opp-table {

compatible = "operating-points-v2";

phandle = <0xbc>;

opp-300 {

opp-hz = <0x00 0x11e1>;

};

opp-600 {

opp-hz = <0x00 0x23c3>;

};

opp-806 {

opp-hz = <0x00 0x300a>;

};

opp-466 {

opp-hz = <0x00 0x1bc6>;

};

opp-933 {

opp-hz = <0x00 0x379c>;

};

};

qcom,msm-pcm-dtmf {

compatible = "qcom,msm-pcm-dtmf";

phandle = <0x490>;

};

qcom,gpi-dma@0x800000 {

iommus = <0x30 0x216 0x00>;

qcom,gpii-mask = <0x0f>;

qcom,smmu-cfg = <0x01>;

reg-names = "gpi-top";

interrupts = <0x00 0xf4 0x00 0x00 0xf5 0x00 0x00 0xf6 0x00 0x00 0xf7 0x00 0x00 0xf8 0x00 0x00 0xf9 0x00 0x00 0xfa 0x00 0x00 0xfb 0x00>;

qcom,ev-factor = <0x02>;

qcom,iova-range = <0x00 0x100000 0x00 0x100000>;

compatible = "qcom,gpi-dma";

status = "ok";

qcom,max-num-gpii = <0x08>;

reg = <0x800000 0x60000>;

phandle = <0x165>;

#dma-cells = <0x05>;

};

rpmh-regulator-ldoa2 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa2";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l2 {

regulator-max-microvolt = <0x101d00>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0xe6780>;

regulator-min-microvolt = <0xe6780>;

regulator-name = "pm6150_l2";

qcom,set = <0x03>;

phandle = <0x403>;

};

};

msm_cdc_pinctrl@29 {

pinctrl-names = "aud_active\0aud_sleep";

pinctrl-0 = <0x509>;

compatible = "qcom,msm-cdc-pinctrl";

qcom,lpi-gpios;

pinctrl-1 = <0x50a>;

status = "disabled";

phandle = <0x510>;

};

mem_dump {

memory-region = <0x53>;

compatible = "qcom,mem-dump";

tmc_etf {

qcom,dump-size = <0x10000>;

qcom,dump-id = <0xf0>;

};

fcm {

qcom,dump-size = <0x8400>;

qcom,dump-id = <0xee>;

};

etf_reg {

qcom,dump-size = <0x1000>;

qcom,dump-id = <0x101>;

};

rpm_sw {

qcom,dump-size = <0x28000>;

qcom,dump-id = <0xea>;

};

etfswao_reg {

qcom,dump-size = <0x1000>;

qcom,dump-id = <0x102>;

};

etr_reg {

qcom,dump-size = <0x1000>;

qcom,dump-id = <0x100>;

};

pmic {

qcom,dump-size = <0x10000>;

qcom,dump-id = <0xe4>;

};

etf_swao {

qcom,dump-size = <0x8400>;

qcom,dump-id = <0xf1>;

};

misc_data {

qcom,dump-size = <0x1000>;

qcom,dump-id = <0xe8>;

};

rpmh {

qcom,dump-size = <0x2000000>;

qcom,dump-id = <0xec>;

};

};

qcom,msm-pcm {

qcom,msm-pcm-dsp-id = <0x00>;

compatible = "qcom,msm-pcm-dsp";

phandle = <0x25e>;

};

qcom,dsi-display {

vdda-3p3-supply = <0x40c>;

pinctrl-names = "panel_active\0panel_suspend";

qcom,panel-te-source = <0x00>;

pinctrl-0 = <0x3c6 0x2ed>;

clock-names = "mux_byte_clk0\0mux_pixel_clk0\0mux_byte_clk1\0mux_pixel_clk1\0src_byte_clk0\0src_pixel_clk0\0shadow_byte_clk0\0shadow_pixel_clk0";

clocks = <0x36a 0x06 0x36a 0x09 0x36b 0x20 0x36b 0x23 0x36a 0x03 0x36a 0x08 0x36a 0x11 0x36a 0x15>;

qcom,dsi-display-list = <0x53f 0x540 0x541 0x542 0x543 0x544 0x545 0x546 0x547 0x548 0x549 0x54a 0x54b 0x54c 0x54d 0x54e 0x54f 0x550 0x551 0x552 0x553 0x554 0x555 0x556 0x557 0x557 0x558 0x559 0x55a 0x55b>;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

ibb-supply = <0x2f0>;

qcom,dsi-phy = <0x374 0x375>;

compatible = "qcom,dsi-display";

vddio-supply = <0x408>;

pinctrl-1 = <0x3c7>;

lab-supply = <0x2ef>;

phandle = <0x55f>;

qcom,dsi-ctrl = <0x372 0x373>;

qcom,platform-te-gpio = <0x174 0x0a 0x00>;

};

qcom,msm-sec-auxpcm {

qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;

qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;

qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;

qcom,msm-auxpcm-interface = "secondary";

qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;

qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;

qcom,msm-cpudai-afe-clk-ver = <0x02>;

qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;

compatible = "qcom,msm-auxpcm-dev";

qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;

phandle = <0x272>;

qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;

};

qcom,dsi-display@21 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x535>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_g7b_42_02_0b_video_display";

phandle = <0x554>;

};

funnel@6943000 {

arm,primecell-periphid = <0x3b908>;

qcom,proxy-regs = "vddcx\0vdd";

vddcx-supply = <0x1c5>;

clock-names = "apb_pclk\0gpu_apb_clk";

reg-names = "funnel-base";

qcom,proxy-clks = "gpu_apb_clk";

clocks = <0x19 0x00 0x2b 0x08>;

coresight-name = "coresight-funnel-gfx";

vdd-supply = <0x24e>;

compatible = "arm,primecell";

status = "disabled";

reg = <0x6943000 0x1000>;

regulator-names = "vddcx\0vdd";

phandle = <0x455>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x24f>;

phandle = <0x234>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x250>;

phandle = <0x251>;

};

};

};

};

tpdm@6850000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-pimem";

compatible = "arm,primecell";

reg = <0x6850000 0x1000>;

phandle = <0x45b>;

port {

endpoint {

remote-endpoint = <0x256>;

phandle = <0x239>;

};

};

};

qcom,gdsc@ad0b004 {

qcom,poll-cfg-gdscr;

clock-names = "ahb_clk";

clocks = <0x27 0x0e>;

regulator-name = "ife_1_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0xad0b004 0x04>;

phandle = <0x1b8>;

};

msm_cdc_pinctrl_pri {

pinctrl-names = "aud_active\0aud_sleep";

pinctrl-0 = <0x514 0x515 0x516 0x517>;

compatible = "qcom,msm-cdc-pinctrl";

pinctrl-1 = <0x518 0x519 0x51a 0x51b>;

phandle = <0x513>;

};

cti@7900000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-apss_cti2";

compatible = "arm,primecell";

reg = <0x7900000 0x1000>;

phandle = <0x460>;

};

spi@0x890000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x17e>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

interrupts = <0x00 0x25d 0x00>;

clocks = <0x27 0x4c 0x27 0x67 0x27 0x68>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x168>;

spi-max-frequency = <0x2faf080>;

dma-names = "tx\0rx";

compatible = "qcom,spi-geni";

pinctrl-1 = <0x17f>;

status = "disabled";

reg = <0x890000 0x4000>;

phandle = <0x357>;

dmas = <0x165 0x00 0x04 0x01 0x40 0x00 0x165 0x01 0x04 0x01 0x40 0x00>;

};

i2c@0xa80000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x184>;

clock-names = "se-clk\0m-ahb\0s-ahb";

interrupts = <0x00 0x161 0x00>;

clocks = <0x27 0x57 0x27 0x69 0x27 0x6a>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x182>;

dma-names = "tx\0rx";

compatible = "qcom,i2c-geni";

pinctrl-1 = <0x185>;

status = "disabled";

reg = <0xa80000 0x4000>;

phandle = <0x35a>;

dmas = <0x183 0x00 0x00 0x03 0x40 0x00 0x183 0x01 0x00 0x03 0x40 0x00>;

};

qcom,mdss_rotator@ae00000 {

power-domains = <0x1a6>;

qcom,mdss-rot-mode = <0x01>;

rot-vdd-supply = <0xcb>;

qcom,mdss-rot-safe-lut = <0xffff 0xffff>;

clock-names = "gcc_iface\0gcc_bus\0iface_clk\0rot_clk";

reg-names = "mdp_phys\0rot_vbif_phys";

qcom,msm-bus,name = "mdss_rotator";

interrupts = <0x02 0x00>;

clocks = <0x27 0x1c 0x27 0x20 0x2a 0x01 0x2a 0x22>;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x03>;

interrupt-parent = <0x1a6>;

qcom,mdss-rot-vbif-memtype = <0x03 0x03>;

qcom,mdss-sbuf-headroom = <0x14>;

qcom,mdss-rot-qos-cpu-dma-latency = <0x4b>;

qcom,mdss-highest-bank-bit = <0x01>;

qcom,mdss-rot-vbif-qos-setting = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>;

compatible = "qcom,sde_rotator";

qcom,mdss-rot-cdp-setting = <0x01 0x01>;

qcom,mdss-rot-danger-lut = <0x00 0x00>;

qcom,mdss-default-ot-rd-limit = <0x20>;

qcom,supply-names = "rot-vdd";

qcom,mdss-rot-qos-lut = <0x00 0x00 0x00 0x00>;

qcom,mdss-default-ot-wr-limit = <0x20>;

reg = <0xae00000 0xac000 0xaeb8000 0x3000>;

#list-cells = <0x01>;

phandle = <0x36e>;

qcom,mdss-rot-qos-cpu-mask = <0x0f>;

qcom,msm-bus,vectors-KBps = <0x19 0x200 0x00 0x00 0x19 0x200 0x00 0x61a800 0x19 0x200 0x00 0x61a800>;

cache-slices = <0x1a7 0x04>;

cache-slice-names = "rotator";

qcom,smmu_rot_unsec_cb {

iommus = <0x30 0x1020 0x00>;

compatible = "qcom,smmu_sde_rot_unsec";

phandle = <0x370>;

};

qcom,rot-reg-bus {

qcom,msm-bus,name = "mdss_rot_reg";

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

phandle = <0x36f>;

qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00>;

};

qcom,smmu_rot_sec_cb {

iommus = <0x30 0x1021 0x00>;

compatible = "qcom,smmu_sde_rot_sec";

phandle = <0x371>;

};

};

qcom,msm-dai-q6-meta-mi2s-prim {

qcom,msm-dai-q6-meta-mi2s-dev-id = <0x1300>;

qcom,msm-mi2s-rx-lines = <0xff 0x0f 0x03 0x03>;

qcom,msm-mi2s-member-id = <0x00 0x01 0x02 0x03>;

qcom,msm-mi2s-num-members = <0x04>;

compatible = "qcom,msm-dai-q6-meta-mi2s";

phandle = <0x493>;

};

maxim_ds28e16 {

label = "max_ds28e16";

compatible = "maxim,ds28e16";

maxim,version = <0x01>;

status = "ok";

phandle = <0x5b2>;

};

cti@6017000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti7";

compatible = "arm,primecell";

reg = <0x6017000 0x1000>;

phandle = <0x47c>;

};

qcom,cpu6-llcc-ddr-lat {

qcom,src-dst-ports = <0x81 0x200>;

governor = "performance";

compatible = "qcom,devbw";

phandle = <0xc4>;

qcom,active-only;

operating-points-v2 = <0xbe>;

};

cti@6b21000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-aop-m3";

compatible = "arm,primecell";

reg = <0x6b21000 0x1000>;

phandle = <0x473>;

};

qcom,dsi-display@11 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x52d>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_rm69298_truly_amoled_vid_display";

phandle = <0x54a>;

};

qcom,msm-dai-mi2s {

compatible = "qcom,msm-dai-mi2s";

phandle = <0x491>;

qcom,msm-dai-q6-mi2s-prim {

qcom,msm-dai-q6-mi2s-dev-id = <0x00>;

qcom,msm-mi2s-rx-lines = <0x01>;

qcom,msm-mi2s-tx-lines = <0x02>;

compatible = "qcom,msm-dai-q6-mi2s";

phandle = <0x26c>;

};

qcom,msm-dai-q6-mi2s-quin {

qcom,msm-dai-q6-mi2s-dev-id = <0x04>;

qcom,msm-mi2s-rx-lines = <0x01>;

qcom,msm-mi2s-tx-lines = <0x02>;

compatible = "qcom,msm-dai-q6-mi2s";

phandle = <0x270>;

};

qcom,msm-dai-q6-mi2s-senary {

qcom,msm-dai-q6-mi2s-dev-id = <0x06>;

qcom,msm-mi2s-rx-lines = <0x00>;

qcom,msm-mi2s-tx-lines = <0x03>;

compatible = "qcom,msm-dai-q6-mi2s";

phandle = <0x492>;

};

qcom,msm-dai-q6-mi2s-quat {

qcom,msm-dai-q6-mi2s-dev-id = <0x03>;

qcom,msm-mi2s-rx-lines = <0x01>;

qcom,msm-mi2s-tx-lines = <0x02>;

compatible = "qcom,msm-dai-q6-mi2s";

phandle = <0x26f>;

};

qcom,msm-dai-q6-mi2s-tert {

qcom,msm-dai-q6-mi2s-dev-id = <0x02>;

qcom,msm-mi2s-rx-lines = <0x00>;

qcom,msm-mi2s-tx-lines = <0x03>;

compatible = "qcom,msm-dai-q6-mi2s";

phandle = <0x26e>;

};

qcom,msm-dai-q6-mi2s-sec {

qcom,msm-dai-q6-mi2s-dev-id = <0x01>;

qcom,msm-mi2s-rx-lines = <0x01>;

qcom,msm-mi2s-tx-lines = <0x00>;

compatible = "qcom,msm-dai-q6-mi2s";

phandle = <0x26d>;

};

};

gpio_keys {

pinctrl-names = "default";

pinctrl-0 = <0x561>;

label = "gpio-keys";

compatible = "gpio-keys";

vol_up {

linux,can-disable;

label = "volume_up";

linux,input-type = <0x01>;

gpio-key,wakeup;

linux,code = <0x73>;

debounce-interval = <0x0f>;

gpios = <0x2ec 0x02 0x01>;

};

};

modem_etm0 {

qcom,inst-id = <0x02>;

coresight-name = "coresight-modem-etm0";

compatible = "qcom,coresight-remote-etm";

port {

endpoint {

remote-endpoint = <0x1f1>;

phandle = <0x1e5>;

};

};

};

qcom,lpm-levels {

#address-cells = <0x01>;

#size-cells = <0x00>;

compatible = "qcom,lpm-levels";

qcom,pm-cluster@0 {

qcom,psci-mode-mask = <0xfff>;

#address-cells = <0x01>;

qcom,clstr-tmr-add = <0x3e8>;

#size-cells = <0x00>;

label = "L3";

qcom,psci-mode-shift = <0x04>;

reg = <0x00>;

qcom,pm-cluster-level@3 {

qcom,exit-latency-us = <0x19a2>;

qcom,psci-mode = <0xc24>;

qcom,is-reset;

label = "llcc-off";

qcom,notify-rpm;

qcom,min-child-idx = <0x02>;

qcom,min-residency-us = <0x2662>;

reg = <0x03>;

qcom,entry-latency-us = <0xcbf>;

};

qcom,pm-cpu@1 {

qcom,psci-mode-mask = <0x0f>;

qcom,tmr-add = <0x64>;

#address-cells = <0x01>;

qcom,cpu = <0x17 0x18>;

#size-cells = <0x00>;

qcom,psci-mode-shift = <0x00>;

qcom,ref-premature-cnt = <0x03>;

qcom,ref-stddev = <0x64>;

qcom,disable-ipi-prediction;

qcom,pm-cpu-level@2 {

qcom,exit-latency-us = <0x73e>;

qcom,is-reset;

qcom,psci-cpu-mode = <0x04>;

label = "rail-pc";

qcom,use-broadcast-timer;

qcom,min-residency-us = <0x15b3>;

reg = <0x02>;

qcom,entry-latency-us = <0x20e>;

};

qcom,pm-cpu-level@0 {

qcom,exit-latency-us = <0x42>;

qcom,psci-cpu-mode = <0x01>;

label = "wfi";

qcom,min-residency-us = <0x79>;

reg = <0x00>;

qcom,entry-latency-us = <0x37>;

};

qcom,pm-cpu-level@1 {

qcom,exit-latency-us = <0x4dc>;

qcom,is-reset;

qcom,psci-cpu-mode = <0x03>;

label = "pc";

qcom,use-broadcast-timer;

qcom,min-residency-us = <0x89f>;

reg = <0x01>;

qcom,entry-latency-us = <0x20b>;

};

};

qcom,pm-cluster-level@1 {

qcom,exit-latency-us = <0xbe8>;

qcom,psci-mode = <0x04>;

qcom,is-reset;

label = "l3-pc";

qcom,min-child-idx = <0x02>;

qcom,min-residency-us = <0x17e6>;

reg = <0x01>;

qcom,entry-latency-us = <0xac0>;

};

qcom,pm-cluster-level@2 {

qcom,exit-latency-us = <0x11d2>;

qcom,psci-mode = <0x224>;

qcom,is-reset;

label = "cx-off";

qcom,notify-rpm;

qcom,min-child-idx = <0x02>;

qcom,min-residency-us = <0x2113>;

reg = <0x02>;

qcom,entry-latency-us = <0xe36>;

};

qcom,pm-cpu@0 {

qcom,psci-mode-mask = <0x0f>;

qcom,tmr-add = <0x3e8>;

#address-cells = <0x01>;

qcom,cpu = <0x11 0x12 0x13 0x14 0x15 0x16>;

#size-cells = <0x00>;

qcom,psci-mode-shift = <0x00>;

qcom,ref-premature-cnt = <0x01>;

qcom,ref-stddev = <0x1f4>;

qcom,disable-ipi-prediction;

qcom,pm-cpu-level@2 {

qcom,exit-latency-us = <0x393>;

qcom,is-reset;

qcom,psci-cpu-mode = <0x04>;

label = "rail-pc";

qcom,use-broadcast-timer;

qcom,min-residency-us = <0xfa1>;

reg = <0x02>;

qcom,entry-latency-us = <0x2be>;

};

qcom,pm-cpu-level@0 {

qcom,exit-latency-us = <0x3c>;

qcom,psci-cpu-mode = <0x01>;

label = "wfi";

qcom,min-residency-us = <0x79>;

reg = <0x00>;

qcom,entry-latency-us = <0x3d>;

};

qcom,pm-cpu-level@1 {

qcom,exit-latency-us = <0x385>;

qcom,is-reset;

qcom,psci-cpu-mode = <0x03>;

label = "pc";

qcom,use-broadcast-timer;

qcom,min-residency-us = <0x6ee>;

reg = <0x01>;

qcom,entry-latency-us = <0x225>;

};

};

qcom,pm-cluster-level@0 {

qcom,exit-latency-us = <0x258>;

qcom,psci-mode = <0x01>;

label = "l3-wfi";

qcom,min-residency-us = <0x4ec>;

reg = <0x00>;

qcom,entry-latency-us = <0x294>;

};

};

};

fingerprint_fortsense {

fs,gpio-irq = <0x174 0x39 0x00>;

fs,gpio-reset = <0x174 0x3a 0x00>;

compatible = "fs,fingerprint";

status = "ok";

fs_vdd-supply = <0x411>;

};

qcom,msm_fastrpc {

qcom,fastrpc-adsp-audio-pdr;

qcom,rpc-latency-us = <0x263>;

compatible = "qcom,msm-fastrpc-compute";

qcom,fastrpc-adsp-sensors-pdr;

qcom,adsp-remoteheap-vmid = <0x16 0x25>;

qcom,msm_fastrpc_compute_cb3 {

iommus = <0x30 0x1423 0x00 0x30 0x1443 0x00>;

dma-coherent;

label = "cdsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb1 {

iommus = <0x30 0x1421 0x00 0x30 0x1441 0x00>;

dma-coherent;

label = "cdsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb15 {

iommus = <0x30 0x1b28 0x00>;

dma-coherent;

shared-cb = <0x03>;

label = "adsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb13 {

iommus = <0x30 0x1b26 0x00>;

dma-coherent;

label = "adsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb6 {

iommus = <0x30 0x1406 0x60>;

dma-coherent;

label = "cdsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb11 {

iommus = <0x30 0x1b24 0x00>;

dma-coherent;

label = "adsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb4 {

iommus = <0x30 0x1424 0x00 0x30 0x1444 0x00>;

dma-coherent;

label = "cdsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb2 {

iommus = <0x30 0x1422 0x00 0x30 0x1442 0x00>;

dma-coherent;

label = "cdsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb9 {

iommus = <0x30 0x1409 0x60>;

dma-coherent;

qcom,secure-context-bank;

label = "cdsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb14 {

iommus = <0x30 0x1b27 0x00>;

dma-coherent;

label = "adsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb12 {

iommus = <0x30 0x1b25 0x00>;

dma-coherent;

label = "adsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb5 {

iommus = <0x30 0x1425 0x00 0x30 0x1445 0x00>;

dma-coherent;

label = "cdsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

qcom,msm_fastrpc_compute_cb10 {

iommus = <0x30 0x1b23 0x00>;

dma-coherent;

label = "adsprpc-smd";

compatible = "qcom,msm-fastrpc-compute-cb";

};

};

qcom,camera-flash@0 {

cell-index = <0x00>;

torch-source = <0x2f6>;

switch-source = <0x2fb>;

compatible = "qcom,camera-flash";

status = "ok";

reg = <0x00 0x00>;

phandle = <0x57e>;

flash-source = <0x2f3>;

};

ddr-bw-opp-table {

compatible = "operating-points-v2";

phandle = <0xbe>;

opp-1017 {

opp-hz = <0x00 0xf27>;

};

opp-300 {

opp-hz = <0x00 0x478>;

};

opp-451 {

opp-hz = <0x00 0x6b8>;

};

opp-1353 {

opp-hz = <0x00 0x1429>;

};

opp-1804 {

opp-hz = <0x00 0x1ae1>;

};

opp-768 {

opp-hz = <0x00 0xb71>;

};

opp-200 {

opp-hz = <0x00 0x2fa>;

};

opp-681 {

opp-hz = <0x00 0xa25>;

};

opp-1555 {

opp-hz = <0x00 0x172b>;

};

opp-547 {

opp-hz = <0x00 0x826>;

};

};

qcom,gpubw {

qcom,src-dst-ports = <0x1a 0x200>;

governor = "bw_vbif";

compatible = "qcom,devbw";

phandle = <0x2a4>;

operating-points-v2 = <0x2a3>;

};

replicator@604a000 {

arm,primecell-periphid = <0x3b909>;

clock-names = "apb_pclk";

reg-names = "replicator-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-replicator-qdss1";

compatible = "arm,primecell";

reg = <0x604a000 0x1000>;

phandle = <0x41e>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x01>;

endpoint {

remote-endpoint = <0x1d3>;

phandle = <0x1f9>;

};

};

port@1 {

reg = <0x01>;

endpoint {

slave-mode;

remote-endpoint = <0x1d4>;

phandle = <0x1d1>;

};

};

};

};

cti@6014000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti4";

compatible = "arm,primecell";

reg = <0x6014000 0x1000>;

phandle = <0x479>;

};

rx_npl_clk {

qcom,codec-ext-clk-src = <0x06>;

#clock-cells = <0x01>;

compatible = "qcom,audio-ref-clk";

phandle = <0x4e4>;

qcom,codec-lpass-clk-id = <0x30f>;

qcom,codec-lpass-ext-clk-freq = <0x1588800>;

};

tpdm@69d0000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-qm";

compatible = "arm,primecell";

reg = <0x69d0000 0x1000>;

phandle = <0x45a>;

port {

endpoint {

remote-endpoint = <0x255>;

phandle = <0x238>;

};

};

};

rpmh-regulator-ldoa16 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa16";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l16 {

regulator-max-microvolt = <0x2d6900>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x1b7740>;

regulator-min-microvolt = <0x1b7740>;

regulator-name = "pm6150_l16";

qcom,set = <0x03>;

phandle = <0x40b>;

};

};

ipa_smmu_ap {

iommus = <0x30 0x520 0x00>;

qcom,smmu-s1-bypass;

qcom,additional-mapping = <0x146a8000 0x146a8000 0x2000>;

qcom,iova-mapping = <0x20000000 0x40000000>;

compatible = "qcom,ipa-smmu-ap-cb";

phandle = <0x31c>;

};

etm@7340000 {

arm,primecell-periphid = <0xbb95d>;

clock-names = "apb_pclk";

clocks = <0x19 0x00>;

cpu = <0x14>;

qcom,tupwr-disable;

coresight-name = "coresight-etm3";

compatible = "arm,primecell";

reg = <0x7340000 0x1000>;

phandle = <0x43f>;

port {

endpoint {

remote-endpoint = <0x220>;

phandle = <0x218>;

};

};

};

qcom,battery-data {

qcom,batt-id-range-pct = <0x0f>;

phandle = <0x58e>;

qcom,04890898_xiaomi_K6_SWBN53_5020mah_FG {

qcom,max-voltage-uv = <0x43e6d0>;

mi,six-pin-battery;

qcom,battery-type = "K6_sunwoda_5020mah";

qcom,jeita-fcc-ranges = <0x00 0x32 0xef420 0x33 0x64 0x258960 0x65 0x96 0x347d80 0x97 0x1e0 0x5b8d80 0x1e1 0x258 0x258960>;

qcom,nom-batt-capacity-mah = <0x139c>;

mi,step-chg-hysteresis = <0x1388>;

mi,use-bq-pump;

qcom,qg-batt-profile-ver = <0x64>;

qcom,fastchg-current-ma = <0x1770>;

qcom,jeita-fv-ranges = <0x00 0x32 0x43e6d0 0x33 0x64 0x43e6d0 0x65 0x96 0x43e6d0 0x97 0x1e0 0x4434f0 0x1e1 0x258 0x3e8fa0>;

qcom,ffc-max-voltage-uv = <0x4434f0>;

qcom,step-chg-ranges = <0x2dcaa8 0x40d990 0x5b8d80 0x40d991 0x426030 0x4ac4a0 0x426031 0x43e6d0 0x4ac4a0 0x43e6d1 0x440de0 0x3b8260 0x440de1 0x4434f0 0x3b8260>;

qcom,battery-therm-kohm = <0x64>;

qcom,batt-id-kohm = <0x64>;

qcom,battery-beta = <0x109a>;

qcom,fg-cc-cv-threshold-uv = <0x43bfc0>;

qcom,pc-temp-z2-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x2b8b 0x283a 0x2a3d 0x28a3 0x281a 0x2a9d 0x2a1c 0x2a52 0x290d 0x28dc 0x29ea 0x2a32 0x2a59 0x2955 0x28b8 0x2991 0x2a18 0x2a4e 0x2970 0x289b 0x295b 0x29f9 0x2a1f 0x2957 0x2892 0x2932 0x29cc 0x29eb 0x292d 0x2883 0x2910 0x299d 0x29b6 0x290c 0x2879 0x28f3 0x297c 0x2984 0x28ed 0x2868 0x28e4 0x2960 0x295f 0x28d5 0x2859 0x28de 0x2954 0x2940 0x28c4 0x2855 0x28da 0x2955 0x2935 0x28b6 0x2852 0x28dc 0x2957 0x294b 0x28aa 0x2838 0x28ed 0x2960 0x296c 0x28a0 0x27d9 0x2905 0x298d 0x297e 0x2895 0x27a0 0x2924 0x29bc 0x298a 0x287c 0x27a4 0x294e 0x29d3 0x2998 0x2866 0x27ac 0x2976 0x29e6 0x29ad 0x2858 0x27b8 0x299f 0x29f9 0x29c5 0x2836 0x27d1 0x29c2 0x2a13 0x29da 0x2830 0x27ed 0x29db 0x2a24 0x29ed 0x2848 0x280a 0x29ef 0x2a24 0x2a06 0x2871 0x2828 0x29f8 0x2a20 0x2a3a 0x28dd 0x284b 0x29e9 0x2a18 0x2a6d 0x299a 0x2871 0x29cc 0x29f9 0x2a62 0x29d2 0x2895 0x29c0 0x29d9 0x2a1b 0x295b 0x28b0 0x29bd 0x29e1 0x29f4 0x28e9 0x28cc 0x29bb 0x2a10 0x2a44 0x2942 0x28fb 0x29c0 0x2a38 0x2aaf 0x2a21 0x293b 0x29d2 0x2a4f 0x2ab9 0x2a60 0x294c 0x29e3 0x2a5f 0x2a9a 0x29d2 0x28b4 0x29f0 0x2a5d 0x2a74 0x2936 0x2802 0x29fb 0x2a47 0x2a3a 0x28f6 0x27cc 0x2a05 0x2a35 0x2a03 0x28ca 0x27a7 0x2a0d 0x2a32 0x29fd 0x28b4 0x27a3 0x2a16 0x2a30 0x2a09 0x28c1 0x27d2 0x2a22 0x2a32 0x2a1b 0x28df 0x2818 0x2a31 0x2a41 0x2a44 0x292b 0x285e 0x2a44 0x2a59 0x2a7f 0x29af 0x28ae 0x2a65 0x2a7b 0x2aba 0x2a02 0x28eb 0x2a8d 0x2aa9 0x2aff 0x2a40 0x2914 0x2ab4 0x2acb 0x2b25 0x2a6e 0x2943 0x2ada 0x2adc 0x2b2a 0x2a8a 0x29b1 0x2b24 0x2af6 0x2b2e 0x2a9b 0x2a24 0x2b9c 0x2b36 0x2b3a 0x2a91 0x2a38 0x2afb 0x2c81 0x2b74 0x2a1b 0x29be 0x2a46 0x2ce2 0x2b8c 0x297a 0x28e7 0x2a12 0x2d0e 0x2b57 0x2974 0x28d4 0x2a0c 0x2cff 0x2b49 0x2975 0x28f4 0x2a17 0x2d65 0x2b7d 0x2a06 0x298c 0x29d5 0x2df3 0x2bbb 0x29c7 0x2938 0x29ba 0x2e30 0x2b50 0x28ac 0x2810 0x290f 0x2da6 0x2ab5 0x285b 0x27cf 0x289e 0x2cf8 0x2a64 0x2812 0x27a2 0x27c5 0x2bd5 0x2a13 0x27f2 0x274e 0x27c5 0x2bd5 0x2a13 0x27f2 0x274e 0x27c5 0x2bd5 0x2a13 0x27f2 0x274e>;

};

qcom,pc-temp-z6-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x3c94 0x3a90 0x394b 0x38dc 0x38b6 0x3c90 0x3ad3 0x396b 0x38f4 0x38ce 0x3c84 0x3ad0 0x397c 0x3902 0x38dc 0x3c6f 0x3ab3 0x397a 0x3906 0x38e3 0x3c3e 0x3a95 0x396e 0x3902 0x38e1 0x3c06 0x3a79 0x3960 0x38fc 0x38dc 0x3bdc 0x3a5e 0x3955 0x38f6 0x38d8 0x3bb6 0x3a44 0x394b 0x38f1 0x38d4 0x3b94 0x3a2c 0x3940 0x38eb 0x38d0 0x3b75 0x3a17 0x3935 0x38e2 0x38ca 0x3b59 0x3a04 0x392b 0x38da 0x38c3 0x3b40 0x39f3 0x3921 0x38d3 0x38bd 0x3b2a 0x39e3 0x3917 0x38ce 0x38b9 0x3b15 0x39d3 0x3910 0x38c9 0x38b5 0x3aff 0x39c6 0x3909 0x38c4 0x38b1 0x3aea 0x39be 0x3903 0x38c0 0x38ad 0x3adb 0x39b7 0x38fd 0x38bb 0x38a9 0x3acf 0x39b3 0x38f8 0x38b6 0x38a5 0x3ac7 0x39b1 0x38f5 0x38b2 0x38a1 0x3ac4 0x39af 0x38f2 0x38af 0x389e 0x3ac2 0x39bc 0x38f1 0x38ad 0x389b 0x3ac1 0x39e0 0x390b 0x38b9 0x38a2 0x3ad5 0x39f1 0x392d 0x38d8 0x38bf 0x3af7 0x39f2 0x3931 0x38e3 0x38cc 0x3b01 0x39f3 0x3930 0x38e2 0x38cb 0x3afd 0x39f1 0x392d 0x38e0 0x38c8 0x3af8 0x39ea 0x3929 0x38de 0x38c6 0x3af1 0x39e2 0x3925 0x38dc 0x38c5 0x3ae6 0x39dd 0x3921 0x38d9 0x38c3 0x3adc 0x39d8 0x391d 0x38d5 0x38be 0x3ad4 0x39d4 0x3919 0x38d0 0x38b7 0x3acd 0x39d0 0x3914 0x38ca 0x38b2 0x3ac7 0x39cd 0x3910 0x38c4 0x38ad 0x3ac3 0x39ca 0x390c 0x38bf 0x38a8 0x3abf 0x39c7 0x3909 0x38bc 0x38a4 0x3abc 0x39c6 0x3906 0x38ba 0x38a1 0x3ab9 0x39c4 0x3903 0x38b7 0x389f 0x3ab8 0x39c4 0x3901 0x38b4 0x389d 0x3aba 0x39c5 0x3901 0x38b4 0x389d 0x3abc 0x39c7 0x3906 0x38b8 0x38a0 0x3abc 0x39c7 0x3908 0x38bc 0x38a4 0x3aba 0x39c3 0x3906 0x38bd 0x38a7 0x3ab7 0x39be 0x3903 0x38be 0x38aa 0x3aaf 0x39b9 0x3900 0x38bd 0x38ab 0x3a77 0x399d 0x38f0 0x38b4 0x38a3 0x3a6c 0x398b 0x38df 0x38a2 0x3890 0x3a68 0x3984 0x38da 0x389c 0x388b 0x3a66 0x3981 0x38d1 0x3894 0x3880 0x3a69 0x397f 0x38cb 0x3889 0x3877 0x3a6e 0x3987 0x38d1 0x3896 0x3887 0x3a7a 0x3991 0x38e0 0x38a6 0x3898 0x3a83 0x3996 0x38e3 0x38aa 0x389c 0x3a8d 0x399e 0x38e7 0x38ae 0x38a0 0x3aa0 0x39a8 0x38ec 0x38b0 0x38a3 0x3aa0 0x39a8 0x38ec 0x38b0 0x38a3 0x3aa0 0x39a8 0x38ec 0x38b0 0x38a3>;

};

qcom,pc-temp-y2-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x2965 0x2a0e 0x2c86 0x2d4c 0x2bc0 0x2b78 0x2986 0x2a33 0x2c7b 0x2d10 0x2b86 0x2b44 0x29d5 0x2a77 0x2c6c 0x2cd0 0x2b4a 0x2b06 0x2a33 0x2ac3 0x2c5a 0x2c93 0x2b10 0x2ac7 0x2a83 0x2b02 0x2c46 0x2c5e 0x2add 0x2a91 0x2aa7 0x2b1d 0x2c2f 0x2c39 0x2ab5 0x2a6c 0x2aa7 0x2b1b 0x2c10 0x2c20 0x2a93 0x2a56 0x2aa7 0x2b16 0x2bf2 0x2c0d 0x2a78 0x2a44 0x2aa7 0x2b17 0x2be9 0x2bfa 0x2a6b 0x2a32 0x2aa9 0x2b24 0x2be5 0x2be5 0x2a64 0x2a19 0x2aad 0x2b31 0x2be4 0x2bda 0x2a5f 0x2a08 0x2acd 0x2b30 0x2bf2 0x2be1 0x2a5b 0x2a04 0x2b0e 0x2b28 0x2c12 0x2bf1 0x2a56 0x2a03 0x2b44 0x2b36 0x2c33 0x2c02 0x2a64 0x2a04 0x2b84 0x2b92 0x2c57 0x2c1b 0x2ab1 0x2a06 0x2bb3 0x2bec 0x2c82 0x2c3d 0x2aed 0x2a08 0x2bc0 0x2c1b 0x2cc7 0x2c72 0x2af9 0x2a0a 0x2bc9 0x2c51 0x2d11 0x2cbc 0x2b02 0x2a0d 0x2bd5 0x2c62 0x2d2d 0x2d19 0x2b37 0x2a34 0x2bee 0x2c6b 0x2d38 0x2da2 0x2bfe 0x2aee 0x2c0a 0x2c76 0x2d3d 0x2ded 0x2c7d 0x2b68 0x2c1f 0x2c82 0x2d42 0x2db6 0x2c4e 0x2b5e 0x2c31 0x2c93 0x2d4e 0x2d5f 0x2bfe 0x2b4e 0x2c35 0x2ca3 0x2d5a 0x2d53 0x2be5 0x2b4b 0x2c17 0x2cbb 0x2d72 0x2d77 0x2be3 0x2b4e 0x2be6 0x2cce 0x2d89 0x2d9f 0x2bf0 0x2b52 0x2b43 0x2cb8 0x2d98 0x2dbd 0x2c2e 0x2b69 0x29df 0x2c76 0x2da7 0x2ddb 0x2c85 0x2b97 0x291f 0x2c51 0x2dbe 0x2dfb 0x2ca2 0x2bd5 0x27cd 0x2c58 0x2de8 0x2e20 0x2c9e 0x2c42 0x266a 0x2c5d 0x2e03 0x2e40 0x2ca7 0x2c9f 0x2627 0x2c31 0x2ded 0x2e58 0x2d02 0x2cd8 0x260d 0x2bc0 0x2dc0 0x2e6a 0x2d79 0x2d04 0x25f9 0x2b30 0x2dac 0x2e72 0x2d97 0x2d1a 0x25e7 0x29e6 0x2da6 0x2e76 0x2d9b 0x2d38 0x25da 0x2886 0x2d9e 0x2e73 0x2d99 0x2d3c 0x25d3 0x27c1 0x2d79 0x2e44 0x2d31 0x2cef 0x25cf 0x2692 0x2d2d 0x2df6 0x2c93 0x2c77 0x25cb 0x25f4 0x2cde 0x2dd0 0x2c79 0x2c2f 0x25c8 0x25dd 0x2c89 0x2dbd 0x2c95 0x2bfe 0x25c6 0x25d0 0x2c27 0x2daa 0x2ca7 0x2bdb 0x25c4 0x25c9 0x2bac 0x2d90 0x2c8b 0x2bc8 0x25c3 0x25c5 0x2b21 0x2d6b 0x2c4e 0x2bb1 0x25c2 0x25c2 0x2a95 0x2d03 0x2ba6 0x2b3c 0x25c0 0x25c0 0x2a0f 0x2c8c 0x2afd 0x2a95 0x25bf 0x25bf 0x2a1a 0x2c48 0x2ae7 0x2a50 0x25be 0x25bf 0x2a13 0x2c37 0x2b28 0x2a58 0x25be 0x25be 0x29f2 0x2c32 0x2b4e 0x2a87 0x25bd 0x25bd 0x29e3 0x2c38 0x2b88 0x2a79 0x25bb 0x25bc 0x29d4 0x2c55 0x2afb 0x2a52 0x25ba 0x25bb 0x298e 0x2c23 0x2a7c 0x2a0b 0x25b8 0x25ba 0x28fb 0x2bb6 0x2a49 0x29d6 0x25b5 0x25b9 0x26dc 0x2b46 0x2a1d 0x297e 0x25b2 0x25b7 0x25fa 0x2ae6 0x299b 0x28ce 0x25b2 0x25b7 0x25fa 0x2ae6 0x299b 0x28ce 0x25b2 0x25b7 0x25fa 0x2ae6 0x299b 0x28ce>;

};

qcom,pc-temp-y6-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x15e9 0x1508 0x1416 0x1399 0x137a 0x1373 0x15f5 0x151c 0x1421 0x139a 0x137b 0x1374 0x1604 0x1530 0x142b 0x139b 0x137c 0x1376 0x1613 0x1542 0x1433 0x139d 0x137d 0x1377 0x161e 0x154e 0x1438 0x139e 0x137e 0x1378 0x1623 0x1553 0x143a 0x139f 0x1380 0x1379 0x1622 0x1550 0x1438 0x13a0 0x1381 0x137a 0x161f 0x154a 0x1434 0x13a1 0x1382 0x137a 0x161c 0x1543 0x1431 0x13a2 0x1383 0x137b 0x1617 0x153c 0x142f 0x13a4 0x1384 0x137c 0x1614 0x1538 0x142e 0x13a5 0x1385 0x137d 0x1616 0x1539 0x142f 0x13a7 0x1387 0x137e 0x1619 0x153c 0x142f 0x13a9 0x1388 0x137f 0x161d 0x153f 0x1430 0x13ac 0x138a 0x1381 0x1623 0x1542 0x1433 0x13af 0x138c 0x1382 0x1627 0x1544 0x1436 0x13b3 0x138f 0x1384 0x1615 0x1543 0x143e 0x13b7 0x1392 0x1386 0x15ea 0x153f 0x1447 0x13bc 0x1394 0x1389 0x15d5 0x1537 0x1447 0x13c1 0x1399 0x138d 0x15cd 0x1518 0x1437 0x13c8 0x13a1 0x1394 0x15c6 0x14f7 0x1424 0x13cc 0x13a6 0x1398 0x15be 0x14e4 0x1414 0x13bd 0x139a 0x138e 0x15b5 0x14d5 0x1405 0x13a5 0x1387 0x137f 0x15ad 0x14ca 0x13fe 0x139c 0x1380 0x1379 0x15a4 0x14c3 0x13fa 0x1399 0x137e 0x1377 0x159e 0x14bc 0x13f8 0x1398 0x137d 0x1376 0x159d 0x14b2 0x13f8 0x1399 0x137d 0x1377 0x15a0 0x14a8 0x13f8 0x139b 0x137f 0x1378 0x15a4 0x14a4 0x13f9 0x139d 0x1381 0x1379 0x15b4 0x14a9 0x13fa 0x139f 0x1383 0x137b 0x15cd 0x14b2 0x13fa 0x13a1 0x1386 0x137e 0x15e5 0x14c0 0x13f9 0x13a3 0x1389 0x1381 0x1600 0x14db 0x13f8 0x13a5 0x138c 0x1384 0x161f 0x14fa 0x13f7 0x13a7 0x138d 0x1384 0x1641 0x151e 0x13f7 0x13a9 0x138c 0x1384 0x1667 0x1547 0x13f7 0x13aa 0x138b 0x1383 0x168e 0x1574 0x13fc 0x13a5 0x1387 0x1380 0x16b9 0x15a5 0x1407 0x139e 0x1381 0x137c 0x16e2 0x15d7 0x1411 0x139b 0x1381 0x137b 0x1707 0x1609 0x141c 0x139b 0x1381 0x137d 0x172c 0x163c 0x1428 0x139b 0x1381 0x137e 0x1755 0x166f 0x1437 0x139c 0x1382 0x137e 0x1780 0x16a4 0x144a 0x139e 0x1382 0x137c 0x17b6 0x16e3 0x1461 0x139d 0x137d 0x1375 0x17fc 0x1731 0x147f 0x13a0 0x137e 0x1376 0x184c 0x1784 0x147e 0x13a6 0x138b 0x1388 0x1842 0x175f 0x1485 0x13ae 0x1396 0x1394 0x1880 0x1799 0x149f 0x13b8 0x13a0 0x139d 0x18cf 0x17d6 0x14bb 0x13c3 0x13a6 0x139d 0x1931 0x1812 0x14cd 0x13be 0x138c 0x1382 0x19b6 0x1850 0x14d6 0x13aa 0x1386 0x1380 0x1a95 0x1896 0x14fb 0x13af 0x138a 0x1383 0x1cfb 0x1923 0x155a 0x13b7 0x1390 0x1388 0x2413 0x1a28 0x1602 0x13c9 0x139f 0x139e 0x2413 0x1a28 0x1602 0x13c9 0x139f 0x139e 0x2413 0x1a28 0x1602 0x13c9 0x139f 0x139e>;

};

qcom,pc-temp-z3-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x4c4f 0x4bcc 0x4b8c 0x4b7d 0x4b7d 0x4c97 0x4c14 0x4bbb 0x4b91 0x4b87 0x4cd1 0x4c3b 0x4bde 0x4bae 0x4b9e 0x4cf6 0x4c56 0x4bef 0x4bc2 0x4bb4 0x4d11 0x4c6a 0x4bfa 0x4bcc 0x4bbd 0x4d25 0x4c7b 0x4c01 0x4bd4 0x4bc3 0x4d34 0x4c86 0x4c08 0x4bdc 0x4bca 0x4d41 0x4c87 0x4c0d 0x4be4 0x4bd1 0x4d48 0x4c86 0x4c0d 0x4be7 0x4bd4 0x4d4d 0x4c84 0x4c0c 0x4be4 0x4bd3 0x4d51 0x4c81 0x4c0a 0x4bde 0x4bcf 0x4d50 0x4c7b 0x4c03 0x4bd8 0x4bcb 0x4d4b 0x4c74 0x4bfa 0x4bd0 0x4bc4 0x4d44 0x4c69 0x4bf1 0x4bc9 0x4bbe 0x4d3b 0x4c5f 0x4be8 0x4bc4 0x4bba 0x4d2f 0x4c5a 0x4be1 0x4bc0 0x4bb6 0x4d25 0x4c56 0x4bdd 0x4bbc 0x4bb3 0x4d1d 0x4c51 0x4bda 0x4bb8 0x4bb0 0x4d15 0x4c48 0x4bd7 0x4bb4 0x4bad 0x4d10 0x4c42 0x4bd3 0x4baf 0x4ba8 0x4d0c 0x4c50 0x4bd1 0x4bac 0x4ba4 0x4d0a 0x4c79 0x4be0 0x4bae 0x4ba3 0x4d19 0x4c89 0x4bf4 0x4bb3 0x4ba4 0x4d32 0x4c76 0x4bf0 0x4bb4 0x4ba4 0x4d38 0x4c5a 0x4bd3 0x4ba3 0x4b9f 0x4d2d 0x4c4a 0x4bc3 0x4b93 0x4b99 0x4d1e 0x4c3d 0x4bc3 0x4ba6 0x4ba6 0x4d12 0x4c37 0x4bc3 0x4bd4 0x4bd0 0x4d05 0x4c3e 0x4bca 0x4be4 0x4be2 0x4cfe 0x4c4a 0x4be4 0x4be2 0x4bd8 0x4cfb 0x4c54 0x4bf4 0x4bde 0x4bca 0x4cf9 0x4c5e 0x4bf5 0x4bd7 0x4bc1 0x4cf7 0x4c64 0x4bf5 0x4bcb 0x4bba 0x4cf5 0x4c61 0x4bf2 0x4bc0 0x4bb2 0x4cf2 0x4c5c 0x4beb 0x4bb8 0x4ba9 0x4cee 0x4c58 0x4be4 0x4bb1 0x4ba1 0x4ce9 0x4c54 0x4bdc 0x4bad 0x4b9e 0x4ce3 0x4c50 0x4bd5 0x4ba9 0x4b9b 0x4cdb 0x4c4b 0x4bd3 0x4ba7 0x4b9a 0x4cd1 0x4c44 0x4bd1 0x4ba6 0x4b99 0x4cc7 0x4c3d 0x4bd1 0x4ba5 0x4b99 0x4cbc 0x4c38 0x4bd2 0x4bae 0x4ba3 0x4cab 0x4c31 0x4bd2 0x4bb9 0x4bb3 0x4c8c 0x4c26 0x4bcd 0x4bb7 0x4bb4 0x4b90 0x4bf6 0x4bb8 0x4bab 0x4ba9 0x4b69 0x4be0 0x4bae 0x4b90 0x4b90 0x4b62 0x4bd2 0x4bad 0x4b8e 0x4b8c 0x4b5f 0x4bd2 0x4ba2 0x4b8c 0x4b82 0x4b5e 0x4ba7 0x4b9b 0x4b7d 0x4b7a 0x4b5d 0x4bb7 0x4b95 0x4b8d 0x4b86 0x4b61 0x4b6a 0x4b9c 0x4ba4 0x4ba0 0x4b61 0x4b65 0x4b92 0x4ba7 0x4ba0 0x4b63 0x4b61 0x4b8f 0x4ba9 0x4ba2 0x4b68 0x4b5a 0x4b90 0x4b9d 0x4ba0 0x4b68 0x4b5a 0x4b90 0x4b9d 0x4ba0 0x4b68 0x4b5a 0x4b90 0x4b9d 0x4ba0>;

};

qcom,pc-temp-v1-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0xac5b 0xacdf 0xad2f 0xad4b 0xad54 0xab9b 0xac29 0xac88 0xacac 0xacb6 0xaad0 0xab6b 0xabd6 0xabfe 0xac0a 0xa9fb 0xaaa6 0xab1a 0xab46 0xab53 0xa919 0xa9d6 0xaa54 0xaa83 0xaa93 0xa82f 0xa8f2 0xa981 0xa9b4 0xa9c7 0xa743 0xa804 0xa89c 0xa8d6 0xa8ed 0xa652 0xa715 0xa7ad 0xa7e8 0xa804 0xa563 0xa621 0xa6bc 0xa6f7 0xa713 0xa476 0xa52f 0xa5c6 0xa602 0xa620 0xa38e 0xa441 0xa4d2 0xa50d 0xa52a 0xa2ab 0xa355 0xa3df 0xa41b 0xa438 0xa1cd 0xa26f 0xa2f1 0xa32c 0xa348 0xa0f6 0xa18d 0xa208 0xa241 0xa25c 0xa029 0xa0b1 0xa125 0xa159 0xa174 0x9f63 0x9fe1 0xa049 0xa077 0xa091 0x9e98 0x9f17 0x9f73 0x9f9c 0x9fb5 0x9dc2 0x9e50 0x9ea3 0x9ec9 0x9edf 0x9cf1 0x9d94 0x9dde 0x9dfe 0x9e11 0x9c36 0x9cca 0x9d26 0x9d42 0x9d52 0x9b90 0x9bc7 0x9c55 0x9c7e 0x9c92 0x9ada 0x9a96 0x9b33 0x9b84 0x9ba4 0x99e5 0x99a9 0x9a0b 0x9a63 0x9a88 0x98e1 0x9904 0x994c 0x9987 0x99a2 0x9836 0x987e 0x98c2 0x98ee 0x9904 0x97c9 0x980f 0x9846 0x986a 0x987e 0x9773 0x97b2 0x97d1 0x97e7 0x97f6 0x9728 0x975b 0x9764 0x976b 0x9773 0x96e9 0x9705 0x96fc 0x96fa 0x96fe 0x96ad 0x96b2 0x9697 0x9693 0x9699 0x9671 0x9664 0x963b 0x9635 0x963c 0x9638 0x961a 0x95e9 0x95e1 0x95e4 0x9604 0x95d7 0x959e 0x9595 0x9591 0x95d3 0x959f 0x955a 0x954c 0x9541 0x95a6 0x956e 0x951c 0x9505 0x94f4 0x957c 0x953d 0x94e3 0x94bf 0x94a8 0x9555 0x9511 0x94af 0x947e 0x945b 0x9521 0x94df 0x947b 0x943d 0x940d 0x94d0 0x9492 0x9431 0x93eb 0x93b2 0x9469 0x942a 0x93c9 0x937f 0x9343 0x93f5 0x93b5 0x9353 0x9305 0x92c5 0x9369 0x932d 0x92d2 0x927d 0x9235 0x92cb 0x9295 0x9245 0x91ea 0x919a 0x921c 0x91e1 0x91a0 0x914b 0x90fa 0x91be 0x915f 0x9121 0x90d5 0x9092 0x9167 0x9116 0x90d6 0x9097 0x9056 0x9146 0x9103 0x90c1 0x9082 0x9041 0x9128 0x90e9 0x90b2 0x9071 0x9032 0x9103 0x90cb 0x9094 0x904e 0x9001 0x9098 0x9041 0x9015 0x8f96 0x8f2b 0x8f45 0x8ecb 0x8ead 0x8e1e 0x8dab 0x8d62 0x8cdb 0x8cce 0x8c32 0x8bbd 0x8afe 0x8a5c 0x8a64 0x89b7 0x893d 0x87c0 0x86ec 0x8717 0x8651 0x85cc 0x829f 0x8159 0x81e8 0x80d9 0x8038 0x7530 0x7530 0x7530 0x7530 0x7530>;

};

qcom,pc-temp-y3-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x347f 0x3468 0x340e 0x33e7 0x33e0 0x33df 0x3486 0x346b 0x3412 0x33e9 0x33e1 0x33df 0x3492 0x346e 0x3416 0x33eb 0x33e1 0x33e0 0x34a1 0x3471 0x3419 0x33ec 0x33e2 0x33e0 0x34ad 0x3473 0x341c 0x33ee 0x33e2 0x33e1 0x34b3 0x3475 0x341f 0x33ef 0x33e3 0x33e2 0x34b4 0x3476 0x3420 0x33ef 0x33e4 0x33e3 0x34b5 0x3477 0x3421 0x33f0 0x33e5 0x33e4 0x34b4 0x3478 0x3423 0x33f1 0x33e7 0x33e5 0x34af 0x3478 0x3425 0x33f2 0x33e8 0x33e5 0x34ab 0x3478 0x3426 0x33f2 0x33e8 0x33e5 0x34b7 0x347f 0x3426 0x33f2 0x33e9 0x33e6 0x34cd 0x348b 0x3425 0x33f2 0x33e9 0x33e7 0x34cf 0x348a 0x3424 0x33f3 0x33ea 0x33e8 0x34a2 0x3462 0x3422 0x33f7 0x33ee 0x33e9 0x347d 0x3441 0x341f 0x33f9 0x33f1 0x33ea 0x3480 0x3449 0x341b 0x33f8 0x33f0 0x33eb 0x3488 0x345d 0x3417 0x33f7 0x33ee 0x33ec 0x348a 0x3463 0x3415 0x33f8 0x33ee 0x33ed 0x347f 0x3456 0x3414 0x33fa 0x33f2 0x33ef 0x3471 0x3447 0x3413 0x33fc 0x33f4 0x33f0 0x3467 0x343f 0x3410 0x33f8 0x33ef 0x33eb 0x345f 0x3439 0x340b 0x33f0 0x33e6 0x33e4 0x3457 0x3432 0x3409 0x33ec 0x33e2 0x33e2 0x3450 0x342c 0x3407 0x33e9 0x33e1 0x33e1 0x3449 0x3426 0x3406 0x33e8 0x33e0 0x33e1 0x3439 0x3422 0x3405 0x33e9 0x33e1 0x33e0 0x3420 0x341f 0x3405 0x33ea 0x33e1 0x33e0 0x3417 0x341b 0x3404 0x33ea 0x33e1 0x33e1 0x341f 0x3410 0x3402 0x33e9 0x33e0 0x33e2 0x342b 0x3408 0x3401 0x33e9 0x33df 0x33e2 0x3439 0x3409 0x3401 0x33e9 0x33e0 0x33e2 0x344a 0x3413 0x3400 0x33e9 0x33e1 0x33e1 0x345e 0x341c 0x3400 0x33e9 0x33e1 0x33e2 0x3474 0x3424 0x3400 0x33ea 0x33e2 0x33e2 0x348e 0x342d 0x3400 0x33ea 0x33e2 0x33e3 0x34ad 0x343c 0x3401 0x33ea 0x33e1 0x33e2 0x34d2 0x3453 0x3405 0x33e9 0x33e0 0x33e0 0x34f8 0x346e 0x3408 0x33e9 0x33e0 0x33e0 0x351f 0x348e 0x340a 0x33e9 0x33e2 0x33e1 0x3546 0x34b5 0x340c 0x33e9 0x33e4 0x33e2 0x3570 0x34e1 0x340e 0x33e9 0x33e4 0x33e2 0x359c 0x3514 0x3410 0x33e9 0x33e4 0x33e2 0x35d3 0x3551 0x3415 0x33e9 0x33e2 0x33df 0x3618 0x359c 0x341c 0x33ec 0x33e3 0x33e0 0x3663 0x35e2 0x3421 0x33f1 0x33eb 0x33e8 0x364a 0x35b3 0x3425 0x33f6 0x33ee 0x33ea 0x368c 0x35e7 0x342f 0x33fa 0x33f0 0x33eb 0x36e2 0x3618 0x343b 0x33fd 0x33f0 0x33ea 0x374b 0x3654 0x3442 0x33fc 0x33e9 0x33e5 0x37e1 0x368d 0x3444 0x33f5 0x33e8 0x33e5 0x38e3 0x36d9 0x344c 0x33f9 0x33ea 0x33e8 0x3b92 0x3780 0x3465 0x33fc 0x33f1 0x33ee 0x4378 0x38bc 0x34d2 0x3407 0x33f9 0x33f7 0x4378 0x38bc 0x34d2 0x3407 0x33f9 0x33f7 0x4378 0x38bc 0x34d2 0x3407 0x33f9 0x33f7>;

};

qcom,pc-temp-z4-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x3cb2 0x3b84 0x3a97 0x3a22 0x39ea 0x3c9d 0x3bcc 0x3a96 0x3a2a 0x39ff 0x3c7c 0x3bb9 0x3a94 0x3a21 0x39fb 0x3c4c 0x3b66 0x3a86 0x3a15 0x39f4 0x3bed 0x3b17 0x3a5b 0x3a00 0x39e6 0x3b87 0x3ad9 0x3a32 0x39e6 0x39cf 0x3b3c 0x3aa1 0x3a13 0x39cf 0x39bb 0x3afa 0x3a74 0x39f8 0x39b8 0x39a9 0x3ac2 0x3a4f 0x39e1 0x39a6 0x3999 0x3a91 0x3a2f 0x39cc 0x3995 0x398a 0x3a67 0x3a13 0x39bb 0x3989 0x397f 0x3a46 0x39fb 0x39ad 0x3985 0x397b 0x3a2b 0x39e6 0x39a2 0x3983 0x397a 0x3a14 0x39d3 0x399c 0x3980 0x3979 0x39fd 0x39c5 0x3999 0x397c 0x3975 0x39e9 0x39ba 0x3995 0x3977 0x3971 0x39df 0x39b3 0x398e 0x3973 0x396c 0x39dc 0x39b1 0x3986 0x396e 0x3967 0x39d9 0x39b4 0x3983 0x396a 0x3963 0x39d8 0x39bb 0x3981 0x3968 0x3962 0x39d6 0x39c9 0x3981 0x3967 0x3961 0x39d6 0x39e7 0x39a4 0x397d 0x3972 0x39f0 0x3a04 0x39da 0x39bb 0x39b3 0x3a1f 0x3a26 0x39fa 0x39e0 0x39d3 0x3a31 0x3a3f 0x3a12 0x39f1 0x39d3 0x3a35 0x3a41 0x3a1b 0x39fa 0x39d2 0x3a36 0x3a3d 0x3a14 0x39e1 0x39be 0x3a33 0x3a36 0x3a05 0x39a1 0x3984 0x3a25 0x3a21 0x39ee 0x3981 0x396a 0x3a15 0x3a03 0x39c6 0x3977 0x3969 0x3a05 0x39ea 0x39a8 0x3971 0x3968 0x39f4 0x39d3 0x3998 0x396e 0x3966 0x39e5 0x39c3 0x398d 0x396c 0x3961 0x39d9 0x39bc 0x3989 0x396b 0x395f 0x39cf 0x39b7 0x3988 0x396d 0x3961 0x39c6 0x39b4 0x3987 0x396e 0x3962 0x39be 0x39b1 0x3988 0x396e 0x3963 0x39b8 0x39b0 0x3989 0x396e 0x3963 0x39b5 0x39b1 0x398c 0x3970 0x3965 0x39b2 0x39b4 0x3995 0x397b 0x396f 0x39ab 0x39b4 0x399a 0x3984 0x3977 0x399e 0x39a8 0x3992 0x397a 0x396f 0x3992 0x3999 0x3987 0x396d 0x3962 0x3988 0x398e 0x3984 0x396d 0x3963 0x3a10 0x3970 0x3973 0x3966 0x395e 0x3a26 0x395d 0x3957 0x395c 0x394f 0x3a25 0x395d 0x394b 0x3950 0x3946 0x3a1f 0x3952 0x3942 0x3940 0x393b 0x3a1d 0x397a 0x393d 0x393b 0x3930 0x3a1c 0x396c 0x394d 0x3943 0x3947 0x3a25 0x39d7 0x3963 0x3946 0x3946 0x3a2b 0x39df 0x3970 0x3947 0x394a 0x3a2e 0x39e8 0x3976 0x3948 0x394a 0x3a36 0x39f2 0x3977 0x3954 0x394c 0x3a36 0x39f2 0x3977 0x3954 0x394c 0x3a36 0x39f2 0x3977 0x3954 0x394c>;

};

qcom,pc-temp-v2-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0xad4d 0xad39 0xad2f 0xad2a 0xad02 0xacee 0xac29 0xac30 0xac52 0xac5c 0xac31 0xac1e 0xab1e 0xab36 0xab7a 0xab8f 0xab61 0xab4f 0xaa31 0xaa50 0xaaa7 0xaac3 0xaa94 0xaa82 0xa963 0xa97e 0xa9dd 0xa9fa 0xa9c9 0xa9b8 0xa891 0xa8a8 0xa90a 0xa928 0xa8f7 0xa8e6 0xa7a8 0xa7b9 0xa821 0xa844 0xa814 0xa804 0xa6b4 0xa6bf 0xa72c 0xa754 0xa727 0xa719 0xa5bc 0xa5c2 0xa637 0xa663 0xa638 0xa62b 0xa4bc 0xa4bf 0xa53f 0xa56d 0xa543 0xa536 0xa3c2 0xa3c5 0xa449 0xa477 0xa450 0xa443 0xa2d9 0xa2e0 0xa356 0xa385 0xa35f 0xa352 0xa1fa 0xa206 0xa267 0xa294 0xa270 0xa265 0xa120 0xa12a 0xa17d 0xa1a9 0xa187 0xa17c 0xa051 0xa04b 0xa097 0xa0c4 0xa0a3 0xa098 0x9f6f 0x9f6f 0x9fba 0x9fe4 0x9fc5 0x9fba 0x9e3d 0x9e9c 0x9eee 0x9f0b 0x9eed 0x9ee4 0x9cd7 0x9dcb 0x9e25 0x9e37 0x9e1a 0x9e13 0x9bb7 0x9cde 0x9d41 0x9d69 0x9d50 0x9d4b 0x9adb 0x9bbe 0x9c39 0x9ca4 0x9c92 0x9c8e 0x9a10 0x9a9f 0x9b33 0x9bce 0x9bc4 0x9bc2 0x993f 0x99a8 0x9a3f 0x9ac1 0x9abb 0x9abd 0x9871 0x98c7 0x9958 0x99a6 0x99a2 0x99a7 0x97b1 0x9800 0x9896 0x98d1 0x98cf 0x98d6 0x96f9 0x9751 0x97f0 0x9828 0x982a 0x9832 0x9654 0x96b1 0x975c 0x9796 0x9799 0x97a1 0x95c7 0x960e 0x96d5 0x9714 0x9718 0x971d 0x9549 0x9570 0x965a 0x96a1 0x96a4 0x96a6 0x94ed 0x94f8 0x95e9 0x9632 0x9638 0x9639 0x94ae 0x949d 0x9581 0x95c9 0x95d3 0x95d5 0x9479 0x9457 0x9520 0x9568 0x9577 0x9578 0x9443 0x9428 0x94c2 0x950f 0x9524 0x9523 0x940f 0x9405 0x946b 0x94be 0x94d6 0x94d3 0x93d7 0x93e2 0x941d 0x9473 0x9481 0x9479 0x939d 0x93bd 0x93d6 0x942e 0x9429 0x9417 0x935f 0x9394 0x9398 0x93e5 0x93c9 0x93af 0x931d 0x935f 0x9365 0x938a 0x935e 0x9339 0x92d7 0x931b 0x9338 0x9328 0x92ed 0x92bc 0x9288 0x92cc 0x92f9 0x92ca 0x9286 0x9250 0x9226 0x926d 0x92a0 0x9270 0x9228 0x91f2 0x91bd 0x9200 0x9236 0x920e 0x91c4 0x918e 0x915b 0x9188 0x91b6 0x919c 0x9150 0x9117 0x90fb 0x9102 0x9128 0x9120 0x90d5 0x9099 0x90a4 0x9092 0x90a2 0x9096 0x904e 0x900e 0x9053 0x902f 0x903c 0x903e 0x9001 0x8fc6 0x8ffb 0x8fca 0x8ffd 0x9017 0x8fe6 0x8fad 0x8fc7 0x8f8c 0x8fde 0x9009 0x8fda 0x8fa0 0x8f86 0x8f3e 0x8fb7 0x8ff3 0x8fc2 0x8f86 0x8f26 0x8ed5 0x8f6b 0x8fc2 0x8f81 0x8f2f 0x8e81 0x8e37 0x8eb3 0x8f17 0x8e6e 0x8df4 0x8d72 0x8d4a 0x8d40 0x8d79 0x8cae 0x8c2a 0x8bcc 0x8bbd 0x8b15 0x8b5c 0x8a70 0x89e0 0x8968 0x8972 0x881e 0x8892 0x877e 0x86d5 0x85e5 0x8632 0x840c 0x84b2 0x8344 0x828c 0x8024 0x80e2 0x7ce0 0x7e6b 0x7cce 0x7b70 0x6ea4 0x7318 0x6820 0x7079 0x69aa 0x6832>;

};

qcom,fcc1-temp-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-data = <0x1295 0x131b 0x1385 0x13bf 0x13d6>;

};

qcom,pc-temp-y4-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x4160 0x4123 0x40b5 0x406a 0x4050 0x404d 0x418a 0x415d 0x40d4 0x406b 0x4051 0x404f 0x41d7 0x41b9 0x40f8 0x406c 0x4054 0x4051 0x422e 0x421b 0x4119 0x406e 0x4056 0x4052 0x4277 0x426b 0x4131 0x4070 0x4058 0x4053 0x429b 0x428e 0x413b 0x4072 0x4059 0x4054 0x42a0 0x428a 0x4137 0x4075 0x405a 0x4053 0x42a2 0x4280 0x412e 0x4078 0x405b 0x4053 0x42a5 0x4275 0x4128 0x407b 0x405c 0x4053 0x42a9 0x4267 0x4124 0x407f 0x405e 0x4056 0x42ac 0x425d 0x4122 0x4084 0x4061 0x4058 0x429c 0x4257 0x4126 0x408b 0x4065 0x405a 0x427f 0x4253 0x412f 0x4093 0x406a 0x405c 0x4283 0x425f 0x413a 0x4099 0x406d 0x405f 0x42f3 0x42c9 0x414c 0x409e 0x406e 0x4063 0x4350 0x4321 0x4163 0x40a4 0x406f 0x4067 0x42f9 0x430c 0x418b 0x40b4 0x4078 0x406c 0x4232 0x42cb 0x41b6 0x40ca 0x4087 0x4072 0x41e0 0x4286 0x41b7 0x40dc 0x4097 0x407e 0x41d0 0x4232 0x4180 0x40f0 0x40ad 0x4092 0x41c2 0x41e2 0x4142 0x40f9 0x40b8 0x409e 0x41ab 0x41ac 0x4111 0x40d0 0x409e 0x408a 0x418a 0x4181 0x40e7 0x408d 0x4073 0x4068 0x4168 0x415f 0x40d2 0x4079 0x4063 0x405b 0x413b 0x4146 0x40c6 0x4072 0x405e 0x4056 0x411c 0x412d 0x40c0 0x4070 0x405c 0x4053 0x4126 0x4103 0x40be 0x4072 0x405e 0x4055 0x4148 0x40cd 0x40bd 0x4078 0x4062 0x4058 0x4160 0x40ba 0x40bd 0x407d 0x4068 0x405c 0x416e 0x40c5 0x40bf 0x4084 0x4072 0x4062 0x417b 0x40d6 0x40c0 0x408b 0x407d 0x4068 0x4186 0x40e3 0x40bb 0x4092 0x4086 0x4072 0x4190 0x40ef 0x40b0 0x4099 0x408e 0x407d 0x419b 0x4101 0x40a9 0x409d 0x408e 0x407f 0x41a8 0x4125 0x40a2 0x40a1 0x408b 0x407c 0x41b3 0x414d 0x409e 0x40a3 0x4086 0x4078 0x41b8 0x4167 0x40a5 0x4093 0x407a 0x406f 0x41bb 0x4183 0x40b5 0x4078 0x406a 0x4064 0x41bc 0x418f 0x40c3 0x406f 0x4063 0x4062 0x41b8 0x4190 0x40cd 0x406c 0x405f 0x4064 0x41b3 0x418f 0x40d7 0x406b 0x405d 0x4065 0x41b3 0x418a 0x40e2 0x406f 0x405c 0x4063 0x41b7 0x417b 0x40ec 0x4073 0x405c 0x405f 0x41c0 0x417c 0x40f1 0x406b 0x404e 0x404a 0x41d9 0x418b 0x40fc 0x406b 0x404e 0x4049 0x41f6 0x41b6 0x40f2 0x4072 0x4066 0x4074 0x41d3 0x41a7 0x40fc 0x407f 0x4084 0x4097 0x41e4 0x41cf 0x411d 0x4098 0x40a5 0x40b5 0x41f5 0x4205 0x4143 0x40b8 0x40b6 0x40b9 0x4200 0x4224 0x415a 0x40a9 0x406f 0x4063 0x4200 0x4240 0x414b 0x4072 0x405b 0x405b 0x41f7 0x423f 0x4148 0x4076 0x405f 0x405b 0x4234 0x4238 0x4185 0x4081 0x405f 0x405b 0x44ae 0x4236 0x41de 0x409e 0x407b 0x4089 0x44ae 0x4236 0x41de 0x409e 0x407b 0x4089 0x44ae 0x4236 0x41de 0x409e 0x407b 0x4089>;

};

qcom,pc-temp-z1-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x3024 0x2dea 0x2bc0 0x2ab7 0x2a5d 0x302e 0x2e0c 0x2be0 0x2ade 0x2a85 0x3034 0x2e16 0x2bf3 0x2aeb 0x2a92 0x3037 0x2e15 0x2bf6 0x2aee 0x2a98 0x3038 0x2e10 0x2bf2 0x2aed 0x2a98 0x3037 0x2e04 0x2bed 0x2aea 0x2a96 0x3035 0x2df4 0x2be6 0x2ae6 0x2a94 0x3033 0x2de7 0x2bdc 0x2ae2 0x2a91 0x302e 0x2dda 0x2bd4 0x2adf 0x2a8f 0x300e 0x2dce 0x2bcb 0x2add 0x2a8f 0x2fe4 0x2dc1 0x2bc6 0x2adb 0x2a8f 0x2fd3 0x2db4 0x2bc3 0x2ada 0x2a8e 0x2fcc 0x2db0 0x2bc1 0x2ad9 0x2a8e 0x2fc5 0x2dae 0x2bc0 0x2ad8 0x2a8d 0x2fb7 0x2dad 0x2bbf 0x2ad8 0x2a8d 0x2fa6 0x2dab 0x2bbf 0x2ad8 0x2a8e 0x2f99 0x2da9 0x2bbe 0x2ad9 0x2a8e 0x2f8b 0x2da7 0x2bbe 0x2ad9 0x2a90 0x2f80 0x2da0 0x2bbe 0x2ad9 0x2a91 0x2f7e 0x2d99 0x2bbf 0x2ada 0x2a92 0x2f7e 0x2d99 0x2bbf 0x2ada 0x2a93 0x2f7f 0x2d9b 0x2bbf 0x2adb 0x2a94 0x2f80 0x2d9d 0x2bc0 0x2adb 0x2a94 0x2f84 0x2da3 0x2bc1 0x2adc 0x2a95 0x2f86 0x2da9 0x2bc3 0x2add 0x2a97 0x2f84 0x2da9 0x2bc5 0x2adf 0x2a9a 0x2f84 0x2da7 0x2bc8 0x2ae2 0x2a9c 0x2f8b 0x2da5 0x2bcb 0x2ae5 0x2a9f 0x2f94 0x2da8 0x2bcf 0x2ae8 0x2aa2 0x2f9a 0x2dac 0x2bd3 0x2aeb 0x2aa4 0x2f9a 0x2dae 0x2bd7 0x2aef 0x2aa7 0x2f9a 0x2db0 0x2bdb 0x2af2 0x2aaa 0x2f9c 0x2db3 0x2bdf 0x2af5 0x2aae 0x2fa7 0x2db7 0x2be4 0x2af9 0x2ab2 0x2fb2 0x2dbc 0x2bea 0x2afe 0x2ab5 0x2fb7 0x2dc1 0x2bef 0x2b02 0x2ab9 0x2fb9 0x2dc5 0x2bf3 0x2b06 0x2abd 0x2fba 0x2dcb 0x2bf6 0x2b0a 0x2ac0 0x2fcb 0x2dd5 0x2bfb 0x2b0d 0x2ac4 0x2fe0 0x2de6 0x2c03 0x2b11 0x2ac7 0x2fe5 0x2df2 0x2c09 0x2b15 0x2ac9 0x2fea 0x2df9 0x2c0e 0x2b18 0x2acc 0x2ff3 0x2e04 0x2c12 0x2b1a 0x2ace 0x3009 0x2e1e 0x2c18 0x2b1d 0x2ad0 0x301e 0x2e1e 0x2c23 0x2b22 0x2ad3 0x300c 0x2e16 0x2c28 0x2b25 0x2ad5 0x3015 0x2e1c 0x2c28 0x2b25 0x2ad5 0x300e 0x2e18 0x2c26 0x2b26 0x2ad7 0x3004 0x2e12 0x2c28 0x2b28 0x2ad9 0x301b 0x2e17 0x2c34 0x2b2e 0x2add 0x302a 0x2e2b 0x2c39 0x2b32 0x2ae1 0x303f 0x2e3b 0x2c40 0x2b39 0x2ae7 0x311f 0x2e59 0x2c46 0x2b3f 0x2aed 0x3044 0x2e53 0x2c54 0x2b4b 0x2af8 0x3044 0x2e53 0x2c54 0x2b4b 0x2af8 0x3044 0x2e53 0x2c54 0x2b4b 0x2af8>;

};

qcom,pc-temp-z5-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x3352 0x32b9 0x34bc 0x3633 0x380e 0x376c 0x398a 0x3bb1 0x3a34 0x3a7e 0x3ad8 0x3d06 0x4090 0x40b8 0x413f 0x3d58 0x3f3c 0x428a 0x4579 0x47b9 0x3f17 0x414f 0x439c 0x479d 0x4ab6 0x40d7 0x4380 0x44bc 0x4970 0x4cfe 0x432d 0x4593 0x462a 0x4c9c 0x504a 0x4602 0x4773 0x47a7 0x513a 0x5542 0x4935 0x491e 0x4911 0x54b4 0x59e6 0x4d46 0x4af9 0x4a75 0x573a 0x5de3 0x51c6 0x4d43 0x4bf6 0x58db 0x6116 0x55f2 0x4fe4 0x4e1f 0x5842 0x6119 0x5a28 0x52d8 0x4fe4 0x55de 0x5e52 0x5e75 0x5652 0x4fca 0x5473 0x5c8d 0x6282 0x59c7 0x4eb6 0x556e 0x5d04 0x66a0 0x5d63 0x4e30 0x56e0 0x5e18 0x6c3a 0x60bf 0x5065 0x57e5 0x5ff5 0x76e2 0x6172 0x53cd 0x5a64 0x641c 0x802c 0x5f28 0x559f 0x5c65 0x6751 0x8152 0x5cfd 0x56a8 0x5e9e 0x6916 0x8070 0x7580 0x58ba 0x6093 0x6a3b 0x801a 0xb7b7 0x6cb5 0x6141 0x68a5 0x98ab 0xd2e7 0x8539 0x613f 0x60fc 0xc286 0xabdf 0x8086 0x5f37 0x57f2 0xccae 0x7914 0x5f36 0x4e44 0x4aed 0xb56f 0x6571 0x49e9 0x3e8e 0x400c 0x9a13 0x59ef 0x45f9 0x44a4 0x48d9 0x8c6e 0x55b9 0x43d9 0x5659 0x671e 0x8232 0x57fa 0x45a6 0x61a0 0x73c1 0x7e47 0x5d05 0x4f91 0x688b 0x6dd1 0x80f5 0x64ab 0x5a27 0x6c4d 0x6768 0x865c 0x736d 0x632f 0x6afd 0x675e 0x8c3c 0x80a1 0x6b8e 0x67b5 0x6925 0x93f8 0x8823 0x7197 0x665c 0x6977 0x9b89 0x8dd2 0x76c5 0x6808 0x67a8 0xa11e 0x910a 0x78f3 0x69a8 0x6617 0xa5df 0x9342 0x7721 0x69d7 0x6701 0xaa1b 0x9465 0x73bf 0x69ad 0x6945 0xae67 0x9218 0x70a8 0x677c 0x6918 0xb1e2 0x8c28 0x6caa 0x608a 0x5ff4 0xb357 0x88a3 0x6a9f 0x5ba2 0x5832 0xb37a 0x86c9 0x6ad4 0x64c8 0x67c7 0xb17b 0x8618 0x6b05 0x7092 0x7eda 0xa7c5 0x85b2 0x6621 0x6d0f 0x7f20 0x42b2 0x82a3 0x61ec 0x62bf 0x6ff9 0x349c 0x79d8 0x6524 0x4de4 0x51d8 0x3394 0x65d9 0x6b27 0x50dc 0x528a 0x3351 0x6cc9 0x65e9 0x5ad2 0x53ef 0x3334 0x566d 0x6585 0x54da 0x5b5a 0x336c 0x52f5 0x5425 0x6285 0x5eaa 0x33bc 0x3534 0x47d7 0x5bda 0x5f40 0x330a 0x33da 0x3fac 0x58ae 0x56d7 0x3298 0x3299 0x3c9d 0x5317 0x50a9 0x31f6 0x3125 0x3b54 0x42d6 0x459b 0x31f6 0x3125 0x3b54 0x42d6 0x459b 0x31f6 0x3125 0x3b54 0x42d6 0x459b>;

};

qcom,fcc2-temp-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-data = <0x1368 0x1367 0x138c 0x139a 0x139a 0x1397>;

};

qcom,pc-temp-y1-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x1768 0x15c5 0x14a8 0x1395 0x1300 0x12cd 0x175c 0x15c5 0x14b1 0x1395 0x12ff 0x12cd 0x174f 0x15c5 0x14b8 0x1394 0x12fe 0x12cc 0x1743 0x15c6 0x14bc 0x1392 0x12fd 0x12cc 0x1739 0x15c7 0x14be 0x1391 0x12fc 0x12cb 0x1735 0x15c8 0x14bf 0x138f 0x12fb 0x12ca 0x1737 0x15cb 0x14bc 0x138c 0x12fb 0x12ca 0x173a 0x15cf 0x14b7 0x138a 0x12fa 0x12c9 0x173d 0x15d0 0x14b3 0x1388 0x12f9 0x12c9 0x1742 0x15ca 0x14ae 0x1386 0x12f8 0x12c8 0x1746 0x15c5 0x14aa 0x1385 0x12f7 0x12c8 0x1745 0x15c5 0x14a7 0x1384 0x12f6 0x12c7 0x1742 0x15c6 0x14a4 0x1384 0x12f5 0x12c7 0x1742 0x15c5 0x14a4 0x1383 0x12f4 0x12c6 0x1748 0x15bf 0x14a4 0x1381 0x12f4 0x12c6 0x1751 0x15ba 0x14a5 0x1380 0x12f4 0x12c6 0x175b 0x15c4 0x14a4 0x1380 0x12f4 0x12c5 0x1766 0x15d7 0x14a3 0x1380 0x12f4 0x12c5 0x1769 0x15dd 0x14a3 0x1381 0x12f4 0x12c5 0x1764 0x15d2 0x14a5 0x1382 0x12f4 0x12c6 0x175f 0x15c9 0x14a7 0x1383 0x12f4 0x12c7 0x175b 0x15c9 0x14a5 0x1384 0x12f6 0x12c8 0x1750 0x15cb 0x14a2 0x1384 0x12f8 0x12c8 0x174c 0x15cb 0x14a2 0x1385 0x12f9 0x12c9 0x174c 0x15cd 0x14a6 0x1387 0x12f9 0x12cb 0x174a 0x15cf 0x14a9 0x138a 0x12fa 0x12cc 0x1746 0x15ce 0x14a8 0x138b 0x12fa 0x12cd 0x173e 0x15c9 0x14a5 0x138d 0x12fc 0x12cf 0x1739 0x15c4 0x14a6 0x138f 0x12fd 0x12d0 0x1735 0x15c5 0x14ac 0x1391 0x12ff 0x12d2 0x1731 0x15c7 0x14b0 0x1394 0x1301 0x12d4 0x172f 0x15c5 0x14b1 0x1395 0x1303 0x12d5 0x172e 0x15c0 0x14b0 0x1396 0x1304 0x12d6 0x172d 0x15be 0x14b1 0x1398 0x1306 0x12d7 0x1729 0x15c1 0x14b7 0x139a 0x1308 0x12d8 0x1724 0x15c4 0x14bb 0x139c 0x1309 0x12da 0x1721 0x15c1 0x14b9 0x139d 0x130a 0x12db 0x171c 0x15b8 0x14b4 0x139d 0x130b 0x12dc 0x1718 0x15b1 0x14b3 0x139e 0x130c 0x12dd 0x1711 0x15ac 0x14b5 0x13a1 0x130d 0x12df 0x170b 0x15a7 0x14b8 0x13a3 0x130e 0x12e0 0x170b 0x15a6 0x14bd 0x13a5 0x130f 0x12e1 0x170b 0x15a8 0x14c3 0x13a8 0x1312 0x12e3 0x1708 0x15aa 0x14cb 0x13ab 0x1314 0x12e5 0x1710 0x15ad 0x14cc 0x13b0 0x1318 0x12e7 0x175b 0x15bc 0x14d5 0x13b5 0x1318 0x12e8 0x173f 0x15c3 0x14dd 0x13b4 0x1318 0x12e8 0x1740 0x15cd 0x14d4 0x13b8 0x1318 0x12e8 0x1739 0x15d3 0x1569 0x13b2 0x1318 0x12e9 0x174d 0x15d4 0x14f9 0x13b2 0x1319 0x12e9 0x1751 0x15d6 0x14d8 0x13b8 0x131a 0x12eb 0x1745 0x15cf 0x14e6 0x13bc 0x131e 0x12ef 0x1739 0x15d1 0x14e2 0x13c3 0x1323 0x12f3 0x1777 0x15d9 0x14e4 0x13cd 0x132b 0x12fb 0x1777 0x15d9 0x14e4 0x13cd 0x132b 0x12fb 0x1777 0x15d9 0x14e4 0x13cd 0x132b 0x12fb>;

};

qcom,pc-temp-y5-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x30d6 0x3d28 0x48ec 0x4a0a 0x48c8 0x4c34 0x353f 0x3ef9 0x4846 0x481e 0x474e 0x4a58 0x3a8f 0x40c2 0x477f 0x4638 0x4506 0x4899 0x3fe4 0x426d 0x46b0 0x4457 0x4288 0x4718 0x4460 0x43e1 0x45f4 0x427c 0x4069 0x45f7 0x471f 0x4506 0x4564 0x40a7 0x3f42 0x4558 0x4873 0x45ff 0x44fd 0x3ebf 0x3ede 0x455e 0x494d 0x46bf 0x4497 0x3ced 0x3e88 0x4593 0x4940 0x46cd 0x440f 0x3b89 0x3e13 0x44df 0x47d6 0x4627 0x433f 0x3a6b 0x3d5d 0x41f0 0x46bf 0x45a7 0x4259 0x3951 0x3c7b 0x3f71 0x4b53 0x47ed 0x40ca 0x37d0 0x3b0e 0x3e71 0x5424 0x4c50 0x3ea2 0x3676 0x399d 0x3dbc 0x55ba 0x4c88 0x3cf8 0x366c 0x39d9 0x3d4e 0x4e47 0x43d4 0x3b63 0x3772 0x3c75 0x3d8f 0x4808 0x3c83 0x3a97 0x381d 0x3e29 0x3ddb 0x4d00 0x4491 0x3bad 0x3754 0x3bd5 0x3d2c 0x5812 0x5652 0x3e70 0x3618 0x382f 0x3c3b 0x5b8d 0x5bc3 0x429f 0x377c 0x385c 0x3cc9 0x58bc 0x5917 0x4aec 0x409c 0x3d75 0x3edf 0x55e9 0x56a4 0x5111 0x4839 0x423f 0x4171 0x5555 0x56ff 0x52a1 0x4afa 0x4504 0x4504 0x547c 0x5835 0x5395 0x4cb6 0x470f 0x488e 0x536e 0x58f5 0x5417 0x4c2a 0x46c2 0x4903 0x51a8 0x5966 0x5476 0x47d2 0x433d 0x47c8 0x4ef3 0x59ba 0x54c8 0x44f0 0x4041 0x461c 0x46c9 0x591d 0x5512 0x4645 0x3f8c 0x4327 0x3730 0x5681 0x5556 0x485e 0x3f7c 0x3fde 0x3102 0x52a9 0x55a0 0x486f 0x3f03 0x3f58 0x30f9 0x451b 0x5601 0x4688 0x3c8e 0x3fe0 0x311b 0x3803 0x5681 0x4546 0x3af5 0x404d 0x317c 0x37b3 0x58d9 0x45d4 0x3c65 0x4041 0x324d 0x3a48 0x5c9c 0x4736 0x3f65 0x4055 0x3310 0x3c1b 0x5cdd 0x498b 0x4244 0x4220 0x339c 0x3c25 0x5773 0x4e97 0x4567 0x487f 0x342f 0x3ba5 0x5240 0x5292 0x4842 0x4cb6 0x3530 0x3afe 0x5094 0x544e 0x4a62 0x4c8d 0x36b5 0x38f9 0x4f5e 0x556d 0x4c52 0x4c18 0x375e 0x37e1 0x4d54 0x5491 0x4ecc 0x4cec 0x3676 0x37d3 0x4961 0x4e97 0x5200 0x51c9 0x3505 0x37c7 0x454e 0x4927 0x54a7 0x5777 0x33fd 0x3782 0x41e2 0x46b3 0x56bf 0x5d77 0x3323 0x36ec 0x3f84 0x4524 0x57e4 0x615d 0x3309 0x36bb 0x3f62 0x4459 0x4d04 0x4ac0 0x3316 0x3689 0x3ecb 0x4367 0x4250 0x4207 0x3326 0x3514 0x4112 0x432d 0x45ac 0x4188 0x33f0 0x35e4 0x4197 0x4679 0x4584 0x3f8f 0x3482 0x36c1 0x4361 0x485d 0x4389 0x3e65 0x3590 0x3801 0x47f8 0x4947 0x441c 0x3d8e 0x362d 0x3c42 0x4c6e 0x4bab 0x428d 0x4194 0x36b1 0x3fa8 0x4b05 0x4bf6 0x423e 0x3fe5 0x35ec 0x3ce5 0x45c4 0x4d9a 0x407f 0x4001 0x3258 0x3722 0x387d 0x4cc1 0x4df6 0x47da 0x2a28 0x339f 0x3511 0x57ae 0x5fcc 0x66db 0x2a28 0x339f 0x3511 0x57ae 0x5fcc 0x66db 0x2a28 0x339f 0x3511 0x57ae 0x5fcc 0x66db>;

};

};

qcom,4890802_xiaomi_K6_NVT_5020mAH_PM7150 {

qcom,max-voltage-uv = <0x43e6d0>;

mi,six-pin-battery;

qcom,battery-type = "K6_nvt_5020mah";

qcom,jeita-fcc-ranges = <0x00 0x32 0xef420 0x33 0x64 0x258960 0x65 0x96 0x347d80 0x97 0x1e0 0x5b8d80 0x1e1 0x258 0x258960>;

qcom,nom-batt-capacity-mah = <0x139c>;

mi,step-chg-hysteresis = <0x1388>;

mi,use-bq-pump;

qcom,qg-batt-profile-ver = <0x64>;

qcom,fastchg-current-ma = <0x1770>;

qcom,jeita-fv-ranges = <0x00 0x32 0x43e6d0 0x33 0x64 0x43e6d0 0x65 0x96 0x43e6d0 0x97 0x1e0 0x4434f0 0x1e1 0x258 0x3e8fa0>;

qcom,ffc-max-voltage-uv = <0x4434f0>;

qcom,step-chg-ranges = <0x2dcaa8 0x40d990 0x5b8d80 0x40d991 0x426030 0x4ac4a0 0x426031 0x43e6d0 0x4ac4a0 0x43e6d1 0x440de0 0x3b8260 0x440de1 0x4434f0 0x3b8260>;

qcom,battery-therm-kohm = <0x64>;

qcom,batt-id-kohm = <0x64>;

qcom,battery-beta = <0x109a>;

qcom,fg-cc-cv-threshold-uv = <0x43bfc0>;

qcom,pc-temp-z2-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x282c 0x2a5f 0x2a22 0x2817 0x27b1 0x27f9 0x298b 0x28d6 0x2861 0x27a9 0x2830 0x2905 0x2912 0x285d 0x27aa 0x2858 0x28dd 0x2939 0x285b 0x27b3 0x284e 0x28ba 0x291e 0x284f 0x27b1 0x2838 0x2897 0x28e2 0x282c 0x279e 0x282f 0x2870 0x28b1 0x2810 0x2790 0x282e 0x2856 0x2885 0x27de 0x2779 0x282d 0x2849 0x286d 0x27b1 0x275e 0x2828 0x283e 0x286e 0x27ae 0x275c 0x281b 0x283d 0x2870 0x27a4 0x2760 0x280f 0x284b 0x2872 0x279c 0x2766 0x2806 0x2860 0x2874 0x279a 0x2771 0x27ff 0x2873 0x2878 0x2798 0x277c 0x27ff 0x2889 0x2886 0x279d 0x2786 0x2807 0x289e 0x289b 0x27ac 0x2799 0x2812 0x28b3 0x28a9 0x27b8 0x27a2 0x281e 0x28c7 0x28b4 0x27c3 0x27a7 0x282d 0x28da 0x28bf 0x27d0 0x27ac 0x283d 0x28ec 0x28c9 0x27dd 0x27b3 0x284e 0x28fc 0x28d5 0x27ef 0x27c2 0x285f 0x2911 0x290c 0x2829 0x27d6 0x2872 0x2923 0x2999 0x28fa 0x27ff 0x2885 0x2932 0x29d9 0x2983 0x281f 0x2897 0x2947 0x296a 0x290d 0x2828 0x28a4 0x294d 0x28ea 0x2853 0x282d 0x28b0 0x293c 0x28e0 0x2846 0x282b 0x28ba 0x292a 0x28e7 0x28a7 0x2813 0x28c5 0x2929 0x28f3 0x28de 0x27f1 0x28cd 0x292a 0x2927 0x28a0 0x27ad 0x28d0 0x292d 0x2957 0x283d 0x2766 0x28d3 0x2935 0x2948 0x2801 0x275e 0x28d6 0x2941 0x2918 0x27d0 0x276a 0x28dd 0x2949 0x2907 0x27c0 0x277a 0x28e6 0x2951 0x2915 0x27d6 0x2791 0x28eb 0x2958 0x292b 0x27fb 0x27b1 0x28ee 0x2960 0x293e 0x281e 0x27e2 0x28f3 0x2969 0x2955 0x2846 0x282a 0x28fe 0x2978 0x2975 0x286b 0x285e 0x290f 0x298d 0x29af 0x2893 0x2880 0x2920 0x299c 0x29d9 0x28b0 0x2894 0x2933 0x29a2 0x29ce 0x28ba 0x2895 0x294b 0x29a8 0x29b9 0x28c1 0x2891 0x296f 0x29b4 0x29b3 0x28d1 0x289b 0x2a82 0x2a2c 0x29cd 0x28d7 0x28a0 0x2ac3 0x2a65 0x29e8 0x28e8 0x2871 0x2a88 0x2a70 0x29d2 0x28d0 0x2865 0x29f6 0x2abb 0x29b4 0x28d2 0x2881 0x29c1 0x2b34 0x29ad 0x28e1 0x2894 0x2973 0x2ba5 0x29eb 0x2926 0x28f1 0x2801 0x2b9d 0x29e4 0x28f8 0x2889 0x2854 0x2b68 0x29ad 0x2879 0x27e6 0x288d 0x2aa8 0x299a 0x282d 0x27a5 0x27b9 0x295f 0x2959 0x27fb 0x2772 0x27b9 0x295f 0x2959 0x27fb 0x2772 0x27b9 0x295f 0x2959 0x27fb 0x2772>;

};

qcom,pc-temp-z6-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x3d0d 0x3ae6 0x3958 0x38fa 0x38af 0x3d90 0x3aef 0x39b2 0x390c 0x38e0 0x3d47 0x3aed 0x3999 0x3902 0x38db 0x3cea 0x3ac9 0x397a 0x38f2 0x38cf 0x3c96 0x3a85 0x3962 0x38e6 0x38c7 0x3c3f 0x3a54 0x394c 0x38dc 0x38c2 0x3bf6 0x3a2d 0x3939 0x38d3 0x38bc 0x3bb8 0x3a0d 0x392a 0x38cb 0x38b4 0x3b83 0x39f2 0x391d 0x38c4 0x38ad 0x3b56 0x39dc 0x3911 0x38be 0x38a9 0x3b2f 0x39c7 0x3907 0x38b9 0x38a7 0x3b0e 0x39b4 0x38ff 0x38b4 0x38a4 0x3af2 0x39a6 0x38fa 0x38b1 0x38a1 0x3ad9 0x399d 0x38f6 0x38ae 0x389f 0x3ac3 0x3997 0x38f1 0x38aa 0x389c 0x3aad 0x3992 0x38ed 0x38a7 0x3898 0x3a9d 0x398e 0x38ea 0x38a4 0x3895 0x3a95 0x398a 0x38e7 0x38a1 0x3892 0x3a90 0x3984 0x38e4 0x389e 0x388f 0x3a8a 0x397e 0x38e0 0x3899 0x388b 0x3a83 0x397c 0x38dd 0x3894 0x3885 0x3a7d 0x397f 0x38e7 0x3897 0x3887 0x3a7d 0x3985 0x390b 0x38b9 0x38a4 0x3a81 0x3998 0x391c 0x38d0 0x38ba 0x3a88 0x39bb 0x391c 0x38ce 0x38b8 0x3a9d 0x39c7 0x391a 0x38c9 0x38b3 0x3ab7 0x39c0 0x3917 0x38c6 0x38b0 0x3abd 0x39b6 0x3910 0x38c4 0x38ae 0x3abd 0x39b0 0x390b 0x38c1 0x38ab 0x3abd 0x39ab 0x390a 0x38bd 0x38a7 0x3ab9 0x39a7 0x3908 0x38b9 0x38a2 0x3ab1 0x39a5 0x3905 0x38b5 0x389e 0x3aab 0x39a3 0x3901 0x38af 0x3899 0x3aa8 0x39a2 0x38fe 0x38ab 0x3894 0x3aa4 0x39a0 0x38fc 0x38a7 0x388f 0x3aa1 0x399f 0x38fa 0x38a4 0x3889 0x3a9d 0x399d 0x38f8 0x38a2 0x3886 0x3a9b 0x399c 0x38f6 0x389f 0x3884 0x3a9c 0x399d 0x38f6 0x389f 0x3884 0x3a9d 0x399d 0x38f8 0x38a3 0x3889 0x3a9f 0x399e 0x38fa 0x38a7 0x388e 0x3aa4 0x399d 0x38f8 0x38a6 0x388e 0x3aa6 0x399b 0x38f3 0x38a3 0x388e 0x3aa8 0x399a 0x38f1 0x38a4 0x3892 0x3a94 0x398d 0x38ea 0x38a1 0x3890 0x3a8e 0x3983 0x38e0 0x3894 0x3880 0x3a8c 0x3980 0x38dc 0x3891 0x387d 0x3a88 0x397c 0x38d8 0x388b 0x3876 0x3a87 0x3978 0x38d1 0x3882 0x386d 0x3a89 0x3979 0x38cf 0x387d 0x3866 0x3a8c 0x397f 0x38d8 0x388c 0x3879 0x3a95 0x398b 0x38e2 0x3899 0x3888 0x3aaa 0x3995 0x38e6 0x389e 0x388d 0x3ac7 0x39ab 0x38ee 0x38a2 0x3891 0x3ac7 0x39ab 0x38ee 0x38a2 0x3891 0x3ac7 0x39ab 0x38ee 0x38a2 0x3891>;

};

qcom,pc-temp-y2-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x294b 0x29a1 0x2b8e 0x2cad 0x2b51 0x2b32 0x2969 0x29c2 0x2b97 0x2c62 0x2b23 0x2b02 0x299a 0x29f7 0x2b94 0x2c17 0x2af0 0x2acb 0x29d0 0x2a31 0x2b89 0x2bd0 0x2abf 0x2a94 0x29fe 0x2a60 0x2b78 0x2b93 0x2a96 0x2a67 0x2a17 0x2a73 0x2b63 0x2b67 0x2a7b 0x2a4b 0x2a1b 0x2a6f 0x2b44 0x2b48 0x2a6e 0x2a3e 0x2a1d 0x2a6a 0x2b21 0x2b2f 0x2a64 0x2a34 0x2a24 0x2a6c 0x2b08 0x2b18 0x2a58 0x2a24 0x2a3f 0x2a82 0x2af2 0x2b01 0x2a49 0x2a04 0x2a60 0x2a9b 0x2aea 0x2aee 0x2a37 0x29f2 0x2a76 0x2aac 0x2af3 0x2add 0x2a1c 0x29fa 0x2a8a 0x2abf 0x2b08 0x2ad1 0x2a04 0x2a05 0x2aab 0x2ae7 0x2b2b 0x2ad4 0x2a04 0x29fc 0x2aff 0x2b51 0x2b68 0x2ae7 0x2a11 0x29e2 0x2b45 0x2b9e 0x2ba6 0x2b02 0x2a18 0x29d4 0x2b48 0x2bc4 0x2be0 0x2b35 0x2a11 0x29d2 0x2b43 0x2be9 0x2c16 0x2b7d 0x2a0b 0x29d3 0x2b42 0x2bec 0x2c48 0x2be0 0x2a2f 0x29e4 0x2b4b 0x2bd2 0x2c77 0x2c5c 0x2aa7 0x2a1c 0x2b56 0x2bbf 0x2c86 0x2c85 0x2b04 0x2a58 0x2b5c 0x2bce 0x2c7b 0x2c74 0x2b3f 0x2a9d 0x2b60 0x2be7 0x2c70 0x2c5b 0x2b64 0x2ad7 0x2b62 0x2bea 0x2c75 0x2c40 0x2b5d 0x2af0 0x2b54 0x2bda 0x2c85 0x2c1d 0x2b3e 0x2b04 0x2b3a 0x2bc0 0x2c8f 0x2c15 0x2b36 0x2b0b 0x2b21 0x2b97 0x2c98 0x2c41 0x2b57 0x2b0e 0x2b06 0x2b59 0x2c9e 0x2c72 0x2b7b 0x2b15 0x2ad5 0x2adc 0x2c97 0x2c92 0x2b94 0x2b29 0x291e 0x2988 0x2c84 0x2cb8 0x2bba 0x2b52 0x26aa 0x28b9 0x2c7c 0x2cd5 0x2bcd 0x2b7f 0x260e 0x2839 0x2c7c 0x2cfc 0x2bf3 0x2bb7 0x25fa 0x2746 0x2c7b 0x2d14 0x2c23 0x2be3 0x25ee 0x26c5 0x2c6d 0x2d09 0x2c4c 0x2bf3 0x25e5 0x2649 0x2c4d 0x2cf0 0x2c71 0x2bff 0x25dd 0x25f7 0x2c24 0x2cdd 0x2c77 0x2bfd 0x25d7 0x25e1 0x2be3 0x2ccc 0x2c50 0x2bd6 0x25d2 0x25d4 0x2b93 0x2cbc 0x2c1c 0x2bb2 0x25ce 0x25cc 0x2b3b 0x2ca8 0x2be3 0x2ba9 0x25ca 0x25c8 0x2ad2 0x2c90 0x2ba8 0x2b9e 0x25c8 0x25c4 0x2a5f 0x2c83 0x2ba2 0x2b89 0x25c6 0x25c1 0x29dc 0x2c72 0x2bc4 0x2b49 0x25c4 0x25bf 0x28bd 0x2c50 0x2bc7 0x2b35 0x25c3 0x25be 0x26d5 0x2c03 0x2b9e 0x2b3c 0x25c1 0x25bc 0x262e 0x2bc5 0x2b6a 0x2b06 0x25bf 0x25bb 0x25fe 0x2b95 0x2b3e 0x2a85 0x25be 0x25ba 0x25df 0x2bab 0x2aea 0x2a63 0x25bd 0x25ba 0x25ce 0x2ba3 0x2af1 0x2a6c 0x25bb 0x25b9 0x25c5 0x2b94 0x2b02 0x2a53 0x25b8 0x25b8 0x25bf 0x2b93 0x2b37 0x2a62 0x25b4 0x25b6 0x25ba 0x2b44 0x2afa 0x2a55 0x25b1 0x25b2 0x25b7 0x2adb 0x2aa4 0x2a1b 0x25b0 0x25b0 0x25b4 0x2a4b 0x2a36 0x29b5 0x25af 0x25b0 0x25b3 0x2991 0x29af 0x2931 0x25af 0x25b0 0x25b3 0x2991 0x29af 0x2931 0x25af 0x25b0 0x25b3 0x2991 0x29af 0x2931>;

};

qcom,pc-temp-y6-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x15dd 0x150f 0x142e 0x13a3 0x1375 0x136c 0x15e6 0x1523 0x143c 0x13a2 0x1376 0x136d 0x15ec 0x1533 0x1446 0x13a2 0x1377 0x136f 0x15f0 0x153f 0x144c 0x13a2 0x1377 0x1370 0x15f3 0x1547 0x144f 0x13a1 0x1378 0x1371 0x15f4 0x154a 0x144f 0x13a1 0x1378 0x1371 0x15f3 0x1546 0x144d 0x13a1 0x1379 0x1372 0x15f0 0x1540 0x1447 0x13a1 0x1379 0x1372 0x15ec 0x153a 0x1443 0x13a1 0x137a 0x1372 0x15e7 0x1534 0x143f 0x13a1 0x137a 0x1372 0x15e3 0x1531 0x143e 0x13a2 0x137b 0x1373 0x15e1 0x1534 0x143e 0x13a3 0x137c 0x1373 0x15df 0x1538 0x143e 0x13a4 0x137d 0x1374 0x15de 0x153c 0x143e 0x13a7 0x137e 0x1375 0x15da 0x1540 0x1441 0x13aa 0x1380 0x1376 0x15d4 0x1542 0x1445 0x13ae 0x1381 0x1377 0x15c9 0x153c 0x144e 0x13b2 0x1384 0x1379 0x15b6 0x152e 0x1457 0x13b8 0x1388 0x137b 0x15a9 0x151c 0x1453 0x13c0 0x138d 0x137f 0x15a2 0x1500 0x1442 0x13cb 0x1396 0x1386 0x159c 0x14ea 0x1431 0x13cd 0x1398 0x1389 0x1598 0x14e1 0x141f 0x13be 0x1394 0x1387 0x1595 0x14db 0x1410 0x13ac 0x138d 0x1384 0x1593 0x14d5 0x1409 0x13a0 0x1384 0x137d 0x1592 0x14d0 0x1405 0x1398 0x1379 0x1372 0x1591 0x14ca 0x1402 0x1395 0x1375 0x136e 0x158f 0x14c1 0x1400 0x1395 0x1375 0x136e 0x158c 0x14b9 0x13ff 0x1396 0x1375 0x136e 0x158b 0x14b8 0x13fe 0x1397 0x1376 0x136e 0x1594 0x14c3 0x13fe 0x1399 0x1377 0x136f 0x15a6 0x14d2 0x13fd 0x139b 0x1379 0x1370 0x15b9 0x14e6 0x13fa 0x139d 0x137b 0x1373 0x15ce 0x1501 0x13f8 0x139e 0x137e 0x1375 0x15e5 0x151f 0x13fb 0x139f 0x1381 0x1379 0x15fe 0x1542 0x1405 0x13a0 0x1383 0x137c 0x161a 0x1569 0x1411 0x13a0 0x1383 0x137c 0x1639 0x1595 0x141f 0x139d 0x1380 0x1378 0x1659 0x15c7 0x1431 0x139b 0x137c 0x1374 0x167b 0x15fb 0x1446 0x139b 0x137b 0x1374 0x169d 0x1634 0x145e 0x139c 0x137a 0x1375 0x16be 0x1671 0x147a 0x139d 0x137b 0x1377 0x16e4 0x16b1 0x1498 0x13a4 0x137e 0x137b 0x170d 0x16f7 0x14ba 0x13a7 0x137e 0x137a 0x1740 0x1743 0x14e1 0x13a8 0x1377 0x1370 0x1784 0x17a0 0x1511 0x13a9 0x1372 0x136a 0x17f0 0x17d2 0x1537 0x13ac 0x137a 0x1374 0x181c 0x1813 0x1573 0x13b5 0x1383 0x137f 0x185b 0x1868 0x15c1 0x13bf 0x138f 0x138b 0x18f3 0x18c8 0x1632 0x13cd 0x139a 0x1397 0x1a15 0x195e 0x16d0 0x13d8 0x13a0 0x139b 0x1dcc 0x1ac5 0x17c8 0x13d7 0x1389 0x1380 0x2989 0x217d 0x192c 0x13d2 0x1382 0x137b 0x46c0 0x3c73 0x1cd2 0x13f1 0x1387 0x137e 0xb1f2 0xded8 0x37c8 0x1424 0x1390 0x1385 0xb1f2 0xded8 0x37c8 0x1424 0x1390 0x1385 0xb1f2 0xded8 0x37c8 0x1424 0x1390 0x1385>;

};

qcom,pc-temp-z3-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x4c2c 0x4c64 0x4bd1 0x4b90 0x4b82 0x4ca3 0x4c55 0x4bca 0x4bb1 0x4ba5 0x4cf0 0x4c50 0x4be4 0x4bba 0x4baf 0x4d1c 0x4c5e 0x4bf2 0x4bbf 0x4bb3 0x4d2b 0x4c6e 0x4bf4 0x4bc3 0x4bb8 0x4d35 0x4c71 0x4bf6 0x4bc6 0x4bbf 0x4d36 0x4c71 0x4bf7 0x4bc7 0x4bc1 0x4d2f 0x4c70 0x4bf8 0x4bc9 0x4bc0 0x4d25 0x4c6d 0x4bf9 0x4bcb 0x4bbe 0x4d1e 0x4c67 0x4bf5 0x4bca 0x4bbd 0x4d18 0x4c60 0x4bee 0x4bc4 0x4bbc 0x4d12 0x4c57 0x4be8 0x4bc0 0x4bbb 0x4d0b 0x4c4d 0x4be3 0x4bbe 0x4bba 0x4d05 0x4c46 0x4bdf 0x4bbd 0x4bb7 0x4cff 0x4c3f 0x4bdb 0x4bbb 0x4bb5 0x4cf7 0x4c3a 0x4bd8 0x4bb9 0x4bb1 0x4ced 0x4c37 0x4bd6 0x4bb7 0x4bae 0x4cdf 0x4c33 0x4bd3 0x4bb5 0x4bab 0x4cce 0x4c2d 0x4bd1 0x4bb2 0x4ba8 0x4cc3 0x4c26 0x4bcc 0x4bac 0x4ba4 0x4cbd 0x4c24 0x4bc8 0x4ba5 0x4b9e 0x4cb9 0x4c27 0x4bcd 0x4ba5 0x4b9e 0x4cb9 0x4c2c 0x4be0 0x4bb2 0x4ba3 0x4cbb 0x4c31 0x4be9 0x4bbb 0x4ba8 0x4cbe 0x4c38 0x4bd8 0x4bb1 0x4ba8 0x4cc5 0x4c3a 0x4bc4 0x4ba0 0x4ba7 0x4cce 0x4c30 0x4bc3 0x4ba4 0x4baa 0x4cd0 0x4c27 0x4bc6 0x4bc4 0x4bbf 0x4ccc 0x4c26 0x4bcb 0x4bd7 0x4bcc 0x4cc6 0x4c27 0x4bdc 0x4bd3 0x4bc7 0x4cc1 0x4c29 0x4bec 0x4bcd 0x4bbf 0x4cba 0x4c2d 0x4beb 0x4bc5 0x4bb8 0x4cb5 0x4c32 0x4be4 0x4bbd 0x4bb3 0x4cb1 0x4c32 0x4bdf 0x4bb5 0x4bac 0x4cad 0x4c31 0x4bda 0x4baf 0x4ba3 0x4ca9 0x4c30 0x4bd6 0x4baa 0x4b9a 0x4ca5 0x4c2c 0x4bd1 0x4ba5 0x4b95 0x4ca1 0x4c27 0x4bcc 0x4b9f 0x4b91 0x4c9c 0x4c22 0x4bc9 0x4b9e 0x4b90 0x4c97 0x4c1e 0x4bc8 0x4b9f 0x4b90 0x4c91 0x4c19 0x4bc7 0x4ba0 0x4b90 0x4c88 0x4c16 0x4bc4 0x4b9f 0x4b93 0x4c7f 0x4c11 0x4bc0 0x4b9e 0x4b98 0x4c75 0x4c0a 0x4bbc 0x4b9f 0x4b9c 0x4c2a 0x4bf0 0x4bb4 0x4b9f 0x4b9c 0x4c15 0x4bde 0x4bac 0x4b93 0x4b90 0x4be8 0x4bdb 0x4ba8 0x4b8f 0x4b8f 0x4b6c 0x4bbf 0x4ba4 0x4b8c 0x4b83 0x4b67 0x4b85 0x4b99 0x4b85 0x4b7f 0x4b5f 0x4b85 0x4b93 0x4b82 0x4b7a 0x4b49 0x4b83 0x4b98 0x4b8e 0x4b85 0x4b58 0x4b7e 0x4b9c 0x4b9d 0x4b93 0x4b69 0x4b79 0x4b97 0x4b9e 0x4b95 0x4b7e 0x4b92 0x4b96 0x4b99 0x4b96 0x4b7e 0x4b92 0x4b96 0x4b99 0x4b96 0x4b7e 0x4b92 0x4b96 0x4b99 0x4b96>;

};

qcom,pc-temp-v1-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0xac3c 0xaccb 0xad2e 0xad4e 0xad57 0xab5b 0xabe8 0xac43 0xac4e 0xac51 0xaa76 0xab05 0xab6a 0xab76 0xab77 0xa98e 0xaa25 0xaa92 0xaaa8 0xaaad 0xa8a2 0xa945 0xa9b3 0xa9d0 0xa9d6 0xa7b2 0xa85b 0xa8d0 0xa8f3 0xa8f9 0xa6c2 0xa769 0xa7e3 0xa80d 0xa814 0xa5d1 0xa674 0xa6ed 0xa71b 0xa727 0xa4e1 0xa580 0xa5f5 0xa623 0xa635 0xa3f7 0xa48b 0xa4fe 0xa52e 0xa541 0xa311 0xa39d 0xa409 0xa43a 0xa44a 0xa231 0xa2b3 0xa319 0xa349 0xa358 0xa155 0xa1cf 0xa22f 0xa25b 0xa269 0xa080 0xa0f3 0xa14a 0xa170 0xa17f 0x9faf 0xa01c 0xa06b 0xa08f 0xa09d 0x9ee2 0x9f4a 0x9f93 0x9fb3 0x9fc1 0x9e1c 0x9e7c 0x9ec3 0x9ee1 0x9eee 0x9d5b 0x9db8 0x9dfb 0x9e16 0x9e22 0x9ca0 0x9d05 0x9d3e 0x9d55 0x9d5f 0x9bf5 0x9c5d 0x9c97 0x9ca9 0x9caf 0x9b5f 0x9bb0 0x9bed 0x9c02 0x9c07 0x9acd 0x9aff 0x9b08 0x9b2e 0x9b38 0x9a33 0x9a41 0x99e2 0x9a0b 0x9a1e 0x9994 0x994e 0x98fd 0x9914 0x9927 0x98eb 0x9838 0x9867 0x987e 0x988f 0x981f 0x9788 0x97ef 0x9808 0x9816 0x9753 0x972f 0x9784 0x9791 0x979d 0x96d0 0x96eb 0x9726 0x971d 0x9726 0x9676 0x969f 0x96cb 0x96b4 0x96b9 0x9631 0x9656 0x966c 0x9655 0x9658 0x95ff 0x9613 0x9616 0x9601 0x9601 0x95d7 0x95d3 0x95d0 0x95b6 0x95b1 0x95b1 0x9599 0x9594 0x9573 0x9567 0x958e 0x9566 0x955b 0x9533 0x9522 0x956e 0x9539 0x9527 0x94f7 0x94e2 0x954f 0x9511 0x94f5 0x94bd 0x94a3 0x9534 0x94f0 0x94c7 0x9483 0x9461 0x9512 0x94ce 0x949b 0x944a 0x941d 0x94de 0x9497 0x945e 0x9403 0x93cc 0x9498 0x9442 0x9404 0x93a3 0x9365 0x9440 0x93de 0x9399 0x9336 0x92f0 0x93c6 0x9365 0x9326 0x92c6 0x9279 0x933a 0x92d8 0x92a2 0x9247 0x91f7 0x9299 0x922e 0x91fd 0x91a5 0x914f 0x91fd 0x9193 0x9161 0x9112 0x90c3 0x9176 0x9123 0x90f3 0x90b8 0x907a 0x914d 0x90ff 0x90d4 0x9098 0x905a 0x9135 0x90e9 0x90bc 0x9082 0x9045 0x910f 0x90d3 0x90ab 0x906f 0x9030 0x90ee 0x90ae 0x9085 0x9042 0x8ffb 0x90bb 0x9007 0x8fbc 0x8f5d 0x8f07 0x8fe7 0x8e55 0x8e0d 0x8dab 0x8d57 0x8e0f 0x8c0a 0x8bc9 0x8b6b 0x8b19 0x8b8d 0x88d2 0x88ab 0x885b 0x880c 0x8759 0x833d 0x83c8 0x8399 0x8356 0x7530 0x7530 0x7530 0x7530 0x7530>;

};

qcom,pc-temp-y3-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x3473 0x3457 0x3410 0x33ee 0x33e1 0x33dd 0x3477 0x345a 0x3413 0x33ee 0x33e1 0x33de 0x347d 0x345f 0x3416 0x33ee 0x33e1 0x33df 0x3485 0x3464 0x3419 0x33ee 0x33e2 0x33e0 0x348c 0x3468 0x341c 0x33ef 0x33e3 0x33e1 0x348f 0x346a 0x341e 0x33ef 0x33e3 0x33e2 0x3490 0x346c 0x3420 0x33ef 0x33e4 0x33e2 0x3490 0x346c 0x3422 0x33f0 0x33e5 0x33e3 0x3490 0x346c 0x3423 0x33f1 0x33e6 0x33e3 0x348e 0x3469 0x3425 0x33f1 0x33e6 0x33e4 0x348c 0x3467 0x3426 0x33f2 0x33e6 0x33e4 0x3492 0x346e 0x3427 0x33f2 0x33e6 0x33e5 0x34a1 0x3479 0x3427 0x33f2 0x33e7 0x33e5 0x34a4 0x3475 0x3426 0x33f3 0x33e7 0x33e6 0x3483 0x3456 0x3421 0x33f6 0x33e7 0x33e6 0x3462 0x3441 0x341d 0x33f8 0x33e8 0x33e6 0x3463 0x3448 0x341a 0x33f8 0x33ea 0x33e6 0x346b 0x3453 0x3418 0x33f9 0x33ec 0x33e6 0x346e 0x3453 0x3416 0x33f8 0x33ed 0x33e8 0x3465 0x3444 0x3415 0x33f7 0x33ee 0x33eb 0x3459 0x3436 0x3412 0x33f6 0x33ee 0x33ec 0x3453 0x3431 0x340d 0x33f4 0x33ec 0x33ea 0x3450 0x342d 0x3408 0x33f1 0x33e8 0x33e6 0x344d 0x3428 0x3405 0x33ed 0x33e5 0x33e3 0x344a 0x3422 0x3404 0x33ea 0x33e1 0x33e0 0x3447 0x341d 0x3402 0x33e8 0x33e0 0x33df 0x343f 0x341a 0x3400 0x33e8 0x33e0 0x33df 0x342a 0x3416 0x33ff 0x33e8 0x33e0 0x33df 0x341e 0x340f 0x33fd 0x33e8 0x33df 0x33df 0x3423 0x33fa 0x33fc 0x33e9 0x33df 0x33de 0x342e 0x33ed 0x33fb 0x33e9 0x33de 0x33de 0x3437 0x33f7 0x33fa 0x33e8 0x33df 0x33de 0x3441 0x340b 0x33f9 0x33e8 0x33df 0x33de 0x344d 0x341b 0x33fa 0x33e7 0x33df 0x33de 0x345c 0x342a 0x33fc 0x33e7 0x33e0 0x33e0 0x346d 0x343c 0x33fe 0x33e7 0x33e0 0x33e0 0x3482 0x344f 0x3400 0x33e7 0x33e0 0x33df 0x349a 0x3465 0x3403 0x33e7 0x33df 0x33de 0x34b6 0x3484 0x3406 0x33e7 0x33df 0x33de 0x34d4 0x34b2 0x3409 0x33e7 0x33e0 0x33de 0x34f7 0x34ea 0x340d 0x33e8 0x33e0 0x33df 0x351d 0x352c 0x3411 0x33ea 0x33e2 0x33e0 0x3544 0x3579 0x3418 0x33eb 0x33e1 0x33e0 0x3577 0x35ce 0x3421 0x33ea 0x33df 0x33dd 0x35bb 0x3639 0x3436 0x33ea 0x33de 0x33dc 0x362f 0x366d 0x344a 0x33ec 0x33e3 0x33e1 0x3658 0x36b9 0x3467 0x33f0 0x33e6 0x33e4 0x3694 0x3719 0x348b 0x33f4 0x33e9 0x33e6 0x3736 0x377d 0x34e4 0x33f8 0x33ea 0x33e8 0x3870 0x381f 0x356e 0x33fb 0x33ea 0x33e6 0x3c9b 0x39b3 0x3666 0x33fa 0x33e6 0x33e4 0x4b24 0x41ea 0x37f6 0x33fb 0x33e5 0x33e3 0x7284 0x6594 0x3c35 0x3406 0x33e9 0x33e6 0xffff 0xffff 0x5ca9 0x341a 0x33f0 0x33ef 0xffff 0xffff 0x5ca9 0x341a 0x33f0 0x33ef 0xffff 0xffff 0x5ca9 0x341a 0x33f0 0x33ef>;

};

qcom,pc-temp-z4-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x3deb 0x3b60 0x3a1b 0x3a2c 0x39bc 0x3ef6 0x3bc6 0x3b0a 0x3a3d 0x3a0c 0x3e3a 0x3bdd 0x3abe 0x3a22 0x39fd 0x3d5d 0x3b88 0x3a68 0x39f4 0x39db 0x3cb5 0x3b02 0x3a33 0x39d6 0x39c3 0x3c19 0x3aa5 0x3a06 0x39be 0x39af 0x3ba0 0x3a64 0x39e2 0x39aa 0x399e 0x3b42 0x3a31 0x39c3 0x3994 0x398c 0x3af4 0x3a09 0x39ab 0x3983 0x397e 0x3ab2 0x39e9 0x399a 0x397b 0x3977 0x3a7a 0x39cf 0x398c 0x3976 0x3973 0x3a4b 0x39b7 0x3984 0x3972 0x3970 0x3a23 0x39a6 0x3980 0x396d 0x396d 0x3a02 0x399e 0x397c 0x3969 0x3969 0x39e5 0x3999 0x3977 0x3964 0x3966 0x39c8 0x3995 0x3972 0x395f 0x3963 0x39b9 0x3992 0x396e 0x395b 0x3960 0x39ba 0x3990 0x396b 0x3957 0x395d 0x39c0 0x398a 0x3967 0x3954 0x395a 0x39c1 0x3982 0x3963 0x3950 0x3954 0x39b2 0x397f 0x3960 0x394d 0x394e 0x39a1 0x3981 0x396d 0x3954 0x3954 0x399f 0x3986 0x39a4 0x398e 0x3991 0x39a0 0x39a6 0x39cc 0x39bc 0x39c0 0x39a1 0x39ee 0x39e1 0x39c3 0x39bb 0x39c2 0x3a0a 0x39ed 0x39c7 0x39ae 0x39f3 0x39ff 0x39e8 0x39be 0x399b 0x39ff 0x39ee 0x39d1 0x398d 0x397a 0x39ff 0x39df 0x39b9 0x396c 0x3964 0x39fe 0x39cf 0x399e 0x3967 0x3960 0x39f9 0x39c0 0x3988 0x3963 0x395d 0x39eb 0x39b1 0x3980 0x3961 0x3959 0x39de 0x39a5 0x397c 0x395e 0x3955 0x39d3 0x399e 0x397a 0x395c 0x3952 0x39c8 0x3999 0x3979 0x395a 0x394f 0x39bc 0x3995 0x3978 0x3959 0x394e 0x39b0 0x3990 0x3977 0x3959 0x394e 0x39a5 0x398c 0x3975 0x395a 0x394e 0x3999 0x3989 0x3975 0x395c 0x394f 0x398e 0x3987 0x3977 0x3963 0x395b 0x3988 0x3985 0x397a 0x396a 0x3966 0x3984 0x397c 0x3975 0x3967 0x3962 0x397d 0x3971 0x396b 0x3961 0x3959 0x396c 0x396a 0x3966 0x395f 0x395e 0x3967 0x3957 0x3957 0x3957 0x3959 0x3968 0x394c 0x3944 0x3945 0x3941 0x3997 0x3948 0x3940 0x3942 0x393b 0x3a1e 0x395b 0x3939 0x3939 0x3937 0x3a20 0x3995 0x3936 0x392d 0x3929 0x3a24 0x398d 0x3933 0x3924 0x3920 0x3a35 0x3991 0x393b 0x3937 0x393e 0x3a23 0x39a6 0x3945 0x393b 0x3945 0x3a28 0x39b2 0x394c 0x393e 0x394b 0x3a2b 0x39a5 0x3950 0x3945 0x394b 0x3a2b 0x39a5 0x3950 0x3945 0x394b 0x3a2b 0x39a5 0x3950 0x3945 0x394b>;

};

qcom,pc-temp-v2-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0xad43 0xad39 0xad2a 0xad1b 0xacf3 0xacee 0xac0a 0xabff 0xac0e 0xac09 0xabe5 0xabdd 0xaaed 0xaae2 0xab05 0xab05 0xaae5 0xaadd 0xa9f2 0xa9e6 0xaa13 0xaa15 0xa9f9 0xa9f1 0xa91a 0xa90b 0xa938 0xa938 0xa91f 0xa919 0xa843 0xa82f 0xa858 0xa856 0xa840 0xa83d 0xa75c 0xa73e 0xa766 0xa767 0xa753 0xa752 0xa66d 0xa646 0xa66e 0xa673 0xa661 0xa660 0xa57c 0xa54d 0xa575 0xa57d 0xa56d 0xa56d 0xa485 0xa44f 0xa47b 0xa485 0xa476 0xa477 0xa38f 0xa35d 0xa384 0xa391 0xa382 0xa384 0xa2a1 0xa280 0xa293 0xa29f 0xa293 0xa295 0xa1b7 0xa1ac 0xa1a7 0xa1b2 0xa1a7 0xa1aa 0xa0c7 0xa0d9 0xa0bf 0xa0cc 0xa0c1 0xa0c4 0x9fd2 0xa006 0x9fde 0x9fec 0x9fe0 0x9fe3 0x9ed8 0x9f2c 0x9f09 0x9f13 0x9f08 0x9f0a 0x9dcf 0x9e46 0x9e4b 0x9e41 0x9e38 0x9e38 0x9cbc 0x9d53 0x9d8b 0x9d75 0x9d70 0x9d6f 0x9bc3 0x9c54 0x9cab 0x9cb9 0x9cb6 0x9cb5 0x9aed 0x9b41 0x9baf 0x9c07 0x9c04 0x9c07 0x9a27 0x9a42 0x9aba 0x9b3c 0x9b41 0x9b49 0x9968 0x996a 0x99c6 0x9a3c 0x9a58 0x9a69 0x98b4 0x98a9 0x98e5 0x993e 0x996d 0x9984 0x9809 0x97f3 0x982a 0x9871 0x989c 0x98b4 0x9769 0x974c 0x9788 0x97bc 0x97da 0x97ed 0x96d0 0x96aa 0x96f4 0x9724 0x973d 0x974c 0x9637 0x9600 0x966c 0x96a5 0x96bf 0x96cc 0x959a 0x9560 0x95f0 0x9635 0x9652 0x965d 0x9521 0x94f3 0x9582 0x95cf 0x95eb 0x95f4 0x94d1 0x94a5 0x951d 0x9571 0x958c 0x9593 0x9493 0x9467 0x94bd 0x951a 0x9537 0x953c 0x9456 0x9435 0x945d 0x94c9 0x94ec 0x94ef 0x941d 0x940b 0x940e 0x947d 0x94a4 0x94a6 0x93e4 0x93de 0x93dc 0x9437 0x945f 0x945f 0x93ac 0x93b2 0x93b6 0x93f5 0x941c 0x9419 0x9374 0x9383 0x938d 0x93b0 0x93cd 0x93c3 0x9338 0x9351 0x9364 0x9369 0x936e 0x9352 0x92f9 0x931b 0x9335 0x931f 0x930c 0x92e0 0x92b3 0x92da 0x92f9 0x92d2 0x92b1 0x9280 0x9266 0x928d 0x92b0 0x9282 0x9256 0x9227 0x9210 0x9235 0x9256 0x922d 0x91fb 0x91cc 0x91b8 0x91cd 0x91df 0x91d0 0x91a1 0x9172 0x915e 0x9153 0x9152 0x9157 0x912b 0x90fd 0x9106 0x90c4 0x90ab 0x90c4 0x9098 0x9063 0x90b3 0x9035 0x900c 0x903f 0x9022 0x8fef 0x9064 0x8fbb 0x8fa7 0x9005 0x8ff4 0x8fc2 0x9039 0x8f91 0x8f85 0x8ff8 0x8feb 0x8fb8 0x900a 0x8f71 0x8f63 0x8fe4 0x8fde 0x8faa 0x8fd9 0x8f4e 0x8f32 0x8fc6 0x8fc6 0x8f92 0x8fa7 0x8f2a 0x8ed1 0x8f7a 0x8f85 0x8f4c 0x8f6e 0x8eeb 0x8df6 0x8e81 0x8e74 0x8e29 0x8f14 0x8e17 0x8c27 0x8c82 0x8c8a 0x8c45 0x8e5c 0x8bf5 0x898d 0x89eb 0x8a08 0x89c6 0x8cda 0x88ab 0x8586 0x8644 0x868e 0x8652 0x89ed 0x835b 0x7ef2 0x80a5 0x814a 0x8120 0x8636 0x7db4 0x6bec 0x6bcc 0x6e89 0x71d2>;

};

qcom,fcc1-temp-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-data = <0x12cd 0x1366 0x13d6 0x13f6 0x13ff>;

};

qcom,pc-temp-y4-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x412c 0x4135 0x40c2 0x406f 0x4049 0x4048 0x4159 0x4164 0x40e7 0x4070 0x404b 0x404a 0x4197 0x41ab 0x410d 0x4072 0x404c 0x404c 0x41d9 0x41f6 0x412f 0x4072 0x404d 0x404d 0x4211 0x4232 0x4146 0x4073 0x404e 0x404e 0x4230 0x424b 0x414f 0x4073 0x404e 0x404e 0x423b 0x4245 0x4149 0x4073 0x404d 0x404d 0x4241 0x423b 0x413e 0x4072 0x404c 0x404c 0x4242 0x4238 0x4135 0x4072 0x404c 0x404c 0x4241 0x4237 0x412e 0x4074 0x404e 0x404c 0x423f 0x4237 0x412b 0x4076 0x4050 0x404c 0x422f 0x4238 0x412d 0x407b 0x4053 0x404c 0x420f 0x423c 0x4133 0x4082 0x4056 0x404e 0x4208 0x4251 0x413f 0x4087 0x4059 0x404f 0x423f 0x42a7 0x4159 0x408c 0x405e 0x4052 0x4275 0x42df 0x4177 0x4093 0x4063 0x4056 0x4250 0x42b6 0x41a0 0x40a3 0x4068 0x405b 0x41dd 0x4260 0x41c2 0x40b8 0x4070 0x4061 0x419d 0x4219 0x41b5 0x40d7 0x4080 0x406c 0x418e 0x41d5 0x4180 0x4100 0x409b 0x407d 0x4183 0x41a0 0x414b 0x410a 0x40a5 0x4084 0x4173 0x417f 0x4117 0x40db 0x409c 0x4084 0x4160 0x4166 0x40eb 0x40a1 0x408e 0x4083 0x414b 0x414c 0x40d5 0x4082 0x4077 0x4077 0x412e 0x4133 0x40c5 0x406b 0x4058 0x4058 0x4114 0x4115 0x40ba 0x4065 0x404e 0x404b 0x410a 0x40e0 0x40b1 0x4064 0x404e 0x404a 0x4104 0x40a8 0x40aa 0x4064 0x404e 0x4049 0x4102 0x40a5 0x40a4 0x4067 0x4050 0x404a 0x4111 0x40cd 0x409e 0x406c 0x4056 0x404e 0x412c 0x40ea 0x4095 0x4071 0x405c 0x4054 0x413c 0x40e9 0x407f 0x4075 0x4065 0x405b 0x4146 0x40e7 0x4070 0x4078 0x406c 0x4064 0x414d 0x40f1 0x4074 0x407a 0x4073 0x406d 0x4154 0x4104 0x4080 0x407a 0x4079 0x4076 0x4159 0x4118 0x408f 0x4079 0x4079 0x4077 0x415e 0x412c 0x40a3 0x406d 0x406d 0x4068 0x4162 0x413d 0x40b9 0x4063 0x4062 0x405c 0x4164 0x4141 0x40cd 0x4061 0x405c 0x405c 0x4160 0x4141 0x40e0 0x4060 0x4058 0x405f 0x4157 0x4140 0x40eb 0x4063 0x4059 0x4063 0x4152 0x413c 0x40f0 0x406e 0x4060 0x406d 0x4151 0x4132 0x40f2 0x4071 0x405e 0x406b 0x4154 0x4125 0x40f3 0x4071 0x404c 0x404f 0x4167 0x4117 0x40f0 0x406a 0x403d 0x403a 0x4177 0x4106 0x40ea 0x406b 0x4047 0x404d 0x4175 0x4109 0x40fc 0x407a 0x4060 0x406d 0x416e 0x4114 0x4128 0x408e 0x4082 0x4092 0x417b 0x4125 0x413e 0x40b3 0x40a7 0x40b5 0x418a 0x413c 0x416f 0x40d1 0x40ba 0x40c5 0x41d6 0x4158 0x41a1 0x40c8 0x4074 0x406d 0x4399 0x4210 0x41b0 0x40a7 0x405a 0x405c 0x490a 0x477c 0x4233 0x40c8 0x405d 0x405b 0x5dd2 0x7d98 0x538d 0x40fa 0x4066 0x405a 0x5dd2 0x7d98 0x538d 0x40fa 0x4066 0x405a 0x5dd2 0x7d98 0x538d 0x40fa 0x4066 0x405a>;

};

qcom,pc-temp-z1-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x2fac 0x2dba 0x2bfe 0x2af9 0x2a90 0x2fa4 0x2da6 0x2c0d 0x2ae6 0x2a7d 0x2f98 0x2d94 0x2bf4 0x2ada 0x2a76 0x2f8c 0x2d85 0x2bdf 0x2ad0 0x2a72 0x2f7f 0x2d78 0x2bd6 0x2ac9 0x2a6d 0x2f74 0x2d6d 0x2bcf 0x2ac2 0x2a68 0x2f6c 0x2d63 0x2bc5 0x2abd 0x2a64 0x2f5e 0x2d59 0x2bb4 0x2ab7 0x2a61 0x2f4d 0x2d4d 0x2ba8 0x2ab3 0x2a5f 0x2f3c 0x2d41 0x2ba4 0x2ab1 0x2a5d 0x2f26 0x2d35 0x2ba2 0x2ab0 0x2a5c 0x2f16 0x2d27 0x2ba1 0x2aaf 0x2a5b 0x2f0d 0x2d1e 0x2ba1 0x2aad 0x2a5b 0x2f07 0x2d23 0x2ba0 0x2aac 0x2a5a 0x2f01 0x2d2c 0x2b9f 0x2aac 0x2a5b 0x2ef4 0x2d2f 0x2b9d 0x2aac 0x2a5b 0x2ee9 0x2d2d 0x2b9d 0x2aad 0x2a5b 0x2eea 0x2d2c 0x2b9d 0x2aad 0x2a5d 0x2eed 0x2d2b 0x2b9d 0x2aae 0x2a5e 0x2ef1 0x2d2a 0x2b9f 0x2ab0 0x2a5f 0x2f0d 0x2d2a 0x2ba2 0x2ab2 0x2a60 0x2f2c 0x2d2f 0x2ba4 0x2ab2 0x2a61 0x2f29 0x2d34 0x2ba6 0x2ab2 0x2a63 0x2f0f 0x2d36 0x2ba8 0x2ab2 0x2a66 0x2efc 0x2d38 0x2ba9 0x2ab4 0x2a67 0x2f00 0x2d3b 0x2baa 0x2ab9 0x2a69 0x2f09 0x2d3e 0x2bae 0x2abd 0x2a6b 0x2f0e 0x2d43 0x2bb4 0x2ac1 0x2a6e 0x2f2e 0x2d47 0x2bb8 0x2ac4 0x2a71 0x2f4b 0x2d4d 0x2bb9 0x2ac7 0x2a73 0x2f40 0x2d52 0x2bbb 0x2aca 0x2a76 0x2f1f 0x2d56 0x2bbe 0x2acd 0x2a79 0x2f17 0x2d59 0x2bc4 0x2ad0 0x2a7c 0x2f8a 0x2d5d 0x2bc9 0x2ad3 0x2a7f 0x3014 0x2d61 0x2bcc 0x2ad7 0x2a83 0x300d 0x2d65 0x2bcf 0x2adb 0x2a86 0x2f8f 0x2d6d 0x2bd4 0x2ae0 0x2a8a 0x2f41 0x2d76 0x2bd9 0x2ae3 0x2a8d 0x2f4b 0x2d7f 0x2bdf 0x2ae7 0x2a90 0x2f5b 0x2d89 0x2be6 0x2aec 0x2a93 0x2f68 0x2d91 0x2bed 0x2af0 0x2a96 0x2f74 0x2d98 0x2bf2 0x2af3 0x2a9a 0x2f80 0x2d9e 0x2bf7 0x2af7 0x2a9d 0x2f8b 0x2da7 0x2bff 0x2afa 0x2a9f 0x2fa2 0x2da7 0x2c06 0x2afe 0x2aa2 0x3005 0x2daf 0x2c08 0x2b02 0x2aa3 0x3084 0x2da7 0x2c0c 0x2b02 0x2aa3 0x2f98 0x2dae 0x2c0f 0x2b01 0x2aa3 0x2fa0 0x2dab 0x2c07 0x2b03 0x2aa5 0x2fb9 0x2db8 0x2c0e 0x2b09 0x2aa8 0x2fcc 0x2dca 0x2c1e 0x2b0e 0x2aad 0x2fc7 0x2dcf 0x2c1e 0x2b16 0x2ab4 0x2fcc 0x2dd3 0x2c2f 0x2b1f 0x2abc 0x2fd6 0x2e0b 0x2c3b 0x2b2d 0x2ac9 0x2fd6 0x2e0b 0x2c3b 0x2b2d 0x2ac9 0x2fd6 0x2e0b 0x2c3b 0x2b2d 0x2ac9>;

};

qcom,pc-temp-z5-lut {

qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x318d 0x3ac2 0x3d1b 0x383a 0x3947 0x342e 0x3bdd 0x3c8e 0x435b 0x44b4 0x36eb 0x3d43 0x421d 0x470b 0x4ad2 0x3965 0x3f3e 0x45f5 0x4a9f 0x4e64 0x3b56 0x41ed 0x47ca 0x4d19 0x52ee 0x3d07 0x446a 0x4912 0x4ecb 0x580c 0x3eba 0x4698 0x4b31 0x50d3 0x5c94 0x407e 0x48ea 0x4ebd 0x5616 0x6034 0x427a 0x4ba1 0x523b 0x5bc7 0x6379 0x44eb 0x4ea8 0x554a 0x5cdc 0x66c6 0x47d8 0x5206 0x57e2 0x5c4f 0x6a10 0x4b22 0x561c 0x58b0 0x5cf6 0x6d53 0x4ef4 0x598f 0x5898 0x601b 0x7119 0x539a 0x5b9a 0x58c3 0x63e1 0x7498 0x59de 0x5d49 0x5a4a 0x6735 0x7730 0x63dd 0x5f70 0x5cd9 0x6b37 0x7985 0x6a44 0x637a 0x5f99 0x6f5a 0x7acd 0x6820 0x668b 0x62e4 0x74f1 0x7fdb 0x62dc 0x66a2 0x65f6 0x7862 0x846d 0x60eb 0x6609 0x67f2 0x75cb 0x85b9 0x648f 0x674a 0x6a51 0x70e2 0x880a 0x6b8d 0x79c7 0x79cf 0x72e6 0x88a9 0x76b6 0x8ed5 0xa69a 0x87ae 0x8847 0x8b40 0x9709 0xbaad 0x9604 0x877c 0xa16f 0x9d17 0x8e5e 0x79b4 0x739a 0xbbcc 0x9d8b 0x5971 0x4cb5 0x51b8 0xd3c2 0x8655 0x5152 0x4960 0x4f41 0xd6ae 0x6dc1 0x4f31 0x615a 0x695d 0xc767 0x6b24 0x4f81 0x72c9 0x7b87 0xb522 0x6abd 0x62ca 0x784e 0x7dc0 0xa7a7 0x6aec 0x791b 0x7b8e 0x7eab 0x9b62 0x73ae 0x7ecd 0x7ad0 0x7f2f 0x94d8 0x810a 0x8173 0x76d8 0x80aa 0x919c 0x8bae 0x84ef 0x7507 0x8068 0x8fb1 0x960a 0x8b12 0x7782 0x7923 0x8f40 0x9a78 0x8f6e 0x7a32 0x714f 0x8f3c 0x9aa5 0x8e98 0x7959 0x7090 0x8f88 0x9a32 0x8c20 0x7679 0x7099 0x944f 0x990d 0x8ad0 0x7573 0x7076 0x9b91 0x9617 0x8a51 0x763f 0x6e2c 0x9cbe 0x92d5 0x895a 0x76fe 0x6bea 0x985a 0x8f95 0x8330 0x7268 0x6da7 0x979b 0x8c6b 0x7a38 0x6a8c 0x73ab 0x9edf 0x88b7 0x764b 0x7067 0x823d 0x7c4a 0x8194 0x7896 0x769c 0x8930 0x6b34 0x75c9 0x7b1c 0x6714 0x6f17 0x59da 0x70ac 0x7113 0x5f00 0x66e3 0x3069 0x4e21 0x6f67 0x5f22 0x560a 0x2fe4 0x374a 0x5ddb 0x6180 0x6114 0x2f2c 0x3822 0x5ab4 0x6b05 0x70c7 0x2dd3 0x3789 0x5cd0 0x6e4c 0x688e 0x2f0a 0x3507 0x526f 0x67a9 0x5b09 0x2f80 0x336f 0x48eb 0x5d36 0x4fd8 0x3183 0x3708 0x4571 0x4b6b 0x45c3 0x3183 0x3708 0x4571 0x4b6b 0x45c3 0x3183 0x3708 0x4571 0x4b6b 0x45c3>;

};

qcom,fcc2-temp-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-data = <0x1344 0x1395 0x13d2 0x13dc 0x13d3 0x13cc>;

};

qcom,pc-temp-y1-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x1697 0x1559 0x148e 0x1385 0x12db 0x12a2 0x16a9 0x1561 0x1483 0x1380 0x12dc 0x12a1 0x16b6 0x1566 0x1478 0x137c 0x12dc 0x12a1 0x16bf 0x156a 0x146e 0x1377 0x12db 0x12a1 0x16c4 0x156c 0x1466 0x1374 0x12db 0x12a0 0x16c6 0x156e 0x1463 0x1371 0x12da 0x12a0 0x16c1 0x1578 0x1464 0x136f 0x12d9 0x129f 0x16b7 0x1587 0x1466 0x136e 0x12d7 0x129f 0x16b3 0x1587 0x1465 0x136d 0x12d5 0x129e 0x16b1 0x1572 0x145f 0x136d 0x12d4 0x129d 0x16af 0x1563 0x145b 0x136c 0x12d3 0x129d 0x16ae 0x1561 0x145d 0x1369 0x12d2 0x129c 0x16ac 0x1560 0x145e 0x1365 0x12d2 0x129c 0x16ac 0x155f 0x145e 0x1364 0x12d1 0x129c 0x16ae 0x155f 0x145e 0x1363 0x12d1 0x129c 0x16b0 0x155f 0x145e 0x1363 0x12d1 0x129d 0x16b4 0x1563 0x145f 0x1362 0x12d0 0x129c 0x16b9 0x1568 0x1460 0x1361 0x12d0 0x129c 0x16bc 0x1569 0x1461 0x1362 0x12d0 0x129c 0x16bb 0x1569 0x1463 0x1364 0x12d0 0x129d 0x16b9 0x1569 0x1464 0x1365 0x12d1 0x129e 0x16b9 0x156a 0x1466 0x1367 0x12d2 0x129f 0x16b8 0x156e 0x1468 0x1369 0x12d4 0x12a0 0x16b7 0x1572 0x1469 0x136c 0x12d5 0x12a2 0x16b3 0x157c 0x1469 0x136f 0x12d8 0x12a5 0x16af 0x1582 0x1469 0x1371 0x12da 0x12a6 0x16b2 0x157b 0x1468 0x1372 0x12dc 0x12a7 0x16c0 0x1571 0x1468 0x1373 0x12dd 0x12a7 0x16c7 0x156d 0x146a 0x1375 0x12df 0x12a8 0x16bd 0x156b 0x146e 0x1379 0x12e0 0x12ab 0x16ae 0x156b 0x1470 0x137c 0x12e2 0x12ad 0x16ab 0x1573 0x146f 0x1381 0x12e5 0x12ae 0x16b0 0x1582 0x146e 0x1384 0x12e8 0x12b0 0x16b4 0x1585 0x1471 0x1384 0x12ea 0x12b2 0x16b1 0x157a 0x1474 0x1383 0x12ed 0x12b5 0x16aa 0x1571 0x1476 0x1384 0x12ef 0x12b7 0x16a9 0x1572 0x1478 0x138a 0x12f1 0x12b8 0x16ac 0x1574 0x1479 0x138d 0x12f2 0x12b9 0x16ae 0x1575 0x1478 0x138c 0x12f3 0x12ba 0x16ab 0x1575 0x1477 0x138b 0x12f3 0x12bb 0x16a4 0x1577 0x1478 0x138c 0x12f4 0x12bc 0x16a4 0x1577 0x147d 0x1390 0x12f5 0x12bd 0x16bc 0x1576 0x147e 0x1394 0x12f6 0x12be 0x16c5 0x1578 0x147f 0x1399 0x12f7 0x12c1 0x16aa 0x157c 0x1485 0x13a0 0x12fd 0x12c4 0x16c5 0x158f 0x1491 0x13a7 0x1300 0x12c6 0x16d4 0x1597 0x1491 0x13a7 0x1300 0x12c7 0x16e6 0x15a2 0x1499 0x13a7 0x1301 0x12c7 0x16f1 0x15a6 0x149b 0x13a6 0x1304 0x12c7 0x171a 0x15a5 0x1492 0x13ab 0x1301 0x12c8 0x1708 0x15aa 0x14a9 0x13ab 0x1302 0x12ca 0x175a 0x15cd 0x14bc 0x13b5 0x1309 0x12cd 0x177f 0x160e 0x14f4 0x13c5 0x130f 0x12d4 0x17cb 0x162a 0x151f 0x13d9 0x1318 0x12dc 0x17cb 0x162a 0x151f 0x13d9 0x1318 0x12dc 0x17cb 0x162a 0x151f 0x13d9 0x1318 0x12dc>;

};

qcom,pc-temp-y5-lut {

qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;

qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;

qcom,lut-data = <0x3956 0x39ed 0x4452 0x5a3e 0x51bf 0x49a6 0x3b55 0x3bb4 0x44cb 0x55c8 0x4fa5 0x4c20 0x3d43 0x3d82 0x4540 0x50e4 0x4db3 0x4e85 0x3f0f 0x3f35 0x45b0 0x4c2f 0x4c0f 0x508f 0x40a7 0x40ac 0x461b 0x4845 0x4adf 0x51f6 0x41fa 0x41c4 0x4682 0x45c4 0x4a45 0x5275 0x4302 0x42a4 0x46f9 0x4480 0x4a7a 0x5219 0x43e1 0x4348 0x4759 0x438a 0x4acd 0x5154 0x44b1 0x4322 0x4735 0x422e 0x49c6 0x503f 0x454e 0x41cf 0x463f 0x4060 0x467a 0x4e68 0x4632 0x40f1 0x4507 0x3ec2 0x43b3 0x4cb5 0x4af0 0x43b8 0x43a4 0x3c86 0x4203 0x4b38 0x5398 0x4828 0x41e2 0x3a96 0x406c 0x499a 0x55e0 0x4838 0x3f35 0x3ab4 0x3ea7 0x4790 0x4cdd 0x438e 0x3b62 0x3bb7 0x3cb5 0x446a 0x43fe 0x406c 0x39f0 0x3c1c 0x3bfc 0x41a5 0x48b5 0x4a9b 0x3e4e 0x3aaf 0x3c86 0x3f01 0x573a 0x5af4 0x456c 0x3928 0x3d33 0x3d16 0x5d38 0x5d3d 0x4c4f 0x3a18 0x3d05 0x3d25 0x5861 0x5718 0x53db 0x3e1a 0x3c0e 0x3e23 0x52e7 0x52e5 0x5737 0x43e8 0x3c8f 0x3ff1 0x52ca 0x54b4 0x5800 0x50d0 0x4914 0x4925 0x54b2 0x5806 0x585e 0x5b38 0x55b9 0x5282 0x56a6 0x59ac 0x5918 0x58b7 0x54a8 0x5372 0x5899 0x5a99 0x5aea 0x519b 0x4f69 0x5326 0x5a27 0x5b38 0x5ba3 0x4f2f 0x4c69 0x5273 0x561b 0x59b4 0x5acd 0x4f2d 0x4afe 0x50b7 0x435d 0x5558 0x5a1f 0x4f4d 0x49b2 0x4e3f 0x367d 0x4e9b 0x5c17 0x506a 0x475a 0x4ac9 0x3455 0x3dd3 0x6028 0x5292 0x4391 0x4657 0x3322 0x33c5 0x611e 0x53a2 0x426e 0x446a 0x32fa 0x34ee 0x5d4e 0x545b 0x4334 0x43d2 0x3326 0x36fc 0x58d5 0x5564 0x4494 0x438c 0x3371 0x3784 0x5678 0x580b 0x47d6 0x4693 0x3431 0x37b0 0x5492 0x5bc4 0x4d72 0x4ddd 0x356a 0x37f1 0x523e 0x5d7f 0x5221 0x51a5 0x3668 0x387a 0x4ef5 0x5e5f 0x565f 0x5307 0x3765 0x3940 0x4cb0 0x5e3b 0x5966 0x542b 0x37f7 0x3a27 0x4bc0 0x5a23 0x5b01 0x5604 0x37e9 0x3b78 0x4ad4 0x5479 0x5c13 0x5826 0x37b2 0x3c3b 0x4a38 0x5360 0x5c1e 0x590f 0x3737 0x3bd6 0x49d5 0x53cd 0x5b2a 0x5965 0x353f 0x3ae6 0x47cc 0x51d8 0x5a35 0x5a21 0x33c1 0x394d 0x41b7 0x4d02 0x5804 0x5cb0 0x3228 0x3890 0x3cd3 0x49df 0x4b8d 0x4dbd 0x32aa 0x36a6 0x39f4 0x4b6e 0x4d2e 0x496e 0x32b7 0x36cd 0x396d 0x4d24 0x495b 0x4246 0x32f5 0x373e 0x36f4 0x4a75 0x44d3 0x3d59 0x336b 0x36b3 0x38fe 0x48ca 0x4102 0x3b81 0x3428 0x370c 0x387f 0x4795 0x3fbe 0x39db 0x32c0 0x37ad 0x380c 0x472c 0x404e 0x3fd8 0x2b6e 0x3032 0x360f 0x4a23 0x43c7 0x3e37 0x2655 0x2694 0x324e 0x4889 0x46ef 0x3ed2 0x2442 0x23ae 0x2540 0x4791 0x51a6 0x4e27 0x2442 0x23ae 0x2540 0x4791 0x51a6 0x4e27 0x2442 0x23ae 0x2540 0x4791 0x51a6 0x4e27>;

};

};

};

jtagmm@7440000 {

clock-names = "core_clk";

reg-names = "etm-base";

clocks = <0x19 0x00>;

compatible = "qcom,jtagv8-mm";

qcom,coresight-jtagmm-cpu = <0x15>;

reg = <0x7440000 0x1000>;

phandle = <0x2ac>;

};

interrupt-controller@b220000 {

interrupt-parent = <0x1a>;

compatible = "qcom,pdc-sdmmagpie";

#interrupt-cells = <0x03>;

reg = <0xb220000 0x400>;

phandle = <0x01>;

interrupt-controller;

};

kryo-erp {

interrupts = <0x01 0x06 0x04 0x00 0x23 0x04>;

compatible = "arm,arm64-kryo-cpu-erp";

interrupt-names = "l1-l2-faultirq\0l3-scu-faultirq";

};

qusb@88e2000 {

qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>;

clock-names = "ref_clk_src\0cfg_ahb_clk";

reg-names = "qusb_phy_base\0efuse_addr\0refgen_north_bg_reg_addr";

qcom,qusb-phy-reg-offset = <0x240 0x1a0 0x210 0x230 0xa8 0x254 0x198 0x27c 0x280 0x284 0x288 0x2a0>;

qcom,qusb-phy-init-seq = <0x23 0x210 0x03 0x04 0x7c 0x18c 0x80 0x2c 0x0a 0x184 0x19 0xb4 0x40 0x194 0x16 0x198 0x21 0x214 0x08 0x220 0x58 0x224 0x07 0x240 0x29 0x244 0xca 0x248 0x07 0x24c 0x03 0x250 0x30 0x23c 0x22 0x210>;

phy_type = "utmi";

resets = <0x27 0x09>;

clocks = <0x2f 0x00 0x27 0x97>;

vdd-supply = <0x1a9>;

compatible = "qcom,qusb2phy-v2";

qcom,efuse-bit-pos = <0x19>;

reg = <0x88e2000 0x400 0x780200 0x04 0x88e7014 0x04>;

phandle = <0x25a>;

qcom,efuse-num-bits = <0x03>;

qcom,qusb-phy-host-init-seq = <0x23 0x210 0x03 0x04 0x7c 0x18c 0x80 0x2c 0x0a 0x184 0x19 0xb4 0x40 0x194 0x20 0x198 0x21 0x214 0x00 0x220 0x18 0x224 0x37 0x240 0x29 0x244 0xca 0x248 0x04 0x24c 0x03 0x250 0x00 0x23c 0x22 0x210>;

reset-names = "phy_reset";

vdda33-supply = <0xa5>;

vdda18-supply = <0x1cf>;

};

qcom,wdt@17c10000 {

qcom,bark-time = <0x4e20>;

reg-names = "wdt-base";

qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100 0x10100 0x10100 0x25900 0x25900>;

interrupts = <0x00 0x00 0x00 0x00 0x01 0x00>;

qcom,wakeup-enable;

compatible = "qcom,msm-watchdog";

qcom,ipi-ping;

qcom,pet-time = <0x3a98>;

reg = <0x17c10000 0x1000>;

phandle = <0x2bb>;

};

cti@6867000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-turing";

compatible = "arm,primecell";

reg = <0x6867000 0x1000>;

phandle = <0x46e>;

};

cti@6011000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti1";

compatible = "arm,primecell";

reg = <0x6011000 0x1000>;

phandle = <0x476>;

};

qcom,cpu-llcc-ddr-bw {

qcom,src-dst-ports = <0x81 0x200>;

governor = "performance";

compatible = "qcom,devbw";

phandle = <0xbf>;

qcom,active-only;

operating-points-v2 = <0xbe>;

};

demux {

compatible = "qcom,demux";

};

qcom,jpegenc@ac4e000 {

clock-names = "jpegenc_clk_src\0jpegenc_clk";

reg-names = "jpege_hw";

reg-cam-base = <0x4e000>;

cell-index = <0x00>;

camss-vdd-supply = <0x1ae>;

interrupts = <0x00 0x1da 0x00>;

clocks = <0x29 0x4d 0x29 0x4c>;

clock-cntl-level = "nominal";

compatible = "qcom,cam_jpeg_enc";

src-clock-name = "jpegenc_clk_src";

status = "ok";

interrupt-names = "jpeg";

reg = <0xac4e000 0x4000>;

regulator-names = "camss-vdd";

phandle = <0x397>;

clock-rates = <0x23c34600 0x00>;

};

simtray {

compatible = "xiaomi,simtray-status";

status-gpio = <0x174 0x52 0x00>;

};

qcom,msm-lsm-client {

compatible = "qcom,msm-lsm-client";

phandle = <0x267>;

};

tpda@7862000 {

arm,primecell-periphid = <0x3b969>;

clock-names = "apb_pclk";

reg-names = "tpda-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpda-apss";

qcom,dsb-elem-size = <0x00 0x20>;

compatible = "arm,primecell";

qcom,tpda-atid = <0x42>;

reg = <0x7862000 0x1000>;

phandle = <0x435>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x20b>;

phandle = <0x207>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x20c>;

phandle = <0x20d>;

};

};

};

};

ssphy@88e8000 {

qcom,vbus-valid-override;

qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>;

clock-names = "aux_clk\0pipe_clk\0ref_clk_src\0ref_clk\0com_aux_clk\0cfg_ahb_clk";

reg-names = "qmp_phy_base";

resets = <0x27 0x05 0x27 0x07>;

clocks = <0x27 0x93 0x27 0x96 0x2f 0x00 0x27 0x92 0x27 0x95 0x27 0x97>;

extcon = <0x25b>;

vdd-supply = <0x1a9>;

qcom,qmp-phy-reg-offset = <0x1d74 0x1cd8 0x1cdc 0x1c04 0x1c00 0x1c08 0xffff 0x2a18 0x08 0x04 0x1c 0x00 0x10 0x0c 0x1a0c>;

compatible = "qcom,usb-ssphy-qmp-dp-combo";

status = "disabled";

reg = <0x88e8000 0x3000>;

phandle = <0x25d>;

reset-names = "global_phy_reset\0phy_reset";

qcom,qmp-phy-init-seq = <0x1048 0x07 0x00 0x1080 0x14 0x00 0x1034 0x08 0x00 0x1138 0x30 0x00 0x103c 0x02 0x00 0x108c 0x08 0x00 0x115c 0x16 0x00 0x1164 0x01 0x00 0x113c 0x80 0x00 0x10b0 0x82 0x00 0x10b8 0xab 0x00 0x10bc 0xea 0x00 0x10c0 0x02 0x00 0x1060 0x06 0x00 0x1068 0x16 0x00 0x1070 0x36 0x00 0x10dc 0x00 0x00 0x10d8 0x3f 0x00 0x10f8 0x01 0x00 0x10f4 0xc9 0x00 0x1148 0x0a 0x00 0x10a0 0x00 0x00 0x109c 0x34 0x00 0x1098 0x15 0x00 0x1090 0x04 0x00 0x1154 0x00 0x00 0x1094 0x00 0x00 0x10f0 0x00 0x00 0x1040 0x0a 0x00 0x1010 0x01 0x00 0x101c 0x31 0x00 0x1020 0x01 0x00 0x1014 0x00 0x00 0x1018 0x00 0x00 0x1024 0x85 0x00 0x1028 0x07 0x00 0x1430 0x0b 0x00 0x14d4 0x0f 0x00 0x14d8 0x4e 0x00 0x14dc 0x18 0x00 0x14f8 0x77 0x00 0x14fc 0x80 0x00 0x1504 0x03 0x00 0x150c 0x16 0x00 0x1564 0x05 0x00 0x14c0 0x03 0x00 0x1830 0x0b 0x00 0x18d4 0x0f 0x00 0x18d8 0x4e 0x00 0x18dc 0x18 0x00 0x18f8 0x77 0x00 0x18fc 0x80 0x00 0x1904 0x03 0x00 0x190c 0x16 0x00 0x1964 0x05 0x00 0x18c0 0x03 0x00 0x1260 0x10 0x00 0x12a4 0x12 0x00 0x128c 0x16 0x00 0x1248 0x09 0x00 0x1244 0x06 0x00 0x1660 0x10 0x00 0x16a4 0x12 0x00 0x168c 0x16 0x00 0x1648 0x09 0x00 0x1644 0x06 0x00 0x1cc8 0x83 0x00 0x1ccc 0x09 0x00 0x1cd0 0xa2 0x00 0x1cd4 0x40 0x00 0x1cc4 0x02 0x00 0x1c80 0xd1 0x00 0x1c84 0x1f 0x00 0x1c88 0x47 0x00 0x1c64 0x1b 0x00 0x1434 0x75 0x00 0x1834 0x75 0x00 0x1dd8 0xba 0x00 0x1c0c 0x9f 0x00 0x1c10 0x9f 0x00 0x1c14 0xb7 0x00 0x1c18 0x4e 0x00 0x1c1c 0x65 0x00 0x1c20 0x6b 0x00 0x1c24 0x15 0x00 0x1c28 0x0d 0x00 0x1c2c 0x15 0x00 0x1c30 0x0d 0x00 0x1c34 0x15 0x00 0x1c38 0x0d 0x00 0x1c3c 0x15 0x00 0x1c40 0x1d 0x00 0x1c44 0x15 0x00 0x1c48 0x0d 0x00 0x1c4c 0x15 0x00 0x1c50 0x0d 0x00 0x1e0c 0x21 0x00 0x1e10 0x60 0x00 0x1c5c 0x02 0x00 0x1ca0 0x04 0x00 0x1c8c 0x44 0x00 0x1c70 0xe7 0x00 0x1c74 0x03 0x00 0x1c78 0x40 0x00 0x1c7c 0x00 0x00 0x1cb8 0x75 0x00 0x1cb0 0x86 0x00 0x1cbc 0x13 0x00 0x1cac 0x04 0x00 0xffffffff 0xffffffff 0x00>;

core-supply = <0x1a8>;

};

qcom,msm_npu@9800000 {

iommus = <0x30 0x1461 0x00>;

clock-names = "qdss_clk\0armwic_core_clk\0cal_dp_clk\0cal_dp_cdc_clk\0conf_noc_ahb_clk\0comp_noc_axi_clk\0npu_core_clk\0npu_core_cti_clk\0npu_core_apb_clk\0npu_core_atb_clk\0npu_cpc_clk\0npu_cpc_timer_clk\0qtimer_core_clk\0sleep_clk\0bwmon_clk\0perf_cnt_clk\0bto_core_clk\0xo_clk";

reg-names = "tcm\0core\0bwmon\0qfprom_physical";

interrupts = <0x00 0x247 0x01 0x00 0x249 0x01 0x00 0x24b 0x01>;

clocks = <0x19 0x00 0x2c 0x04 0x2c 0x08 0x2c 0x07 0x2c 0x0b 0x2c 0x0a 0x2c 0x0e 0x2c 0x10 0x2c 0x0c 0x2c 0x0d 0x2c 0x11 0x2c 0x12 0x2c 0x14 0x2c 0x15 0x2c 0x06 0x2c 0x13 0x2c 0x05 0x2c 0x16>;

vdd-supply = <0x23>;

compatible = "qcom,msm-npu";

qcom,vdd_cx-uV-uA = <0x181 0x186a0>;

interrupt-names = "error_irq\0wdg_bite_irq\0ipc_irq";

reg = <0x9800000 0x40000 0x9900000 0x10000 0x9960200 0x600 0x780000 0x7000>;

phandle = <0x79>;

mboxes = <0x2a5 0x00 0x2a6 0x00>;

cache-slices = <0x1a7 0x17>;

vdd_cx-supply = <0x1d>;

qcom,proxy-reg-names = "vdd\0vdd_cx";

qcom,npubw-dev = <0xc8>;

qcom,npu-cxlimit-enable;

mbox-names = "npu_low\0npu_high";

#cooling-cells = <0x02>;

cache-slice-names = "npu";

qcom,npu-pwrlevels {

#address-cells = <0x01>;

#size-cells = <0x00>;

initial-pwrlevel = <0x04>;

compatible = "qcom,npu-pwrlevels";

qcom,npu-pwrlevel@3 {

clk-freq = <0x00 0x11e1a300 0x23c34600 0x23c34600 0x47868c0 0x18054ac0 0x11e1a300 0x8f0d180 0x124f800 0xe4e1c00 0x11e1a300 0x124f800 0x124f800 0x00 0x124f800 0x23c34600 0x124f800 0x124f800>;

vreg = <0x04>;

reg = <0x03>;

};

qcom,npu-pwrlevel@1 {

clk-freq = <0x00 0x8f0d180 0x17d78400 0x17d78400 0x23c3460 0xbebc200 0x8f0d180 0x47868c0 0x124f800 0x7270e00 0x8f0d180 0x124f800 0x124f800 0x00 0x124f800 0x17d78400 0x124f800 0x124f800>;

vreg = <0x02>;

reg = <0x01>;

};

qcom,npu-pwrlevel@4 {

clk-freq = <0x00 0x17d78400 0x29b92700 0x29b92700 0x47868c0 0x1fc4ef40 0x17d78400 0x8f0d180 0x124f800 0x11e1a300 0x17d78400 0x124f800 0x124f800 0x00 0x124f800 0x29b92700 0x124f800 0x124f800>;

vreg = <0x06>;

reg = <0x04>;

};

qcom,npu-pwrlevel@2 {

clk-freq = <0x00 0xbebc200 0x1bce39a0 0x1bce39a0 0x23c3460 0x11e1a300 0xbebc200 0x47868c0 0x124f800 0x7270e00 0xbebc200 0x124f800 0x124f800 0x00 0x124f800 0x1bce39a0 0x124f800 0x124f800>;

vreg = <0x03>;

reg = <0x02>;

};

qcom,npu-pwrlevel@0 {

clk-freq = <0x00 0x5f5e100 0x11e1a300 0x11e1a300 0x1c9c380 0x8f0d180 0x5f5e100 0x23c3460 0x124f800 0x3938700 0x5f5e100 0x124f800 0x124f800 0x00 0x124f800 0x11e1a300 0x124f800 0x124f800>;

vreg = <0x01>;

reg = <0x00>;

};

};

};

qcom,msm-tert-auxpcm {

qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;

qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;

qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;

qcom,msm-auxpcm-interface = "tertiary";

qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;

qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;

qcom,msm-cpudai-afe-clk-ver = <0x02>;

qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;

compatible = "qcom,msm-auxpcm-dev";

qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;

phandle = <0x273>;

qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;

};

qcom,msm-transcode-loopback {

compatible = "qcom,msm-transcode-loopback";

phandle = <0x48b>;

};

qcom,dsi-display@8 {

qcom,dsi-phy-num = <0x00 0x01>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x52a>;

qcom,dsi-ctrl-num = <0x00 0x01>;

qcom,display-type = "primary";

label = "dsi_dual_sim_dsc_375_cmd_display";

phandle = <0x547>;

};

cti@69a4000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-wcss_cti0";

compatible = "arm,primecell";

status = "disabled";

reg = <0x69a4000 0x1000>;

phandle = <0x46a>;

};

qcom,ion {

#address-cells = <0x01>;

#size-cells = <0x00>;

compatible = "qcom,msm-ion";

qcom,ion-heap@13 {

memory-region = <0x1c2>;

qcom,ion-heap-type = "DMA";

reg = <0x0d>;

};

qcom,ion-heap@14 {

qcom,ion-heap-type = "SECURE_CARVEOUT";

reg = <0x0e>;

cdsp {

memory-region = <0x1c4>;

token = <0x20000000>;

};

};

qcom,ion-heap@10 {

memory-region = <0x1c3>;

qcom,ion-heap-type = "HYP_CMA";

reg = <0x0a>;

};

qcom,ion-heap@9 {

qcom,ion-heap-type = "SYSTEM_SECURE";

reg = <0x09>;

};

qcom,ion-heap@19 {

memory-region = <0x1c1>;

qcom,ion-heap-type = "DMA";

reg = <0x13>;

};

qcom,ion-heap@27 {

memory-region = <0x9a>;

qcom,ion-heap-type = "DMA";

reg = <0x1b>;

};

qcom,ion-heap@25 {

qcom,ion-heap-type = "SYSTEM";

reg = <0x19>;

phandle = <0x39b>;

};

};

dbu1 {

enable-active-high;

regulator-name = "dbu1";

startup-delay-us = <0x00>;

compatible = "regulator-fixed";

phandle = <0x512>;

};

rpmh-regulator-ldoc9 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoc9";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150l-l9 {

regulator-max-microvolt = <0x328980>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x2d0370>;

regulator-min-microvolt = <0x2d0370>;

regulator-name = "pm6150l_l9";

qcom,set = <0x03>;

phandle = <0x413>;

};

};

qcom,msm-adsp-loader {

qcom,adsp-state = <0x00>;

compatible = "qcom,adsp-loader";

status = "ok";

};

syscon@0x5091508 {

compatible = "syscon";

reg = <0x5091508 0x04>;

phandle = <0xcd>;

};

qcom,gdsc@17d044 {

qcom,no-status-check-on-disable;

qcom,gds-timeout = <0x1f4>;

regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x17d044 0x04>;

phandle = <0x1ca>;

};

qcom,gpi-dma@0xa00000 {

iommus = <0x30 0x4d6 0x00>;

qcom,gpii-mask = <0x0f>;

qcom,smmu-cfg = <0x01>;

reg-names = "gpi-top";

interrupts = <0x00 0x117 0x00 0x00 0x118 0x00 0x00 0x119 0x00 0x00 0x11a 0x00 0x00 0x11b 0x00 0x00 0x11c 0x00 0x00 0x125 0x00 0x00 0x126 0x00>;

qcom,ev-factor = <0x02>;

qcom,iova-range = <0x00 0x100000 0x00 0x100000>;

compatible = "qcom,gpi-dma";

status = "ok";

qcom,max-num-gpii = <0x08>;

reg = <0xa00000 0x60000>;

phandle = <0x183>;

#dma-cells = <0x05>;

};

qcom,msm-dai-q6-meta-mi2s-sec {

qcom,msm-dai-q6-meta-mi2s-dev-id = <0x1302>;

qcom,msm-mi2s-rx-lines = <0xff 0x0f 0x03 0x03>;

qcom,msm-mi2s-member-id = <0x00 0x01 0x02 0x03>;

qcom,msm-mi2s-num-members = <0x04>;

compatible = "qcom,msm-dai-q6-meta-mi2s";

phandle = <0x494>;

};

rpmh-regulator-bobc1 {

qcom,mode-threshold-currents = <0x00 0xf4240 0x1e8480>;

qcom,regulator-type = "pmic5-bob";

qcom,send-defaults;

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "bobc1";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x00 0x02 0x04>;

regulator-pm6150l-bob-ao {

regulator-max-microvolt = <0x3c6cc0>;

qcom,init-mode = <0x03>;

qcom,init-voltage = <0x324b00>;

regulator-min-microvolt = <0x324b00>;

regulator-name = "pm6150l_bob_ao";

qcom,set = <0x01>;

phandle = <0x416>;

};

regulator-pm6150l-bob {

regulator-max-microvolt = <0x3c6cc0>;

qcom,init-mode = <0x00>;

qcom,init-voltage = <0x324b00>;

regulator-min-microvolt = <0x324b00>;

regulator-name = "pm6150l_bob";

qcom,set = <0x03>;

phandle = <0x415>;

};

};

qcom,msm-dai-q6-hdmi_ms {

compatible = "qcom,msm-dai-q6-hdmi";

qcom,msm-dai-q6-dev-id = <0x6002>;

phandle = <0x48e>;

};

rpmh-regulator-smpf2 {

compatible = "qcom,rpmh-xob-regulator";

qcom,resource-name = "smpf2";

mboxes = <0x1b 0x00>;

regulator-pm8009-s2 {

regulator-max-microvolt = <0x2c4020>;

regulator-min-microvolt = <0x2c4020>;

regulator-name = "pm8009_s2";

qcom,set = <0x03>;

phandle = <0x401>;

};

};

qcom,gdsc@ad08004 {

qcom,poll-cfg-gdscr;

clock-names = "ahb_clk";

qcom,support-hw-trigger;

clocks = <0x27 0x0e>;

regulator-name = "ipe_0_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0xad08004 0x04>;

phandle = <0x1b9>;

};

rpmh-regulator-ldof7 {

compatible = "qcom,rpmh-xob-regulator";

qcom,resource-name = "ldof7";

mboxes = <0x1b 0x00>;

regulator-pm8009-l7 {

regulator-max-microvolt = <0x1b7740>;

regulator-min-microvolt = <0x1b7740>;

regulator-name = "pm8009_l7";

qcom,set = <0x03>;

phandle = <0x41c>;

};

};

qcom,rpmh {

#clock-cells = <0x01>;

compatible = "qcom,rpmh-clk-sdmmagpie";

phandle = <0x2f>;

mboxes = <0x1b 0x00>;

mbox-names = "apps";

};

qcom,mdss_dsi_g7b_42_02_0b_dsc_video {

qcom,mdss-pan-physical-width-dimension = <0x44>;

qcom,mdss-dsi-panel-name = "xiaomi 42 02 0b video mode dsc dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x88>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-underflow-color = <0x00>;

qcom,mdss-dsi-t-clk-post = <0x0e>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-panel-id = <0x00>;

qcom,mdss-dsi-pan-enable-smart-fps;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-panel-max-luminance = <0x0f 0x20>;

qcom,bl-update-flag = "delay_until_first_frame";

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,mdss-dsi-panel-xy-coordinate = <0x0f 0x18>;

qcom,mdss-dsi-panel-max-luminance-valid = <0x01 0x01>;

qcom,dispparam-enabled;

qcom,mdss-dsi-panel-peak-brightness = <0x401640>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-pan-enable-dynamic-fps;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x00 0x0a 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,mdss-dsi-lane-0-state;

qcom,dsi-supported-dfps-list = <0x1e 0x3c 0x5a 0x78>;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-panel-on-dimming-delay = <0x78>;

qcom,mdss-dsi-t-clk-pre = <0x34>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,cont-splash-enabled;

qcom,mdss-dsi-panel-model = "xiaomi 42 02 0b VIDEO PANEL";

phandle = <0x535>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-bpp = <0x18>;

qcom,disp-panel-offon-mode-enabled;

qcom,mdss-brightness-max-level = <0xfff>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x01 0x01>;

qcom,mdss-dsi-panel-framerate = <0x78>;

qcom,mdss-dsi-h-pulse-width = <0x0c>;

qcom,compression-mode = "dsc";

qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode";

qcom,mdss-dsi-panel-height = <0x924>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x10150100 0x02 0xfb011501 0x00 0x2fb0139 0x1000000 0x3c21b 0xa0150100 0x02 0xff201501 0x00 0x2fb0115 0x1000000 0x2fb01 0x15010000 0x206 0x50150100 0x02 0x7281501 0x00 0x269ea15 0x1000000 0x295d1 0x15010000 0x296 0xd1150100 0x02 0x890c1501 0x00 0x28a0c15 0x1000000 0x2ff24 0x15010000 0x2fb 0x1150100 0x02 0xfb011501 0x00 0x2012115 0x1000000 0x20221 0x15010000 0x203 0x10150100 0x02 0x4241501 0x00 0x2070115 0x1000000 0x2080b 0x15010000 0x20a 0xc150100 0x02 0xb0f1501 0x00 0x20c2215 0x1000000 0x20d2c 0x15010000 0x20e 0x2e150100 0x02 0xf301501 0x00 0x2103215 0x1000000 0x21217 0x15010000 0x213 0x17150100 0x02 0x14151501 0x00 0x2151515 0x1000000 0x21613 0x15010000 0x217 0x13150100 0x02 0x19211501 0x00 0x21b1015 0x1000000 0x21c24 0x15010000 0x21d 0x21150100 0x02 0x1f011501 0x00 0x2200b15 0x1000000 0x2220c 0x15010000 0x223 0xf150100 0x02 0x24221501 0x00 0x2252d15 0x1000000 0x2262f 0x15010000 0x227 0x31150100 0x02 0x28331501 0x00 0x22a1715 0x1000000 0x22b17 0x15010000 0x22d 0x15150100 0x02 0x2f151501 0x00 0x2301315 0x1000000 0x23113 0x15010000 0x232 0x5150100 0x02 0x33031501 0x00 0x2340315 0x1000000 0x23501 0x15010000 0x236 0x3c150100 0x02 0x4e3b1501 0x00 0x24f3b15 0x1000000 0x2533b 0x15010000 0x279 0x22150100 0x02 0x7b901501 0x00 0x27d0315 0x1000000 0x28003 0x15010000 0x281 0x3150100 0x02 0x82131501 0x00 0x2843115 0x1000000 0x28504 0x15010000 0x286 0x4150100 0x02 0x87041501 0x00 0x2901315 0x1000000 0x29231 0x15010000 0x293 0x4150100 0x02 0x94041501 0x00 0x2950415 0x1000000 0x29cf4 0x15010000 0x29d 0x1150100 0x02 0xa0101501 0x00 0x2a21015 0x1000000 0x2a403 0x15010000 0x2a5 0x3150100 0x02 0xc90c1501 0x00 0x2d13415 0x1000000 0x2d980 0x15010000 0x2ff 0x25150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x2665d 0x15010000 0x267 0x10150100 0x02 0x68581501 0x00 0x2691015 0x1000000 0x26b00 0x15010000 0x271 0x6d150100 0x02 0x77721501 0x00 0x27e2d15 0x1000000 0x28100 0x15010000 0x284 0x78150100 0x02 0x85751501 0x00 0x28d0015 0x1000000 0x2c1a9 0x15010000 0x2c2 0x5a150100 0x02 0xc3071501 0x00 0x2ef0815 0x1000000 0x2f114 0x15010000 0x2ff 0x26150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x20010 0x15010000 0x201 0x7c150100 0x02 0x3001501 0x00 0x2047c15 0x1000000 0x20508 0x15010000 0x206 0x21150100 0x02 0x8211501 0x00 0x2140215 0x1000000 0x21501 0x15010000 0x274 0xaf150100 0x02 0x81101501 0x00 0x2830415 0x1000000 0x28402 0x15010000 0x285 0x1150100 0x02 0x86021501 0x00 0x2870115 0x1000000 0x28806 0x15010000 0x28a 0x1a150100 0x02 0x8b111501 0x00 0x28c2415 0x1000000 0x28e42 0x15010000 0x28f 0x11150100 0x02 0x90111501 0x00 0x2911115 0x1000000 0x29a80 0x15010000 0x29b 0x42150100 0x02 0x9c001501 0x00 0x29d0015 0x1000000 0x29e00 0x15010000 0x2ff 0x27150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x22081 0x15010000 0x221 0x82150100 0x02 0x25811501 0x00 0x226ab15 0x1000000 0x26e12 0x15010000 0x26f 0x150100 0x02 0x70001501 0x00 0x2710015 0x1000000 0x27200 0x15010000 0x273 0x76150100 0x02 0x74101501 0x00 0x2753215 0x1000000 0x27654 0x15010000 0x277 0x150100 0x02 0x7d091501 0x00 0x27e2715 0x1000000 0x28027 0x15010000 0x282 0x9150100 0x02 0x83271501 0x00 0x2880315 0x1000000 0x28903 0x15010000 0x2ff 0x2a150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x20607 0x15010000 0x20a 0x60150100 0x02 0x15071501 0x00 0x216c315 0x1000000 0x21a40 0x15010000 0x21b 0xa150100 0x02 0x1d0a1501 0x00 0x21e4215 0x1000000 0x21f42 0x15010000 0x220 0x42150100 0x02 0x37701501 0x00 0x2444c15 0x1000000 0x24af0 0x15010000 0x24e 0x4150100 0x02 0x4f041501 0x00 0x2574315 0x1000000 0x25843 0x15010000 0x259 0x43150100 0x02 0x621c1501 0x00 0x2634c15 0x1000000 0x2794c 0x15010000 0x27a 0x9150100 0x02 0x7c011501 0x00 0x27ff015 0x1000000 0x28304 0x15010000 0x284 0x4150100 0x02 0x8c431501 0x00 0x28d4315 0x1000000 0x28e43 0x15010000 0x297 0x1c150100 0x02 0x984c1501 0x00 0x2a9a015 0x1000000 0x2dea0 0x15010000 0x2ff 0x2c150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x2030f 0x15010000 0x204 0xf150100 0x02 0x50f1501 0x00 0x20d0115 0x1000000 0x20e3c 0x15010000 0x217 0x3b150100 0x02 0x183b1501 0x00 0x2193b15 0x1000000 0x22f10 0x15010000 0x230 0x40150100 0x02 0x32001501 0x00 0x2334015 0x1000000 0x23521 0x15010000 0x237 0x21150100 0x02 0x3a011501 0x00 0x23b0115 0x1000000 0x24d0f 0x15010000 0x24e 0x4150100 0x02 0x4f0a1501 0x00 0x2560f15 0x1000000 0x2580f 0x15010000 0x259 0xf150100 0x02 0x61011501 0x00 0x2623c15 0x1000000 0x26b3b 0x15010000 0x26c 0x3b150100 0x02 0x6d3b1501 0x00 0x2811015 0x1000000 0x28240 0x15010000 0x284 0x150100 0x02 0x85401501 0x00 0x2872115 0x1000000 0x28921 0x15010000 0x28c 0x1150100 0x02 0x8d011501 0x00 0x29d0f15 0x1000000 0x29e04 0x15010000 0x29f 0xa150100 0x02 0xffe01501 0x00 0x2fb0115 0x1000000 0x2fb01 0x15010000 0x2ff 0xf0150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x2ffd0 0x15010000 0x2fb 0x1150100 0x02 0xfb011501 0x00 0x2ff2015 0x1000000 0x2fb01 0x15010000 0x2fb 0x1390100 0x11 0xb0000000 0x17003a00 0x55006d00 0x81009400 0xa5390100 0x11 0xb100b500 0xea011101 0x50017e01 0xca020302 0x5390100 0x11 0xb2023e02 0x7f02ac02 0xe3030903 0x37034703 0x56390100 0x0d 0xb3036903 0x7f039b03 0xbb03d403 0xd8390100 0x11 0xb4000000 0x17003a00 0x55006d00 0x81009400 0xa5390100 0x11 0xb500b500 0xea011101 0x50017e01 0xca020302 0x5390100 0x11 0xb6023e02 0x7f02ac02 0xe3030903 0x37034703 0x56390100 0x0d 0xb7036903 0x7f039b03 0xbb03d403 0xd8390100 0x11 0xb8000000 0x17003a00 0x55006d00 0x81009400 0xa5390100 0x11 0xb900b500 0xea011101 0x50017e01 0xca020302 0x5390100 0x11 0xba023e02 0x7f02ac02 0xe3030903 0x37034703 0x56390100 0x0d 0xbb036903 0x7f039b03 0xbb03d403 0xd8150100 0x02 0xff211501 0x00 0x2fb0115 0x1000000 0x2fb01 0x39010000 0x11b0 0x17 0x3a0055 0x6d0081 0x9400a5 0x39010000 0x11b1 0xb500ea 0x1110150 0x17e01ca 0x2030205 0x39010000 0x11b2 0x23e027f 0x2ac02e3 0x3090337 0x3470356 0x39010000 0xdb3 0x369037f 0x39b03bb 0x3d403d8 0x39010000 0x11b4 0x17 0x3a0055 0x6d0081 0x9400a5 0x39010000 0x11b5 0xb500ea 0x1110150 0x17e01ca 0x2030205 0x39010000 0x11b6 0x23e027f 0x2ac02e3 0x3090337 0x3470356 0x39010000 0xdb7 0x369037f 0x39b03bb 0x3d403d8 0x39010000 0x11b8 0x17 0x3a0055 0x6d0081 0x9400a5 0x39010000 0x11b9 0xb500ea 0x1110150 0x17e01ca 0x2030205 0x39010000 0x11ba 0x23e027f 0x2ac02e3 0x3090337 0x3470356 0x39010000 0xdbb 0x369037f 0x39b03bb 0x3d403d8 0x15010000 0x2ff 0x10150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x251ff 0x15010000 0x253 0x2c150100 0x02 0x55010501 0x7800 0x2110005 0x1000000 0x22900>;

qcom,mdss-dsi-h-front-porch = <0x64>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x78>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x14>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x220809 0x25230909 0x6020400>;

qcom,mdss-dsi-v-back-porch = <0x08>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x02>;

qcom,mdss-dsi-h-sync-pulse = <0x01>;

qcom,mdss-dsc-scr-version = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 46 00 02 10 00];

qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode";

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-v-front-porch = <0x0a>;

qcom,mdss-dsi-displayoff-command = [05 01 00 00 20 00 02 28 00];

qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00];

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

qcom,mdss-dsc-version = <0x11>;

};

};

};

qcom,msm-quat-auxpcm {

qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;

qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;

qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;

qcom,msm-auxpcm-interface = "quaternary";

qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;

qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;

qcom,msm-cpudai-afe-clk-ver = <0x02>;

qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;

compatible = "qcom,msm-auxpcm-dev";

qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;

phandle = <0x274>;

qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;

};

rx_core_clk {

qcom,codec-ext-clk-src = <0x05>;

#clock-cells = <0x01>;

compatible = "qcom,audio-ref-clk";

phandle = <0x4e3>;

qcom,codec-lpass-clk-id = <0x30e>;

qcom,codec-lpass-ext-clk-freq = <0x1588800>;

};

refgen-regulator@ff1000 {

regulator-enable-ramp-delay = <0x05>;

regulator-name = "refgen";

compatible = "qcom,refgen-regulator";

qcom,proxy-consumer-enable;

reg = <0xff1000 0x60>;

phandle = <0x1af>;

proxy-supply = <0x1af>;

};

qcom,msm-audio-apr {

qcom,subsys-name = "apr_adsp";

compatible = "qcom,msm-audio-apr";

phandle = <0x4ac>;

qcom,msm-audio-ion {

iommus = <0x30 0x1b21 0x00>;

qcom,smmu-enabled;

qcom,smmu-sid-mask = <0x00 0x0f>;

compatible = "qcom,msm-audio-ion";

phandle = <0x4ad>;

qcom,smmu-version = <0x02>;

};

qcom,q6core-audio {

compatible = "qcom,q6core-audio";

phandle = <0x4ae>;

bolero-cdc {

qcom,num-macros = <0x03>;

slew_rate_val2 = <0x0f 0x00>;

qcom,va-without-decimation;

slew_rate_reg2 = <0x62b6f004 0x00>;

compatible = "qcom,bolero-codec";

slew_rate_val1 = <0x3333 0x00>;

phandle = <0x4af>;

slew_rate_reg1 = <0x62b6f000 0x00>;

wcd937x-codec {

qcom,rx-slave = <0x4ed>;

qcom,cdc-vddpx-1-voltage = <0x1b7740 0x1b7740>;

qcom,cdc-vdd-mic-bias-voltage = <0x324b00 0x324b00>;

qcom,cdc-vddpx-1-current = <0x2710>;

qcom,cdc-vdd-mic-bias-current = <0x61a8>;

qcom,wcd-rst-gpio-node = <0x4ec>;

qcom,tx-slave = <0x4ee>;

qcom,tx_swr_ch_map = <0x00 0x12 0x01 0x00 0x12 0x01 0x13 0x01 0x00 0x14 0x01 0x14 0x02 0x00 0x15 0x02 0x16 0x01 0x00 0x16 0x02 0x17 0x02 0x00 0x17 0x02 0x11 0x04 0x00 0x18 0x03 0x18 0x01 0x00 0x1a 0x03 0x19 0x02 0x00 0x1b 0x03 0x1a 0x04 0x00 0x1c 0x03 0x1b 0x08 0x00 0x1d>;

qcom,cdc-micbias2-mv = <0xabe>;

cdc-vdd-ldo-rxtx-supply = <0x31>;

qcom,rx_swr_ch_map = <0x00 0x09 0x01 0x00 0x09 0x00 0x0a 0x02 0x00 0x0a 0x01 0x0d 0x01 0x00 0x0d 0x02 0x0b 0x01 0x00 0x0b 0x02 0x0c 0x02 0x00 0x0c 0x03 0x0e 0x01 0x00 0x0e 0x04 0x0f 0x01 0x00 0x0f 0x04 0x10 0x02 0x00 0x10>;

cdc-vdd-buck-supply = <0x40a>;

qcom,cdc-vdd-ldo-rxtx-voltage = <0x1b7740 0x1b7740>;

qcom,cdc-static-supplies = "cdc-vdd-ldo-rxtx\0cdc-vddpx-1\0cdc-vdd-mic-bias";

qcom,cdc-vdd-ldo-rxtx-current = <0x61a8>;

qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>;

compatible = "qcom,wcd937x-codec";

qcom,cdc-vdd-buck-current = <0x9eb10>;

cdc-vdd-mic-bias-supply = <0x415>;

qcom,cdc-micbias1-mv = <0xabe>;

cdc-vddpx-1-supply = <0x31>;

phandle = <0x4f5>;

qcom,cdc-on-demand-supplies = "cdc-vdd-buck";

qcom,cdc-micbias3-mv = <0xabe>;

};

rx-macro@62ee0000 {

clock-names = "rx_core_clk\0rx_npl_clk";

clocks = <0x4e3 0x00 0x4e4 0x00>;

qcom,rx_mclk_mode_muxsel = <0x62c25020>;

compatible = "qcom,rx-macro";

reg = <0x62ee0000 0x00>;

qcom,rx-bcl-pmic-params = [00 00 1e];

phandle = <0x594>;

qcom,rx-swr-gpios = <0x4e5>;

rx_swr_master {

qcom,swr-clock-stop-mode0 = <0x01>;

#address-cells = <0x02>;

qcom,swr-num-dev = <0x01>;

interrupts = <0x00 0x129 0x00>;

swrm-io-base = <0x62ef0000 0x00>;

#size-cells = <0x00>;

qcom,swr_master_id = <0x02>;

compatible = "qcom,swr-mstr";

interrupt-names = "swr_master_irq";

qcom,swr-port-mapping = <0x01 0x09 0x01 0x01 0x0a 0x02 0x02 0x0d 0x01 0x03 0x0b 0x01 0x03 0x0c 0x02 0x04 0x0e 0x01 0x05 0x0f 0x01 0x05 0x10 0x02>;

phandle = <0x595>;

qcom,swr-num-ports = <0x05>;

wcd937x-rx-slave {

compatible = "qcom,wcd937x-slave";

reg = <0x00 0x1170224>;

phandle = <0x4ed>;

};

};

};

wsa-macro@62f00000 {

qcom,wsa-swr-gpios = <0x4e8>;

clock-names = "wsa_core_clk\0wsa_npl_clk";

clocks = <0x4e6 0x00 0x4e7 0x00>;

qcom,wsa-bcl-pmic-params = [00 00 1e];

compatible = "qcom,wsa-macro";

status = "disabled";

reg = <0x62f00000 0x00>;

phandle = <0x596>;

wsa_swr_master {

#address-cells = <0x02>;

qcom,swr-num-dev = <0x02>;

interrupts = <0x00 0x127 0x00>;

swrm-io-base = <0x62f10000 0x00>;

#size-cells = <0x00>;

qcom,swr_master_id = <0x01>;

compatible = "qcom,swr-mstr";

interrupt-names = "swr_master_irq";

qcom,swr-port-mapping = <0x01 0x01 0x01 0x02 0x03 0x0f 0x03 0x02 0x03 0x04 0x05 0x01 0x05 0x07 0x0f 0x06 0x06 0x03 0x07 0x04 0x03 0x08 0x08 0x03>;

phandle = <0x597>;

qcom,swr-num-ports = <0x08>;

wsa881x@21170213 {

qcom,bolero-handle = <0x4af>;

compatible = "qcom,wsa881x";

reg = <0x00 0x21170213>;

qcom,spkr-sd-n-node = <0x4e9>;

phandle = <0x4f3>;

};

wsa881x@20170212 {

qcom,bolero-handle = <0x4af>;

compatible = "qcom,wsa881x";

reg = <0x00 0x20170212>;

qcom,spkr-sd-n-node = <0x4ea>;

phandle = <0x4f2>;

};

wsa881x@21170214 {

qcom,bolero-handle = <0x4af>;

compatible = "qcom,wsa881x";

reg = <0x00 0x21170214>;

qcom,spkr-sd-n-node = <0x4ea>;

phandle = <0x4f4>;

};

wsa881x@20170211 {

qcom,bolero-handle = <0x4af>;

compatible = "qcom,wsa881x";

reg = <0x00 0x20170211>;

qcom,spkr-sd-n-node = <0x4e9>;

phandle = <0x4f1>;

};

};

};

va-macro@62f20000 {

clock-names = "va_core_clk";

clocks = <0x4eb 0x00>;

compatible = "qcom,va-macro";

reg = <0x62f20000 0x00>;

phandle = <0x598>;

};

tx-macro@62ec0000 {

clock-names = "tx_core_clk\0tx_npl_clk";

clocks = <0x4e0 0x00 0x4e1 0x00>;

qcom,tx-dmic-sample-rate = <0x249f00>;

compatible = "qcom,tx-macro";

reg = <0x62ec0000 0x00>;

phandle = <0x592>;

qcom,tx-swr-gpios = <0x4e2>;

tx_swr_master {

qcom,swr-clock-stop-mode0 = <0x01>;

#address-cells = <0x02>;

qcom,swr-num-dev = <0x01>;

interrupts = <0x00 0x128 0x00 0x00 0x1f4 0x00>;

swrm-io-base = <0x62ed0000 0x00>;

#size-cells = <0x00>;

qcom,swr_master_id = <0x03>;

compatible = "qcom,swr-mstr";

interrupt-names = "swr_master_irq\0swr_wake_irq";

qcom,swr-port-mapping = <0x01 0x21 0x0f 0x02 0x12 0x01 0x02 0x13 0x02 0x03 0x14 0x01 0x03 0x15 0x02 0x04 0x16 0x01 0x04 0x17 0x02 0x04 0x18 0x04 0x04 0x19 0x08 0x05 0x1a 0x01 0x05 0x1b 0x02 0x05 0x1c 0x04 0x05 0x1d 0x08>;

phandle = <0x593>;

qcom,swr-wakeup-required = <0x00>;

qcom,swr-mstr-tx-wakeup-capable;

qcom,swr-mstr-irq-wakeup-capable = <0x01>;

qcom,swr-num-ports = <0x05>;

wcd937x-tx-slave {

compatible = "qcom,wcd937x-slave";

reg = <0x00 0x1170223>;

phandle = <0x4ee>;

};

};

};

};

sound {

qcom,audio-routing = "AMIC2\0MIC BIAS2\0MIC BIAS2\0Analog Mic2\0AMIC1\0MIC BIAS1\0MIC BIAS1\0Analog Mic1\0AMIC3\0MIC BIAS3\0MIC BIAS3\0Analog Mic3\0AMIC4\0MIC BIAS3\0TX_AIF1 CAP\0VA_MCLK\0TX_AIF2 CAP\0VA_MCLK\0RX AIF1 PB\0VA_MCLK\0RX AIF2 PB\0VA_MCLK\0RX AIF3 PB\0VA_MCLK\0RX AIF4 PB\0VA_MCLK\0HPHL_OUT\0VA_MCLK\0HPHR_OUT\0VA_MCLK\0AUX_OUT\0VA_MCLK\0IN1_HPHL\0HPHL_OUT\0IN2_HPHR\0HPHR_OUT\0IN3_AUX\0AUX_OUT\0TX SWR_ADC0\0ADC1_OUTPUT\0TX SWR_ADC2\0ADC2_OUTPUT\0TX SWR_ADC3\0ADC3_OUTPUT\0RX_TX DEC0_INP\0TX DEC0 MUX\0RX_TX DEC1_INP\0TX DEC1 MUX\0RX_TX DEC2_INP\0TX DEC2 MUX\0RX_TX DEC3_INP\0TX DEC3 MUX\0SpkrLeft IN\0WSA_SPK1 OUT\0SpkrRight IN\0WSA_SPK2 OUT\0WSA_SPK1 OUT\0VA_MCLK\0WSA_SPK2 OUT\0VA_MCLK";

qcom,ext-disp-audio-rx = <0x01>;

qcom,msm-mbhc-gnd-swh = <0x01>;

asoc-codec = <0x48c 0x4af 0x376>;

asoc-cpu-names = "msm-dai-q6-dp.24608\0msm-dai-q6-mi2s.0\0msm-dai-q6-mi2s.1\0msm-dai-q6-mi2s.2\0msm-dai-q6-mi2s.3\0msm-dai-q6-mi2s.4\0msm-dai-q6-auxpcm.1\0msm-dai-q6-auxpcm.2\0msm-dai-q6-auxpcm.3\0msm-dai-q6-auxpcm.4\0msm-dai-q6-auxpcm.5\0msm-dai-q6-dev.224\0msm-dai-q6-dev.225\0msm-dai-q6-dev.241\0msm-dai-q6-dev.240\0msm-dai-q6-dev.32771\0msm-dai-q6-dev.32772\0msm-dai-q6-dev.32773\0msm-dai-q6-dev.32770\0msm-dai-q6-dev.16398\0msm-dai-q6-dev.16399\0msm-dai-q6-dev.16401\0msm-dai-q6-dev.16400\0msm-dai-q6-dev.8194\0msm-dai-q6-dev.8195\0msm-dai-q6-dev.28672\0msm-dai-q6-dev.28673\0msm-dai-q6-tdm.36864\0msm-dai-q6-tdm.36865\0msm-dai-q6-tdm.36880\0msm-dai-q6-tdm.36881\0msm-dai-q6-tdm.36896\0msm-dai-q6-tdm.36897\0msm-dai-q6-tdm.36912\0msm-dai-q6-tdm.36913\0msm-dai-q6-tdm.36928\0msm-dai-q6-tdm.36929\0msm-dai-cdc-dma-dev.45056\0msm-dai-cdc-dma-dev.45057\0msm-dai-cdc-dma-dev.45058\0msm-dai-cdc-dma-dev.45059\0msm-dai-cdc-dma-dev.45061\0msm-dai-cdc-dma-dev.45104\0msm-dai-cdc-dma-dev.45105\0msm-dai-cdc-dma-dev.45106\0msm-dai-cdc-dma-dev.45107\0msm-dai-cdc-dma-dev.45108\0msm-dai-cdc-dma-dev.45109\0msm-dai-cdc-dma-dev.45110\0msm-dai-cdc-dma-dev.45111\0msm-dai-cdc-dma-dev.45112\0msm-dai-cdc-dma-dev.45113\0msm-dai-cdc-dma-dev.45114\0msm-dai-cdc-dma-dev.45115\0msm-dai-cdc-dma-dev.45116\0msm-dai-cdc-dma-dev.45118";

qcom,cdc-dmic01-gpios = <0x4ef>;

asoc-codec-names = "msm-stub-codec.1\0bolero_codec\0msm-ext-disp-audio-codec-rx";

qcom,msm_audio_ssr_devs = <0x4ac 0x4ae 0x4f6 0x4af>;

qcom,codec-aux-devs = <0x4f5>;

asoc-cpu = <0x26b 0x26c 0x26d 0x26e 0x26f 0x270 0x271 0x272 0x273 0x274 0x275 0x276 0x277 0x278 0x279 0x27a 0x27b 0x27c 0x27d 0x27e 0x27f 0x280 0x281 0x282 0x283 0x284 0x285 0x286 0x287 0x288 0x289 0x28a 0x28b 0x28c 0x28d 0x28e 0x28f 0x290 0x291 0x292 0x293 0x294 0x295 0x296 0x297 0x298 0x299 0x29a 0x29b 0x29c 0x29d 0x29e 0x29f 0x2a0 0x2a1 0x2a2>;

qcom,msm-mi2s-master = <0x01 0x01 0x01 0x01 0x01>;

qcom,wsa-devs = <0x4f1 0x4f2 0x4f3 0x4f4>;

qcom,model = "sm6150-idp-snd-card";

compatible = "qcom,sm6150-asoc-snd";

qcom,msm-mbhc-hphl-swh = <0x01>;

qcom,pri-mi2s-gpios = <0x513>;

qcom,auxpcm-audio-intf = <0x01>;

phandle = <0x4b7>;

qcom,codec-max-aux-devs = <0x01>;

asoc-platform-names = "msm-pcm-dsp.0\0msm-pcm-dsp.1\0msm-pcm-dsp.2\0msm-voip-dsp\0msm-pcm-voice\0msm-pcm-loopback\0msm-compress-dsp\0msm-pcm-hostless\0msm-pcm-afe\0msm-lsm-client\0msm-pcm-routing\0msm-compr-dsp\0msm-pcm-dsp-noirq";

qcom,mi2s-audio-intf = <0x01>;

qcom,wsa-aux-dev-prefix = "SpkrLeft\0SpkrRight\0SpkrLeft\0SpkrRight";

qcom,wsa-max-devs = <0x00>;

asoc-platform = <0x25e 0x25f 0x260 0x261 0x262 0x263 0x264 0x265 0x266 0x267 0x268 0x269 0x26a>;

qcom,wcn-btfm = <0x01>;

qcom,cdc-dmic23-gpios = <0x4f0>;

};

};

};

qcom,msm-dai-fe {

compatible = "qcom,msm-dai-fe";

};

timer@0x17c20000 {

#address-cells = <0x01>;

#size-cells = <0x01>;

clock-frequency = <0x124f800>;

compatible = "arm,armv7-timer-mem";

ranges;

reg = <0x17c20000 0x1000>;

frame@17c2b000 {

interrupts = <0x00 0x0d 0x04>;

frame-number = <0x05>;

status = "disabled";

reg = <0x17c2b000 0x1000>;

};

frame@17c25000 {

interrupts = <0x00 0x0a 0x04>;

frame-number = <0x02>;

status = "disabled";

reg = <0x17c25000 0x1000>;

};

frame@0x17c21000 {

interrupts = <0x00 0x08 0x04 0x00 0x06 0x04>;

frame-number = <0x00>;

reg = <0x17c21000 0x1000 0x17c22000 0x1000>;

};

frame@17c2d000 {

interrupts = <0x00 0x0e 0x04>;

frame-number = <0x06>;

status = "disabled";

reg = <0x17c2d000 0x1000>;

};

frame@17c27000 {

interrupts = <0x00 0x0b 0x04>;

frame-number = <0x03>;

status = "disabled";

reg = <0x17c27000 0x1000>;

};

frame@17c29000 {

interrupts = <0x00 0x0c 0x04>;

frame-number = <0x04>;

status = "disabled";

reg = <0x17c29000 0x1000>;

};

frame@17c23000 {

interrupts = <0x00 0x09 0x04>;

frame-number = <0x01>;

status = "disabled";

reg = <0x17c23000 0x1000>;

};

};

tpdm@6834000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-modem-1";

compatible = "arm,primecell";

reg = <0x6834000 0x1000>;

phandle = <0x428>;

port {

endpoint {

remote-endpoint = <0x1f0>;

phandle = <0x1ee>;

};

};

};

spi@0xa90000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x19d>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

interrupts = <0x00 0x165 0x00>;

clocks = <0x27 0x5f 0x27 0x69 0x27 0x6a>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x182>;

spi-max-frequency = <0x2faf080>;

dma-names = "tx\0rx";

compatible = "qcom,spi-geni";

pinctrl-1 = <0x19e>;

status = "disabled";

reg = <0xa90000 0x4000>;

phandle = <0x366>;

dmas = <0x183 0x00 0x04 0x01 0x40 0x00 0x183 0x01 0x04 0x01 0x40 0x00>;

};

rpmh-regulator-modemlvl {

compatible = "qcom,rpmh-arc-regulator";

qcom,resource-name = "mss.lvl";

mboxes = <0x1b 0x00>;

regulator-pm6150l-s7 {

regulator-max-microvolt = <0x10000>;

regulator-min-microvolt = <0x11>;

regulator-name = "pm6150l_s7_level";

qcom,init-voltage-level = <0x11>;

qcom,set = <0x03>;

phandle = <0xb0>;

};

};

qcom,gdsc@17d034 {

qcom,no-status-check-on-disable;

qcom,gds-timeout = <0x1f4>;

regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x17d034 0x04>;

phandle = <0x1c6>;

};

qcom,mdss_dsi_xiaomi_f4_42_06_0c_fhd_cmd {

qcom,ulps-enabled;

qcom,disp-doze-backlight-threshold = <0x08>;

qcom,mdss-pan-physical-width-dimension = <0x45>;

qcom,mdss-dsi-panel-name = "xiaomi f4 42 06 0c fhd cmd dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x95>;

qcom,mdss-dsi-te-using-te-pin;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-t-clk-post = <0x0e>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-panel-id = <0x00>;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,bl-update-flag = "delay_until_first_frame";

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,disp-fod-off-dimming-delay = <0x55>;

qcom,dispparam-enabled;

qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-bl-dcs-type-ss-ea;

qcom,mdss-dsi-reset-sequence = <0x00 0x01 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-panel-on-dimming-delay = <0xc8>;

qcom,mdss-dsi-t-clk-pre = <0x33>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,mdss-dsi-te-pin-select = <0x01>;

phandle = <0x53c>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-panel-sleepwrmod = <0x00>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-brightness-max-level = <0x7ff>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x00 0x01>;

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x04>;

qcom,mdss-dsi-panel-jitter = <0x05 0x01>;

qcom,mdss-dsi-panel-height = <0x924>;

qcom,mdss-dsi-on-command = [39 00 00 00 00 00 02 fe 00 39 00 00 00 00 00 02 c2 08 39 00 00 00 00 00 02 35 00 39 01 00 00 00 00 03 51 00 ff 05 01 00 00 78 00 02 11 00 05 01 00 00 00 00 02 29 00];

qcom,mdss-dsi-h-front-porch = <0x1c>;

qcom,mdss-dsi-h-back-porch = <0x24>;

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsi-panel-clockrate = <0x4190ab00>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x04>;

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-phy-timings = <0x220808 0x25220908 0x6020400>;

qcom,mdss-dsi-v-back-porch = <0x04>;

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsi-v-front-porch = <0x08>;

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

};

};

rpmh-regulator-gfxlvl {

compatible = "qcom,rpmh-arc-regulator";

qcom,resource-name = "gfx.lvl";

mboxes = <0x1b 0x00>;

regulator-pm6150-s2-level {

regulator-max-microvolt = <0x10000>;

regulator-min-microvolt = <0x11>;

regulator-name = "pm6150_s2_level";

qcom,init-voltage-level = <0x11>;

qcom,set = <0x03>;

phandle = <0x20>;

};

};

audio_etm0 {

qcom,inst-id = <0x05>;

coresight-name = "coresight-audio-etm0";

compatible = "qcom,coresight-remote-etm";

port {

endpoint {

remote-endpoint = <0x1e3>;

phandle = <0x1e0>;

};

};

};

ufsice@1d90000 {

clock-names = "ufs_core_clk\0bus_clk\0iface_clk\0ice_core_clk";

qcom,bus-vector-names = "MIN\0MAX";

qcom,msm-bus,name = "ufs_ice_noc";

qcom,instance-type = "ufs";

clocks = <0x27 0x7e 0x27 0x7c 0x27 0x7d 0x27 0x81>;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

qcom,op-freq-hz = <0x00 0x00 0x00 0x11e1a300>;

compatible = "qcom,ice";

vdd-hba-supply = <0x9b>;

reg = <0x1d90000 0x8000>;

phandle = <0x2dd>;

qcom,msm-bus,vectors-KBps = <0x01 0x28a 0x00 0x00 0x01 0x28a 0x3e8 0x00>;

qcom,enable-ice-clk;

};

rpmh-regulator-ldoa14 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa14";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l14 {

regulator-max-microvolt = <0x1c5200>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x1a3ec0>;

regulator-min-microvolt = <0x1a3ec0>;

regulator-name = "pm6150_l14";

qcom,set = <0x03>;

phandle = <0x409>;

};

};

qcom,csid-lite0@acc8000 {

camss-supply = <0x1ae>;

clock-control-debugfs = "true";

clock-names = "ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_clk";

reg-names = "csid-lite";

reg-cam-base = <0xc8000>;

cell-index = <0x02>;

interrupts = <0x00 0x1b6 0x00>;

clocks = <0x29 0x42 0x29 0x41 0x29 0x1b 0x29 0x40 0x29 0x3f 0x29 0x3e>;

clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";

compatible = "qcom,csid-lite175";

src-clock-name = "ife_csid_clk_src";

status = "ok";

interrupt-names = "csid-lite";

reg = <0xacc8000 0x1000>;

regulator-names = "camss";

phandle = <0x391>;

clock-rates = <0x11e1a300 0x00 0x00 0x00 0x1312d000 0x00 0x16e36000 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x17d78400 0x00 0x00 0x00 0x23c34600 0x00>;

};

qcom,cpu6-llcc-ddr-latmon {

qcom,cachemiss-ev = <0x1000>;

qcom,core-dev-table = <0xc4c70 0x6b8 0x10b170 0x826 0x1433e0 0xf27 0x1a1300 0x172b 0x253500 0x1ae1>;

qcom,cpulist = <0x17 0x18>;

compatible = "qcom,arm-memlat-mon";

phandle = <0x318>;

qcom,target-dev = <0xc4>;

};

qcom,ipe0 {

ipe0-vdd-supply = <0x1b9>;

clock-control-debugfs = "true";

clock-names = "ipe_0_ahb_clk\0ipe_0_areg_clk\0ipe_0_axi_clk\0ipe_0_clk_src\0ipe_0_clk";

reg-names = "ipe0_top";

reg-cam-base = <0x87000>;

cell-index = <0x00>;

clocks = <0x29 0x43 0x29 0x44 0x29 0x45 0x29 0x47 0x29 0x46>;

clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo";

compatible = "qcom,cam-ipe";

src-clock-name = "ipe_0_clk_src";

status = "ok";

reg = <0xac87000 0x3000>;

regulator-names = "ipe0-vdd";

phandle = <0x394>;

qcom,cam-cx-ipeak = <0x1a3 0x03>;

clock-rates = <0x00 0x00 0x00 0x1443fd00 0x00 0x00 0x00 0x00 0x19a14780 0x00 0x00 0x00 0x00 0x1efe9200 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600 0x00>;

};

qcom,mdss_dp_pll@ae90000 {

clock-names = "iface_clk\0ref_clk_src\0ref_clk\0cfg_ahb_clk\0pipe_clk";

reg-names = "pll_base\0phy_base\0ln_tx0_base\0ln_tx1_base\0gdsc_base";

cell-index = <0x00>;

clocks = <0x2a 0x01 0x2f 0x00 0x27 0x92 0x27 0x97 0x27 0x96>;

#clock-cells = <0x01>;

label = "MDSS DP PLL";

compatible = "qcom,mdss_dp_pll_10nm";

gdsc-supply = <0xcb>;

clock-rate = <0x00>;

reg = <0x88ea000 0x200 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0xaf03000 0x08>;

phandle = <0x1aa>;

qcom,platform-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,platform-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x00>;

qcom,supply-name = "gdsc";

qcom,supply-max-voltage = <0x00>;

reg = <0x00>;

qcom,supply-min-voltage = <0x00>;

};

};

};

spi@0xa88000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x19b>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

interrupts = <0x00 0x163 0x00>;

clocks = <0x27 0x5b 0x27 0x69 0x27 0x6a>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x182>;

spi-max-frequency = <0x2faf080>;

dma-names = "tx\0rx";

compatible = "qcom,spi-geni";

pinctrl-1 = <0x19c>;

status = "ok";

reg = <0xa88000 0x4000>;

phandle = <0x365>;

dmas = <0x183 0x00 0x02 0x01 0x40 0x00 0x183 0x01 0x02 0x01 0x40 0x00>;

irled@0 {

spi-max-frequency = <0x124f800>;

compatible = "ir-spi";

status = "ok";

reg = <0x00>;

};

};

dsu_pmu@0 {

interrupts = <0x00 0x32 0x04>;

compatible = "arm,dsu-pmu";

cpus = <0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18>;

};

cti@6c29000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-dlct_cti0";

compatible = "arm,primecell";

reg = <0x6c29000 0x1000>;

phandle = <0x468>;

};

cti@6b05000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-swao_cti1";

compatible = "arm,primecell";

reg = <0x6b05000 0x1000>;

phandle = <0x470>;

};

arm,smmu-kgsl@5040000 {

#global-interrupts = <0x02>;

clock-names = "gcc_gpu_memnoc_gfx_clk";

attach-impl-defs = <0x6000 0x2378 0x6060 0x1055 0x678c 0x08 0x6794 0x28 0x6800 0x06 0x6900 0x3ff 0x6924 0x204 0x6928 0x11000 0x6930 0x800 0x6960 0xffffffff 0x6b64 0x1a5551 0x6b68 0x9a82a382>;

interrupts = <0x00 0xe5 0x04 0x00 0xe7 0x04 0x00 0x16c 0x04 0x00 0x16d 0x04 0x00 0x16e 0x04 0x00 0x16f 0x04 0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04 0x00 0x173 0x04>;

clocks = <0x27 0x2b>;

qcom,disable-atos;

qcom,regulator-names = "vdd";

vdd-supply = <0x1c5>;

qcom,use-3-lvl-tables;

#iommu-cells = <0x01>;

compatible = "qcom,smmu-v2";

status = "ok";

reg = <0x5040000 0x10000>;

phandle = <0x1cd>;

qcom,dynamic;

};

qcom,cpu0-llcc-ddr-lat {

qcom,src-dst-ports = <0x81 0x200>;

governor = "performance";

compatible = "qcom,devbw";

phandle = <0xc3>;

qcom,active-only;

operating-points-v2 = <0xbe>;

};

timer {

interrupts = <0x01 0x01 0xf08 0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x00 0xf08>;

clock-frequency = <0x124f800>;

compatible = "arm,armv8-timer";

};

qcom,smp2p-cdsp {

qcom,local-pid = <0x00>;

interrupts = <0x00 0x240 0x01>;

qcom,remote-pid = <0x05>;

compatible = "qcom,smp2p";

qcom,smem = <0x5e 0x1b0>;

qcom,ipc = <0x99 0x00 0x06>;

qcom,smp2p-rdbg5-out {

qcom,entry-name = "rdbg";

#qcom,smem-state-cells = <0x01>;

phandle = <0x1be>;

};

qcom,smp2p-qvrexternal5-out {

qcom,entry-name = "qvrexternal";

#qcom,smem-state-cells = <0x01>;

phandle = <0x1c0>;

};

slave-kernel {

qcom,entry-name = "slave-kernel";

#interrupt-cells = <0x02>;

phandle = <0xae>;

interrupt-controller;

};

master-kernel {

qcom,entry-name = "master-kernel";

#qcom,smem-state-cells = <0x01>;

phandle = <0xaf>;

};

qcom,smp2p-rdbg5-in {

qcom,entry-name = "rdbg";

#interrupt-cells = <0x02>;

phandle = <0x1bf>;

interrupt-controller;

};

};

tx_swr_clk_data_pinctrl {

pinctrl-names = "aud_active\0aud_sleep";

pinctrl-0 = <0x503 0x504 0x505>;

compatible = "qcom,msm-cdc-pinctrl";

qcom,lpi-gpios;

pinctrl-1 = <0x506 0x507 0x508>;

phandle = <0x4e2>;

};

rpmh-regulator-ldoa9 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa9";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l9 {

regulator-max-microvolt = <0xb98c0>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x98580>;

regulator-min-microvolt = <0x98580>;

regulator-name = "pm6150_l9";

qcom,set = <0x03>;

phandle = <0xb8>;

};

};

dsi_panel_pwr_supply {

#address-cells = <0x01>;

#size-cells = <0x00>;

phandle = <0x520>;

qcom,panel-supply-entry@1 {

qcom,supply-disable-load = <0x64>;

qcom,supply-enable-load = <0x186a0>;

qcom,supply-name = "lab";

qcom,supply-max-voltage = <0x5b8d80>;

reg = <0x01>;

qcom,supply-min-voltage = <0x4630c0>;

};

qcom,panel-supply-entry@2 {

qcom,supply-disable-load = <0x64>;

qcom,supply-enable-load = <0x186a0>;

qcom,supply-name = "ibb";

qcom,supply-max-voltage = <0x5b8d80>;

reg = <0x02>;

qcom,supply-min-voltage = <0x4630c0>;

};

qcom,panel-supply-entry@0 {

qcom,supply-disable-load = <0x50>;

qcom,supply-enable-load = <0x7d00>;

qcom,supply-name = "vddio";

qcom,supply-max-voltage = <0x1d0d80>;

reg = <0x00>;

qcom,supply-min-voltage = <0x1b7740>;

};

};

rpmh-regulator-lmxlvl {

compatible = "qcom,rpmh-arc-regulator";

qcom,resource-name = "lmx.lvl";

mboxes = <0x1b 0x00>;

regulator-pm6150-l7 {

regulator-max-microvolt = <0x10000>;

regulator-min-microvolt = <0x11>;

regulator-name = "pm6150_l7_level";

qcom,init-voltage-level = <0x11>;

qcom,set = <0x03>;

phandle = <0xa0>;

};

};

i2c@0x890000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x16f>;

clock-names = "se-clk\0m-ahb\0s-ahb";

interrupts = <0x00 0x25d 0x00>;

clocks = <0x27 0x4c 0x27 0x67 0x27 0x68>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x168>;

dma-names = "tx\0rx";

compatible = "qcom,i2c-geni";

pinctrl-1 = <0x170>;

status = "ok";

reg = <0x890000 0x4000>;

phandle = <0x351>;

dmas = <0x165 0x00 0x04 0x03 0x40 0x00 0x165 0x01 0x04 0x03 0x40 0x00>;

aw882xx_smartpa@34 {

pinctrl-names = "default\0sleep";

irq-gpio = <0x174 0x5d 0x00>;

pinctrl-0 = <0x51c>;

monitor-flag = <0x01>;

interrupts = <0x5d 0x00>;

interrupt-parent = <0x174>;

reset-gpio = <0x174 0x40 0x00>;

compatible = "awinic,aw882xx_smartpa";

sound-channel = <0x00>;

pinctrl-1 = <0x51d>;

status = "ok";

interrupt-names = "smartpa_irq";

reg = <0x34>;

aw-cali-mode = "aw_class";

};

aw882xx_smartpa@35 {

pinctrl-names = "default\0sleep";

irq-gpio = <0x174 0x38 0x00>;

pinctrl-0 = <0x51e>;

monitor-flag = <0x01>;

interrupts = <0x38 0x00>;

interrupt-parent = <0x174>;

reset-gpio = <0x174 0x48 0x00>;

compatible = "awinic,aw882xx_smartpa";

sound-channel = <0x01>;

pinctrl-1 = <0x51f>;

status = "ok";

interrupt-names = "smartpa_irq";

reg = <0x35>;

aw-cali-mode = "aw_class";

};

};

qcom,bus_proxy_client {

qcom,msm-bus,name = "bus-proxy-client";

qcom,msm-bus,active-only;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

compatible = "qcom,bus-proxy-client";

status = "ok";

phandle = <0x320>;

qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x16 0x200 0x00 0x4c4b40>;

};

qcom,ipa@1e00000 {

qcom,use-ipa-tethering-bridge;

qcom,ipa-hw-mode = <0x00>;

qcom,ipa-hw-ver = <0x10>;

qcom,smmu-fast-map;

reg-names = "ipa-base\0gsi-base";

qcom,bus-vector-names = "MIN\0SVS2\0SVS\0NOMINAL\0TURBO";

qcom,msm-bus,name = "ipa";

qcom,throughput-threshold = <0x136 0x258 0x3e8>;

interrupts = <0x00 0x137 0x00 0x00 0x1b0 0x00>;

qcom,use-ipa-pm;

qcom,msm-bus,num-paths = <0x04>;

qcom,msm-bus,num-cases = <0x05>;

qcom,ipa-wdi2_over_gsi;

compatible = "qcom,ipa";

qcom,arm-smmu;

interrupt-names = "ipa-irq\0gsi-irq";

qcom,use-64-bit-dma-mask;

qcom,bandwidth-vote-for-ipa;

reg = <0x1e00000 0x34000 0x1e04000 0x2c000>;

qcom,ipa-fltrt-not-hashable;

phandle = <0x30f>;

qcom,msm-bus,vectors-KBps = <0x5a 0x200 0x00 0x00 0x5a 0x249 0x00 0x00 0x01 0x2a4 0x00 0x00 0x8f 0x309 0x00 0x00 0x5a 0x200 0x13880 0x71868 0x5a 0x249 0x13880 0x10bda 0x01 0x2a4 0x13880 0x1e 0x8f 0x309 0x00 0x1e 0x5a 0x200 0x13880 0x1e8480 0x5a 0x249 0x13880 0x414c5 0x01 0x2a4 0x13880 0x1ad42 0x8f 0x309 0x00 0x6d 0x5a 0x200 0x324b0 0x3d0900 0x5a 0x249 0x324b0 0xae101 0x01 0x2a4 0x324b0 0x78000 0x8f 0x309 0x00 0x1eb 0x5a 0x200 0x324b0 0x556eb4 0x5a 0x249 0x324b0 0x15eb41 0x01 0x2a4 0x324b0 0x78000 0x8f 0x309 0x00 0x1eb>;

qcom,ee = <0x00>;

qcom,modem-cfg-emb-pipe-flt;

qcom,scaling-exceptions;

qcom,ipa-wdi2;

qcom,ipa-endp-delay-wa;

qcom,smp2p_map_ipa_1_in {

interrupts-extended = <0xbb 0x00 0x00>;

compatible = "qcom,smp2p-map-ipa-1-in";

interrupt-names = "ipa-smp2p-in";

};

qcom,smp2p_map_ipa_1_out {

qcom,smem-state-names = "ipa-smp2p-out";

compatible = "qcom,smp2p-map-ipa-1-out";

qcom,smem-states = <0xba 0x00>;

};

};

qcom,dsi-display@28 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x53c>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_xiaomi_f4_42_06_0c_fhd_cmd_display";

phandle = <0x553>;

};

qcom,msm-dai-q6-dp {

compatible = "qcom,msm-dai-q6-hdmi";

qcom,msm-dai-q6-dev-id = <0x6020>;

phandle = <0x26b>;

};

syscon@1f40000 {

compatible = "syscon";

reg = <0x1f40000 0x20000>;

phandle = <0x8f>;

};

wcd9xxx-irq {

pinctrl-names = "default";

pinctrl-0 = <0x3d4>;

qcom,gpio-connect = <0x174 0x7a 0x00>;

interrupt-parent = <0x174>;

compatible = "qcom,wcd9xxx-irq";

#interrupt-cells = <0x01>;

status = "disabled";

phandle = <0x50f>;

interrupt-controller;

};

qcom,snoc_cnoc_keepalive {

qcom,src-dst-ports = <0x01 0x273>;

governor = "powersave";

compatible = "qcom,devbw";

status = "ok";

phandle = <0x31f>;

qcom,active-only;

operating-points-v2 = <0xca>;

};

qcom,rmnet-ipa {

qcom,ipa-napi-enable;

qcom,rmnet-ipa-ssr;

qcom,ipa-advertise-sg-support;

compatible = "qcom,rmnet-ipa3";

qcom,ipa-platform-type-msm;

};

cti@78f0000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-apss_cti1";

compatible = "arm,primecell";

reg = <0x78f0000 0x1000>;

phandle = <0x45f>;

};

rpmh-regulator-ldoc11 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoc11";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150l-l11 {

regulator-max-microvolt = <0x33e140>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x2d0370>;

regulator-min-microvolt = <0x2d0370>;

regulator-name = "pm6150l_l11";

qcom,set = <0x03>;

phandle = <0x414>;

};

};

qcom,mdss_dsi_pll@ae94a00 {

clock-names = "iface_clk";

reg-names = "pll_base\0phy_base\0gdsc_base\0dynamic_pll_base";

cell-index = <0x00>;

memory-region = <0x1a5>;

clocks = <0x2a 0x01>;

#clock-cells = <0x01>;

label = "MDSS DSI 0 PLL";

compatible = "qcom,mdss_dsi_pll_10nm";

gdsc-supply = <0xcb>;

clock-rate = <0x00>;

reg = <0xae94a00 0x1e0 0xae94400 0x800 0xaf03000 0x08 0xae94200 0x100>;

phandle = <0x36a>;

qcom,platform-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,platform-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x00>;

qcom,supply-name = "gdsc";

qcom,supply-max-voltage = <0x00>;

reg = <0x00>;

qcom,supply-min-voltage = <0x00>;

};

};

};

i2c@0x888000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x16b>;

clock-names = "se-clk\0m-ahb\0s-ahb";

interrupts = <0x00 0x25b 0x00>;

clocks = <0x27 0x48 0x27 0x67 0x27 0x68>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x168>;

dma-names = "tx\0rx";

compatible = "qcom,i2c-geni";

pinctrl-1 = <0x16c>;

status = "ok";

reg = <0x888000 0x4000>;

phandle = <0x34f>;

dmas = <0x165 0x00 0x02 0x03 0x40 0x00 0x165 0x01 0x02 0x03 0x40 0x00>;

qcom,clk-freq-out = <0xf4240>;

nq@28 {

pinctrl-names = "nfc_active\0nfc_suspend";

pinctrl-0 = <0x3a9 0x3ab 0x3ad>;

qcom,nq-clkreq = <0x174 0x1f 0x00>;

qcom,nq-firm = <0x174 0x24 0x00>;

qcom,nq-irq = <0x174 0x25 0x00>;

qcom,nq-ven = <0x174 0x42 0x00>;

interrupts = <0x25 0x00>;

interrupt-parent = <0x174>;

compatible = "qcom,nq-nci";

pinctrl-1 = <0x3aa 0x3ac 0x3ae>;

interrupt-names = "nfc_irq";

reg = <0x28>;

};

};

qcom,kgsl-busmon {

label = "kgsl-busmon";

compatible = "qcom,kgsl-busmon";

phandle = <0x4cf>;

};

qcom,dsi-display@6 {

qcom,dsi-phy-num = <0x00 0x01>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x528>;

qcom,dsi-ctrl-num = <0x00 0x01>;

qcom,display-type = "primary";

label = "dsi_dual_sim_cmd_display";

phandle = <0x545>;

};

qcom,dsi-display@18 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x533>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_ss_fhd_eb_f10_cmd_display";

phandle = <0x550>;

};

qcom,cpu6-cpu-ddr-latfloor {

qcom,src-dst-ports = <0x81 0x200>;

governor = "performance";

compatible = "qcom,devbw";

phandle = <0xc6>;

qcom,active-only;

operating-points-v2 = <0xbe>;

};

slim@62e40000 {

reg-names = "slimbus_physical\0slimbus_bam_physical";

cell-index = <0x03>;

qcom,iommu-s1-bypass;

interrupts = <0x00 0x123 0x00 0x00 0x124 0x00>;

compatible = "qcom,slim-ngd";

status = "ok";

interrupt-names = "slimbus_irq\0slimbus_bam_irq";

reg = <0x62e40000 0x2c000 0x62e04000 0x20000>;

phandle = <0x2b8>;

qcom,iommu_slim_ctrl_cb {

iommus = <0x30 0x1bf3 0x00>;

compatible = "qcom,iommu-slim-ctrl-cb";

phandle = <0x2b9>;

};

wcn3990 {

qcom,btfm-slim-ifd = "btfmslim_slave_ifd";

elemental-addr = [00 01 20 02 17 02];

qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];

compatible = "qcom,btfmslim_slave";

phandle = <0x2ba>;

};

};

qcom,kgsl-iommu@5040000 {

clock-names = "iface_clk\0mem_clk\0mem_iface_clk";

qcom,retention;

clocks = <0x27 0x28 0x27 0x1b 0x27 0x2b>;

qcom,micro-mmu-control = <0x6000>;

qcom,protect = <0x40000 0x10000>;

compatible = "qcom,kgsl-smmu-v2";

reg = <0x5040000 0x10000>;

phandle = <0x4d0>;

qcom,hyp_secure_alloc;

qcom,secure_align_mask = <0xfff>;

gfx3d_user {

iommus = <0x1cd 0x00>;

label = "gfx3d_user";

compatible = "qcom,smmu-kgsl-cb";

phandle = <0x4d1>;

qcom,gpu-offset = <0x48000>;

};

gfx3d_secure {

iommus = <0x1cd 0x02>;

compatible = "qcom,smmu-kgsl-cb";

phandle = <0x4d2>;

};

};

rpmh-regulator-ldoc7 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoc7";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150l-l7 {

regulator-max-microvolt = <0x328980>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x328980>;

regulator-min-microvolt = <0x328980>;

regulator-name = "pm6150l_l7";

qcom,set = <0x03>;

phandle = <0x411>;

};

};

apps_iommu_test_device {

iommus = <0x30 0x21 0x00>;

compatible = "iommu-debug-test";

};

etm@7240000 {

arm,primecell-periphid = <0xbb95d>;

clock-names = "apb_pclk";

clocks = <0x19 0x00>;

cpu = <0x13>;

qcom,tupwr-disable;

coresight-name = "coresight-etm2";

compatible = "arm,primecell";

reg = <0x7240000 0x1000>;

phandle = <0x43e>;

port {

endpoint {

remote-endpoint = <0x21f>;

phandle = <0x217>;

};

};

};

qcom,qmp-aop@c300000 {

qcom,early-boot;

reg-names = "msgram\0irq-reg-base";

interrupts = <0x00 0x185 0x01>;

#mbox-cells = <0x01>;

label = "aop";

mbox-desc-offset = <0x00>;

priority = <0x00>;

compatible = "qcom,qmp-mbox";

reg = <0xc300000 0x1000 0x17c0000c 0x04>;

phandle = <0x1c>;

qcom,irq-mask = <0x01>;

};

qcedev@1de0000 {

iommus = <0x30 0x506 0x11 0x30 0x516 0x11>;

qcom,ce-hw-shared;

qcom,ce-device = <0x00>;

reg-names = "crypto-base\0crypto-bam-base";

qcom,msm-bus,name = "qcedev-noc";

qcom,bam-ee = <0x00>;

interrupts = <0x00 0x110 0x00>;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

compatible = "qcom,qcedev";

qcom,no-clock-support;

qcom,bam-pipe-pair = <0x03>;

reg = <0x1de0000 0x20000 0x1dc4000 0x24000>;

phandle = <0x2df>;

qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180>;

qcom,smmu-s1-enable;

qcom,ce-hw-instance = <0x00>;

};

rpmh-regulator-ldof5 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldof5";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm8009-l5 {

regulator-max-microvolt = <0x2c4fc0>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x292340>;

regulator-min-microvolt = <0x292340>;

regulator-name = "pm8009_l5";

qcom,set = <0x03>;

phandle = <0x41a>;

};

};

cti@6c20000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-venus-arm9";

compatible = "arm,primecell";

reg = <0x6c20000 0x1000>;

phandle = <0x475>;

};

csr@6001000 {

qcom,set-byte-cntr-support;

qcom,blk-size = <0x01>;

qcom,hwctrl-set-support;

reg-names = "csr-base";

coresight-name = "coresight-csr";

qcom,usb-bam-support;

compatible = "qcom,coresight-csr";

reg = <0x6001000 0x1000>;

phandle = <0x1d6>;

};

qcom,cpu-cpu-llcc-bwmon@90b6300 {

reg-names = "base\0global_base";

interrupts = <0x00 0x245 0x04>;

compatible = "qcom,bimc-bwmon4";

qcom,hw-timer-hz = <0x124f800>;

qcom,mport = <0x00>;

qcom,count-unit = <0x10000>;

reg = <0x90b6300 0x300 0x90b6200 0x200>;

phandle = <0x311>;

qcom,target-dev = <0xbd>;

};

qcom,msm-dai-q6-spdif-pri-tx {

compatible = "qcom,msm-dai-q6-spdif";

qcom,msm-dai-q6-dev-id = <0x5001>;

phandle = <0x4c9>;

};

jtagmm@7340000 {

clock-names = "core_clk";

reg-names = "etm-base";

clocks = <0x19 0x00>;

compatible = "qcom,jtagv8-mm";

qcom,coresight-jtagmm-cpu = <0x14>;

reg = <0x7340000 0x1000>;

phandle = <0x2ab>;

};

qcom,videocc@ab00000 {

#reset-cells = <0x01>;

reg-names = "cc_base\0efuse";

#clock-cells = <0x01>;

compatible = "qcom,videocc-sdmmagpie\0syscon";

reg = <0xab00000 0x10000 0x786018 0x04>;

phandle = <0x28>;

vdd_cx-supply = <0x1d>;

};

qcom,sde_rscc@af20000 {

qcom,sde-rsc-version = <0x02>;

clock-names = "vsync_clk\0gdsc_clk\0iface_clk";

reg-names = "drv\0wrapper";

cell-index = <0x00>;

qcom,sde-dram-channels = <0x02>;

clocks = <0x2a 0x25 0x2a 0x1d 0x2a 0x24>;

vdd-supply = <0xcb>;

compatible = "qcom,sde-rsc";

clock-rate = <0x00 0x00 0x00>;

reg = <0xaf20000 0x1c44 0xaf30000 0x3fd4>;

phandle = <0x36d>;

mboxes = <0xcf 0x00>;

mbox-names = "disp_rsc";

qcom,sde-llcc-bus {

qcom,msm-bus,name = "disp_rsc_llcc";

qcom,msm-bus,active-only;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x03>;

qcom,msm-bus,vectors-KBps = <0x4e21 0x5021 0x00 0x00 0x4e21 0x5021 0x00 0x61a800 0x4e21 0x5021 0x00 0x61a800>;

};

qcom,sde-data-bus {

qcom,msm-bus,name = "disp_rsc_mnoc";

qcom,msm-bus,active-only;

qcom,msm-bus,num-paths = <0x02>;

qcom,msm-bus,num-cases = <0x03>;

qcom,msm-bus,vectors-KBps = <0x4e23 0x5023 0x00 0x00 0x4e24 0x5023 0x00 0x00 0x4e23 0x5023 0x00 0x61a800 0x4e24 0x5023 0x00 0x61a800 0x4e23 0x5023 0x00 0x61a800 0x4e24 0x5023 0x00 0x61a800>;

};

qcom,sde-ebi-bus {

qcom,msm-bus,name = "disp_rsc_ebi";

qcom,msm-bus,active-only;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x03>;

qcom,msm-bus,vectors-KBps = <0x4e20 0x5020 0x00 0x00 0x4e20 0x5020 0x00 0x61a800 0x4e20 0x5020 0x00 0x61a800>;

};

};

qcom,csid0@acb3000 {

camss-supply = <0x1ae>;

clock-control-debugfs = "true";

clock-names = "ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_clk\0ife_axi_clk";

reg-names = "csid";

reg-cam-base = <0xb3000>;

ife0-supply = <0x1b7>;

cell-index = <0x00>;

interrupts = <0x00 0x1d0 0x00>;

clocks = <0x29 0x35 0x29 0x34 0x29 0x1b 0x29 0x33 0x29 0x32 0x29 0x31 0x29 0x30>;

clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";

compatible = "qcom,csid175_200";

src-clock-name = "ife_csid_clk_src";

status = "ok";

interrupt-names = "csid";

reg = <0xacb3000 0x1000>;

regulator-names = "camss\0ife0";

phandle = <0x38d>;

clock-rates = <0x11e1a300 0x00 0x00 0x00 0x16a65700 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x1e65fb80 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x25f7d940 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x2d4cae00 0x00 0x00>;

};

syscon@182a0018 {

compatible = "syscon";

reg = <0x182a0018 0x04>;

phandle = <0x2d>;

};

qcom,vidc0 {

qcom,allowed-clock-rates = <0xe4e1c00 0x14257880 0x15c17540>;

iris-ctl-supply = <0xb4>;

qcom,cx-ipeak-data = <0x1a3 0x05>;

qcom,clock-freq-threshold = <0x1fc4ef40>;

sku-index = <0x00>;

clock-names = "video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk";

vcodec-supply = <0x1a1>;

interrupts = <0x00 0xae 0x04>;

cvp-supply = <0x1a2>;

clocks = <0x28 0x08 0x28 0x03 0x28 0x05 0x28 0x07 0x28 0x04 0x28 0x06 0x28 0x09>;

compatible = "qcom,msm-vidc\0qcom,sdmmagpie-vidc";

status = "ok";

reg = <0xaa00000 0x200000>;

phandle = <0x368>;

qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk";

qcom,clock-configs = <0x00 0x00 0x00 0x01 0x01 0x01 0x00>;

venus_bus_ddr {

qcom,bus-governor = "msm-vidc-ddr";

label = "venus-ddr";

compatible = "qcom,msm-vidc,bus";

qcom,bus-slave = <0x200>;

qcom,bus-master = <0x3f>;

qcom,bus-range-kbps = <0x3e8 0x63af88>;

};

qcom,msm-vidc,mem_cdsp {

memory-region = <0x1a4>;

compatible = "qcom,msm-vidc,mem-cdsp";

};

non_secure_cb {

iommus = <0x30 0x1080 0x60>;

virtual-addr-pool = <0x25800000 0xba800000>;

label = "venus_ns";

compatible = "qcom,msm-vidc,context-bank";

buffer-types = <0xfff>;

};

secure_non_pixel_cb {

iommus = <0x30 0x1084 0x60>;

qcom,secure-context-bank;

virtual-addr-pool = <0x1000000 0x24800000>;

label = "venus_sec_non_pixel";

compatible = "qcom,msm-vidc,context-bank";

buffer-types = <0x480>;

};

arm9_bus_ddr {

qcom,bus-governor = "performance";

label = "venus-arm9-ddr";

compatible = "qcom,msm-vidc,bus";

qcom,bus-slave = <0x200>;

qcom,bus-master = <0x3f>;

qcom,bus-range-kbps = <0x3e8 0x3e8>;

};

bus_cnoc {

qcom,bus-governor = "performance";

label = "cnoc";

compatible = "qcom,msm-vidc,bus";

qcom,bus-slave = <0x254>;

qcom,bus-master = <0x01>;

qcom,bus-range-kbps = <0x3e8 0x3e8>;

};

secure_bitstream_cb {

iommus = <0x30 0x1081 0x04>;

qcom,secure-context-bank;

virtual-addr-pool = <0x500000 0xdfb00000>;

label = "venus_sec_bitstream";

compatible = "qcom,msm-vidc,context-bank";

buffer-types = <0x241>;

};

secure_pixel_cb {

iommus = <0x30 0x1083 0x20>;

qcom,secure-context-bank;

virtual-addr-pool = <0x500000 0xdfb00000>;

label = "venus_sec_pixel";

compatible = "qcom,msm-vidc,context-bank";

buffer-types = <0x106>;

};

};

cti@601f000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti15";

compatible = "arm,primecell";

reg = <0x601f000 0x1000>;

phandle = <0x484>;

};

qcom,llcc@9200000 {

qcom,llcc-banks-off = <0x00 0x80000>;

reg-names = "llcc_base";

qcom,llcc-broadcast-off = <0x400000>;

compatible = "qcom,llcc-core\0syscon\0simple-mfd";

reg = <0x9200000 0x450000>;

qcom,sdmmagpie-llcc {

max-slices = <0x20>;

compatible = "qcom,sdmmagpie-llcc";

phandle = <0x1a7>;

#cache-cells = <0x01>;

cap-based-alloc-and-pwr-collapse;

};

llcc_1_dcache {

qcom,dump-size = <0x6c000>;

phandle = <0x51>;

};

qcom,llcc-erp {

compatible = "qcom,llcc-erp";

};

llcc_2_dcache {

qcom,dump-size = <0x6c000>;

phandle = <0x52>;

};

qcom,llcc-perfmon {

clock-names = "qdss_clk";

clocks = <0x19 0x00>;

compatible = "qcom,llcc-perfmon";

};

qcom,llcc-amon {

compatible = "qcom,llcc-amon";

};

};

qcom,msm-pcm-dsp-noirq {

qcom,latency-level = "ultra";

compatible = "qcom,msm-pcm-dsp-noirq";

phandle = <0x26a>;

qcom,msm-pcm-low-latency;

};

thermal-message {

board-sensor = "VIRTUAL-SENSOR";

phandle = <0x5b4>;

};

qcom,gdsc@0b00814 {

clock-names = "ahb_clk";

clocks = <0x27 0x9b>;

regulator-name = "mvsc_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0xab00814 0x04>;

phandle = <0xb4>;

};

qcom,gdsc@0f03000 {

qcom,poll-cfg-gdscr;

clock-names = "ahb_clk";

qcom,support-hw-trigger;

clocks = <0x27 0x1c>;

regulator-name = "mdss_core_gdsc";

compatible = "qcom,gdsc";

status = "ok";

qcom,proxy-consumer-enable;

reg = <0xaf03000 0x04>;

phandle = <0xcb>;

proxy-supply = <0xcb>;

};

qcom,mpm2-sleep-counter@0xc221000 {

clock-frequency = <0x8000>;

compatible = "qcom,mpm2-sleep-counter";

reg = <0xc221000 0x1000>;

};

rpmh-regulator-ldoa12 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa12";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l12 {

regulator-max-microvolt = <0x1dc900>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x19e100>;

regulator-min-microvolt = <0x19e100>;

regulator-name = "pm6150_l12";

qcom,set = <0x03>;

phandle = <0x407>;

};

};

tmc@6048000 {

iommus = <0x30 0x5e0 0x00 0x30 0x4a0 0x00>;

arm,buffer-size = <0x400000>;

arm,primecell-periphid = <0x3b961>;

coresight-ctis = <0x1d5 0x1d5>;

clock-names = "apb_pclk";

reg-names = "tmc-base\0bam-base";

interrupts = <0x00 0x10e 0x01>;

clocks = <0x19 0x00>;

coresight-name = "coresight-tmc-etr";

compatible = "arm,primecell";

interrupt-names = "byte-cntr-irq";

reg = <0x6048000 0x1000 0x6064000 0x15000>;

phandle = <0x41f>;

coresight-csr = <0x1d6>;

port {

endpoint {

slave-mode;

remote-endpoint = <0x1d7>;

phandle = <0x1d0>;

};

};

};

funnel@6832000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-modem";

compatible = "arm,primecell";

reg = <0x6832000 0x1000>;

phandle = <0x424>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1e8>;

phandle = <0x1e7>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x1e9>;

phandle = <0x1eb>;

};

};

port@2 {

reg = <0x01>;

endpoint {

slave-mode;

remote-endpoint = <0x1ea>;

phandle = <0x1ed>;

};

};

};

};

qcom,chd_sliver {

qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060 0x18040060 0x18050060>;

label = "silver";

qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058 0x18040058 0x18050058>;

compatible = "qcom,core-hang-detect";

};

cti@601c000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti12";

compatible = "arm,primecell";

reg = <0x601c000 0x1000>;

phandle = <0x481>;

};

qcom,qupv3_1_geni_se@0xac0000 {

qcom,iommu-s1-bypass;

qcom,bus-mas-id = <0x98>;

qcom,bus-slv-id = <0x200>;

compatible = "qcom,qupv3-geni-se";

reg = <0xac0000 0x2000>;

phandle = <0x182>;

qcom,iommu_qupv3_1_geni_se_cb {

iommus = <0x30 0x4c3 0x00>;

compatible = "qcom,qupv3-geni-se-cb";

phandle = <0x358>;

};

};

wsa_spkr_en1_pinctrl {

pinctrl-names = "aud_active\0aud_sleep";

pinctrl-0 = <0x3d1>;

compatible = "qcom,msm-cdc-pinctrl";

pinctrl-1 = <0x3d0>;

status = "disabled";

phandle = <0x4e9>;

};

qcom,qup_uart@0x88c000 {

pinctrl-names = "default\0sleep";

pinctrl-0 = <0x171 0x172 0x173>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

clocks = <0x27 0x4a 0x27 0x67 0x27 0x68>;

qcom,wrapper-core = <0x168>;

interrupts-extended = <0x01 0x00 0x25c 0x00 0x174 0x29 0x00>;

compatible = "qcom,msm-geni-serial-hs";

pinctrl-1 = <0x171 0x172 0x173>;

status = "ok";

reg = <0x88c000 0x4000>;

phandle = <0x352>;

qcom,wakeup-byte = <0xfd>;

};

syscon@90b0000 {

compatible = "syscon";

reg = <0x90b0000 0x1000>;

phandle = <0x2e>;

};

qcom,dp_display@0 {

qcom,dp-gpio-aux-switch;

qcom,aux-cfg1-settings = <0x2413231d>;

pinctrl-names = "mdss_dp_active\0mdss_dp_sleep";

qcom,usbplug-cc-gpio = <0x174 0x68 0x00>;

qcom,aux-cfg6-settings = [38 0a];

pinctrl-0 = <0x3ca 0x1ac>;

qcom,ext-disp = <0x1ab>;

clock-names = "core_aux_clk\0core_usb_ahb_clk\0core_usb_ref_clk_src\0core_usb_ref_clk\0core_usb_pipe_clk\0link_clk\0link_iface_clk\0crypto_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0pixel1_parent\0strm0_pixel_clk\0strm1_pixel_clk";

reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_mmss_cc\0qfprom_physical\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1";

qcom,aux-cfg2-settings = [28 24];

cell-index = <0x00>;

interrupts = <0x0c 0x00>;

clocks = <0x2a 0x0b 0x27 0x97 0x2f 0x00 0x27 0x92 0x27 0x96 0x2a 0x0f 0x2a 0x11 0x2a 0x0d 0x2a 0x15 0x1aa 0x05 0x2a 0x13 0x1aa 0x05 0x2a 0x14 0x2a 0x12>;

qcom,max-pclk-frequency-khz = <0xa4cb8>;

qcom,aux-cfg7-settings = [3c 03];

interrupt-parent = <0x1a6>;

qcom,aux-cfg3-settings = [2c 00];

vdda-1p2-supply = <0x1a8>;

qcom,aux-cfg8-settings = [40 bb];

compatible = "qcom,dp-display";

pinctrl-1 = <0x3cb 0x1ad>;

status = "disabled";

vdda-0p9-supply = <0x1a9>;

qcom,aux-cfg4-settings = [30 0a];

reg = <0xae90000 0xdc 0xae90200 0xc0 0xae90400 0x508 0xae90a00 0x94 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0xaf02000 0x1e0 0x780000 0x621c 0x88ea030 0x10 0x88e8000 0x20 0xaee1000 0x34 0xae91000 0x94>;

phandle = <0x377>;

qcom,aux-en-gpio = <0x174 0x2a 0x00>;

qcom,aux-cfg9-settings = [44 03];

qcom,aux-cfg0-settings = [20 00];

qcom,dp-usbpd-detection = <0x25b>;

qcom,aux-sel-gpio = <0x174 0x21 0x00>;

qcom,aux-cfg5-settings = [34 26];

qcom,ctrl-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,ctrl-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x5528>;

qcom,supply-name = "vdda-1p2";

qcom,supply-max-voltage = <0x12cc80>;

reg = <0x00>;

qcom,supply-min-voltage = <0x1174c0>;

};

};

qcom,phy-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,phy-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x8ca0>;

qcom,supply-name = "vdda-0p9";

qcom,supply-max-voltage = <0xe09c0>;

reg = <0x00>;

qcom,supply-min-voltage = <0xc92c0>;

};

};

qcom,core-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,core-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x00>;

qcom,supply-name = "refgen";

qcom,supply-max-voltage = <0x00>;

reg = <0x00>;

qcom,supply-min-voltage = <0x00>;

};

};

};

cp_qc30 {

mi,support-qc3p5-without-smb;

mi,qc3-bus-curr-max = <0x834>;

mi,qc3-bus-volt-max = <0x2ee0>;

compatible = "xiaomi,cp-qc30";

status = "ok";

mi,qc3-ffc-bat-volt-max = <0x1176>;

mi,qc3-bat-curr-max = <0x1518>;

mi,qc3-bat-volt-max = <0x1162>;

};

qcom,msm-dai-tdm-quin-tx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9041>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9141>;

phandle = <0x4c3>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-quin-tx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9041>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x28f>;

};

};

qcom,dsi-display@26 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x53a>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_xiaomi_f4_41_06_0a_fhd_cmd_display";

phandle = <0x551>;

};

qcom,cci@ac4b000 {

pinctrl-names = "cam_default\0cam_suspend";

#address-cells = <0x01>;

pinctrl-0 = <0x1b4>;

clock-names = "cci_clk\0cci_1_clk_src";

reg-names = "cci";

reg-cam-base = <0x4b000>;

cell-index = <0x01>;

gpio-req-tbl-num = <0x00 0x01>;

interrupts = <0x00 0x1cd 0x00>;

clocks = <0x29 0x17 0x29 0x18>;

gdscr-supply = <0x1ae>;

#size-cells = <0x00>;

gpio-req-tbl-label = "CCI_I2C_DATA2\0CCI_I2C_CLK2";

clock-cntl-level = "lowsvs";

compatible = "qcom,cci";

src-clock-name = "cci_1_clk_src";

pinctrl-1 = <0x1b5>;

status = "ok";

interrupt-names = "cci";

reg = <0xac4b000 0x1000>;

regulator-names = "gdscr";

phandle = <0x381>;

clock-rates = <0x00 0x23c3460>;

gpio-req-tbl-flags = <0x01 0x01>;

gpios = <0x174 0x1b 0x00 0x174 0x1c 0x00>;

qcom,i2c_custom_mode {

hw-tsu-sto = <0x28>;

cci-clk-src = <0x23c3460>;

hw-tsp = <0x03>;

hw-trdhld = <0x06>;

hw-thigh = <0x26>;

hw-tlow = <0x38>;

status = "ok";

hw-thd-dat = <0x16>;

hw-tsu-sta = <0x28>;

hw-scl-stretch-en = <0x01>;

phandle = <0x384>;

hw-tbuf = <0x3e>;

hw-thd-sta = <0x23>;

};

qcom,cam-sensor@1 {

cam_v_custom1-supply = <0x57a>;

rgltr-max-voltage = <0x1b7740 0x2ab980 0x1b7740 0x00>;

pinctrl-names = "cam_default\0cam_suspend";

eeprom-src = <0x57d>;

pinctrl-0 = <0x56c 0x57b 0x578>;

clock-names = "cam_clk";

cell-index = <0x01>;

gpio-req-tbl-num = <0x00 0x01 0x02>;

sensor-position-yaw = <0xb4>;

cci-device = <0x01>;

clocks = <0x29 0x50>;

rgltr-load-current = <0x2bf20 0x1d4c0 0x1b7740 0x00>;

cam_vio-supply = <0x579>;

rgltr-cntrl-support;

cam_vana-supply = <0x56b>;

gpio-req-tbl-label = "CAMIF_MCLK0\0CAMD_RESET\0CAMD_CUSTOM1";

gpio-reset = <0x01>;

csiphy-sd-index = <0x03>;

clock-cntl-level = "turbo";

gpio-custom1 = <0x02>;

cci-master = <0x00>;

gpio-no-mux = <0x00>;

compatible = "qcom,cam-sensor";

rgltr-min-voltage = <0x1b7740 0x2ab980 0x1b7740 0x00>;

sensor-position-roll = <0x5a>;

pinctrl-1 = <0x56e 0x57c 0x575>;

status = "ok";

reg = <0x01>;

regulator-names = "cam_vio\0cam_vana\0cam_v_custom1\0cam_clk";

sensor-position-pitch = <0x00>;

cam_clk-supply = <0x1ae>;

clock-rates = <0x124f800>;

gpio-req-tbl-flags = <0x01 0x00 0x00>;

gpios = <0x174 0x0d 0x00 0x174 0x15 0x00 0x174 0x58 0x00>;

};

qcom,i2c_standard_mode {

hw-tsu-sto = <0xcc>;

cci-clk-src = <0x23c3460>;

hw-tsp = <0x03>;

hw-trdhld = <0x06>;

hw-thigh = <0xc9>;

hw-tlow = <0xae>;

status = "ok";

hw-thd-dat = <0x16>;

hw-tsu-sta = <0xe7>;

hw-scl-stretch-en = <0x00>;

phandle = <0x382>;

hw-tbuf = <0xe3>;

hw-thd-sta = <0xa2>;

};

qcom,cam-res-mgr {

compatible = "qcom,cam-res-mgr";

status = "ok";

};

qcom,cam-sensor@4 {

rgltr-max-voltage = <0x1b7740 0x00>;

pinctrl-names = "cam_default\0cam_suspend";

eeprom-src = <0x57f>;

pinctrl-0 = <0x580 0x581>;

clock-names = "cam_clk";

cell-index = <0x04>;

gpio-req-tbl-num = <0x00 0x01>;

sensor-position-yaw = <0xb4>;

cci-device = <0x01>;

clocks = <0x29 0x52>;

rgltr-load-current = <0x2bf20 0x00>;

cam_vio-supply = <0x57a>;

rgltr-cntrl-support;

gpio-req-tbl-label = "CAMIF_MCLK1\0CAMU_RESET";

gpio-reset = <0x01>;

csiphy-sd-index = <0x02>;

clock-cntl-level = "turbo";

sensor-mode = <0x00>;

cci-master = <0x00>;

gpio-no-mux = <0x00>;

compatible = "qcom,cam-sensor";

rgltr-min-voltage = <0x1b7740 0x00>;

led-flash-src = <0x57e>;

sensor-position-roll = <0x5a>;

pinctrl-1 = <0x582 0x583>;

status = "ok";

reg = <0x04>;

regulator-names = "cam_vio\0cam_clk";

sensor-position-pitch = <0x00>;

cam_clk-supply = <0x1ae>;

clock-rates = <0x124f800>;

gpio-req-tbl-flags = <0x01 0x00>;

gpios = <0x174 0x0e 0x00 0x174 0x19 0x00>;

};

qcom,eeprom@1 {

cam_v_custom1-supply = <0x57a>;

rgltr-max-voltage = <0x1b7740 0x2ab980 0x1b7740 0x00>;

pinctrl-names = "cam_default\0cam_suspend";

pinctrl-0 = <0x56c 0x57b 0x578>;

clock-names = "cam_clk";

cell-index = <0x01>;

gpio-req-tbl-num = <0x00 0x01 0x02>;

cci-device = <0x01>;

clocks = <0x29 0x50>;

rgltr-load-current = <0x2bf20 0x1d4c0 0x1b7740 0x00>;

cam_vio-supply = <0x579>;

rgltr-cntrl-support;

cam_vana-supply = <0x56b>;

gpio-req-tbl-label = "CAMIF_MCLK0\0CAMD_RESET\0CAMD_CUSTOM1";

gpio-reset = <0x01>;

csiphy-sd-index = <0x03>;

clock-cntl-level = "turbo";

gpio-custom1 = <0x02>;

cci-master = <0x00>;

gpio-no-mux = <0x00>;

compatible = "qcom,eeprom";

rgltr-min-voltage = <0x1b7740 0x2ab980 0x1b7740 0x00>;

pinctrl-1 = <0x56e 0x57c 0x575>;

status = "ok";

reg = <0x01>;

regulator-names = "cam_vio\0cam_vana\0cam_v_custom1\0cam_clk";

phandle = <0x57d>;

cam_clk-supply = <0x1ae>;

clock-rates = <0x124f800>;

gpio-req-tbl-flags = <0x01 0x00 0x00>;

gpios = <0x174 0x0d 0x00 0x174 0x15 0x00 0x174 0x58 0x00>;

};

qcom,i2c_fast_plus_mode {

hw-tsu-sto = <0x11>;

cci-clk-src = <0x23c3460>;

hw-tsp = <0x03>;

hw-trdhld = <0x03>;

hw-thigh = <0x10>;

hw-tlow = <0x16>;

status = "ok";

hw-thd-dat = <0x10>;

hw-tsu-sta = <0x12>;

hw-scl-stretch-en = <0x00>;

phandle = <0x385>;

hw-tbuf = <0x18>;

hw-thd-sta = <0x0f>;

};

qcom,i2c_fast_mode {

hw-tsu-sto = <0x28>;

cci-clk-src = <0x23c3460>;

hw-tsp = <0x03>;

hw-trdhld = <0x06>;

hw-thigh = <0x26>;

hw-tlow = <0x38>;

status = "ok";

hw-thd-dat = <0x16>;

hw-tsu-sta = <0x28>;

hw-scl-stretch-en = <0x00>;

phandle = <0x383>;

hw-tbuf = <0x3e>;

hw-thd-sta = <0x23>;

};

qcom,eeprom@4 {

rgltr-max-voltage = <0x1b7740>;

cell-index = <0x04>;

cci-device = <0x01>;

rgltr-load-current = <0x2bf20>;

cam_vio-supply = <0x57a>;

rgltr-cntrl-support;

cci-master = <0x00>;

compatible = "qcom,eeprom";

rgltr-min-voltage = <0x1b7740>;

status = "ok";

reg = <0x04>;

regulator-names = "cam_vio";

phandle = <0x57f>;

};

};

tpdm@6860000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-turing";

compatible = "arm,primecell";

reg = <0x6860000 0x1000>;

phandle = <0x452>;

qcom,msr-fix-req;

port {

endpoint {

remote-endpoint = <0x24a>;

phandle = <0x246>;

};

};

};

qcom,cam-fd {

compat-hw-name = "qcom,fd";

compatible = "qcom,cam-fd";

status = "ok";

num-fd = <0x01>;

};

cti@6a10000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-ddr_dl_1_cti0";

compatible = "arm,primecell";

reg = <0x6a10000 0x1000>;

phandle = <0x463>;

};

gpio-regulator@2 {

regulator-max-microvolt = <0x1b7740>;

gpio = <0x2ec 0x04 0x00>;

regulator-enable-ramp-delay = <0x64>;

enable-active-high;

regulator-min-microvolt = <0x1b7740>;

regulator-name = "camera_v_swio_depth_regulator";

compatible = "regulator-fixed";

reg = <0x02 0x00>;

phandle = <0x57a>;

vin-supply = <0x3fe>;

};

qcom,msm-dai-q6-spdif-pri-rx {

compatible = "qcom,msm-dai-q6-spdif";

qcom,msm-dai-q6-dev-id = <0x5000>;

phandle = <0x4c8>;

};

qcom,lrme@ac6b000 {

camss-supply = <0x1ae>;

clock-names = "lrme_clk_src\0lrme_clk";

reg-names = "lrme";

reg-cam-base = <0x6b000>;

cell-index = <0x00>;

interrupts = <0x00 0x1dc 0x00>;

clocks = <0x29 0x4f 0x29 0x4e>;

clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";

compatible = "qcom,lrme";

src-clock-name = "lrme_clk_src";

status = "ok";

interrupt-names = "lrme";

reg = <0xac6b000 0xa00>;

regulator-names = "camss";

phandle = <0x39a>;

clock-rates = <0xe4e1c00 0x00 0x11e1a300 0x00 0x1312d000 0x00 0x17d78400 0x00>;

};

qcom,gdsc@ad0c1c4 {

qcom,poll-cfg-gdscr;

clock-names = "ahb_clk";

clocks = <0x27 0x0e>;

regulator-name = "titan_top_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0xad0c1c4 0x04>;

phandle = <0x1ae>;

};

i2c@0xa90000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x18d>;

clock-names = "se-clk\0m-ahb\0s-ahb";

interrupts = <0x00 0x165 0x00>;

clocks = <0x27 0x5f 0x27 0x69 0x27 0x6a>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x182>;

dma-names = "tx\0rx";

compatible = "qcom,i2c-geni";

pinctrl-1 = <0x18e>;

status = "disabled";

reg = <0xa90000 0x4000>;

phandle = <0x35f>;

dmas = <0x183 0x00 0x04 0x03 0x40 0x00 0x183 0x01 0x04 0x03 0x40 0x00>;

};

suspendable-ddr-bw-opp-table {

compatible = "operating-points-v2";

phandle = <0xc7>;

opp-1017 {

opp-hz = <0x00 0xf27>;

};

opp-300 {

opp-hz = <0x00 0x478>;

};

opp-451 {

opp-hz = <0x00 0x6b8>;

};

opp-1353 {

opp-hz = <0x00 0x1429>;

};

opp-1804 {

opp-hz = <0x00 0x1ae1>;

};

opp-768 {

opp-hz = <0x00 0xb71>;

};

opp-200 {

opp-hz = <0x00 0x2fa>;

};

opp-681 {

opp-hz = <0x00 0xa25>;

};

opp-1555 {

opp-hz = <0x00 0x172b>;

};

opp-547 {

opp-hz = <0x00 0x826>;

};

opp-0 {

opp-hz = <0x00 0x00>;

};

};

qcom,cpu0-cpu-ddr-latfloor {

qcom,src-dst-ports = <0x81 0x200>;

governor = "performance";

compatible = "qcom,devbw";

phandle = <0xc5>;

qcom,active-only;

operating-points-v2 = <0xbe>;

};

tpdm@6b52000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-dl-south";

compatible = "arm,primecell";

reg = <0x6b52000 0x1000>;

phandle = <0x44f>;

port {

endpoint {

remote-endpoint = <0x244>;

phandle = <0x243>;

};

};

};

qcom,dsi-display@4 {

qcom,dsi-phy-num = <0x00 0x01>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x526>;

qcom,dsi-ctrl-num = <0x00 0x01>;

qcom,display-type = "primary";

label = "dsi_dual_sim_vid_display";

phandle = <0x543>;

};

qcom,csiphy@ace4000 {

clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk";

reg-names = "csiphy";

reg-cam-base = <0xe4000>;

csi-vdd-voltage = <0x124f80>;

cell-index = <0x02>;

interrupts = <0x00 0x1df 0x00>;

clocks = <0x29 0x1b 0x29 0x24 0x29 0x26 0x29 0x21 0x29 0x20>;

gdscr-supply = <0x1ae>;

clock-cntl-level = "svs\0svs_l1\0turbo";

compatible = "qcom,csiphy-v1.2\0qcom,csiphy";

src-clock-name = "csi2phytimer_clk_src";

mipi-csi-vdd-supply = <0x1a8>;

status = "ok";

interrupt-names = "csiphy";

reg = <0xace4000 0x2000>;

regulator-names = "gdscr\0refgen";

phandle = <0x37a>;

refgen-supply = <0x1af>;

clock-rates = <0x16e36000 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00>;

};

qcom,dsi-display@16 {

qcom,dsi-phy-num = <0x01>;

qcom,dsi-select-clocks = "mux_byte_clk1\0mux_pixel_clk1";

qcom,dsi-panel = <0x530>;

qcom,dsi-ctrl-num = <0x01>;

qcom,display-type = "secondary";

label = "dsi_nt35695b_truly_fhd_cmd_sec_display";

phandle = <0x55d>;

};

aop-msg-client {

compatible = "qcom,debugfs-qmp-client";

mboxes = <0x1c 0x00>;

mbox-names = "aop";

};

qcom,bps {

clock-control-debugfs = "true";

clock-names = "bps_ahb_clk\0bps_areg_clk\0bps_axi_clk\0bps_clk_src\0bps_clk";

reg-names = "bps_top";

reg-cam-base = <0x6f000>;

cell-index = <0x00>;

bps-vdd-supply = <0x1bb>;

clocks = <0x29 0x0d 0x29 0x0e 0x29 0x0f 0x29 0x11 0x29 0x10>;

clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo";

compatible = "qcom,cam-bps";

src-clock-name = "bps_clk_src";

status = "ok";

reg = <0xac6f000 0x3000>;

regulator-names = "bps-vdd";

phandle = <0x396>;

qcom,cam-cx-ipeak = <0x1a3 0x03>;

clock-rates = <0x00 0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600 0x00>;

};

rpmh-regulator-ldoc5 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoc5";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150l-l5 {

regulator-max-microvolt = <0x2d0370>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x192580>;

regulator-min-microvolt = <0x192580>;

regulator-name = "pm6150l_l5";

qcom,set = <0x03>;

phandle = <0x40f>;

};

};

qcom,mdss_dsi_ss_fhd_ea_f10_cmd {

qcom,ulps-enabled;

qcom,disp-doze-backlight-threshold = <0x08>;

qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode";

qcom,mdss-pan-physical-width-dimension = <0x44>;

qcom,mdss-dsi-panel-name = "ss ea fhd cmd dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x93>;

qcom,mdss-dsi-panel-elvss-dimming-read-length = <0x01>;

qcom,mdss-dsi-te-using-te-pin;

qcom,samsung-prepare-hbm;

qcom,mdss-dsi-te-dcs-command = <0x01>;

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-t-clk-post = <0x0f>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-te-check-enable;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-panel-id = <0x00>;

qcom,mdss-dsi-dispparam-hbm-fod-on-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 b0 03 39 00 00 00 00 00 02 b7 c9 39 00 00 00 00 00 02 b0 07 39 00 00 00 00 00 02 b7 91 39 00 00 00 00 00 03 b7 01 43 39 00 00 00 00 00 03 f0 a5 a5 39 01 00 00 01 00 02 53 e0];

qcom,mdss-dsi-dispparam-hbm-fod-off-command = [39 01 00 00 00 00 02 53 20 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 b7 01 4b 39 00 00 00 00 00 02 b0 03 39 00 00 00 00 00 02 b7 49 39 00 00 00 00 00 02 b0 07 39 00 00 00 00 00 02 b7 91 39 01 00 00 01 00 03 f0 a5 a5];

qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode";

qcom,mdss-dsi-panel-fod-dimlayer-enabled;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,bl-update-flag = "delay_until_first_frame";

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,disp-fod-off-dimming-delay = <0x55>;

qcom,elvss_dimming_check_enable;

qcom,dispparam-enabled;

qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-bl-dcs-type-ss-ea;

qcom,mdss-dsi-reset-sequence = <0x00 0x01 0x01 0x0a>;

qcom,mdss-dsi-dispparam-elvss-dimming-read-command = <0x6010001 0x1b7>;

qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-panel-on-dimming-delay = <0x78>;

qcom,mdss-dsi-t-clk-pre = <0x37>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,mdss-dsi-panel-model = "SS FHD EA CMD PANEL";

qcom,mdss-dsi-te-pin-select = <0x01>;

qcom,mdss-dsi-dispparam-elvss-dimming-offset-command = [39 01 00 00 00 00 02 b0 07];

phandle = <0x532>;

qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-panel-sleepwrmod = <0x00>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-wr-mem-continue = <0x3c>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-wr-mem-start = <0x2c>;

qcom,esd-err-irq-gpio = <0x174 0x20 0x2002>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-brightness-max-level = <0x7ff>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-dispparam-hbm-fod2norm-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 b2 00 40 39 00 00 00 00 00 02 b0 04 39 00 00 00 00 00 02 b2 80 39 00 00 00 00 00 02 f7 03 39 01 00 00 00 00 03 f0 a5 a5];

qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode";

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x00 0x01>;

qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-framerate = <0x3c>;

qcom,mdss-dsi-h-pulse-width = <0x14>;

qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00];

qcom,mdss-dsi-dispparam-hbm-fod2norm-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-jitter = <0x05 0x01>;

qcom,mdss-dsi-nolp-command = [05 01 00 00 22 00 02 28 00 39 01 00 00 00 00 02 53 20 05 01 00 00 00 00 02 29 00];

qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode";

qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode";

qcom,mdss-dsi-doze-lbm-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 d4 8b 39 00 00 00 00 00 02 b0 a5 39 00 00 00 00 00 02 c7 00 39 00 00 00 00 00 02 b0 69 39 00 00 00 00 00 03 b9 08 8f 39 01 00 00 00 00 02 53 23 39 01 00 00 00 00 03 f0 a5 a5];

qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 e8];

qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28];

qcom,mdss-dsi-panel-height = <0x924>;

qcom,mdss-dsi-on-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 fc 5a 5a 39 00 00 00 00 00 02 b0 0c 39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 b0 2f 39 01 00 00 00 00 02 d1 01 39 00 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 03 fc a5 a5 05 01 00 00 0a 00 02 11 00 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 35 00 39 00 00 00 00 00 03 b7 01 4b 39 00 00 00 00 00 02 b0 06 39 00 00 00 00 00 02 b7 10 39 01 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 05 2b 00 00 09 23 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 fc 5a 5a 39 00 00 00 00 00 02 b0 23 39 00 00 00 00 00 02 d1 11 39 00 00 00 00 00 0c e9 11 55 a6 75 a3 b9 a1 4a 00 1a b8 39 00 00 00 00 00 07 e1 00 00 02 02 42 02 39 00 00 00 00 00 07 e2 00 00 00 00 00 00 39 00 00 00 00 00 02 b0 0c 39 00 00 00 00 00 02 e1 19 39 00 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 03 fc a5 a5 39 00 00 00 00 00 02 53 20 39 00 00 00 00 00 03 51 00 00 39 01 00 00 43 00 02 55 00 05 01 00 00 00 00 02 29 00];

qcom,mdss-dsi-h-front-porch = <0x40>;

qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];

qcom,mdss-dsi-h-back-porch = <0x40>;

qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [39 01 00 00 00 00 02 81 91 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b1 00 39 01 00 00 00 00 02 b0 01 39 01 00 00 00 00 16 b1 ae 0c 05 3f c6 14 05 07 aa 4a dd c8 c3 14 c0 e8 dc 19 ff f4 d9 39 01 00 00 00 00 02 b0 16 39 01 00 00 00 00 16 b1 d2 0a 05 1a e6 00 04 07 f5 0c dc db e8 0f dd ee e9 05 ff ff ff 39 01 00 00 00 00 03 f0 a5 a5];

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];

qcom,mdss-dsi-panel-clockrate = <0x4190ab00>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode";

qcom,mdss-dsi-v-pulse-width = <0x14>;

qcom,mdss-dsi-doze-hbm-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 d4 8b 39 00 00 00 00 00 02 b0 a5 39 00 00 00 00 00 02 c7 00 39 00 00 00 00 00 02 b0 69 39 00 00 00 00 00 03 b9 08 8f 39 01 00 00 01 00 02 53 22 39 01 00 00 00 00 03 f0 a5 a5];

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20];

qcom,mdss-dsi-panel-phy-timings = <0x240a0a 0x2625090a 0x6020400>;

qcom,mdss-dsi-v-back-porch = <0x40>;

qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode";

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsi-h-sync-pulse = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00];

qcom,mdss-dsi-dispparam-crc-srgb-on-command = [39 01 00 00 00 00 02 81 90 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b1 00 39 01 00 00 00 00 02 b0 01 39 01 00 00 00 00 16 b1 ae 0c 05 3f c6 14 05 07 aa 4a dd c8 c3 14 c0 e8 dc 19 ff f4 d9 39 01 00 00 00 00 02 b0 16 39 01 00 00 00 00 16 b1 bd 02 00 14 d1 00 04 07 aa 0c ec cb c8 0f dd d9 e4 05 ff ff ff 39 01 00 00 00 00 03 f0 a5 a5];

qcom,mdss-dsi-dispparam-crc-off-command = [39 01 00 00 00 00 02 81 00 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b1 01 39 01 00 00 00 00 03 f0 a5 a5];

qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28];

qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-v-front-porch = <0x40>;

qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];

qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

};

};

};

qcom,gdsc@17d040 {

qcom,no-status-check-on-disable;

qcom,gds-timeout = <0x1f4>;

regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x17d040 0x04>;

phandle = <0x1c8>;

};

i2c@0xa88000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x188>;

clock-names = "se-clk\0m-ahb\0s-ahb";

interrupts = <0x00 0x163 0x00>;

clocks = <0x27 0x5b 0x27 0x69 0x27 0x6a>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x182>;

dma-names = "tx\0rx";

compatible = "qcom,i2c-geni";

pinctrl-1 = <0x189>;

status = "disabled";

reg = <0xa88000 0x4000>;

phandle = <0x35c>;

dmas = <0x183 0x00 0x02 0x03 0x40 0x00 0x183 0x01 0x02 0x03 0x40 0x00>;

};

qcom,kgsl-3d0@5000000 {

qcom,gpu-quirk-secvid-set-once;

qcom,enable-ca-jump;

qcom,ubwc-mode = <0x02>;

qcom,gpu-speed-bin = <0x41a0 0x1fe00000 0x15>;

vddcx-supply = <0x1c5>;

clock-names = "core_clk\0rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk";

qcom,bus-width = <0x20>;

reg-names = "kgsl_3d0_reg_memory\0cx_dbgc\0cx_misc\0qfprom_memory";

qcom,id = <0x00>;

qcom,msm-bus,name = "grp3d";

qcom,highest-bank-bit = <0x0e>;

interrupts = <0x00 0x12c 0x04>;

clocks = <0x2b 0x11 0x2b 0x0e 0x27 0x1b 0x27 0x2b 0x2b 0x0b>;

qcom,msm-bus,num-paths = <0x01>;

qcom,chipid = <0x6010800>;

qcom,msm-bus,num-cases = <0x0c>;

label = "kgsl-3d0";

vdd-supply = <0x24e>;

qcom,pm-qos-active-latency = <0x43>;

compatible = "qcom,kgsl-3d0\0qcom,kgsl-3d";

status = "ok";

qcom,gpu-qdss-stm = <0x161c0000 0x40000>;

qcom,bus-control;

interrupt-names = "kgsl_3d0_irq";

qcom,snapshot-size = <0x200000>;

reg = <0x5000000 0x40000 0x5061000 0x800 0x509e000 0x1000 0x780000 0x6300>;

regulator-names = "vddcx\0vdd";

phandle = <0x21>;

qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x00 0x00 0x1a 0x200 0x00 0x61a80 0x1a 0x200 0x00 0xc3500 0x1a 0x200 0x00 0x124f80 0x1a 0x200 0x00 0x1b86e0 0x1a 0x200 0x00 0x2162e0 0x1a 0x200 0x00 0x2990a0 0x1a 0x200 0x00 0x325aa0 0x1a 0x200 0x00 0x3e12a0 0x1a 0x200 0x00 0x5294a0 0x1a 0x200 0x00 0x5ee8e0 0x1a 0x200 0x00 0x6e1b80>;

cache-slices = <0x1a7 0x0c 0x1a7 0x0b>;

qcom,pm-qos-wakeup-latency = <0x43>;

qcom,no-nap;

qcom,idle-timeout = <0x50>;

qcom,gpubw-dev = <0x2a4>;

qcom,gpu-quirk-hfi-use-reg;

qcom,min-access-length = <0x20>;

#cooling-cells = <0x02>;

qcom,ca-busy-penalty = <0x2ee0>;

cache-slice-names = "gpu\0gpuhtw";

qcom,gpu-mempools {

#address-cells = <0x01>;

#size-cells = <0x00>;

compatible = "qcom,gpu-mempools";

qcom,gpu-mempool@2 {

reg = <0x02>;

qcom,mempool-reserved = <0x100>;

qcom,mempool-page-size = <0x10000>;

};

qcom,gpu-mempool@0 {

qcom,mempool-allocate;

reg = <0x00>;

qcom,mempool-page-size = <0x1000>;

};

qcom,gpu-mempool@3 {

reg = <0x03>;

qcom,mempool-reserved = <0x20>;

qcom,mempool-page-size = <0x100000>;

};

qcom,gpu-mempool@1 {

qcom,mempool-allocate;

reg = <0x01>;

qcom,mempool-page-size = <0x2000>;

};

};

qcom,gpu-pwrlevel-bins {

#address-cells = <0x01>;

#size-cells = <0x00>;

compatible = "qcom,gpu-pwrlevel-bins";

qcom,gpu-pwrlevels-4 {

#address-cells = <0x01>;

qcom,initial-pwrlevel = <0x06>;

#size-cells = <0x00>;

qcom,ca-target-pwrlevel = <0x04>;

qcom,speed-bin = <0xa7>;

qcom,gpu-pwrlevel@1 {

qcom,bus-min = <0x08>;

qcom,bus-freq = <0x0a>;

qcom,bus-max = <0x0b>;

qcom,gpu-freq = <0x26be3680>;

reg = <0x01>;

};

qcom,gpu-pwrlevel@6 {

qcom,bus-min = <0x03>;

qcom,bus-freq = <0x04>;

qcom,bus-max = <0x04>;

qcom,gpu-freq = <0xaba9500>;

reg = <0x06>;

};

qcom,gpu-pwrlevel@4 {

qcom,bus-min = <0x05>;

qcom,bus-freq = <0x07>;

qcom,bus-max = <0x08>;

qcom,gpu-freq = <0x1528dec0>;

reg = <0x04>;

};

qcom,gpu-pwrlevel@2 {

qcom,bus-min = <0x08>;

qcom,bus-freq = <0x09>;

qcom,bus-max = <0x0a>;

qcom,gpu-freq = <0x21ad3740>;

reg = <0x02>;

};

qcom,gpu-pwrlevel@0 {

qcom,bus-min = <0x0a>;

qcom,bus-freq = <0x0b>;

qcom,bus-max = <0x0b>;

qcom,gpu-freq = <0x2faf0800>;

reg = <0x00>;

};

qcom,gpu-pwrlevel@7 {

qcom,bus-min = <0x00>;

qcom,bus-freq = <0x00>;

qcom,bus-max = <0x00>;

qcom,gpu-freq = <0x00>;

reg = <0x07>;

};

qcom,gpu-pwrlevel@5 {

qcom,bus-min = <0x04>;

qcom,bus-freq = <0x06>;

qcom,bus-max = <0x07>;

qcom,gpu-freq = <0xfea18c0>;

reg = <0x05>;

};

qcom,gpu-pwrlevel@3 {

qcom,bus-min = <0x07>;

qcom,bus-freq = <0x08>;

qcom,bus-max = <0x0a>;

qcom,gpu-freq = <0x19a14780>;

reg = <0x03>;

};

};

qcom,gpu-pwrlevels-2 {

#address-cells = <0x01>;

qcom,initial-pwrlevel = <0x06>;

#size-cells = <0x00>;

qcom,ca-target-pwrlevel = <0x04>;

qcom,speed-bin = <0x92>;

qcom,gpu-pwrlevel@1 {

qcom,bus-min = <0x08>;

qcom,bus-freq = <0x0a>;

qcom,bus-max = <0x0b>;

qcom,gpu-freq = <0x26be3680>;

reg = <0x01>;

};

qcom,gpu-pwrlevel@6 {

qcom,bus-min = <0x03>;

qcom,bus-freq = <0x04>;

qcom,bus-max = <0x04>;

qcom,gpu-freq = <0xaba9500>;

reg = <0x06>;

};

qcom,gpu-pwrlevel@4 {

qcom,bus-min = <0x05>;

qcom,bus-freq = <0x07>;

qcom,bus-max = <0x08>;

qcom,gpu-freq = <0x1528dec0>;

reg = <0x04>;

};

qcom,gpu-pwrlevel@2 {

qcom,bus-min = <0x08>;

qcom,bus-freq = <0x09>;

qcom,bus-max = <0x0a>;

qcom,gpu-freq = <0x21ad3740>;

reg = <0x02>;

};

qcom,gpu-pwrlevel@0 {

qcom,bus-min = <0x0a>;

qcom,bus-freq = <0x0b>;

qcom,bus-max = <0x0b>;

qcom,gpu-freq = <0x29b92700>;

reg = <0x00>;

};

qcom,gpu-pwrlevel@7 {

qcom,bus-min = <0x00>;

qcom,bus-freq = <0x00>;

qcom,bus-max = <0x00>;

qcom,gpu-freq = <0x00>;

reg = <0x07>;

};

qcom,gpu-pwrlevel@5 {

qcom,bus-min = <0x04>;

qcom,bus-freq = <0x06>;

qcom,bus-max = <0x07>;

qcom,gpu-freq = <0xfea18c0>;

reg = <0x05>;

};

qcom,gpu-pwrlevel@3 {

qcom,bus-min = <0x07>;

qcom,bus-freq = <0x08>;

qcom,bus-max = <0x0a>;

qcom,gpu-freq = <0x19a14780>;

reg = <0x03>;

};

};

qcom,gpu-pwrlevels-0 {

#address-cells = <0x01>;

qcom,initial-pwrlevel = <0x07>;

#size-cells = <0x00>;

qcom,ca-target-pwrlevel = <0x05>;

qcom,speed-bin = <0x00>;

qcom,gpu-pwrlevel@1 {

qcom,bus-min = <0x0a>;

qcom,bus-freq = <0x0b>;

qcom,bus-max = <0x0b>;

qcom,gpu-freq = <0x2faf0800>;

reg = <0x01>;

};

qcom,gpu-pwrlevel@8 {

qcom,bus-min = <0x00>;

qcom,bus-freq = <0x00>;

qcom,bus-max = <0x00>;

qcom,gpu-freq = <0x00>;

reg = <0x08>;

};

qcom,gpu-pwrlevel@6 {

qcom,bus-min = <0x04>;

qcom,bus-freq = <0x06>;

qcom,bus-max = <0x07>;

qcom,gpu-freq = <0xfea18c0>;

reg = <0x06>;

};

qcom,gpu-pwrlevel@4 {

qcom,bus-min = <0x07>;

qcom,bus-freq = <0x08>;

qcom,bus-max = <0x0a>;

qcom,gpu-freq = <0x19a14780>;

reg = <0x04>;

};

qcom,gpu-pwrlevel@2 {

qcom,bus-min = <0x08>;

qcom,bus-freq = <0x0a>;

qcom,bus-max = <0x0b>;

qcom,gpu-freq = <0x26be3680>;

reg = <0x02>;

};

qcom,gpu-pwrlevel@0 {

qcom,bus-min = <0x0a>;

qcom,bus-freq = <0x0b>;

qcom,bus-max = <0x0b>;

qcom,gpu-freq = <0x312c8040>;

reg = <0x00>;

};

qcom,gpu-pwrlevel@7 {

qcom,bus-min = <0x03>;

qcom,bus-freq = <0x04>;

qcom,bus-max = <0x04>;

qcom,gpu-freq = <0xaba9500>;

reg = <0x07>;

};

qcom,gpu-pwrlevel@5 {

qcom,bus-min = <0x05>;

qcom,bus-freq = <0x07>;

qcom,bus-max = <0x08>;

qcom,gpu-freq = <0x1528dec0>;

reg = <0x05>;

};

qcom,gpu-pwrlevel@3 {

qcom,bus-min = <0x08>;

qcom,bus-freq = <0x09>;

qcom,bus-max = <0x0a>;

qcom,gpu-freq = <0x21ad3740>;

reg = <0x03>;

};

};

qcom,gpu-pwrlevels-3 {

#address-cells = <0x01>;

qcom,initial-pwrlevel = <0x05>;

#size-cells = <0x00>;

qcom,ca-target-pwrlevel = <0x03>;

qcom,speed-bin = <0x80>;

qcom,gpu-pwrlevel@1 {

qcom,bus-min = <0x08>;

qcom,bus-freq = <0x09>;

qcom,bus-max = <0x0a>;

qcom,gpu-freq = <0x21ad3740>;

reg = <0x01>;

};

qcom,gpu-pwrlevel@6 {

qcom,bus-min = <0x00>;

qcom,bus-freq = <0x00>;

qcom,bus-max = <0x00>;

qcom,gpu-freq = <0x00>;

reg = <0x06>;

};

qcom,gpu-pwrlevel@4 {

qcom,bus-min = <0x04>;

qcom,bus-freq = <0x06>;

qcom,bus-max = <0x07>;

qcom,gpu-freq = <0xfea18c0>;

reg = <0x04>;

};

qcom,gpu-pwrlevel@2 {

qcom,bus-min = <0x07>;

qcom,bus-freq = <0x08>;

qcom,bus-max = <0x0a>;

qcom,gpu-freq = <0x19a14780>;

reg = <0x02>;

};

qcom,gpu-pwrlevel@0 {

qcom,bus-min = <0x0a>;

qcom,bus-freq = <0x0b>;

qcom,bus-max = <0x0b>;

qcom,gpu-freq = <0x245bdc80>;

reg = <0x00>;

};

qcom,gpu-pwrlevel@5 {

qcom,bus-min = <0x03>;

qcom,bus-freq = <0x04>;

qcom,bus-max = <0x04>;

qcom,gpu-freq = <0xaba9500>;

reg = <0x05>;

};

qcom,gpu-pwrlevel@3 {

qcom,bus-min = <0x05>;

qcom,bus-freq = <0x07>;

qcom,bus-max = <0x08>;

qcom,gpu-freq = <0x1528dec0>;

reg = <0x03>;

};

};

qcom,gpu-pwrlevels-1 {

#address-cells = <0x01>;

qcom,initial-pwrlevel = <0x07>;

#size-cells = <0x00>;

qcom,ca-target-pwrlevel = <0x05>;

qcom,speed-bin = <0xac>;

qcom,gpu-pwrlevel@1 {

qcom,bus-min = <0x0a>;

qcom,bus-freq = <0x0b>;

qcom,bus-max = <0x0b>;

qcom,gpu-freq = <0x2faf0800>;

reg = <0x01>;

};

qcom,gpu-pwrlevel@8 {

qcom,bus-min = <0x00>;

qcom,bus-freq = <0x00>;

qcom,bus-max = <0x00>;

qcom,gpu-freq = <0x00>;

reg = <0x08>;

};

qcom,gpu-pwrlevel@6 {

qcom,bus-min = <0x04>;

qcom,bus-freq = <0x06>;

qcom,bus-max = <0x07>;

qcom,gpu-freq = <0xfea18c0>;

reg = <0x06>;

};

qcom,gpu-pwrlevel@4 {

qcom,bus-min = <0x07>;

qcom,bus-freq = <0x08>;

qcom,bus-max = <0x0a>;

qcom,gpu-freq = <0x19a14780>;

reg = <0x04>;

};

qcom,gpu-pwrlevel@2 {

qcom,bus-min = <0x08>;

qcom,bus-freq = <0x0a>;

qcom,bus-max = <0x0b>;

qcom,gpu-freq = <0x26be3680>;

reg = <0x02>;

};

qcom,gpu-pwrlevel@0 {

qcom,bus-min = <0x0a>;

qcom,bus-freq = <0x0b>;

qcom,bus-max = <0x0b>;

qcom,gpu-freq = <0x312c8040>;

reg = <0x00>;

};

qcom,gpu-pwrlevel@7 {

qcom,bus-min = <0x03>;

qcom,bus-freq = <0x04>;

qcom,bus-max = <0x04>;

qcom,gpu-freq = <0xaba9500>;

reg = <0x07>;

};

qcom,gpu-pwrlevel@5 {

qcom,bus-min = <0x05>;

qcom,bus-freq = <0x07>;

qcom,bus-max = <0x08>;

qcom,gpu-freq = <0x1528dec0>;

reg = <0x05>;

};

qcom,gpu-pwrlevel@3 {

qcom,bus-min = <0x08>;

qcom,bus-freq = <0x09>;

qcom,bus-max = <0x0a>;

qcom,gpu-freq = <0x21ad3740>;

reg = <0x03>;

};

};

};

};

kgsl_iommu_test_device {

iommus = <0x1cd 0x07>;

compatible = "iommu-debug-test";

};

tpda@7832000 {

arm,primecell-periphid = <0x3b969>;

qcom,cmb-elem-size = <0x00 0x40>;

clock-names = "apb_pclk";

reg-names = "tpda-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpda-olc";

compatible = "arm,primecell";

qcom,tpda-atid = <0x45>;

reg = <0x7832000 0x1000>;

phandle = <0x433>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x208>;

phandle = <0x204>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x209>;

phandle = <0x20a>;

};

};

};

};

qcom,msm_gsi {

compatible = "qcom,msm_gsi";

};

qcom,cpu-cpu-llcc-bw {

qcom,src-dst-ports = <0x01 0x302>;

governor = "performance";

compatible = "qcom,devbw";

phandle = <0xbd>;

qcom,active-only;

operating-points-v2 = <0xbc>;

};

qcom,cdsp-cdsp-l3-lat {

clock-names = "devfreq_clk";

clocks = <0xc0 0x03>;

governor = "powersave";

compatible = "devfreq-simple-dev";

phandle = <0x26>;

};

tpdm@6c28000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-dl-center";

compatible = "arm,primecell";

reg = <0x6c28000 0x1000>;

phandle = <0x44d>;

qcom,msr-fix-req;

port {

endpoint {

remote-endpoint = <0x241>;

phandle = <0x230>;

};

};

};

qcom,smp2p_interrupt_rdbg_5_in {

interrupts-extended = <0x1bf 0x00 0x00>;

compatible = "qcom,smp2p-interrupt-rdbg-5-in";

interrupt-names = "rdbg-smp2p-in";

};

usb_nop_phy {

compatible = "usb-nop-xceiv";

phandle = <0x488>;

};

qcom,msm-dai-tdm-quin-rx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9040>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9140>;

phandle = <0x4c2>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-quin-rx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9040>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x28e>;

};

};

qcom,gdsc@17d030 {

qcom,no-status-check-on-disable;

qcom,gds-timeout = <0x1f4>;

regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x17d030 0x04>;

phandle = <0x1cb>;

};

qcom,csid1@acba000 {

camss-supply = <0x1ae>;

clock-control-debugfs = "true";

clock-names = "ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_clk\0ife_axi_clk";

reg-names = "csid";

reg-cam-base = <0xba000>;

cell-index = <0x01>;

ife1-supply = <0x1b8>;

interrupts = <0x00 0x1d2 0x00>;

clocks = <0x29 0x3c 0x29 0x3b 0x29 0x1b 0x29 0x3a 0x29 0x39 0x29 0x38 0x29 0x37>;

clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";

compatible = "qcom,csid175_200";

src-clock-name = "ife_csid_clk_src";

status = "ok";

interrupt-names = "csid";

reg = <0xacba000 0x1000>;

regulator-names = "camss\0ife1";

phandle = <0x38f>;

clock-rates = <0x11e1a300 0x00 0x00 0x00 0x16a65700 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x1e65fb80 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x25f7d940 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x2d4cae00 0x00 0x00>;

};

cti@69C1000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-dlmm_cti0";

compatible = "arm,primecell";

reg = <0x69c1000 0x1000>;

phandle = <0x466>;

};

cti@6a02000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-ddr_dl_0_cti0";

compatible = "arm,primecell";

reg = <0x6a02000 0x1000>;

phandle = <0x461>;

};

apps_iommu_coherent_test_device {

iommus = <0x30 0x23 0x00>;

dma-coherent;

compatible = "iommu-debug-test";

};

qcom,dsi-display@34 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x53e>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_k6_38_0c_0a_fhd_dsc_video_display";

phandle = <0x55b>;

};

bt_wcn3990 {

qca,bt-vdd-core-supply = <0x32>;

qca,bt-vdd-core-current-level = <0x01>;

qca,bt-vdd-pa-voltage-level = <0x30d400 0x33e140>;

qca,bt-vdd-io-voltage-level = <0x19f0a0 0x1cfde0>;

qca,bt-vdd-xtal-voltage-level = <0x19f0a0 0x1cfde0>;

qca,bt-vdd-pa-supply = <0x33>;

qca,bt-vdd-xtal-supply = <0x34>;

compatible = "qca,wcn3990";

qca,bt-vdd-core-voltage-level = <0x12ff48 0x149970>;

phandle = <0x2b4>;

qca,bt-vdd-pa-current-level = <0x01>;

qca,bt-vdd-io-supply = <0x31>;

qca,bt-vdd-io-current-level = <0x01>;

qca,bt-vdd-xtal-current-level = <0x01>;

};

qcom,gdsc@177004 {

qcom,poll-cfg-gdscr;

regulator-name = "ufs_phy_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0x177004 0x04>;

phandle = <0x9b>;

};

qcom,msm-stub-codec {

compatible = "qcom,msm-stub-codec";

phandle = <0x48c>;

};

rpmh-regulator-ldoa10 {

qcom,mode-threshold-currents = <0x00 0x2710>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa10";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l10 {

regulator-max-microvolt = <0x1bf440>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x1a3ec0>;

regulator-min-microvolt = <0x1a3ec0>;

regulator-name = "pm6150_l10";

qcom,set = <0x03>;

phandle = <0x31>;

};

};

qcom,smp2p_interrupt_rdbg_2_in {

interrupts-extended = <0x1bd 0x00 0x00>;

compatible = "qcom,smp2p-interrupt-rdbg-2-in";

interrupt-names = "rdbg-smp2p-in";

};

qcom,npu-npu-ddr-bw {

qcom,src-dst-ports = <0x9a 0x200>;

governor = "performance";

compatible = "qcom,devbw";

phandle = <0xc8>;

operating-points-v2 = <0xc7>;

};

tpdm@6b44000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-center";

compatible = "arm,primecell";

reg = <0x6b44000 0x1000>;

phandle = <0x45c>;

qcom,msr-fix-req;

port {

endpoint {

remote-endpoint = <0x257>;

phandle = <0x23b>;

};

};

};

qcom,smp2p-modem {

qcom,local-pid = <0x00>;

interrupts = <0x00 0x1c3 0x01>;

qcom,remote-pid = <0x01>;

compatible = "qcom,smp2p";

qcom,smem = <0x1b3 0x1ac>;

qcom,ipc = <0x99 0x00 0x0e>;

qcom,smp2p-ipa-1-in {

qcom,entry-name = "ipa";

#interrupt-cells = <0x02>;

phandle = <0xbb>;

interrupt-controller;

};

slave-kernel {

qcom,entry-name = "slave-kernel";

#interrupt-cells = <0x02>;

phandle = <0xb2>;

interrupt-controller;

};

master-kernel {

qcom,entry-name = "master-kernel";

#qcom,smem-state-cells = <0x01>;

phandle = <0xb3>;

};

qcom,smp2p-ipa-1-out {

qcom,entry-name = "ipa";

#qcom,smem-state-cells = <0x01>;

phandle = <0xba>;

};

qcom,smp2p-wlan-1-in {

qcom,entry-name = "wlan";

#interrupt-cells = <0x02>;

phandle = <0xb9>;

interrupt-controller;

};

};

dummy_sink {

coresight-name = "coresight-eud";

qcom,dummy-sink;

compatible = "qcom,coresight-dummy";

phandle = <0x429>;

port {

endpoint {

slave-mode;

remote-endpoint = <0x1f2>;

phandle = <0x1f3>;

};

};

};

cti@6019000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti9";

compatible = "arm,primecell";

reg = <0x6019000 0x1000>;

phandle = <0x47e>;

};

rpmh-regulator-ldoa5 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa5";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l5 {

regulator-max-microvolt = <0x2ab980>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x27ac40>;

regulator-min-microvolt = <0x27ac40>;

regulator-name = "pm6150_l5";

qcom,set = <0x03>;

phandle = <0x405>;

};

};

qcom,cam-jpeg {

num-jpeg-enc = <0x01>;

num-jpeg-dma = <0x01>;

compat-hw-name = "qcom,jpegenc\0qcom,jpegdma";

compatible = "qcom,cam-jpeg";

status = "ok";

};

qcom,msm-imem@146aa000 {

#address-cells = <0x01>;

#size-cells = <0x01>;

compatible = "qcom,msm-imem";

ranges = <0x00 0x146aa000 0x1000>;

reg = <0x146aa000 0x1000>;

dload_type@1c {

compatible = "qcom,msm-imem-dload-type";

reg = <0x1c 0x04>;

};

restart_reason@65c {

compatible = "qcom,msm-imem-restart_reason";

reg = <0x65c 0x04>;

};

boot_stats@6b0 {

compatible = "qcom,msm-imem-boot_stats";

reg = <0x6b0 0x20>;

};

pil@94c {

compatible = "qcom,msm-imem-pil";

reg = <0x94c 0xc8>;

};

mem_dump_table@10 {

compatible = "qcom,msm-imem-mem_dump_table";

reg = <0x10 0x08>;

};

diag_dload@c8 {

compatible = "qcom,msm-imem-diag-dload";

reg = <0xc8 0xc8>;

};

kaslr_offset@6d0 {

compatible = "qcom,msm-imem-kaslr_offset";

reg = <0x6d0 0x0c>;

};

};

qcom,cpu6-cpu-l3-latmon {

qcom,cachemiss-ev = <0x17>;

qcom,core-dev-table = <0x10b170 0x21301800 0x1433e0 0x2dc6c000 0x1a1300 0x46f41000 0x1d9638 0x5265c000 0x253500 0x56f9a000>;

qcom,cpulist = <0x17 0x18>;

compatible = "qcom,arm-memlat-mon";

phandle = <0x314>;

qcom,target-dev = <0x25>;

};

qcom,gdsc@ad0a004 {

qcom,poll-cfg-gdscr;

clock-names = "ahb_clk";

clocks = <0x27 0x0e>;

regulator-name = "ife_0_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0xad0a004 0x04>;

phandle = <0x1b7>;

};

funnel@6861000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-turing";

compatible = "arm,primecell";

reg = <0x6861000 0x1000>;

phandle = <0x450>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x245>;

phandle = <0x232>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x246>;

phandle = <0x24a>;

};

};

};

};

qcom,dsi-display@24 {

qcom,dsi-phy-num = <0x00 0x01>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x538>;

qcom,dsi-ctrl-num = <0x00 0x01>;

qcom,display-type = "primary";

label = "dsi_sharp_qsync_fhd_video_display";

phandle = <0x559>;

};

ssusb@a600000 {

iommus = <0x30 0x540 0x00>;

qcom,smmu-s1-bypass;

#address-cells = <0x01>;

clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk\0xo";

reg-names = "core_base";

qcom,msm-bus,name = "usb0";

resets = <0x27 0x04>;

interrupts = <0x00 0x1e9 0x00 0x00 0x82 0x00 0x00 0x1e6 0x00 0x00 0x1e8 0x00>;

clocks = <0x27 0x8d 0x27 0x15 0x27 0x0b 0x27 0x8f 0x27 0x91 0x27 0x92>;

qcom,use-pdc-interrupts;

qcom,msm-bus,num-paths = <0x03>;

extcon = <0x25b 0x8a 0x25c>;

#size-cells = <0x01>;

qcom,msm-bus,num-cases = <0x04>;

dpdm-supply = <0x25a>;

qcom,pm-qos-latency = <0x3e>;

qcom,gsi-disable-io-coherency;

qcom,core-clk-rate-hs = <0x3f940ab>;

qcom,num-gsi-evt-buffs = <0x03>;

compatible = "qcom,dwc-usb3-msm";

ranges;

interrupt-names = "dp_hs_phy_irq\0pwr_event_irq\0ss_phy_irq\0dm_hs_phy_irq";

qcom,core-clk-rate = <0x7f28155>;

reg = <0xa600000 0x100000>;

phandle = <0x487>;

qcom,msm-bus,vectors-KBps = <0x3d 0x200 0x00 0x00 0x3d 0x2a4 0x00 0x00 0x01 0x247 0x00 0x00 0x3d 0x200 0xf4240 0x2625a0 0x3d 0x2a4 0x00 0x960 0x01 0x247 0x00 0x9c40 0x3d 0x200 0x3a980 0xaae60 0x3d 0x2a4 0x00 0x960 0x01 0x247 0x00 0x9c40 0x3d 0x200 0x01 0x01 0x3d 0x2a4 0x01 0x01 0x01 0x247 0x01 0x01>;

qcom,dwc-usb3-msm-tx-fifo-size = <0x5328>;

reset-names = "core_reset";

USB3_GDSC-supply = <0x259>;

qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>;

dwc3@a600000 {

linux,sysdev_is_parent;

snps,hird-threshold = [10];

tx-fifo-resize;

snps,dis_enblslpm_quirk;

snps,usb3_lpm_capable;

usb-core-id = <0x00>;

snps,dis_u2_susphy_quirk;

interrupts = <0x00 0x85 0x00>;

num-gsi-eps = <0x03>;

compatible = "snps,dwc3";

snps,disable-clk-gating;

snps,has-lpm-erratum;

reg = <0xa600000 0xcd00>;

usb-phy = <0x25a 0x488>;

dr_mode = "otg";

maximum-speed = "high-speed";

};

qcom,usbbam@a704000 {

qcom,disable-clk-gating;

qcom,usb-bam-num-pipes = <0x04>;

interrupts = <0x00 0x84 0x00>;

qcom,usb-bam-max-mbps-highspeed = <0x190>;

compatible = "qcom,usb-bam-msm";

qcom,usb-bam-max-mbps-superspeed = <0xe10>;

qcom,usb-bam-fifo-baseaddr = <0x146a6000>;

qcom,reset-bam-on-connect;

reg = <0xa704000 0x17000>;

qcom,usb-bam-override-threshold = <0x4001>;

qcom,pipe0 {

qcom,descriptor-fifo-offset = <0x1800>;

qcom,data-fifo-offset = <0x00>;

qcom,usb-bam-mem-type = <0x02>;

qcom,src-bam-pipe-index = <0x00>;

qcom,peer-bam-physical-address = <0x6064000>;

qcom,peer-bam = <0x00>;

qcom,dir = <0x01>;

label = "ssusb-qdss-in-0";

qcom,dst-bam-pipe-index = <0x00>;

qcom,data-fifo-size = <0x1800>;

qcom,pipe-num = <0x00>;

qcom,descriptor-fifo-size = <0x800>;

};

};

};

gpio-regulator@0 {

regulator-max-microvolt = <0x1b7740>;

gpio = <0x2ec 0x04 0x00>;

regulator-enable-ramp-delay = <0x64>;

enable-active-high;

regulator-min-microvolt = <0x1b7740>;

regulator-name = "camera_vddio_regulator";

compatible = "regulator-fixed";

reg = <0x00 0x00>;

phandle = <0x562>;

vin-supply = <0x3fe>;

};

tpda@6831000 {

arm,primecell-periphid = <0x3b969>;

qcom,cmb-elem-size = <0x00 0x40>;

clock-names = "apb_pclk";

reg-names = "tpda-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpda-modem-0";

qcom,dsb-elem-size = <0x00 0x20>;

compatible = "arm,primecell";

qcom,tpda-atid = <0x43>;

reg = <0x6831000 0x1000>;

phandle = <0x425>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1eb>;

phandle = <0x1e9>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x1ec>;

phandle = <0x1ef>;

};

};

};

};

etm@7140000 {

arm,primecell-periphid = <0xbb95d>;

clock-names = "apb_pclk";

clocks = <0x19 0x00>;

cpu = <0x12>;

qcom,tupwr-disable;

coresight-name = "coresight-etm1";

compatible = "arm,primecell";

reg = <0x7140000 0x1000>;

phandle = <0x43d>;

port {

endpoint {

remote-endpoint = <0x21e>;

phandle = <0x216>;

};

};

};

cti@6016000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti6";

compatible = "arm,primecell";

reg = <0x6016000 0x1000>;

phandle = <0x47b>;

};

qcom,glink {

#address-cells = <0x01>;

#size-cells = <0x01>;

compatible = "qcom,glink";

ranges;

adsp {

transport = "smem";

interrupts = <0x00 0xaa 0x01>;

qcom,glink-label = "lpass";

label = "adsp";

qcom,remote-pid = <0x02>;

phandle = <0x94>;

mboxes = <0x93 0x18>;

mbox-names = "adsp_smem";

qcom,adsp_glink_ssr {

qcom,notify-edges = <0x96 0x95>;

qcom,glink-channels = "glink_ssr";

};

qcom,msm_fastrpc_rpmsg {

qcom,intents = <0x64 0x40>;

compatible = "qcom,msm-fastrpc-rpmsg";

qcom,glink-channels = "fastrpcglink-apps-dsp";

};

qcom,apr_tal_rpmsg {

qcom,intents = <0x200 0x14>;

qcom,glink-channels = "apr_audio_svc";

};

qcom,adsp_qrtr {

qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;

qcom,glink-channels = "IPCRTR";

};

};

wdsp {

transport = "spi";

qcom,glink-label = "wdsp";

label = "wdsp";

tx-descriptors = <0x12000 0x12004>;

qcom,remote-pid = <0x0a>;

phandle = <0x2d6>;

rx-descriptors = <0x1200c 0x12010>;

qcom,diag_data {

qcom,intents = <0x4000 0x02>;

qcom,glink-channels = "DIAG_DATA";

};

qcom,wdsp_nild {

qcom,glink-channels = "g_glink_persistent_data_nild";

};

qcom,wdsp_ctrl {

qcom,intents = <0x400 0x01>;

qcom,glink-channels = "g_glink_ctrl";

};

qcom,diag_ctrl {

qcom,intents = <0x4000 0x01>;

qcom,glink-channels = "DIAG_CTRL";

};

qcom,wdsp_ild {

qcom,glink-channels = "g_glink_persistent_data_ild";

};

qcom,diag_cmd {

qcom,intents = <0x4000 0x01>;

qcom,glink-channels = "DIAG_CMD";

};

qcom,wdsp_data {

qcom,intents = <0x1000 0x02>;

qcom,glink-channels = "g_glink_audio_data";

};

};

cdsp {

transport = "smem";

interrupts = <0x00 0x23e 0x01>;

qcom,glink-label = "cdsp";

label = "cdsp";

qcom,remote-pid = <0x05>;

phandle = <0x95>;

mboxes = <0x93 0x04>;

mbox-names = "cdsp_smem";

qcom,cdsp_qrtr {

qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;

qcom,glink-channels = "IPCRTR";

};

qcom,cdsp_glink_ssr {

qcom,notify-edges = <0x96 0x94>;

qcom,glink-channels = "glink_ssr";

};

qcom,msm_fastrpc_rpmsg {

qcom,intents = <0x64 0x40>;

compatible = "qcom,msm-fastrpc-rpmsg";

qcom,glink-channels = "fastrpcglink-apps-dsp";

};

qcom,msm_cdsprm_rpmsg {

qcom,intents = <0x20 0x0c>;

compatible = "qcom,msm-cdsprm-rpmsg";

qcom,glink-channels = "cdsprmglink-apps-dsp";

qcom,msm_cdsp_rm {

qcom,compute-priority-mode = <0x02>;

qcom,qos-maxhold-ms = <0x14>;

compatible = "qcom,msm-cdsp-rm";

qcom,compute-cx-limit-en;

phandle = <0x7d>;

#cooling-cells = <0x02>;

qcom,qos-latency-us = <0x2c>;

};

qcom,msm_hvx_rm {

compatible = "qcom,msm-hvx-rm";

phandle = <0x2d5>;

#cooling-cells = <0x02>;

};

qcom,cdsp-cdsp-l3-gov {

compatible = "qcom,cdsp-l3";

qcom,target-dev = <0x26>;

};

};

};

modem {

transport = "smem";

interrupts = <0x00 0x1c1 0x01>;

qcom,glink-label = "mpss";

label = "modem";

qcom,remote-pid = <0x01>;

phandle = <0x96>;

mboxes = <0x93 0x0c>;

mbox-names = "mpss_smem";

qcom,modem_qrtr {

qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;

qcom,glink-channels = "IPCRTR";

};

qcom,msm_fastrpc_rpmsg {

qcom,intents = <0x64 0x40>;

compatible = "qcom,msm-fastrpc-rpmsg";

qcom,glink-channels = "fastrpcglink-apps-dsp";

};

qcom,modem_glink_ssr {

qcom,notify-edges = <0x94 0x95>;

qcom,glink-channels = "glink_ssr";

};

qcom,modem_ds {

qcom,intents = <0x4000 0x02>;

qcom,glink-channels = "DS";

};

};

};

qcom,qmp-npu-high@9818000 {

reg-names = "msgram\0irq-reg-base";

interrupts = <0x00 0x24d 0x01>;

#mbox-cells = <0x01>;

label = "npu_qmp_high";

mbox-desc-offset = <0x2000>;

priority = <0x01>;

compatible = "qcom,qmp-mbox";

reg = <0x9818000 0x8000 0x17c00010 0x04>;

phandle = <0x2a6>;

qcom,irq-mask = <0x40>;

};

rpmh-regulator-mxlvl {

compatible = "qcom,rpmh-arc-regulator";

qcom,resource-name = "mx.lvl";

mboxes = <0x1b 0x00>;

regulator-pm6150-s3 {

regulator-max-microvolt = <0x10000>;

regulator-min-microvolt = <0x11>;

regulator-name = "pm6150_s3_level";

qcom,init-voltage-level = <0x11>;

qcom,set = <0x03>;

phandle = <0x1f>;

};

regulator-pm6150-s3-level-ao {

regulator-max-microvolt = <0x10000>;

regulator-min-microvolt = <0x11>;

regulator-name = "pm6150_s3_level_ao";

qcom,init-voltage-level = <0x11>;

qcom,set = <0x01>;

phandle = <0x1ce>;

};

mx-cdev-lvl {

compatible = "qcom,regulator-cooling-device";

phandle = <0x68>;

regulator-cdev-supply = <0x1f>;

regulator-levels = <0x101 0x01>;

#cooling-cells = <0x02>;

};

};

jtagmm@7240000 {

clock-names = "core_clk";

reg-names = "etm-base";

clocks = <0x19 0x00>;

compatible = "qcom,jtagv8-mm";

qcom,coresight-jtagmm-cpu = <0x13>;

reg = <0x7240000 0x1000>;

phandle = <0x2aa>;

};

qcom,ghd {

qcom,config-reg = <0x17e00434>;

qcom,threshold-arr = <0x17e0041c>;

compatible = "qcom,gladiator-hang-detect-v3";

};

qcom,cpu-llcc-ddr-bwmon@90cd000 {

reg-names = "base";

interrupts = <0x00 0x51 0x04>;

compatible = "qcom,bimc-bwmon5";

qcom,hw-timer-hz = <0x124f800>;

qcom,count-unit = <0x10000>;

reg = <0x90cd000 0x1000>;

phandle = <0x312>;

qcom,target-dev = <0xbf>;

};

funnel@6b53000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-dl-south";

compatible = "arm,primecell";

reg = <0x6b53000 0x1000>;

phandle = <0x44e>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x242>;

phandle = <0x231>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x243>;

phandle = <0x244>;

};

};

};

};

qcom,smem {

memory-region = <0x90>;

compatible = "qcom,smem";

phandle = <0x2d4>;

hwlocks = <0x91 0x03>;

};

qcom,msm-dai-q6-afe-loopback-tx {

compatible = "qcom,msm-dai-q6-dev";

qcom,msm-dai-q6-dev-id = <0x6001>;

phandle = <0x4cc>;

};

qcom,dsi-display@2 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x524>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_sw43404_amoled_fhd_plus_cmd_display";

phandle = <0x541>;

};

funnel@6b08000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-swao";

compatible = "arm,primecell";

reg = <0x6b08000 0x1000>;

phandle = <0x42d>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1f8>;

phandle = <0x1f7>;

};

};

port@1 {

reg = <0x06>;

endpoint {

slave-mode;

remote-endpoint = <0x1f9>;

phandle = <0x1d3>;

};

};

port@2 {

reg = <0x07>;

endpoint {

slave-mode;

remote-endpoint = <0x1fa>;

phandle = <0x1fb>;

};

};

};

};

qcom,npucc {

#reset-cells = <0x01>;

reg-names = "cc_base";

#clock-cells = <0x01>;

npu_gdsc-supply = <0x23>;

compatible = "qcom,npucc-sdmmagpie\0syscon";

reg = <0x9910000 0x10000>;

phandle = <0x2c>;

vdd_cx-supply = <0x1d>;

};

qcom,msm-rtb {

compatible = "qcom,msm-rtb";

qcom,rtb-size = <0x100000>;

};

qcom,dsi-display@14 {

qcom,dsi-phy-num = <0x01>;

qcom,dsi-select-clocks = "mux_byte_clk1\0mux_pixel_clk1";

qcom,dsi-panel = <0x530>;

qcom,dsi-ctrl-num = <0x01>;

qcom,display-type = "primary";

label = "dsi_nt35695b_truly_fhd_cmd_display";

phandle = <0x54d>;

};

qcom,msm-hdmi-dba-codec-rx {

compatible = "qcom,msm-hdmi-dba-codec-rx";

phandle = <0x4b9>;

qcom,dba-bridge-chip = "adv7533";

};

cti@6013000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti3";

compatible = "arm,primecell";

reg = <0x6013000 0x1000>;

phandle = <0x478>;

};

qcom,dsi-display-secondary {

vdda-3p3-supply = <0x40c>;

pinctrl-names = "panel_active\0panel_suspend";

qcom,panel-te-source = <0x01>;

pinctrl-0 = <0x3c8>;

clock-names = "mux_byte_clk0\0mux_pixel_clk0\0mux_byte_clk1\0mux_pixel_clk1";

clocks = <0x36a 0x06 0x36a 0x09 0x36b 0x20 0x36b 0x23>;

qcom,dsi-display-list = <0x55c 0x55d>;

label = "secondary";

ibb-supply = <0x2f0>;

qcom,dsi-phy = <0x374 0x375>;

compatible = "qcom,dsi-display";

vddio-supply = <0x408>;

pinctrl-1 = <0x3c9>;

lab-supply = <0x2ef>;

phandle = <0x560>;

qcom,dsi-ctrl = <0x372 0x373>;

qcom,platform-te-gpio = <0x174 0x0b 0x00>;

};

rpmh-regulator-ldoc3 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoc3";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150l-l3 {

regulator-max-microvolt = <0x132a40>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x1174c0>;

regulator-min-microvolt = <0x1174c0>;

regulator-name = "pm6150l_l3";

qcom,set = <0x03>;

phandle = <0x1a8>;

};

};

lpi_pinctrl@62b40000 {

qcom,num-gpios = <0x20>;

clock-names = "lpass_core_hw_vote";

gpio-controller;

clocks = <0x4cd 0x00>;

qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000 0x1c000 0x1d000 0x1e000 0x1f000>;

compatible = "qcom,lpi-pinctrl";

reg = <0x62b40000 0x00>;

phandle = <0x4f6>;

#gpio-cells = <0x02>;

rx_swr_clk_active {

phandle = <0x4ff>;

mux {

function = "func2";

pins = "gpio21";

};

config {

pins = "gpio21";

drive-strength = <0x08>;

bias-bus-hold;

};

};

rx_swr_clk_sleep {

phandle = <0x501>;

mux {

function = "func2";

pins = "gpio21";

};

config {

pins = "gpio21";

drive-strength = <0x02>;

bias-bus-hold;

};

};

dmic01_clk_active {

phandle = <0x4f7>;

mux {

function = "func1";

pins = "gpio26";

};

config {

pins = "gpio26";

drive-strength = <0x08>;

output-high;

};

};

dmic01_clk_sleep {

phandle = <0x4f9>;

mux {

function = "func1";

pins = "gpio26";

};

config {

pins = "gpio26";

drive-strength = <0x02>;

bias-disable;

output-low;

};

};

lpi_wcd934x_reset_active {

phandle = <0x509>;

mux {

function = "func2";

pins = "gpio29";

};

config {

pins = "gpio29";

drive-strength = <0x10>;

output-high;

};

};

rx_swr_data_active {

phandle = <0x500>;

mux {

function = "func2";

pins = "gpio22\0gpio23";

};

config {

pins = "gpio22\0gpio23";

drive-strength = <0x08>;

bias-bus-hold;

};

};

dmic23_data_sleep {

phandle = <0x4fe>;

mux {

function = "func1";

pins = "gpio29";

};

config {

pins = "gpio29";

drive-strength = <0x02>;

pull-down;

input-enable;

};

};

rx_swr_data_sleep {

phandle = <0x502>;

mux {

function = "func2";

pins = "gpio22\0gpio23";

};

config {

pins = "gpio22\0gpio23";

drive-strength = <0x02>;

bias-bus-hold;

};

};

tx_swr_data1_sleep {

phandle = <0x507>;

mux {

function = "func3";

pins = "gpio19";

};

config {

pins = "gpio19";

drive-strength = <0x02>;

bias-bus-hold;

};

};

dmic01_data_sleep {

phandle = <0x4fa>;

mux {

function = "func1";

pins = "gpio27";

};

config {

pins = "gpio27";

drive-strength = <0x02>;

pull-down;

input-enable;

};

};

dmic23_data_active {

phandle = <0x4fc>;

mux {

function = "func1";

pins = "gpio29";

};

config {

pins = "gpio29";

drive-strength = <0x08>;

input-enable;

};

};

lpi_wcd937x_reset_active {

phandle = <0x50b>;

mux {

function = "func2";

pins = "gpio24";

};

config {

pins = "gpio24";

drive-strength = <0x10>;

output-high;

};

};

tx_swr_clk_sleep {

phandle = <0x506>;

mux {

function = "func2";

pins = "gpio18";

};

config {

pins = "gpio18";

drive-strength = <0x02>;

bias-bus-hold;

};

};

tx_swr_clk_active {

phandle = <0x503>;

mux {

function = "func2";

pins = "gpio18";

};

config {

pins = "gpio18";

drive-strength = <0x08>;

bias-bus-hold;

};

};

tx_swr_data1_active {

phandle = <0x504>;

mux {

function = "func3";

pins = "gpio19";

};

config {

pins = "gpio19";

drive-strength = <0x08>;

bias-bus-hold;

};

};

tx_swr_data2_sleep {

phandle = <0x508>;

mux {

function = "func2";

pins = "gpio20";

};

config {

pins = "gpio20";

drive-strength = <0x02>;

bias-bus-hold;

};

};

dmic23_clk_sleep {

phandle = <0x4fd>;

mux {

function = "func1";

pins = "gpio28";

};

config {

pins = "gpio28";

drive-strength = <0x02>;

bias-disable;

output-low;

};

};

tx_swr_data2_active {

phandle = <0x505>;

mux {

function = "func2";

pins = "gpio20";

};

config {

pins = "gpio20";

drive-strength = <0x08>;

bias-bus-hold;

};

};

lpi_wcd937x_reset_sleep {

phandle = <0x50c>;

mux {

function = "func2";

pins = "gpio24";

};

config {

pins = "gpio24";

drive-strength = <0x10>;

bias-disable;

output-low;

};

};

lpi_wcd934x_reset_sleep {

phandle = <0x50a>;

mux {

function = "func2";

pins = "gpio29";

};

config {

pins = "gpio29";

drive-strength = <0x10>;

bias-disable;

output-low;

};

};

dmic23_clk_active {

phandle = <0x4fb>;

mux {

function = "func1";

pins = "gpio28";

};

config {

pins = "gpio28";

drive-strength = <0x08>;

output-high;

};

};

dmic01_data_active {

phandle = <0x4f8>;

mux {

function = "func1";

pins = "gpio27";

};

config {

pins = "gpio27";

drive-strength = <0x08>;

input-enable;

};

};

};

qcrypto@1de0000 {

iommus = <0x30 0x504 0x11 0x30 0x514 0x11>;

qcom,ce-hw-shared;

qcom,ce-device = <0x00>;

reg-names = "crypto-base\0crypto-bam-base";

qcom,use-sw-aes-xts-algo;

qcom,clk-mgmt-sus-res;

qcom,msm-bus,name = "qcrypto-noc";

qcom,bam-ee = <0x00>;

interrupts = <0x00 0x110 0x00>;

qcom,use-sw-aead-algo;

qcom,msm-bus,num-paths = <0x01>;

qcom,msm-bus,num-cases = <0x02>;

compatible = "qcom,qcrypto";

qcom,no-clock-support;

qcom,bam-pipe-pair = <0x02>;

qcom,use-sw-ahash-algo;

qcom,use-sw-aes-ccm-algo;

reg = <0x1de0000 0x20000 0x1dc4000 0x24000>;

phandle = <0x2e1>;

qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180>;

qcom,smmu-s1-enable;

qcom,use-sw-hmac-algo;

qcom,use-sw-aes-cbc-ecb-ctr-algo;

qcom,ce-hw-instance = <0x00>;

};

qcom,cpu0-cpu-l3-lat {

clock-names = "devfreq_clk";

clocks = <0xc0 0x00>;

governor = "performance";

compatible = "devfreq-simple-dev";

phandle = <0x24>;

};

qcom,msm-pcm-voice {

qcom,destroy-cvd;

compatible = "qcom,msm-pcm-voice";

phandle = <0x262>;

};

spi@0x884000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x17a>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

interrupts = <0x00 0x25a 0x00>;

clocks = <0x27 0x46 0x27 0x67 0x27 0x68>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x168>;

spi-max-frequency = <0x2faf080>;

dma-names = "tx\0rx";

compatible = "qcom,spi-geni";

pinctrl-1 = <0x17b>;

status = "disabled";

reg = <0x884000 0x4000>;

phandle = <0x355>;

dmas = <0x165 0x00 0x01 0x01 0x40 0x00 0x165 0x01 0x01 0x01 0x40 0x00>;

};

qcom,msm-dai-tdm-pri-tx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9001>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9101>;

phandle = <0x4bb>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-pri-tx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9001>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x287>;

};

};

sdhci@8804000 {

pinctrl-names = "active\0sleep";

qcom,large-address-bus;

qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;

pinctrl-0 = <0x3e5 0x3e7 0x3e9 0x3eb>;

clock-names = "iface_clk\0core_clk";

qcom,bus-width = <0x04>;

reg-names = "hc_mem";

qcom,msm-bus,name = "sdhc2";

qcom,pm-qos-irq-latency = <0x43 0x43>;

qcom,pm-qos-legacy-latency-us = <0x43 0x43 0x43 0x43>;

interrupts = <0x00 0xcc 0x00 0x00 0xde 0x00>;

qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xc0a4680>;

clocks = <0x27 0x70 0x27 0x71>;

qcom,msm-bus,num-paths = <0x02>;

qcom,msm-bus,num-cases = <0x08>;

qcom,vdd-io-current-level = <0x00 0x55f0>;

qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x60152b0 0xbebc200 0xffffffff>;

qcom,pm-qos-cpu-groups = <0x3f 0xc0>;

qcom,pm-qos-irq-type = "affine_irq";

vdd-supply = <0x413>;

compatible = "qcom,sdhci-msm-v5";

qcom,devfreq,freq-table = <0x2faf080 0xc0a4680>;

vdd-io-supply = <0x410>;

pinctrl-1 = <0x3e6 0x3e8 0x3ea 0x3ec>;

qcom,vdd-current-level = <0x00 0xc3500>;

status = "ok";

qcom,dll-hsr-list = <0x7642c 0x00 0x00 0x10800 0x80040868>;

interrupt-names = "hc_irq\0pwr_irq";

reg = <0x8804000 0x1000>;

phandle = <0x2d9>;

qcom,msm-bus,vectors-KBps = <0x51 0x200 0x00 0x00 0x01 0x260 0x00 0x00 0x51 0x200 0x3e8 0x7d0 0x01 0x260 0x640 0x4e20 0x51 0x200 0x4e20 0x9c40 0x01 0x260 0x4e20 0x9c40 0x51 0x200 0x9c40 0x13880 0x01 0x260 0x7530 0xea60 0x51 0x200 0xea60 0x1d4c0 0x01 0x260 0x9c40 0x13880 0x51 0x200 0x13880 0x27100 0x01 0x260 0xc350 0x186a0 0x51 0x200 0x186a0 0x30d40 0x01 0x260 0xea60 0x1d4c0 0x51 0x200 0x146cc2 0x3e8000 0x01 0x260 0x146cc2 0x3e8000>;

cd-gpios = <0x174 0x45 0x00>;

qcom,bus-speed-mode = "SDR12\0SDR25\0SDR50\0DDR50\0SDR104";

qcom,vdd-io-voltage-level = <0x1b7740 0x2d0370>;

};

rpmh-regulator-ldof1 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldof1";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm8009-l1 {

regulator-max-microvolt = <0x13e5c0>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x10c8e0>;

regulator-min-microvolt = <0x10c8e0>;

regulator-name = "pm8009_l1";

qcom,set = <0x03>;

phandle = <0x417>;

};

};

rpmh-regulator-ldoa19 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa19";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l19 {

regulator-max-microvolt = <0x326a40>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x2cec00>;

regulator-min-microvolt = <0x2cec00>;

regulator-name = "pm6150_l19";

qcom,set = <0x03>;

phandle = <0x40d>;

};

};

cdc_dmic23_pinctrl {

pinctrl-names = "aud_active\0aud_sleep";

pinctrl-0 = <0x4fb 0x4fc>;

compatible = "qcom,msm-cdc-pinctrl";

qcom,lpi-gpios;

pinctrl-1 = <0x4fd 0x4fe>;

phandle = <0x4f0>;

};

llcc-pmu@90cc000 {

reg-names = "lagg-base";

compatible = "qcom,qcom-llcc-pmu";

reg = <0x90cc000 0x300>;

phandle = <0x310>;

};

cti@6010000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti0";

compatible = "arm,primecell";

reg = <0x6010000 0x1000>;

phandle = <0x1d5>;

};

qcom,msm-dai-q6-spdif-sec-tx {

compatible = "qcom,msm-dai-q6-spdif";

qcom,msm-dai-q6-dev-id = <0x5003>;

phandle = <0x4cb>;

};

cti@69a6000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-wcss_cti2";

compatible = "arm,primecell";

status = "disabled";

reg = <0x69a6000 0x1000>;

phandle = <0x46c>;

};

funnel@6043000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-in2";

compatible = "arm,primecell";

reg = <0x6043000 0x1000>;

phandle = <0x431>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x200>;

phandle = <0x1dd>;

};

};

port@1 {

reg = <0x02>;

endpoint {

slave-mode;

remote-endpoint = <0x201>;

phandle = <0x202>;

};

};

};

};

tz-log@146aa720 {

hyplog-address-offset = <0x410>;

compatible = "qcom,tz-log";

qcom,hyplog-enabled;

reg = <0x146aa720 0x3000>;

phandle = <0x2e2>;

hyplog-size-offset = <0x414>;

};

csr@6b0e000 {

qcom,blk-size = <0x01>;

clock-names = "apb_pclk";

reg-names = "csr-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-swao-csr";

qcom,timestamp-support;

compatible = "qcom,coresight-csr";

reg = <0x6b0e000 0x1000>;

phandle = <0x42c>;

};

qcom,qup_uart@0xa94000 {

pinctrl-names = "default\0sleep";

pinctrl-0 = <0x194 0x195 0x196>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

clocks = <0x27 0x61 0x27 0x69 0x27 0x6a>;

qcom,wrapper-core = <0x182>;

interrupts-extended = <0x01 0x00 0x166 0x00 0x174 0x5c 0x00>;

compatible = "qcom,msm-geni-serial-hs";

pinctrl-1 = <0x194 0x195 0x196>;

status = "disabled";

reg = <0xa94000 0x4000>;

phandle = <0x362>;

qcom,wakeup-byte = <0xfd>;

};

qcom,vfe-lite0@acc4000 {

camss-supply = <0x1ae>;

clock-control-debugfs = "true";

clock-names = "ife_clk_src\0ife_clk";

reg-names = "ife-lite";

reg-cam-base = <0xc4000>;

cell-index = <0x02>;

interrupts = <0x00 0x1b2 0x00>;

clocks = <0x29 0x3f 0x29 0x3e>;

clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";

compatible = "qcom,vfe-lite175";

src-clock-name = "ife_clk_src";

status = "ok";

interrupt-names = "ife-lite";

reg = <0xacc4000 0x4000>;

regulator-names = "camss";

phandle = <0x392>;

clock-rates = <0x1312d000 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x23c34600 0x00>;

};

funnel@7800000 {

arm,primecell-periphid = <0x3b908>;

clock-names = "apb_pclk";

reg-names = "funnel-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-funnel-apss";

compatible = "arm,primecell";

reg = <0x7800000 0x1000>;

phandle = <0x43b>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x214>;

phandle = <0x203>;

};

};

port@7 {

reg = <0x06>;

endpoint {

slave-mode;

remote-endpoint = <0x21b>;

phandle = <0x223>;

};

};

port@5 {

reg = <0x04>;

endpoint {

slave-mode;

remote-endpoint = <0x219>;

phandle = <0x221>;

};

};

port@3 {

reg = <0x02>;

endpoint {

slave-mode;

remote-endpoint = <0x217>;

phandle = <0x21f>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x215>;

phandle = <0x21d>;

};

};

port@8 {

reg = <0x07>;

endpoint {

slave-mode;

remote-endpoint = <0x21c>;

phandle = <0x224>;

};

};

port@6 {

reg = <0x05>;

endpoint {

slave-mode;

remote-endpoint = <0x21a>;

phandle = <0x222>;

};

};

port@4 {

reg = <0x03>;

endpoint {

slave-mode;

remote-endpoint = <0x218>;

phandle = <0x220>;

};

};

port@2 {

reg = <0x01>;

endpoint {

slave-mode;

remote-endpoint = <0x216>;

phandle = <0x21e>;

};

};

};

};

qcom,msm-pcm-afe {

compatible = "qcom,msm-pcm-afe";

phandle = <0x266>;

};

etm@7740000 {

arm,primecell-periphid = <0xbb95d>;

clock-names = "apb_pclk";

clocks = <0x19 0x00>;

cpu = <0x18>;

qcom,tupwr-disable;

coresight-name = "coresight-etm7";

compatible = "arm,primecell";

reg = <0x7740000 0x1000>;

phandle = <0x443>;

port {

endpoint {

remote-endpoint = <0x224>;

phandle = <0x21c>;

};

};

};

qcom,cpu0-computemon {

qcom,core-dev-table = <0xbb800 0x478 0x130b00 0x6b8 0x16d7a8 0x826 0x1b8a00 0xb71>;

qcom,cpulist = <0x11 0x12 0x13 0x14 0x15 0x16>;

compatible = "qcom,arm-cpu-mon";

phandle = <0x319>;

qcom,target-dev = <0xc5>;

};

qcom,mdss_dsi_k6_38_0c_0a_fhd_dsc_video {

mi,mdss-dsi-doze-lbm-brightness-value = <0x16>;

qcom,mdss-dsi-bl-min-level = <0x04>;

qcom,mdss-pan-physical-width-dimension = <0x45>;

qcom,mdss-dsi-panel-name = "xiaomi k6 38 0c 0a fhd dsc video dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x9a>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-panel-hbm-off-51-index = <0x01>;

qcom,mdss-dsi-t-clk-post = <0x0f>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-panel-id = <0x00>;

qcom,mdss-dsi-oled-panel-video-mode;

qcom,mdss-dsi-mode-sel-gpio-state = "single_port";

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-bl-max-level = <0x7ff>;

qcom,bl-update-flag = "delay_until_first_frame";

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,dispparam-enabled;

qcom,platform-reset-gpio = <0x2ec 0x09 0x00>;

qcom,mdss-dsi-panel-peak-brightness = <0x401640>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-pan-enable-dynamic-fps;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-bl-dcs-type-ss-ea;

qcom,mdss-dsi-reset-sequence = <0x00 0x01 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,mdss-dsi-lane-0-state;

qcom,dsi-supported-dfps-list = <0x78 0x3c>;

qcom,dispparam-f4-51-ctrl-flag;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-t-clk-pre = <0x37>;

qcom,mdss-dsi-panel-hdr-enabled;

phandle = <0x53e>;

qcom,mdss-dsi-bllp-power-mode;

qcom,panel-supply-entries = <0x521>;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

qcom,mdss-dsi-panel-dc-threshold = <0x1e8>;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-panel-k6-dc-flag;

mi,mdss-dsi-doze-hbm-brightness-value = <0x110>;

qcom,mdss-dsi-lane-1-state;

qcom,platform-te-gpio = <0x174 0x0a 0x00>;

qcom,esd-err-irq-gpio = <0x174 0x20 0x2001>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,mdss-brightness-max-level = <0x7ff>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-dispparam-120hz-dc-crc-setting-command-state = "dsi_hs_mode";

qcom,mdss-dsi-dispparam-120hz-dc-crc-setting-command = <0x39010000 0x3f0 0x5a5a3900 0x00 0x2800539 0x00 0x2b100 0x39000000 0x4b0 0x1b139 0x00 0x16b101 0x01 0x01 0x10101 0x10101 0x10101 0x39000000 0x3f0 0xa5a53901 0x00 0x35101e8>;

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,mdss-dsi-dispparam-60hz-dc-crc-setting-command = <0x39000000 0x3f0 0x5a5a3900 0x00 0x2800539 0x00 0x2b100 0x39000000 0x4b0 0x1b139 0x00 0x16b101 0x01 0x01 0x10101 0x10101 0x10101 0x39000000 0x3f0 0xa5a53901 0x00 0x35101e8>;

qcom,display-topology = <0x01 0x01 0x01>;

qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-framerate = <0x78>;

qcom,mdss-dsi-h-pulse-width = <0x1c>;

qcom,mdss-dsi-dispparam-bc-120hz-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode";

qcom,compression-mode = "dsc";

qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-bc-60hz-command-state = "dsi_lp_mode";

qcom,mdss-dsi-doze-lbm-command = [39 01 00 00 00 00 03 51 00 16];

qcom,mdss-dsi-dispparam-hbm-on-command = <0x39010000 0x253 0xe8390100 0x03 0x5107ff39 0x1000000 0x2f70b>;

qcom,mdss-dsi-dispparam-flat-mode-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-hbm-off-command = [39 00 00 00 00 00 02 53 28 39 01 00 00 00 00 03 51 07 ff];

qcom,mdss-dsi-panel-height = <0x960>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [05 01 00 00 14 00 02 11 00 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 03 b2 01 31 39 01 00 00 00 00 06 df 09 30 95 46 e9 39 01 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 02 9d 01 39 01 00 00 00 00 5a 9e 11 00 00 89 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 00 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 60 21 39 01 00 00 00 00 02 f7 0b 39 01 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 04 b0 00 15 f6 39 01 00 00 00 00 02 f6 f0 39 01 00 00 00 00 04 b0 00 28 f6 39 01 00 00 00 00 02 f6 f0 39 01 00 00 00 00 04 b0 00 3b f6 39 01 00 00 00 00 02 f6 f0 39 01 00 00 00 00 04 b0 00 0a f4 39 01 00 00 00 00 02 f4 98 39 01 00 00 00 00 04 b0 00 11 f4 39 01 00 00 00 00 02 f4 ee 39 01 00 00 00 00 04 b0 00 18 b2 39 01 00 00 00 00 02 b2 1c 39 01 00 00 00 00 03 fc 5a 5a 39 00 00 00 00 00 04 b0 00 11 fe 39 00 00 00 00 00 02 fe 00 39 01 00 00 00 00 03 fc a5 a5 39 01 00 00 00 00 04 b0 00 0d b2 39 01 00 00 00 00 02 b2 20 39 01 00 00 00 00 04 b0 00 0c b2 39 01 00 00 00 00 02 b2 30 39 01 00 00 00 00 02 f7 0b 39 01 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 03 fc 5a 5a 39 01 00 00 00 00 08 e1 83 00 00 81 00 f9 f8 39 01 00 00 00 00 03 ed 00 01 39 01 00 00 00 00 04 b0 00 06 f4 39 01 00 00 00 00 02 f4 1f 39 01 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 03 fc a5 a5 39 01 00 00 00 00 02 53 28 39 01 00 00 64 00 03 51 00 00 05 01 00 00 00 00 02 29 00];

qcom,mdss-dsi-h-front-porch = <0x78>;

qcom,mdss-dsi-dispparam-bc-120hz-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 60 01 39 00 00 00 00 00 02 f7 0b 39 01 00 00 00 00 03 f0 a5 a5];

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x78>;

qcom,mdss-dsi-dispparam-flat-mode-off-command = [39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 04 b0 00 88 b1 39 01 00 00 00 00 29 b1 27 0d fb 0f a4 86 01 ff 10 33 ff 10 ff 35 34 5a 0a 0a 0a 29 29 29 37 37 37 41 41 41 45 45 45 1b 2f da 18 74 80 00 00 22 39 01 00 00 00 00 03 f0 a5 a5];

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x14>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-dispparam-flat-mode-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-dispparam-60hz-dc-crc-setting-command-state = "dsi_lp_mode";

qcom,mdss-dsi-doze-hbm-command = [39 01 00 00 00 00 03 51 01 10];

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20];

qcom,mdss-dsi-panel-phy-timings = <0x240a0a 0x2625090a 0x6020400>;

qcom,mdss-dsi-v-back-porch = <0x0a>;

qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode";

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x02>;

qcom,mdss-dsc-scr-version = <0x00>;

qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 96 00 02 10 00];

qcom,mdss-dsi-dispparam-bc-60hz-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 60 21 39 00 00 00 00 00 02 f7 0b 39 01 00 00 00 00 03 f0 a5 a5];

qcom,mdss-dsi-dispparam-crc-off-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 80 00 39 00 00 00 00 00 02 b1 01 39 01 00 00 00 00 03 f0 a5 a5];

qcom,mdss-dsi-dispparam-flat-mode-on-command = [39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 04 b0 00 88 b1 39 01 00 00 00 00 29 b1 27 2d fb 0f a4 86 01 ff 10 33 ff 10 ff 35 34 5a 0a 0a 0a 29 29 29 37 37 37 41 41 41 45 45 45 1b 2f da 18 74 80 00 00 22 39 01 00 00 00 00 03 f0 a5 a5];

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28];

qcom,mdss-dsi-v-front-porch = <0x14>;

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

qcom,mdss-dsc-version = <0x11>;

};

};

};

tpda@78c0000 {

arm,primecell-periphid = <0x3b969>;

qcom,cmb-elem-size = <0x00 0x20>;

clock-names = "apb_pclk";

reg-names = "tpda-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpda-llm-silver";

compatible = "arm,primecell";

qcom,tpda-atid = <0x48>;

reg = <0x78c0000 0x1000>;

phandle = <0x437>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x20e>;

phandle = <0x205>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x20f>;

phandle = <0x210>;

};

};

};

};

rpmh-regulator-ldoa3 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa3";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l3 {

regulator-max-microvolt = <0x103c40>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0xec540>;

regulator-min-microvolt = <0xec540>;

regulator-name = "pm6150_l3";

qcom,set = <0x03>;

phandle = <0x404>;

};

};

qcom,msm-dai-tdm-tert-tx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9021>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9121>;

phandle = <0x4bf>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-tert-tx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9021>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x28b>;

};

};

qcom,dsi-display@22 {

qcom,dsi-phy-num = <0x00 0x01>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x536>;

qcom,dsi-ctrl-num = <0x00 0x01>;

qcom,display-type = "primary";

label = "dsi_sharp_qsync_wqhd_cmd_display";

phandle = <0x557>;

};

qcom,gdsc@ad07004 {

qcom,poll-cfg-gdscr;

clock-names = "ahb_clk";

qcom,support-hw-trigger;

clocks = <0x27 0x0e>;

regulator-name = "bps_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0xad07004 0x04>;

phandle = <0x1bb>;

};

qcom,msm-dai-tdm-pri-rx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9000>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9100>;

phandle = <0x4ba>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-pri-rx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9000>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x286>;

};

};

mailbox@18220000 {

interrupts = <0x00 0x05 0x00>;

#mbox-cells = <0x01>;

label = "apps_rsc";

qcom,drv-id = <0x02>;

compatible = "qcom,tcs-drv";

reg = <0x18220000 0x100 0x18220d00 0x3000>;

phandle = <0x1b>;

qcom,tcs-config = <0x02 0x02 0x00 0x03 0x01 0x03 0x03 0x01>;

};

cxip-cdev@1fed000 {

qcom,bypass-client-list = <0x3004>;

compatible = "qcom,cxip-lm-cooling-device";

qcom,thermal-client-offset = <0x8000>;

reg = <0x1fed000 0x8004>;

phandle = <0x7b>;

#cooling-cells = <0x02>;

};

qcom,msm-dai-q6-spdif-sec-rx {

compatible = "qcom,msm-dai-q6-spdif";

qcom,msm-dai-q6-dev-id = <0x5002>;

phandle = <0x4ca>;

};

fingerprint_fpc {

pinctrl-names = "fpc1020_reset_reset\0fpc1020_reset_active\0fpc1020_irq_active";

pinctrl-2 = <0x586>;

pinctrl-0 = <0x584>;

interrupts = <0x39 0x00>;

fpc,gpio_irq = <0x174 0x39 0x00>;

interrupt-parent = <0x174>;

compatible = "fpc,fpc1020";

pinctrl-1 = <0x585>;

status = "ok";

fpc,gpio_rst = <0x174 0x3a 0x00>;

fp_vdd_vreg-supply = <0x411>;

};

cti@6b07000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-swao_cti3";

compatible = "arm,primecell";

reg = <0x6b07000 0x1000>;

phandle = <0x472>;

};

qcom,qmp-npu-low@9818000 {

reg-names = "msgram\0irq-reg-base";

interrupts = <0x00 0x24c 0x01>;

#mbox-cells = <0x01>;

label = "npu_qmp_low";

mbox-desc-offset = <0x00>;

priority = <0x00>;

compatible = "qcom,qmp-mbox";

reg = <0x9818000 0x8000 0x17c00010 0x04>;

phandle = <0x2a5>;

qcom,irq-mask = <0x20>;

};

qcom,dsi-display@0 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0\0src_byte_clk0\0src_pixel_clk0\0shadow_byte_clk0\0shadow_pixel_clk0";

qcom,dsi-panel = <0x522>;

qcom,dsi-ctrl-num = <0x00>;

qcom,dsi-display-active;

qcom,display-type = "primary";

label = "dsi_sw43404_amoled_video_display";

phandle = <0x53f>;

};

qmi-tmd-devices {

compatible = "qcom,qmi-cooling-devices";

adsp {

qcom,instance-id = <0x01>;

adsp_vdd {

phandle = <0x6a>;

qcom,qmi-dev-name = "cpuv_restriction_cold";

#cooling-cells = <0x02>;

};

};

cdsp {

qcom,instance-id = <0x43>;

cdsp_vdd {

phandle = <0x6b>;

qcom,qmi-dev-name = "cpuv_restriction_cold";

#cooling-cells = <0x02>;

};

};

modem {

qcom,instance-id = <0x00>;

modem_vdd {

phandle = <0x69>;

qcom,qmi-dev-name = "cpuv_restriction_cold";

#cooling-cells = <0x02>;

};

modem_proc {

phandle = <0x88>;

qcom,qmi-dev-name = "modem";

#cooling-cells = <0x02>;

};

modem_pa {

phandle = <0x84>;

qcom,qmi-dev-name = "pa";

#cooling-cells = <0x02>;

};

modem_skin {

phandle = <0x48a>;

qcom,qmi-dev-name = "modem_skin";

#cooling-cells = <0x02>;

};

modem_current {

phandle = <0x489>;

qcom,qmi-dev-name = "modem_current";

#cooling-cells = <0x02>;

};

};

};

qcom,smp2p_interrupt_qvrexternal_5_out {

qcom,smem-state-names = "qvrexternal-smp2p-out";

compatible = "qcom,smp2p-interrupt-qvrexternal-5-out";

qcom,smem-states = <0x1c0 0x00>;

};

qcom,dsi-display@12 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x52e>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_rm69298_truly_amoled_cmd_display";

phandle = <0x54b>;

};

tx_npl_clk {

qcom,codec-ext-clk-src = <0x08>;

#clock-cells = <0x01>;

compatible = "qcom,audio-ref-clk";

phandle = <0x4e1>;

qcom,codec-lpass-clk-id = <0x30d>;

qcom,codec-lpass-ext-clk-freq = <0x124f800>;

};

replicator@6046000 {

arm,primecell-periphid = <0x3b909>;

clock-names = "apb_pclk";

reg-names = "replicator-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-replicator";

compatible = "arm,primecell";

reg = <0x6046000 0x1000>;

phandle = <0x41d>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1d0>;

phandle = <0x1d7>;

};

};

port@1 {

reg = <0x01>;

endpoint {

remote-endpoint = <0x1d1>;

phandle = <0x1d4>;

};

};

port@2 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x1d2>;

phandle = <0x1d8>;

};

};

};

};

qcom,cpu0-cpu-llcc-latmon {

qcom,cachemiss-ev = <0x2a>;

qcom,core-dev-table = <0x1433e0 0x11e1 0x16d7a8 0x1bc6 0x1b8a00 0x23c3>;

qcom,cpulist = <0x11 0x12 0x13 0x14 0x15 0x16>;

compatible = "qcom,arm-memlat-mon";

phandle = <0x315>;

qcom,target-dev = <0xc1>;

};

rpmh-regulator-ldoc1 {

qcom,mode-threshold-currents = <0x00 0x2710>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoc1";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150l-l1 {

regulator-max-microvolt = <0x1e4600>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x18a880>;

regulator-min-microvolt = <0x18a880>;

regulator-name = "pm6150l_l1";

qcom,set = <0x03>;

phandle = <0x34>;

};

};

tpdm@6830000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-modem-0";

compatible = "arm,primecell";

reg = <0x6830000 0x1000>;

phandle = <0x427>;

port {

endpoint {

remote-endpoint = <0x1ef>;

phandle = <0x1ec>;

};

};

};

cti@6b04000 {

arm,primecell-periphid = <0x3b966>;

clock-names = "apb_pclk";

reg-names = "cti-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-cti-swao_cti0";

compatible = "arm,primecell";

reg = <0x6b04000 0x1000>;

phandle = <0x46f>;

};

qcom,msm-compress-dsp {

compatible = "qcom,msm-compress-dsp";

phandle = <0x264>;

};

qcom,camera-flash@1 {

cell-index = <0x01>;

torch-source = <0x2f6>;

switch-source = <0x2fb>;

compatible = "qcom,camera-flash";

status = "ok";

reg = <0x01 0x00>;

phandle = <0x570>;

flash-source = <0x2f3>;

};

turing_etm0 {

qcom,inst-id = <0x0d>;

coresight-name = "coresight-turing-etm0";

compatible = "qcom,coresight-remote-etm";

port {

endpoint {

remote-endpoint = <0x249>;

phandle = <0x248>;

};

};

};

rpmh-regulator-ldoa17 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

pm6150_l17-parent-supply = <0x1cf>;

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa17";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l17 {

regulator-max-microvolt = <0x315100>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x2dc6c0>;

regulator-min-microvolt = <0x2dc6c0>;

regulator-name = "pm6150_l17";

qcom,set = <0x03>;

phandle = <0xa5>;

};

};

tsens@c223000 {

reg-names = "tsens_srot_physical\0tsens_tm_physical";

interrupts = <0x00 0x1fb 0x00 0x00 0x1fd 0x00>;

#thermal-sensor-cells = <0x01>;

compatible = "qcom,tsens24xx";

interrupt-names = "tsens-upper-lower\0tsens-critical";

reg = <0xc223000 0x08 0xc265000 0x1ff>;

phandle = <0x5a>;

tsens-reinit-wa;

};

qcom,mdss_dsi_pll@ae96a00 {

clock-names = "iface_clk";

reg-names = "pll_base\0phy_base\0gdsc_base\0dynamic_pll_base";

cell-index = <0x01>;

clocks = <0x2a 0x01>;

#clock-cells = <0x01>;

label = "MDSS DSI 1 PLL";

compatible = "qcom,mdss_dsi_pll_10nm";

gdsc-supply = <0xcb>;

clock-rate = <0x00>;

reg = <0xae96a00 0x1e0 0xae96400 0x800 0xaf03000 0x08 0xae96200 0x100>;

phandle = <0x36b>;

qcom,platform-supply-entries {

#address-cells = <0x01>;

#size-cells = <0x00>;

qcom,platform-supply-entry@0 {

qcom,supply-disable-load = <0x00>;

qcom,supply-enable-load = <0x00>;

qcom,supply-name = "gdsc";

qcom,supply-max-voltage = <0x00>;

reg = <0x00>;

qcom,supply-min-voltage = <0x00>;

};

};

};

qcom,cam-req-mgr {

compatible = "qcom,cam-req-mgr";

status = "ok";

};

qcom,msm-dai-tdm-tert-rx {

qcom,msm-cpudai-tdm-clk-rate = <0x177000>;

qcom,msm-cpudai-tdm-data-out = <0x00>;

qcom,msm-cpudai-tdm-data-delay = <0x01>;

qcom,msm-cpudai-tdm-group-port-id = <0x9020>;

qcom,msm-cpudai-tdm-group-num-ports = <0x01>;

qcom,msm-cpudai-tdm-invert-sync = <0x01>;

compatible = "qcom,msm-dai-tdm";

qcom,msm-cpudai-tdm-group-id = <0x9120>;

phandle = <0x4be>;

qcom,msm-cpudai-tdm-sync-src = <0x01>;

qcom,msm-cpudai-tdm-clk-internal = <0x01>;

qcom,msm-cpudai-tdm-sync-mode = <0x01>;

qcom,msm-dai-q6-tdm-tert-rx-0 {

qcom,msm-cpudai-tdm-dev-id = <0x9020>;

qcom,msm-cpudai-tdm-data-align = <0x00>;

compatible = "qcom,msm-dai-q6-tdm";

phandle = <0x28a>;

};

};

spi@0xa84000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x199>;

clock-names = "se-clk\0m-ahb\0s-ahb";

reg-names = "se_phys";

interrupts = <0x00 0x162 0x00>;

clocks = <0x27 0x59 0x27 0x69 0x27 0x6a>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x182>;

spi-max-frequency = <0x2faf080>;

dma-names = "tx\0rx";

compatible = "qcom,spi-geni";

pinctrl-1 = <0x19a>;

status = "disabled";

reg = <0xa84000 0x4000>;

phandle = <0x364>;

dmas = <0x183 0x00 0x01 0x01 0x40 0x00 0x183 0x01 0x01 0x01 0x40 0x00>;

};

qcom,msm-pcm-hostless {

compatible = "qcom,msm-pcm-hostless";

phandle = <0x265>;

};

restart@c264000 {

reg-names = "pshold-base\0tcsr-boot-misc-detect";

compatible = "qcom,pshold";

reg = <0xc264000 0x04 0x1fd3000 0x04>;

};

audio_ext_clk {

pinctrl-names = "active\0sleep";

pinctrl-0 = <0x2e7>;

clock-names = "osr_clk";

qcom,audio-ref-clk-gpio = <0x2e6 0x08 0x00>;

qcom,codec-ext-clk-src = <0x00>;

clocks = <0xa9>;

#clock-cells = <0x01>;

qcom,use-pinctrl = <0x01>;

qcom,node_has_rpm_clock;

compatible = "qcom,audio-ref-clk";

pmic-clock-names = "pm6150_div_clk1";

pinctrl-1 = <0x2e7>;

status = "disabled";

phandle = <0x511>;

};

etm@7040000 {

arm,primecell-periphid = <0xbb95d>;

clock-names = "apb_pclk";

clocks = <0x19 0x00>;

cpu = <0x11>;

qcom,tupwr-disable;

coresight-name = "coresight-etm0";

compatible = "arm,primecell";

reg = <0x7040000 0x1000>;

phandle = <0x43c>;

port {

endpoint {

remote-endpoint = <0x21d>;

phandle = <0x215>;

};

};

};

mailbox@17c00000 {

#mbox-cells = <0x01>;

compatible = "qcom,sm8150-apcs-hmss-global";

reg = <0x17c00000 0x1000>;

phandle = <0x93>;

};

syscon@5091540 {

compatible = "syscon";

reg = <0x5091540 0x04>;

phandle = <0xcc>;

};

qcom,msm-ext-disp {

compatible = "qcom,msm-ext-disp";

phandle = <0x1ab>;

qcom,msm-ext-disp-audio-codec-rx {

compatible = "qcom,msm-ext-disp-audio-codec-rx";

phandle = <0x376>;

};

};

qcom,gdsc@ab00874 {

clock-names = "ahb_clk";

qcom,support-hw-trigger;

clocks = <0x27 0x9b>;

regulator-name = "mvs0_gdsc";

compatible = "qcom,gdsc";

status = "ok";

reg = <0xab00874 0x04>;

phandle = <0x1a1>;

};

qcom,msm-pcm-low-latency {

qcom,msm-pcm-dsp-id = <0x01>;

qcom,latency-level = "regular";

compatible = "qcom,msm-pcm-dsp";

phandle = <0x25f>;

qcom,msm-pcm-low-latency;

};

jtagmm@7140000 {

clock-names = "core_clk";

reg-names = "etm-base";

clocks = <0x19 0x00>;

compatible = "qcom,jtagv8-mm";

qcom,coresight-jtagmm-cpu = <0x12>;

reg = <0x7140000 0x1000>;

phandle = <0x2a9>;

};

ipa_smmu_wlan {

iommus = <0x30 0x521 0x00>;

qcom,smmu-s1-bypass;

qcom,additional-mapping = <0x1e60000 0x1e60000 0x80000>;

compatible = "qcom,ipa-smmu-wlan-cb";

phandle = <0x31d>;

};

rx_swr_clk_data_pinctrl {

pinctrl-names = "aud_active\0aud_sleep";

pinctrl-0 = <0x4ff 0x500>;

compatible = "qcom,msm-cdc-pinctrl";

qcom,lpi-gpios;

pinctrl-1 = <0x501 0x502>;

phandle = <0x4e5>;

};

qcom,msm-pri-auxpcm {

qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;

qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;

qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;

qcom,msm-auxpcm-interface = "primary";

qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;

qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;

qcom,msm-cpudai-afe-clk-ver = <0x02>;

qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;

compatible = "qcom,msm-auxpcm-dev";

qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;

phandle = <0x271>;

qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;

};

rpmh-regulator-ldoa1 {

qcom,mode-threshold-currents = <0x00 0x01>;

qcom,regulator-type = "pmic5-ldo";

compatible = "qcom,rpmh-vrm-regulator";

qcom,resource-name = "ldoa1";

mboxes = <0x1b 0x00>;

qcom,supported-modes = <0x02 0x04>;

regulator-pm6150-l1 {

regulator-max-microvolt = <0x13e5c0>;

qcom,init-mode = <0x02>;

qcom,init-voltage = <0x10b940>;

regulator-min-microvolt = <0x10b940>;

regulator-name = "pm6150_l1";

qcom,set = <0x03>;

phandle = <0x402>;

};

};

tpdm@7860000 {

arm,primecell-periphid = <0x3b968>;

clock-names = "apb_pclk";

reg-names = "tpdm-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpdm-apss";

compatible = "arm,primecell";

reg = <0x7860000 0x1000>;

phandle = <0x436>;

port {

endpoint {

remote-endpoint = <0x20d>;

phandle = <0x20c>;

};

};

};

qcom,dsi-display@9 {

qcom,dsi-phy-num = <0x00 0x01>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x52b>;

qcom,dsi-ctrl-num = <0x00 0x01>;

qcom,display-type = "primary";

label = "dsi_dual_sharp_wqhd_video_display";

phandle = <0x548>;

};

qcom,mdss_dsi_g7b_37_02_0a_dsc_video {

qcom,mdss-pan-physical-width-dimension = <0x46>;

qcom,mdss-dsi-panel-name = "xiaomi 37 02 0a video mode dsc dsi panel";

qcom,mdss-pan-physical-height-dimension = <0x9a>;

qcom,mdss-dsi-color-order = "rgb_swap_rgb";

qcom,mdss-dsi-underflow-color = <0x00>;

qcom,mdss-dsi-t-clk-post = <0x0e>;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-panel-id = <0x00>;

qcom,mdss-dsi-pan-enable-smart-fps;

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-panel-max-luminance = <0x0f 0x20>;

qcom,bl-update-flag = "delay_until_first_frame";

qcom,mdss-dsi-panel-blackness-level = <0xc9e>;

qcom,mdss-dsi-panel-xy-coordinate = <0x0f 0x18>;

qcom,mdss-dsi-qsync-min-refresh-rate = <0x3c>;

qcom,mdss-dsi-panel-max-luminance-valid = <0x01 0x01>;

qcom,dispparam-enabled;

qcom,mdss-dsi-panel-peak-brightness = <0x401640>;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";

qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;

qcom,mdss-dsi-pan-enable-dynamic-fps;

qcom,mdss-dsi-virtual-channel-id = <0x00>;

qcom,mdss-dsi-reset-sequence = <0x01 0x05 0x00 0x01 0x01 0x0a>;

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,is-tddi-flag;

qcom,mdss-dsi-lane-0-state;

qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c 0x32 0x1e>;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-panel-on-dimming-delay = <0xc8>;

qcom,mdss-dsi-t-clk-pre = <0x34>;

qcom,mdss-dsi-panel-hdr-enabled;

qcom,cont-splash-enabled;

qcom,mdss-dsi-panel-model = "xiaomi 37 02 0a VIDEO PANEL";

phandle = <0x534>;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-stream = <0x00>;

qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-tx-eot-append;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-border-color = <0x00>;

qcom,mdss-dsi-lane-1-state;

qcom,esd-err-irq-gpio = <0x174 0x20 0x2002>;

qcom,mdss-dsi-bpp = <0x18>;

qcom,disp-panel-offon-mode-enabled;

qcom,mdss-brightness-max-level = <0xfff>;

qcom,mdss-dsi-display-timings {

timing@0 {

qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_hs_mode";

qcom,mdss-dsi-v-bottom-border = <0x00>;

qcom,display-topology = <0x01 0x01 0x01>;

qcom,mdss-dsi-panel-framerate = <0x78>;

qcom,mdss-dsi-h-pulse-width = <0x0c>;

qcom,mdss-dsi-dispparam-xy-coordinate-command = [15 01 00 00 00 00 02 ff 10 06 01 00 01 05 00 02 a1 00];

qcom,mdss-dsi-read-lockdown-info-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command = [39 01 00 00 00 00 03 51 0d b5];

qcom,mdss-dsi-dispparam-xy-coordinate-command-state = "dsi_hs_mode";

qcom,compression-mode = "dsc";

qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_hs_mode";

qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode";

qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-lcd-hbm-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-cabcmovieon-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 03];

qcom,mdss-dsi-panel-height = <0x960>;

qcom,mdss-dsc-bit-per-pixel = <0x08>;

qcom,mdss-dsi-panel-xy-coordinate = <0x0f 0x18>;

qcom,mdss-dsc-block-prediction-enable;

qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 23 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 00 80 15 00 00 00 00 00 02 07 00 15 00 00 00 00 00 02 08 01 15 00 00 00 00 00 02 09 45 15 01 00 00 00 00 02 ff 20 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 01 66 15 00 00 00 00 00 02 32 4d 15 00 00 00 00 00 02 69 d1 15 00 00 00 00 00 02 f2 64 15 00 00 00 00 00 02 f4 64 15 00 00 00 00 00 02 f6 64 15 00 00 00 00 00 02 f9 64 15 01 00 00 00 00 02 ff 26 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 81 0e 15 00 00 00 00 00 02 84 03 15 00 00 00 00 00 02 86 03 15 00 00 00 00 00 02 88 07 15 01 00 00 00 00 02 ff 27 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 e3 01 15 00 00 00 00 00 02 e4 ec 15 00 00 00 00 00 02 e5 02 15 00 00 00 00 00 02 e6 e3 15 00 00 00 00 00 02 e7 01 15 00 00 00 00 00 02 e8 ec 15 00 00 00 00 00 02 e9 02 15 00 00 00 00 00 02 ea 22 15 00 00 00 00 00 02 eb 03 15 00 00 00 00 00 02 ec 32 15 00 00 00 00 00 02 ed 02 15 00 00 00 00 00 02 ee 22 15 01 00 00 00 00 02 ff 2a 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 0c 04 15 00 00 00 00 00 02 0f 01 15 00 00 00 00 00 02 11 e0 15 00 00 00 00 00 02 15 0e 15 00 00 00 00 00 02 16 78 15 00 00 00 00 00 02 19 0d 15 00 00 00 00 00 02 1a f4 15 00 00 00 00 00 02 37 6e 15 00 00 00 00 00 02 88 76 15 01 00 00 00 00 02 ff 2c 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 4d 1e 15 00 00 00 00 00 02 4e 04 15 00 00 00 00 00 02 4f 00 15 00 00 00 00 00 02 9d 1e 15 00 00 00 00 00 02 9e 04 15 00 00 00 00 00 02 9f 17 15 01 00 00 00 00 02 ff f0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 ff e0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 25 00 15 00 00 00 00 00 02 4e 02 15 00 00 00 00 00 02 85 02 15 01 00 00 00 00 02 ff d0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 09 ad 15 01 00 00 00 00 02 ff 20 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 f8 64 15 01 00 00 00 00 02 ff 2a 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 1a f0 15 00 00 00 00 00 02 30 5e 15 00 00 00 00 00 02 31 ca 15 00 00 00 00 00 02 34 fe 15 00 00 00 00 00 02 35 35 15 00 00 00 00 00 02 36 a2 15 00 00 00 00 00 02 37 f8 15 00 00 00 00 00 02 38 37 15 00 00 00 00 00 02 39 a0 15 00 00 00 00 00 02 3a 5e 15 00 00 00 00 00 02 53 d7 15 00 00 00 00 00 02 88 72 15 01 00 00 00 00 02 ff 24 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 c6 c0 15 01 00 00 00 00 02 ff 23 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 00 80 15 00 00 00 00 00 02 01 84 15 00 00 00 00 00 02 05 2d 15 00 00 00 00 00 02 06 00 15 00 00 00 00 00 02 07 00 15 00 00 00 00 00 02 08 01 15 00 00 00 00 00 02 09 45 15 00 00 00 00 00 02 11 01 15 00 00 00 00 00 02 12 95 15 00 00 00 00 00 02 15 68 15 00 00 00 00 00 02 16 0b 15 00 00 00 00 00 02 29 0a 15 00 00 00 00 00 02 30 ff 15 00 00 00 00 00 02 31 fe 15 00 00 00 00 00 02 32 fd 15 00 00 00 00 00 02 33 fb 15 00 00 00 00 00 02 34 f8 15 00 00 00 00 00 02 35 f5 15 00 00 00 00 00 02 36 f3 15 00 00 00 00 00 02 37 f2 15 00 00 00 00 00 02 38 f2 15 00 00 00 00 00 02 39 f2 15 00 00 00 00 00 02 3a ef 15 00 00 00 00 00 02 3b ec 15 00 00 00 00 00 02 3d e9 15 00 00 00 00 00 02 3f e5 15 00 00 00 00 00 02 40 e5 15 00 00 00 00 00 02 41 e5 15 00 00 00 00 00 02 2a 13 15 00 00 00 00 00 02 45 ff 15 00 00 00 00 00 02 46 f4 15 00 00 00 00 00 02 47 e7 15 00 00 00 00 00 02 48 da 15 00 00 00 00 00 02 49 cd 15 00 00 00 00 00 02 4a c0 15 00 00 00 00 00 02 4b b3 15 00 00 00 00 00 02 4c b2 15 00 00 00 00 00 02 4d b2 15 00 00 00 00 00 02 4e b2 15 00 00 00 00 00 02 4f 99 15 00 00 00 00 00 02 50 80 15 00 00 00 00 00 02 51 68 15 00 00 00 00 00 02 52 66 15 00 00 00 00 00 02 53 66 15 00 00 00 00 00 02 54 66 15 00 00 00 00 00 02 2b 0e 15 00 00 00 00 00 02 58 ff 15 00 00 00 00 00 02 59 fb 15 00 00 00 00 00 02 5a f7 15 00 00 00 00 00 02 5b f3 15 00 00 00 00 00 02 5c ef 15 00 00 00 00 00 02 5d e3 15 00 00 00 00 00 02 5e da 15 00 00 00 00 00 02 5f d8 15 00 00 00 00 00 02 60 d8 15 00 00 00 00 00 02 61 d8 15 00 00 00 00 00 02 62 cb 15 00 00 00 00 00 02 63 bf 15 00 00 00 00 00 02 64 b3 15 00 00 00 00 00 02 65 b2 15 00 00 00 00 00 02 66 b2 15 00 00 00 00 00 02 67 b2 15 01 00 00 00 00 02 ff c0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 9c 11 15 00 00 00 00 00 02 9d 11 15 01 00 00 00 00 02 ff f0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 9c 00 15 01 00 00 00 00 02 ff 10 15 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 03 51 0b 6c 15 00 00 00 00 00 02 53 24 15 01 00 00 46 00 02 11 00 15 01 00 00 00 00 02 29 00 15 01 00 00 00 00 02 ff 27 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 3f 01 15 00 00 00 00 00 02 43 08 15 00 00 00 00 00 02 40 25 15 01 00 00 00 00 02 ff e0 15 00 00 00 00 00 02 35 82 15 01 00 00 00 00 02 ff 10];

qcom,mdss-dsi-h-front-porch = <0x28>;

qcom,mdss-dsc-slice-width = <0x21c>;

qcom,mdss-dsi-h-back-porch = <0x28>;

qcom,mdss-dsi-dispparam-cabcstillon-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 02];

qcom,mdss-dsi-dispparam-cabcuion-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 01];

qcom,mdss-dsi-h-left-border = <0x00>;

qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command = [39 01 00 00 00 00 03 51 0e 8c];

qcom,mdss-dsi-dispparam-lcd-hbm-off-command = [39 01 00 00 00 00 03 51 0b 6c];

qcom,mdss-dsi-h-right-border = <0x00>;

qcom,mdss-dsc-slice-height = <0x14>;

qcom,mdss-dsi-h-sync-skew = <0x00>;

qcom,mdss-dsi-panel-width = <0x438>;

qcom,mdss-dsi-v-pulse-width = <0x02>;

qcom,mdss-dsi-dispparam-cabcoff-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00];

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 24];

qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5020400>;

qcom,mdss-dsi-v-back-porch = <0x1e>;

qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command-state = "dsi_lp_mode";

qcom,default-topology-index = <0x00>;

qcom,mdss-dsi-v-top-border = <0x00>;

qcom,mdss-dsc-slice-per-pkt = <0x02>;

qcom,mdss-dsi-h-sync-pulse = <0x01>;

qcom,mdss-dsc-scr-version = <0x00>;

qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 27 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 3f 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 28 00 15 01 00 00 46 00 02 10 00];

qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode";

qcom,mdss-dsi-dispparam-cabcuion-command-state = "dsi_hs_mode";

qcom,mdss-dsc-bit-per-component = <0x08>;

qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c];

qcom,mdss-dsi-v-front-porch = <0x20>;

qcom,mdss-dsi-displayoff-command = [15 01 00 00 20 00 02 28 00];

qcom,mdss-dsi-displayon-command = [15 01 00 00 14 00 02 29 00];

qcom,mdss-dsi-read-lockdown-info-command = [15 01 00 00 00 00 02 ff 21 06 01 00 00 00 00 01 f1];

qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_hs_mode";

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

qcom,mdss-dsc-version = <0x11>;

};

};

};

i2c@0x884000 {

pinctrl-names = "default\0sleep";

#address-cells = <0x01>;

pinctrl-0 = <0x169>;

clock-names = "se-clk\0m-ahb\0s-ahb";

interrupts = <0x00 0x25a 0x00>;

clocks = <0x27 0x46 0x27 0x67 0x27 0x68>;

#size-cells = <0x00>;

qcom,wrapper-core = <0x168>;

dma-names = "tx\0rx";

compatible = "qcom,i2c-geni";

pinctrl-1 = <0x16a>;

status = "disabled";

reg = <0x884000 0x4000>;

phandle = <0x34e>;

dmas = <0x165 0x00 0x01 0x03 0x40 0x00 0x165 0x01 0x01 0x03 0x40 0x00>;

};

tpda@6b01000 {

arm,primecell-periphid = <0x3b969>;

qcom,cmb-elem-size = <0x00 0x40>;

clock-names = "apb_pclk";

reg-names = "tpda-base";

clocks = <0x19 0x00>;

coresight-name = "coresight-tpda-swao";

qcom,dsb-elem-size = <0x01 0x20>;

compatible = "arm,primecell";

qcom,tpda-atid = <0x47>;

reg = <0x6b01000 0x1000>;

phandle = <0x42e>;

ports {

#address-cells = <0x01>;

#size-cells = <0x00>;

port@0 {

reg = <0x00>;

endpoint {

remote-endpoint = <0x1fb>;

phandle = <0x1fa>;

};

};

port@1 {

reg = <0x00>;

endpoint {

slave-mode;

remote-endpoint = <0x1fc>;

phandle = <0x1fe>;

};

};

port@2 {

reg = <0x01>;

endpoint {

slave-mode;

remote-endpoint = <0x1fd>;

phandle = <0x1ff>;

};

};

};

};

qcom,camcc {

#reset-cells = <0x01>;

reg-names = "cc_base";

#clock-cells = <0x01>;

vdd_mx-supply = <0x1f>;

compatible = "qcom,camcc-sdmmagpie\0syscon";

reg = <0xad00000 0x10000>;

phandle = <0x29>;

vdd_cx-supply = <0x1d>;

};

qcom,dsi-display@20 {

qcom,dsi-phy-num = <0x00>;

qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";

qcom,dsi-panel = <0x534>;

qcom,dsi-ctrl-num = <0x00>;

qcom,display-type = "primary";

label = "dsi_g7b_37_02_0a_video_display";

phandle = <0x556>;

};

slim@62dc0000 {

reg-names = "slimbus_physical\0slimbus_bam_physical";

cell-index = <0x01>;

qcom,iommu-s1-bypass;

interrupts = <0x00 0xa3 0x00 0x00 0xa4 0x00>;

qcom,apps-ch-pipes = <0x7c0000>;

compatible = "qcom,slim-ngd";

status = "disabled";

interrupt-names = "slimbus_irq\0slimbus_bam_irq";

reg = <0x62dc0000 0x2c000 0x62d84000 0x2a000>;

phandle = <0x2b5>;

qcom,ea-pc = <0x300>;

qcom,iommu_slim_ctrl_cb {

iommus = <0x30 0x1be6 0x08 0x30 0x1bed 0x02 0x30 0x1bf0 0x01>;

compatible = "qcom,iommu-slim-ctrl-cb";

phandle = <0x2b6>;

};

tavil_codec {

cdc-buck-sido-supply = <0x512>;

qcom,cdc-buck-sido-voltage = <0x1b7740 0x1b7740>;

qcom,cdc-vddpx-1-voltage = <0x1b7740 0x1b7740>;

qcom,cdc-vdd-mic-bias-voltage = <0x324b00 0x324b00>;

qcom,cdc-buck-sido-current = <0x7a120>;

qcom,cdc-vddpx-1-current = <0x2710>;

qcom,cdc-vdd-mic-bias-current = <0x76c0 0xf4241>;

qcom,wcd-rst-gpio-node = <0x510>;

qcom,wdsp-cmpnt-dev-name = "tavil_codec";

clock-names = "wcd_clk";

cdc-vdd-tx-h-supply = <0x512>;

elemental-addr = [00 01 50 02 17 02];

qcom,cdc-micbias2-mv = <0x708>;

interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>;

clocks = <0x511 0x00>;

cdc-vdd-buck-supply = <0x512>;

qcom,cdc-mclk-clk-rate = <0x927c00>;

cdc-vdd-rx-h-supply = <0x512>;

qcom,cdc-mad-dmic-rate = <0x927c0>;

interrupt-parent = <0x50f>;

qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02];

qcom,cdc-static-supplies = "cdc-vdd-buck\0cdc-buck-sido\0cdc-vdd-tx-h\0cdc-vdd-rx-h\0cdc-vddpx-1";

qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>;

compatible = "qcom,tavil-slim-pgd";

qcom,cdc-vdd-tx-h-voltage = <0x1b7740 0x1b7740>;

qcom,cdc-vdd-buck-current = <0x91050>;

qcom,cdc-micbias4-mv = <0x708>;

cdc-vdd-mic-bias-supply = <0x415>;

qcom,cdc-vdd-tx-h-current = <0x61a8>;

qcom,cdc-micbias1-mv = <0x708>;

status = "disabled";

cdc-vddpx-1-supply = <0x512>;

qcom,cdc-dmic-sample-rate = <0x493e00>;

phandle = <0x50d>;

qcom,vreg-micb-supply = <0x415>;

qcom,cdc-vdd-rx-h-voltage = <0x1b7740 0x1b7740>;

qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias";

qcom,cdc-vdd-rx-h-current = <0x61a8>;

qcom,cdc-slim-ifd = "tavil-slim-ifd";

qcom,cdc-micbias3-mv = <0x708>;

wcd_spi {

qcom,chip-select = <0x00>;

qcom,master-bus-num = <0x00>;

qcom,mem-base-addr = <0x100000>;

qcom,max-frequency = <0x16e3600>;

compatible = "qcom,wcd-spi-v2";

phandle = <0x50e>;

};

};

msm_dai_slim {

elemental-addr = [ff ff ff fe 17 02];

compatible = "qcom,msm-dai-slim";

status = "disabled";

phandle = <0x2b7>;

};

};

};

psci {

method = "smc";

compatible = "arm,psci-1.0";

};

aliases {

spi2 = "/soc/spi@0xa88000";

sdhc2 = "/soc/sdhci@8804000";

i2c1 = "/soc/i2c@0xa84000";

swr2 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/tx-macro@62ec0000/tx_swr_master";

spi0 = "/soc/spi@0x880000";

swr0 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/wsa-macro@62f00000/wsa_swr_master";

hsuart0 = "/soc/qcom,qup_uart@0x88c000";

i2c2 = "/soc/i2c@0xa8c000";

spi1 = "/soc/spi@0x890000";

sdhc1 = "/soc/sdhci@7c4000";

i2c0 = "/soc/i2c@0x888000";

swr1 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/rx-macro@62ee0000/rx_swr_master";

ufshc1 = "/soc/ufshc@1d84000";

serial0 = "/soc/qcom,qup_uart@0xa88000";

};

firmware {

phandle = <0x4d6>;

android {

compatible = "android,firmware";

fstab {

compatible = "android,fstab";

vendor {

fsmgr_flags = "wait,avb";

mnt_flags = "ro,barrier=1,discard";

dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";

type = "ext4";

compatible = "android,vendor";

status = "disabled";

};

};

vbmeta {

parts = "vbmeta,boot,system,vendor,dtbo,recovery";

compatible = "android,vbmeta";

};

};

};

chosen {

linux,initrd-end = <0x00 0x855fee0d>;

bootargs = "rcu_nocbs=0-7 androidboot.hardware=qcom androidboot.memcg=1 androidboot.usbcontroller=a600000.dwc3 loop.max_part=7 lpm_levels.sleep_disabled=1 service_locator.enable=1 swiotlb=1 msm_rtb.filter=0x237 kpti=off androidboot.fstab_suffix=qcom buildvariant=userdebug androidboot.verifiedbootstate=orange androidboot.keymaster=1 androidboot.bootdevice=1d84000.ufshc androidboot.fstab_suffix=default androidboot.boot_devices=soc/1d84000.ufshc androidboot.serialno=c1164428 androidboot.ramdump=disable androidboot.secureboot=1 androidboot.cpuid=0xfa1aafba androidboot.hwversion=10.19.6 androidboot.camera.config=0 androidboot.hwc=GLOBAL androidboot.hwlevel=MP androidboot.product.hardware.sku=pro androidboot.baseband=msm msm_drm.dsi_display0=dsi_k6_38_0c_0a_fhd_dsc_video_display: androidboot.dtbo_idx=18 androidboot.dtb_idx=11 androidboot.batt_verified_result=11 androidboot.profile_vendor_id=0A androidboot.dp=0x0";

kaslr-seed = <0x00 0x00>;

pureason = <0x40011>;

linux,initrd-start = <0x00 0x8544a000>;

rng-seed = <0x59fd9f9e 0xfd1f857d 0xd7e555d9 0xcbfe1c4d 0x923a9a3a 0xc4ce6f00 0xd9c6e1ac 0x5b739e40 0x34d3d117 0x667be11b 0x6de75ac 0x609d5aa8 0x827fcfb3 0x4f2e9358 0xd9851a01 0x4f4803e0 0xeed5c420 0xf1258c5b 0xb37533e4 0xfc06d725 0xef31b301 0x3f8d3529 0x5cb36c07 0xb9294250 0xee59f5f6 0x9adb58ff 0x4ef3f57d 0xb22ea90b 0x16382d46 0x456d75f6 0x1966a8b0 0x63586a5d 0x7043c62e 0xfd4dff94 0x25ec36b7 0x5342a5c8 0xaf87bccd 0xa8a1d9cf 0x73137fd3 0x751481dc 0x19390780 0x88e3710c 0xdbb76e4d 0x3d12bd0f 0xd12e8173 0x178c28f 0x293ed102 0x8924b516 0x1919bab5 0xe582f648 0xf2f4a9a0 0xf2e928c2 0x9c43f83a 0x3a9e36fa 0xc5be173f 0x1cab1ec0 0x75c32daf 0x6e0c8f6c 0x9c77d703 0xccd6206f 0x340c6540 0x61617b73 0x9de96385 0xb86d145f 0x5b3dccb3 0xba36bddd 0xd1c34dde 0x2b6ca024 0xe3bd760b 0x28f77ecc 0xe322bffc 0x802582dd 0x463ff9c4 0xb80ce35d 0x404b98e3 0xf0250f8 0x66ee364 0x33d5fe37 0xb066588d 0xfb7d5a3b 0x8a294b1a 0xb65aa19b 0x5fae7b5e 0x3926b2d7 0xd3a15e3f 0xd8cf5e8 0xbb167a14 0x9f261c08 0x54ea8355 0x8592017b 0x7efafcb 0x4858dd56 0x1a0e8fbd 0xdb29180e 0xdb7a5691 0xb19188bc 0xc7070380 0x75edeccf 0xd9eace07 0xbb7bad4a 0x979d78f0 0x5cfb82b6 0xeba4db03 0x7f69c806 0xa89cfc21 0x6b078b8 0x9e93c6c4 0xa8911f5e 0xcf48ec07 0x74d9d613 0x94ea9f59 0x3c3a62ad 0x1e7e333c 0xbfda48cf 0x36100f60 0x2f1fe66c 0x5c5f842f 0x6be65d80 0x404eef6d 0x78d6d08b 0x5bca78d6 0x994c0c2 0x2678830f 0xed43768a 0x2940fc4b 0x120dd409 0x1fb29db1 0xbf195736>;

};

cpus {

#address-cells = <0x02>;

#size-cells = <0x00>;

cpu@300 {

capacity-dmips-mhz = <0x400>;

qcom,lmh-dcvs = <0x05>;

device_type = "cpu";

sched-energy-costs = <0x02 0x03>;

compatible = "arm,armv8";

next-level-cache = <0x09>;

reg = <0x00 0x300>;

enable-method = "psci";

phandle = <0x14>;

#cooling-cells = <0x02>;

l2-cache {

cache-level = <0x02>;

compatible = "arm,arch-cache";

next-level-cache = <0x06>;

phandle = <0x09>;

};

l1-dcache {

qcom,dump-size = <0x9000>;

compatible = "arm,arch-cache";

phandle = <0x40>;

};

l1-icache {

qcom,dump-size = <0x8800>;

compatible = "arm,arch-cache";

phandle = <0x38>;

};

l2-tlb {

qcom,dump-size = <0x5000>;

phandle = <0x4c>;

};

};

cpu@600 {

capacity-dmips-mhz = <0x6cc>;

qcom,lmh-dcvs = <0x0f>;

device_type = "cpu";

sched-energy-costs = <0x0c 0x0d>;

compatible = "arm,armv8";

next-level-cache = <0x0e>;

reg = <0x00 0x600>;

enable-method = "psci";

phandle = <0x17>;

#cooling-cells = <0x02>;

l2-cache {

qcom,dump-size = <0x48000>;

cache-level = <0x02>;

compatible = "arm,arch-cache";

next-level-cache = <0x06>;

phandle = <0x0e>;

};

l1-dtlb {

qcom,dump-size = <0x480>;

phandle = <0x47>;

};

l1-itlb {

qcom,dump-size = <0x300>;

phandle = <0x45>;

};

l1-dcache {

qcom,dump-size = <0x12000>;

compatible = "arm,arch-cache";

phandle = <0x43>;

};

l1-icache {

qcom,dump-size = <0x11000>;

compatible = "arm,arch-cache";

phandle = <0x3b>;

};

l2-tlb {

qcom,dump-size = <0x7800>;

phandle = <0x4f>;

};

};

cpu-map {

cluster0 {

core5 {

cpu = <0x16>;

};

core3 {

cpu = <0x14>;

};

core1 {

cpu = <0x12>;

};

core4 {

cpu = <0x15>;

};

core2 {

cpu = <0x13>;

};

core0 {

cpu = <0x11>;

};

};

cluster1 {

core1 {

cpu = <0x18>;

};

core0 {

cpu = <0x17>;

};

};

};

cpu@200 {

capacity-dmips-mhz = <0x400>;

qcom,lmh-dcvs = <0x05>;

device_type = "cpu";

sched-energy-costs = <0x02 0x03>;

compatible = "arm,armv8";

next-level-cache = <0x08>;

reg = <0x00 0x200>;

enable-method = "psci";

phandle = <0x13>;

#cooling-cells = <0x02>;

l2-cache {

cache-level = <0x02>;

compatible = "arm,arch-cache";

next-level-cache = <0x06>;

phandle = <0x08>;

};

l1-dcache {

qcom,dump-size = <0x9000>;

compatible = "arm,arch-cache";

phandle = <0x3f>;

};

l1-icache {

qcom,dump-size = <0x8800>;

compatible = "arm,arch-cache";

phandle = <0x37>;

};

l2-tlb {

qcom,dump-size = <0x5000>;

phandle = <0x4b>;

};

};

cpu@500 {

capacity-dmips-mhz = <0x400>;

qcom,lmh-dcvs = <0x05>;

device_type = "cpu";

sched-energy-costs = <0x02 0x03>;

compatible = "arm,armv8";

next-level-cache = <0x0b>;

reg = <0x00 0x500>;

enable-method = "psci";

phandle = <0x16>;

#cooling-cells = <0x02>;

l2-cache {

cache-level = <0x02>;

compatible = "arm,arch-cache";

next-level-cache = <0x06>;

phandle = <0x0b>;

};

l1-dcache {

qcom,dump-size = <0x9000>;

compatible = "arm,arch-cache";

phandle = <0x42>;

};

l1-icache {

qcom,dump-size = <0x8800>;

compatible = "arm,arch-cache";

phandle = <0x3a>;

};

l2-tlb {

qcom,dump-size = <0x5000>;

phandle = <0x4e>;

};

};

cpu@0 {

capacity-dmips-mhz = <0x400>;

qcom,lmh-dcvs = <0x05>;

device_type = "cpu";

sched-energy-costs = <0x02 0x03>;

compatible = "arm,armv8";

next-level-cache = <0x04>;

reg = <0x00 0x00>;

enable-method = "psci";

phandle = <0x11>;

#cooling-cells = <0x02>;

l2-cache {

cache-level = <0x02>;

compatible = "arm,arch-cache";

next-level-cache = <0x06>;

phandle = <0x04>;

l3-cache {

cache-level = <0x03>;

compatible = "arm,arch-cache";

phandle = <0x06>;

};

};

l1-dcache {

qcom,dump-size = <0x9000>;

compatible = "arm,arch-cache";

phandle = <0x3d>;

};

l1-icache {

qcom,dump-size = <0x8800>;

compatible = "arm,arch-cache";

phandle = <0x35>;

};

l2-tlb {

qcom,dump-size = <0x5000>;

phandle = <0x49>;

};

};

cpu@100 {

capacity-dmips-mhz = <0x400>;

qcom,lmh-dcvs = <0x05>;

device_type = "cpu";

sched-energy-costs = <0x02 0x03>;

compatible = "arm,armv8";

next-level-cache = <0x07>;

reg = <0x00 0x100>;

enable-method = "psci";

phandle = <0x12>;

#cooling-cells = <0x02>;

l2-cache {

cache-level = <0x02>;

compatible = "arm,arch-cache";

next-level-cache = <0x06>;

phandle = <0x07>;

};

l1-dcache {

qcom,dump-size = <0x9000>;

compatible = "arm,arch-cache";

phandle = <0x3e>;

};

l1-icache {

qcom,dump-size = <0x8800>;

compatible = "arm,arch-cache";

phandle = <0x36>;

};

l2-tlb {

qcom,dump-size = <0x5000>;

phandle = <0x4a>;

};

};

cpu@400 {

capacity-dmips-mhz = <0x400>;

qcom,lmh-dcvs = <0x05>;

device_type = "cpu";

sched-energy-costs = <0x02 0x03>;

compatible = "arm,armv8";

next-level-cache = <0x0a>;

reg = <0x00 0x400>;

enable-method = "psci";

phandle = <0x15>;

#cooling-cells = <0x02>;

l2-cache {

cache-level = <0x02>;

compatible = "arm,arch-cache";

next-level-cache = <0x06>;

phandle = <0x0a>;

};

l1-dcache {

qcom,dump-size = <0x9000>;

compatible = "arm,arch-cache";

phandle = <0x41>;

};

l1-icache {

qcom,dump-size = <0x8800>;

compatible = "arm,arch-cache";

phandle = <0x39>;

};

l2-tlb {

qcom,dump-size = <0x5000>;

phandle = <0x4d>;

};

};

cpu@700 {

capacity-dmips-mhz = <0x6cc>;

qcom,lmh-dcvs = <0x0f>;

device_type = "cpu";

sched-energy-costs = <0x0c 0x0d>;

compatible = "arm,armv8";

next-level-cache = <0x10>;

reg = <0x00 0x700>;

enable-method = "psci";

phandle = <0x18>;

#cooling-cells = <0x02>;

l2-cache {

qcom,dump-size = <0x48000>;

cache-level = <0x02>;

compatible = "arm,arch-cache";

next-level-cache = <0x06>;

phandle = <0x10>;

};

l1-dtlb {

qcom,dump-size = <0x480>;

phandle = <0x48>;

};

l1-itlb {

qcom,dump-size = <0x300>;

phandle = <0x46>;

};

l1-dcache {

qcom,dump-size = <0x12000>;

compatible = "arm,arch-cache";

phandle = <0x44>;

};

l1-icache {

qcom,dump-size = <0x11000>;

compatible = "arm,arch-cache";

phandle = <0x3c>;

};

l2-tlb {

qcom,dump-size = <0x7800>;

phandle = <0x50>;

};

};

};

__symbols__ {

sdc1_cmd_on = "/soc/pinctrl@3400000/sdc1_cmd_on";

eud_in_replicator_swao = "/soc/dummy_sink/port/endpoint";

qupv3_se11_4uart_pins = "/soc/pinctrl@3400000/qupv3_se11_4uart_pins";

funnel_dl_south_1_out_funnel_qatb = "/soc/funnel_1@6b53000/ports/port@0/endpoint";

mdss_dsi0_pll = "/soc/qcom,mdss_dsi_pll@ae94a00";

smp2p_rdbg5_out = "/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-out";

qupv3_se11_spi_sleep = "/soc/pinctrl@3400000/qupv3_se11_spi_pins/qupv3_se11_spi_sleep";

tpda_olc = "/soc/tpda@7832000";

tdm_pri_tx = "/soc/qcom,msm-dai-tdm-pri-tx";

mas_qxm_camnoc_nrt = "/soc/ad-hoc-bus/mas-qxm-camnoc-nrt";

bcm_sn4 = "/soc/ad-hoc-bus/bcm-sn4";

cdsp_smp2p_in = "/soc/qcom,smp2p-cdsp/slave-kernel";

cti3 = "/soc/cti@6013000";

pm6150_l3 = "/soc/rpmh-regulator-ldoa3/regulator-pm6150-l3";

wled_switch = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800/qcom,wled-switch";

qupv3_se2_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se2_i2c_pins/qupv3_se2_i2c_sleep";

L1_DTLB_600 = "/cpus/cpu@600/l1-dtlb";

cpu6_cpu_l3_latmon = "/soc/qcom,cpu6-cpu-l3-latmon";

fpc_int_low = "/soc/pinctrl@3400000/fpc_reset_int/int_low";

qupv3_se7_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se7_i2c_pins/qupv3_se7_i2c_sleep";

mdss_dp_pll = "/soc/qcom,mdss_dp_pll@ae90000";

va_cdc_dma_0_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-0-tx";

i2c_freq_custom_cci0 = "/soc/qcom,cci@ac4a000/qcom,i2c_custom_mode";

icp_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_icp/iova-mem-map";

mas_qxm_camnoc_hf0_uncomp = "/soc/ad-hoc-bus/mas-qxm-camnoc-hf0-uncomp";

L2A = "/soc/rpmh-regulator-ldoa2/regulator-pm6150-l2";

slv_qhs_cpr_cx = "/soc/ad-hoc-bus/slv-qhs-cpr-cx";

msm_hvx_rm = "/soc/qcom,glink/cdsp/qcom,msm_cdsprm_rpmsg/qcom,msm_hvx_rm";

tpda_swao_in_tpdm_swao0 = "/soc/tpda@6b01000/ports/port@1/endpoint";

cti1_wcss = "/soc/cti@69a5000";

cpu5_config = "/soc/thermal-zones/cpu-0-5-step/trips/cpu5-config";

funnel_in0_in_tpdm_lpass = "/soc/funnel@0x6041000/ports/port@1/endpoint";

pm6150_qg = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qpnp,qg";

titan_top_gdsc = "/soc/qcom,gdsc@ad0c1c4";

fab_ipa_virt = "/soc/ad-hoc-bus/fab-ipa_virt";

pm6150_misc = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,misc@900";

pm6150l_temp_alarm = "/soc/thermal-zones/pm6150l-tz";

tpda_modem_0_out_funnel_modem = "/soc/tpda@6831000/ports/port@0/endpoint";

S2C_LEVEL_AO = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2-level-ao";

etm7 = "/soc/etm@7740000";

tpda_apss_in_tpdm_apss = "/soc/tpda@7862000/ports/port@1/endpoint";

cdsp_sec_mem = "/reserved-memory/cdsp_sec_regions@0x9f800000";

msm_cdsp_rm = "/soc/qcom,glink/cdsp/qcom,msm_cdsprm_rpmsg/qcom,msm_cdsp_rm";

clock_dispcc = "/soc/qcom,dispcc@af00000";

cti1_ddr1 = "/soc/cti@6a11000";

pm6150l_l4 = "/soc/rpmh-regulator-ldoc4/regulator-pm6150l-l4";

thermal_zones = "/soc/thermal-zones";

qcom_msmhdcp = "/soc/qcom,msm_hdcp";

slv_qhs_qupv3_north = "/soc/ad-hoc-bus/slv-qhs-qupv3-north";

funnel_in2_in_funnel_apss_merg = "/soc/funnel@6043000/ports/port@1/endpoint";

tpda_modem_1_in_tpdm_modem_1 = "/soc/tpda@6833000/ports/port@1/endpoint";

intc = "/soc/interrupt-controller@17a00000";

tpda_in_funnel_dl_mm = "/soc/tpda@6004000/ports/port@1/endpoint";

flash_led = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300";

mas_qhm_a2noc_cfg = "/soc/ad-hoc-bus/mas-qhm-a2noc-cfg";

gpu_gx_gdsc = "/soc/qcom,gdsc@509100c";

slv_qhs_tlmm_west = "/soc/ad-hoc-bus/slv-qhs-tlmm-west";

mas_qxm_rot_display = "/soc/ad-hoc-bus/mas-qxm-rot_display";

wsa_swr_clk_active = "/soc/pinctrl@3400000/wsa_swr_clk_pin/wsa_swr_clk_active";

L1_I_100 = "/cpus/cpu@100/l1-icache";

adsp_smp2p_in = "/soc/qcom,smp2p-adsp/slave-kernel";

jpeg_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_jpeg/iova-mem-map";

mas_xm_emmc = "/soc/ad-hoc-bus/mas-xm-emmc";

pm6150l_rgb_led = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d000";

slv_qhs_glm = "/soc/ad-hoc-bus/slv-qhs-glm";

L1A = "/soc/rpmh-regulator-ldoa1/regulator-pm6150-l1";

slv_qns_cnoc = "/soc/ad-hoc-bus/slv-qns-cnoc";

fab_mc_virt_display = "/soc/ad-hoc-bus/fab-mc_virt_display";

pm6150l_torch2 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,torch_2";

cpu0_cpu_llcc_lat = "/soc/qcom,cpu0-cpu-llcc-lat";

sdc2_cmd_on = "/soc/pinctrl@3400000/sdc2_cmd_on";

rx_cdc_dma_6_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-6-rx";

swao_csr = "/soc/csr@6b0e000";

pm6150l_switch0 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,led_switch_0";

adsp_tbu = "/soc/apps-smmu@0x15000000/adsp_tbu@0x1519d000";

tpdm_olc_out_tpda_olc = "/soc/tpdm@7830000/port/endpoint";

tpda_llm_silver_out_funnel_apss_merg = "/soc/tpda@78c0000/ports/port@0/endpoint";

pm6150_pdphy = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,usb-pdphy@1700";

iommu_slim_qca_ctrl_cb = "/soc/slim@62e40000/qcom,iommu_slim_ctrl_cb";

q6_hvx_trip1 = "/soc/thermal-zones/q6-hvx-step/trips/q6-hvx-trip1";

tdm_pri_rx = "/soc/qcom,msm-dai-tdm-pri-rx";

mdss_dsi0 = "/soc/qcom,mdss_dsi_ctrl0@ae94000";

mas_qnm_snoc = "/soc/ad-hoc-bus/mas-qnm-snoc";

i2c_freq_100Khz_cci1 = "/soc/qcom,cci@ac4b000/qcom,i2c_standard_mode";

tpdm_swao0_out_tpda_swao = "/soc/tpdm@6b02000/port/endpoint";

replicator_swao = "/soc/replicator@6b0a000";

funnel_swao_in_replicator1_out = "/soc/funnel@6b08000/ports/port@1/endpoint";

funnel_gfx_out_tpda = "/soc/funnel@6943000/ports/port@0/endpoint";

voice = "/soc/qcom,msm-pcm-voice";

qupv3_se7_spi_sleep = "/soc/pinctrl@3400000/qupv3_se7_spi_pins/qupv3_se7_spi_sleep";

cpu7_0_config = "/soc/thermal-zones/cpu-1-2-step/trips/cpu7-0-config";

kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@5040000";

pri_i2s_data0_sleep = "/soc/pinctrl@3400000/pri_i2s_data0/pri_i2s_data0_sleep";

qupv3_se6_spi_pins = "/soc/pinctrl@3400000/qupv3_se6_spi_pins";

dai_meta_mi2s1 = "/soc/qcom,msm-dai-q6-meta-mi2s-sec";

lcdb_ncp_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00/ncp";

rx_cdc_dma_3_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-3-rx";

qupv3_se3_4uart_pins = "/soc/pinctrl@3400000/qupv3_se3_4uart_pins";

cti10 = "/soc/cti@601a000";

tpda_llm_gold_in_tpdm_llm_gold = "/soc/tpda@78d0000/ports/port@1/endpoint";

slv_ipa_core_slave = "/soc/ad-hoc-bus/slv-ipa-core-slave";

tpda_llm_gold_out_funnel_apss_merg = "/soc/tpda@78d0000/ports/port@0/endpoint";

spkr_2_sd_n_active = "/soc/pinctrl@3400000/spkr_2_sd_n/spkr_2_sd_n_active";

modem_vdd = "/soc/qmi-tmd-devices/modem/modem_vdd";

mas_qhm_cnoc_dc_noc = "/soc/ad-hoc-bus/mas-qhm-cnoc-dc-noc";

anoc_2_tbu = "/soc/apps-smmu@0x15000000/anoc_2_tbu@0x15189000";

slv_qns_pcie_gemnoc = "/soc/ad-hoc-bus/slv-qns-pcie-gemnoc";

lmh_dcvs1 = "/soc/qcom,cpucc@18321000/qcom,limits-dcvs@18350800";

tsens0 = "/soc/tsens@c222000";

ipe_0_gdsc = "/soc/qcom,gdsc@ad08004";

funnel_merg_out_tmc_etf = "/soc/funnel@6045000/ports/port@0/endpoint";

bcm_mc0_display = "/soc/ad-hoc-bus/bcm-mc0_display";

pm6150l_s8 = "/soc/rpmh-regulator-smpc8/regulator-pm6150l-s8";

pm6150_l10 = "/soc/rpmh-regulator-ldoa10/regulator-pm6150-l10";

va_macro = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/va-macro@62f20000";

pil_gpu_mem = "/reserved-memory/gpu_region@97f15000";

ts_int_suspend = "/soc/pinctrl@3400000/pmx_ts_int_suspend/ts_int_suspend";

incall_record_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-tx";

hyp_region = "/reserved-memory/hyp_region@85700000";

tdm_quat_tx = "/soc/qcom,msm-dai-tdm-quat-tx";

green_led = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d000/green";

tpda_llm_silver = "/soc/tpda@78c0000";

rx_cdc_dma_0_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-0-rx";

VDD_CX_LEVEL_AO = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2-level-ao";

nfc_int_suspend = "/soc/pinctrl@3400000/nfc/nfc_int_suspend";

qupv3_se11_i2c_pins = "/soc/pinctrl@3400000/qupv3_se11_i2c_pins";

tpdm_ddr_out_funnel_ddr_0 = "/soc/tpdm@6a00000/port/endpoint";

dai_quin_auxpcm = "/soc/qcom,msm-quin-auxpcm";

replicator_swao_out_funnel_in1 = "/soc/replicator@6b0a000/ports/port@1/endpoint";

slim_aud = "/soc/slim@62dc0000";

npu_npu_ddr_bw = "/soc/qcom,npu-npu-ddr-bw";

funnel_modem_in_tpda_modem_1 = "/soc/funnel@6832000/ports/port@2/endpoint";

batt_trip4 = "/soc/thermal-zones/quiet-therm-step/trips/batt-trip4";

tpdm_north = "/soc/tpdm@6b48000";

pm6150_vadc = "/soc/qcom,spmi@c440000/qcom,pm6150@0/vadc@3100";

VDD_MX_LEVEL_AO = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3-level-ao";

ipa_smmu_uc = "/soc/ipa_smmu_uc";

qupv3_se0_i2c = "/soc/i2c@0x880000";

qupv3_se2_i2c_pins = "/soc/pinctrl@3400000/qupv3_se2_i2c_pins";

glink_cdsp = "/soc/qcom,glink/cdsp";

funnel_apss_in_etm6 = "/soc/funnel@7800000/ports/port@7/endpoint";

bcm_sn2 = "/soc/ad-hoc-bus/bcm-sn2";

slv_qhs_prng = "/soc/ad-hoc-bus/slv-qhs-prng";

mas_qnm_gemnoc = "/soc/ad-hoc-bus/mas-qnm-gemnoc";

cti1 = "/soc/cti@6011000";

tpdm_olc = "/soc/tpdm@7830000";

mas_llcc_mc = "/soc/ad-hoc-bus/mas-llcc-mc";

pm6150_l1 = "/soc/rpmh-regulator-ldoa1/regulator-pm6150-l1";

cti0_swao = "/soc/cti@6b04000";

sdc2_data_on = "/soc/pinctrl@3400000/sdc2_data_on";

vph_lvl1 = "/soc/thermal-zones/pm6150l-vph-lvl1/trips/vph-lvl1";

qupv3_se11_i2c_active = "/soc/pinctrl@3400000/qupv3_se11_i2c_pins/qupv3_se11_i2c_active";

qupv3_se11_spi = "/soc/spi@0xa94000";

wled_torch = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800/qcom,wled-torch";

etm2_out_funnel_apss = "/soc/etm@7240000/port/endpoint";

fab_aggre2_noc = "/soc/ad-hoc-bus/fab-aggre2_noc";

sb_8_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-tx";

L7A_LEVEL = "/soc/rpmh-regulator-lmxlvl/regulator-pm6150-l7";

replicator_swao_in_tmc_etf_swao = "/soc/replicator@6b0a000/ports/port@2/endpoint";

funnel_apss_merg_in_tpda_olc = "/soc/funnel@7810000/ports/port@2/endpoint";

cx_ipeak_lm = "/soc/cx_ipeak@01fed000";

smmu_rot_unsec = "/soc/qcom,mdss_rotator@ae00000/qcom,smmu_rot_unsec_cb";

cpu7_1_config = "/soc/thermal-zones/cpu-1-3-step/trips/cpu7-1-config";

tpda_in_funnel_gfx = "/soc/tpda@6004000/ports/port@6/endpoint";

L2_TLB_0 = "/cpus/cpu@0/l2-tlb";

swr2 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/tx-macro@62ec0000/tx_swr_master";

funnel_in1_in_replicator_swao = "/soc/funnel@6042000/ports/port@2/endpoint";

pcm2 = "/soc/qcom,msm-ultra-low-latency";

etm5 = "/soc/etm@7540000";

mas_alc = "/soc/ad-hoc-bus/mas-alc";

sde_te_suspend = "/soc/pinctrl@3400000/pmx_sde_te/sde_te_suspend";

l_bcl_lvl2 = "/soc/thermal-zones/pm6150l-bcl-lvl2/trips/l-bcl-lvl2";

slv_qhs_tsif = "/soc/ad-hoc-bus/slv-qhs-tsif";

pm6150l_l2 = "/soc/rpmh-regulator-ldoc2/regulator-pm6150l-l2";

silver_trip = "/soc/thermal-zones/quiet-therm-step/trips/silver-trip";

mas_xm_pcie3_0 = "/soc/ad-hoc-bus/mas-xm-pcie3-0";

CPU_COST_0 = "/energy-costs/core-cost0";

sleepstate_smp2p_out = "/soc/qcom,smp2p-adsp/sleepstate-out";

hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = "/soc/qcom,gdsc@17d048";

mas_qnm_mnoc_hf = "/soc/ad-hoc-bus/mas-qnm-mnoc-hf";

L1_I_400 = "/cpus/cpu@400/l1-icache";

funnel_qatb_in_funnel_dl_south_1 = "/soc/funnel@6005000/ports/port@2/endpoint";

qupv3_se4_i2c = "/soc/i2c@0x890000";

sb_5_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-5-tx";

mx_cdev = "/soc/rpmh-regulator-mxlvl/mx-cdev-lvl";

funnel_apss_out_funnel_apss_merg = "/soc/funnel@7800000/ports/port@0/endpoint";

L7F = "/soc/rpmh-regulator-ldof7/regulator-pm8009-l7";

L2_TLB_100 = "/cpus/cpu@100/l2-tlb";

BOB = "/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob";

L1_D_300 = "/cpus/cpu@300/l1-dcache";

incall_record_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-rx";

mnoc_hf_1_tbu = "/soc/apps-smmu@0x15000000/mnoc_hf_1_tbu@0x15191000";

jtag_mm6 = "/soc/jtagmm@7640000";

pm6150_l8_level = "/soc/rpmh-regulator-lcxlvl/regulator-pm6150-l8";

pm6150l_torch0 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,torch_0";

tdm_quat_rx = "/soc/qcom,msm-dai-tdm-quat-rx";

cxip_cdev = "/soc/cxip-cdev@1fed000";

slv_qns_gemnoc_gc = "/soc/ad-hoc-bus/slv-qns-gemnoc-gc";

msm_vidc1 = "/soc/qcom,vidc1";

ufs_phy_gdsc = "/soc/qcom,gdsc@177004";

funnel_merg = "/soc/funnel@6045000";

pm6150_l19 = "/soc/rpmh-regulator-ldoa19/regulator-pm6150-l19";

nfc_enable_active = "/soc/pinctrl@3400000/nfc/nfc_enable_active";

mas_xm_gic = "/soc/ad-hoc-bus/mas-xm-gic";

ufs_dev_reset_assert = "/soc/pinctrl@3400000/ufs_dev_reset_assert";

qupv3_se6_spi = "/soc/spi@0xa80000";

funnel_dl_south_in_tpdm_dl_south = "/soc/funnel@6b53000/ports/port@1/endpoint";

qupv3_se11_4uart = "/soc/qcom,qup_uart@0xa94000";

q6_hvx_trip = "/soc/thermal-zones/q6-hvx-lowf/trips/q6-hvx-trip";

mas_qxm_camnoc_nrt_uncomp = "/soc/ad-hoc-bus/mas-qxm-camnoc-nrt-uncomp";

slv_qhs_usb3_0 = "/soc/ad-hoc-bus/slv-qhs-usb3-0";

cpu_cpu_llcc_bwmon = "/soc/qcom,cpu-cpu-llcc-bwmon@90b6300";

dfps_data_memory = "/reserved-memory/dfps_data_region@9d700000";

sb_2_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-2-tx";

pm6150_s5 = "/soc/rpmh-regulator-smpa5/regulator-pm6150-s5";

qupv3_se4_spi_active = "/soc/pinctrl@3400000/qupv3_se4_spi_pins/qupv3_se4_spi_active";

pm8009_s2 = "/soc/rpmh-regulator-smpf2/regulator-pm8009-s2";

sdc1_rclk_off = "/soc/pinctrl@3400000/sdc1_rclk_off";

ts_reset_suspend = "/soc/pinctrl@3400000/pmx_ts_reset_suspend/ts_reset_suspend";

bcm_mm2 = "/soc/ad-hoc-bus/bcm-mm2";

adsp_smp2p_out = "/soc/qcom,smp2p-adsp/master-kernel";

rot_reg = "/soc/qcom,mdss_rotator@ae00000/qcom,rot-reg-bus";

S7C_LEVEL = "/soc/rpmh-regulator-modemlvl/regulator-pm6150l-s7";

funnel_swao_out_tmc_etf_swao = "/soc/funnel@6b08000/ports/port@0/endpoint";

afe_loopback_tx = "/soc/qcom,msm-dai-q6-afe-loopback-tx";

smem = "/soc/qcom,smem";

L8A_LEVEL = "/soc/rpmh-regulator-lcxlvl/regulator-pm6150-l8";

slv_qhs_ahb2phy_west = "/soc/ad-hoc-bus/slv-qhs-ahb2phy-west";

L6F = "/soc/rpmh-regulator-ldof6/regulator-pm8009-l6";

mas_qxm_ipa = "/soc/ad-hoc-bus/mas-qxm-ipa";

qupv3_se8_i2c = "/soc/i2c@0xa88000";

sb_8_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-rx";

mas_xm_qdss_dap = "/soc/ad-hoc-bus/mas-xm-qdss-dap";

tmc_etr = "/soc/tmc@6048000";

slv_qhs_venus_cfg = "/soc/ad-hoc-bus/slv-qhs-venus-cfg";

stm = "/soc/stm@6002000";

funnel_qatb_in_tpda = "/soc/funnel@6005000/ports/port@1/endpoint";

fab_camnoc_virt = "/soc/ad-hoc-bus/fab-camnoc_virt";

iommu_qupv3_1_geni_se_cb = "/soc/qcom,qupv3_1_geni_se@0xac0000/qcom,iommu_qupv3_1_geni_se_cb";

mas_xm_usb3_0 = "/soc/ad-hoc-bus/mas-xm-usb3-0";

pm8009_l7 = "/soc/rpmh-regulator-ldof7/regulator-pm8009-l7";

cti0_wcss = "/soc/cti@69a4000";

mas_ipa_core_master = "/soc/ad-hoc-bus/mas-ipa-core-master";

bcl_soc = "/soc/qcom,spmi@c440000/qcom,pm6150@0/bcl-soc";

slv_qhs_tcsr = "/soc/ad-hoc-bus/slv-qhs-tcsr";

afe = "/soc/qcom,msm-pcm-afe";

dai_pri_auxpcm = "/soc/qcom,msm-pri-auxpcm";

qupv3_se3_i2c_active = "/soc/pinctrl@3400000/qupv3_se3_i2c_pins/qupv3_se3_i2c_active";

cpu_cpu_llcc_bw = "/soc/qcom,cpu-cpu-llcc-bw";

slv_srvc_mnoc = "/soc/ad-hoc-bus/slv-srvc-mnoc";

disp_rdump_memory = "/reserved-memory/disp_rdump_region@9c000000";

smem_region = "/reserved-memory/smem@86000000";

dai_sen_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-sen-tx/qcom,msm-dai-q6-tdm-sen-tx-0";

mem_client_3_size = "/soc/qcom,memshare/qcom,client_3";

cti0_ddr1 = "/soc/cti@6a10000";

voip = "/soc/qcom,msm-voip-dsp";

fsa4480 = "/soc/i2c@0xa8c000/fsa4480@43";

sde_te1_active = "/soc/pinctrl@3400000/pmx_sde_te/sde_te1_active";

tpda_apss = "/soc/tpda@7862000";

slv_qhs_clk_ctl = "/soc/ad-hoc-bus/slv-qhs-clk-ctl";

bcm_alc = "/soc/ad-hoc-bus/bcm-alc";

sb_5_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-5-rx";

tpda_modem0 = "/soc/tpda@6831000";

qupv3_se11_spi_pins = "/soc/pinctrl@3400000/qupv3_se11_spi_pins";

gpi_dma0 = "/soc/qcom,gpi-dma@0x800000";

qupv3_se7_i2c_pins = "/soc/pinctrl@3400000/qupv3_se7_i2c_pins";

qupv3_se8_2uart = "/soc/qcom,qup_uart@0xa88000";

slv_qhs_crypto0_cfg = "/soc/ad-hoc-bus/slv-qhs-crypto0-cfg";

pri_i2s_sck_sleep = "/soc/pinctrl@3400000/pri_i2s_sck_ws/pri_i2s_sck_sleep";

batt_trip2 = "/soc/thermal-zones/quiet-therm-step/trips/batt-trip2";

L5F = "/soc/rpmh-regulator-ldof5/regulator-pm8009-l5";

tmc_etr_in_replicator = "/soc/tmc@6048000/port/endpoint";

qseecom_mem = "/reserved-memory/qseecom_region@9e400000";

fsa_usbc_ana_en = "/soc/pinctrl@3400000/fsa_usbc_ana_en_n@42/fsa_usbc_ana_en";

stm_out_funnel_in0 = "/soc/stm@6002000/port/endpoint";

dai_tert_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-tert-rx/qcom,msm-dai-q6-tdm-tert-rx-0";

funnel_apss_in_etm4 = "/soc/funnel@7800000/ports/port@5/endpoint";

bcm_sn0 = "/soc/ad-hoc-bus/bcm-sn0";

L2_200 = "/cpus/cpu@200/l2-cache";

tdm_sec_tx = "/soc/qcom,msm-dai-tdm-sec-tx";

funnel_ddr_0_in_tpdm_ddr = "/soc/funnel@6a05000/ports/port@1/endpoint";

funnel_in1_in_modem_etm0 = "/soc/funnel@6042000/ports/port@1/endpoint";

fab_mc_virt = "/soc/ad-hoc-bus/fab-mc_virt";

tpdm_prng = "/soc/tpdm@684c000";

tpdm_prng_out_tpda = "/soc/tpdm@684c000/port/endpoint";

llcc_bw_opp_table = "/soc/llcc-bw-opp-table";

hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = "/soc/qcom,gdsc@17d030";

slv_qhs_venus_throttle_cfg = "/soc/ad-hoc-bus/slv-qhs-venus-throttle-cfg";

dai_sen_auxpcm = "/soc/qcom,msm-sen-auxpcm";

dai_quat_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-quat-rx/qcom,msm-dai-q6-tdm-quat-rx-0";

tx_cdc_dma_5_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-5-tx";

slv_qhs_apss = "/soc/ad-hoc-bus/slv-qhs-apss";

qupv3_se0_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se0_i2c_pins/qupv3_se0_i2c_sleep";

sb_2_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-2-rx";

pm6150_rtc = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,pm6150_rtc";

vbat_lvl1 = "/soc/thermal-zones/pm6150-vbat-lvl1/trips/vbat-lvl1";

rx_macro = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/rx-macro@62ee0000";

swr0 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/wsa-macro@62f00000/wsa_swr_master";

dai_quin_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-quin-rx/qcom,msm-dai-q6-tdm-quin-rx-0";

wsa_cdc_dma_1_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-1-tx";

pcm0 = "/soc/qcom,msm-pcm";

etm3 = "/soc/etm@7340000";

pm6150a_amoled = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled";

qupv3_se8_i2c_active = "/soc/pinctrl@3400000/qupv3_se8_i2c_pins/qupv3_se8_i2c_active";

mas_qxm_gpu = "/soc/ad-hoc-bus/mas-qxm-gpu";

mas_qnm_mnoc_hf_display = "/soc/ad-hoc-bus/mas-qnm-mnoc-hf_display";

qseecom_ta_mem = "/reserved-memory/qseecom_ta_region";

spkr_2_sd_n_sleep = "/soc/pinctrl@3400000/spkr_2_sd_n/spkr_2_sd_n_sleep";

L1_I_700 = "/cpus/cpu@700/l1-icache";

l_bcl_lvl0 = "/soc/thermal-zones/pm6150l-bcl-lvl0/trips/l-bcl-lvl0";

tpda_out_funnel_qatb = "/soc/tpda@6004000/ports/port@0/endpoint";

lcdb_bst_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00/bst";

clock_aop = "/soc/qcom,aopclk";

L4F = "/soc/rpmh-regulator-ldof4/regulator-pm8009-l4";

sde_te1_suspend = "/soc/pinctrl@3400000/pmx_sde_te/sde_te1_suspend";

lcdb_ldo_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00/ldo";

smp2p_rdbg2_out = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-out";

qupv3_se11_rts = "/soc/pinctrl@3400000/qupv3_se11_4uart_pins/qupv3_se11_rts";

L2_TLB_400 = "/cpus/cpu@400/l2-tlb";

system_heap = "/soc/qcom,ion/qcom,ion-heap@25";

tx_cdc_dma_2_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-2-tx";

L1_D_600 = "/cpus/cpu@600/l1-dcache";

replicator1_in_replicator_out = "/soc/replicator@604a000/ports/port@1/endpoint";

smp2p_ipa_1_in = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-in";

smartpa_int_active = "/soc/pinctrl@3400000/smartpa_int_active";

ufs_ice = "/soc/ufsice@1d90000";

mdss_dsi_phy0 = "/soc/qcom,mdss_dsi_phy0@ae94400";

jtag_mm4 = "/soc/jtagmm@7440000";

tpdm_dl_mm_out_funnel_dl_mm = "/soc/tpdm@69c0000/port/endpoint";

smartpa_enable_active = "/soc/pinctrl@3400000/smartpa_enable_active";

funnel_apss_merg_in_funnel_apss = "/soc/funnel@7810000/ports/port@1/endpoint";

qcom_smcinvoke = "/soc/smcinvoke@86d00000";

slv_qhs_ahb2phy_south = "/soc/ad-hoc-bus/slv-qhs-ahb2phy-south";

sdhc_2 = "/soc/sdhci@8804000";

pm6150_l17 = "/soc/rpmh-regulator-ldoa17/regulator-pm6150-l17";

red_led = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d000/led";

etm1_out_funnel_apss = "/soc/etm@7140000/port/endpoint";

lrme_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_lrme/iova-mem-map";

slv_ebi_display = "/soc/ad-hoc-bus/slv-ebi_display";

CPU6 = "/cpus/cpu@600";

tpdm_turing = "/soc/tpdm@6860000";

tdm_sec_rx = "/soc/qcom,msm-dai-tdm-sec-rx";

cam_a5 = "/soc/qcom,a5@ac00000";

funnel_in2 = "/soc/funnel@6043000";

bcm_mm0 = "/soc/ad-hoc-bus/bcm-mm0";

tpdm_wcss_out_funnel_dl_south_1 = "/soc/tpdm@699c000/port/endpoint";

slv_qhs_llcc = "/soc/ad-hoc-bus/slv-qhs-llcc";

ddr_bw_opp_table = "/soc/ddr-bw-opp-table";

tpdm_modem1 = "/soc/tpdm@6834000";

mas_qnm_aggre1_noc = "/soc/ad-hoc-bus/mas-qnm-aggre1-noc";

mdss_dsi1_pll = "/soc/qcom,mdss_dsi_pll@ae96a00";

bcm_mm0_display = "/soc/ad-hoc-bus/bcm-mm0_display";

qupv3_se0_spi_sleep = "/soc/pinctrl@3400000/qupv3_se0_spi_pins/qupv3_se0_spi_sleep";

mas_qnm_mnoc_sf = "/soc/ad-hoc-bus/mas-qnm-mnoc-sf";

smp2p_ipa_1_out = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-out";

sdc2_cd_off = "/soc/pinctrl@3400000/cd_off";

bcm_cn0 = "/soc/ad-hoc-bus/bcm-cn0";

VDD_CX_LEVEL = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2";

fab_gem_noc = "/soc/ad-hoc-bus/fab-gem_noc";

i2c_freq_400Khz_cci1 = "/soc/qcom,cci@ac4b000/qcom,i2c_fast_mode";

tcsr_mutex = "/soc/hwlock";

bcm_sn9 = "/soc/ad-hoc-bus/bcm-sn9";

L1_ITLB_600 = "/cpus/cpu@600/l1-itlb";

cti8 = "/soc/cti@6018000";

bcm_sh2 = "/soc/ad-hoc-bus/bcm-sh2";

fab_config_noc = "/soc/ad-hoc-bus/fab-config_noc";

pm8009_l5 = "/soc/rpmh-regulator-ldof5/regulator-pm8009-l5";

pm6150l_s7_level = "/soc/rpmh-regulator-modemlvl/regulator-pm6150l-s7";

slv_qns_cnoc_a2noc = "/soc/ad-hoc-bus/slv-qns-cnoc-a2noc";

wsa_cdc_dma_1_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-1-rx";

qupv3_se10_spi_active = "/soc/pinctrl@3400000/qupv3_se10_spi_pins/qupv3_se10_spi_active";

qupv3_se4_ctsrx = "/soc/pinctrl@3400000/qupv3_se4_4uart_pins/qupv3_se4_ctsrx";

tpdm_npu = "/soc/tpdm@69e1000";

wlan_msa_mem = "/reserved-memory/wlan_msa_region@97d00000";

hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = "/soc/qcom,gdsc@17d03c";

pm6150l_flash2 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,flash_2";

mvs1_gdsc = "/soc/qcom,gdsc@ab008b4";

L2F = "/soc/rpmh-regulator-ldof2/regulator-pm8009-l2";

tpda_swao_out_funnel_swao = "/soc/tpda@6b01000/ports/port@0/endpoint";

gpubw = "/soc/qcom,gpubw";

compr = "/soc/qcom,msm-compr-dsp";

wsa_swr_data_active = "/soc/pinctrl@3400000/wsa_swr_data_pin/wsa_swr_data_active";

cpu6_cpu_ddr_latfloor = "/soc/qcom,cpu6-cpu-ddr-latfloor";

adsp_mem = "/reserved-memory/adsp_region";

sdc2_clk_off = "/soc/pinctrl@3400000/sdc2_clk_off";

modem_proc = "/soc/qmi-tmd-devices/modem/modem_proc";

mas_qxm_mdp0 = "/soc/ad-hoc-bus/mas-qxm-mdp0";

hwevent = "/soc/hwevent@0x014066f0";

hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = "/soc/qcom,gdsc@17d040";

q6core = "/soc/qcom,msm-audio-apr/qcom,q6core-audio";

qupv3_se7_spi_pins = "/soc/pinctrl@3400000/qupv3_se7_spi_pins";

glink_modem = "/soc/qcom,glink/modem";

L2_500 = "/cpus/cpu@500/l2-cache";

batt_trip0 = "/soc/thermal-zones/quiet-therm-step/trips/batt-trip0";

funnel_swao_in_tpda_swao = "/soc/funnel@6b08000/ports/port@2/endpoint";

tpdm_north_out_tpda = "/soc/tpdm@6b48000/port/endpoint";

pm6150l_l9 = "/soc/rpmh-regulator-ldoc9/regulator-pm6150l-l9";

cam_sensor_mclk1_suspend = "/soc/pinctrl@3400000/cam_sensor_mclk1_suspend";

cti_mss_q6 = "/soc/cti@683b000";

L19A = "/soc/rpmh-regulator-ldoa19/regulator-pm6150-l19";

tpdm_center = "/soc/tpdm@6b44000";

funnel_apss_in_etm2 = "/soc/funnel@7800000/ports/port@3/endpoint";

mas_qxm_camnoc_rt = "/soc/ad-hoc-bus/mas-qxm-camnoc-rt";

pm6150_adc_tm = "/soc/qcom,spmi@c440000/qcom,pm6150@0/adc_tm@3500";

slv_qhs_display_cfg = "/soc/ad-hoc-bus/slv-qhs-display-cfg";

qcom_rng = "/soc/qrng@793000";

ipcb_tgu = "/soc/tgu@6b0c000";

adsp_vdd = "/soc/qmi-tmd-devices/adsp/adsp_vdd";

qupv3_se8_2uart_sleep = "/soc/pinctrl@3400000/qupv3_se8_2uart_pins/qupv3_se8_2uart_sleep";

cam_jpeg_dma = "/soc/qcom,jpegdma@ac52000";

L1F = "/soc/rpmh-regulator-ldof1/regulator-pm8009-l1";

CLUSTER_COST_0 = "/energy-costs/cluster-cost0";

funnel_ddr_0_out_tpda = "/soc/funnel@6a05000/ports/port@0/endpoint";

ife_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_ife/iova-mem-map";

mas_acm_apps = "/soc/ad-hoc-bus/mas-acm-apps";

tpdm_apss = "/soc/tpdm@7860000";

pm6150l_trip1 = "/soc/thermal-zones/pm6150l-tz/trips/trip1";

funnel_turing_in_tpdm_turing = "/soc/funnel@6861000/ports/port@1/endpoint";

wcd_intr_default = "/soc/pinctrl@3400000/wcd9xxx_intr/wcd_intr_default";

tpda = "/soc/tpda@6004000";

slv_qhs_a1_noc_cfg = "/soc/ad-hoc-bus/slv-qhs-a1-noc-cfg";

etm1 = "/soc/etm@7140000";

btfmslim_codec = "/soc/slim@62e40000/wcn3990";

cam_ipe0 = "/soc/qcom,ipe0";

mas_qxm_camnoc_rt_uncomp = "/soc/ad-hoc-bus/mas-qxm-camnoc-rt-uncomp";

cpu0_cpu_l3_lat = "/soc/qcom,cpu0-cpu-l3-lat";

tx_macro = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/tx-macro@62ec0000";

cam_vfe1 = "/soc/qcom,vfe1@acb6000";

sdc2_cmd_off = "/soc/pinctrl@3400000/sdc2_cmd_off";

funnel_merg_in_funnel_in1 = "/soc/funnel@6045000/ports/port@2/endpoint";

L2_TLB_700 = "/cpus/cpu@700/l2-tlb";

qupv3_se3_i2c_pins = "/soc/pinctrl@3400000/qupv3_se3_i2c_pins";

qmp_npu1 = "/soc/qcom,qmp-npu-high@9818000";

L18A = "/soc/rpmh-regulator-ldoa18/regulator-pm6150-l18";

qupv3_se3_4uart = "/soc/qcom,qup_uart@0x88c000";

slv_qhs_compute_dsp_cfg = "/soc/ad-hoc-bus/slv-qhs-compute-dsp-cfg";

L1_I_0 = "/cpus/cpu@0/l1-icache";

clock_npucc = "/soc/qcom,npucc";

fab_dc_noc = "/soc/ad-hoc-bus/fab-dc_noc";

apcs_glb = "/soc/mailbox@17c00000";

slv_qhs_pdm = "/soc/ad-hoc-bus/slv-qhs-pdm";

smmu_rot_sec = "/soc/qcom,mdss_rotator@ae00000/qcom,smmu_rot_sec_cb";

ibat_lvl1 = "/soc/thermal-zones/pm6150-ibat-lvl1/trips/ibat-lvl1";

cti15 = "/soc/cti@601f000";

dai_mi2s4 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quin";

modem_trip3 = "/soc/thermal-zones/quiet-therm-step/trips/modem-trip3";

mas_qhm_qdss_bam = "/soc/ad-hoc-bus/mas-qhm-qdss-bam";

tmc_etf_swao = "/soc/tmc@6b09000";

va_cdc_dma_2_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-2-tx";

mas_qxm_mdp1_display = "/soc/ad-hoc-bus/mas-qxm-mdp1_display";

jtag_mm2 = "/soc/jtagmm@7240000";

pm6150l_l10 = "/soc/rpmh-regulator-ldoc10/regulator-pm6150l-l10";

qupv3_0 = "/soc/qcom,qupv3_0_geni_se@0x8c0000";

LPI_CX_LEVEL = "/soc/rpmh-regulator-lcxlvl/regulator-pm6150-l8";

funnel_gfx = "/soc/funnel@6943000";

slv_qhs_ipa = "/soc/ad-hoc-bus/slv-qhs-ipa";

afe_proxy_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-tx";

tpdm_pimem_out_tpda = "/soc/tpdm@6850000/port/endpoint";

pm6150_l15 = "/soc/rpmh-regulator-ldoa15/regulator-pm6150-l15";

pm6150_s2_level = "/soc/rpmh-regulator-gfxlvl/regulator-pm6150-s2-level";

pil_ipa_gsi_mem = "/reserved-memory/ipa_gsi_region@97f10000";

tmc_etf = "/soc/tmc@6047000";

pri_i2s_data1_sleep = "/soc/pinctrl@3400000/pri_i2s_data1/pri_i2s_data1_sleep";

bcm_sn15 = "/soc/ad-hoc-bus/bcm-sn15";

CPU4 = "/cpus/cpu@400";

L17A = "/soc/rpmh-regulator-ldoa17/regulator-pm6150-l17";

bcm_sh0_display = "/soc/ad-hoc-bus/bcm-sh0_display";

kgsl_smmu = "/soc/arm,smmu-kgsl@5040000";

S2A_LEVEL = "/soc/rpmh-regulator-gfxlvl/regulator-pm6150-s2-level";

funnel_in0 = "/soc/funnel@0x6041000";

tcsr_mutex_block = "/soc/syscon@1f40000";

dai_tert_auxpcm = "/soc/qcom,msm-tert-auxpcm";

qupv3_se10_i2c = "/soc/i2c@0xa90000";

pm6150l_revid = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/qcom,revid@100";

mas_qhm_snoc_cfg = "/soc/ad-hoc-bus/mas-qhm-snoc-cfg";

lpass_core_hw_vote = "/soc/lpass_core_hw_vote";

soc = "/soc";

tpda_in_tpdm_dl_center = "/soc/tpda@6004000/ports/port@2/endpoint";

funnel_dl_south_1 = "/soc/funnel_1@6b53000";

qupv3_se1_i2c = "/soc/i2c@0x884000";

sdc1_clk_on = "/soc/pinctrl@3400000/sdc1_clk_on";

modem_smp2p_out = "/soc/qcom,smp2p-modem/master-kernel";

cx_cdev = "/soc/rpmh-regulator-cxlvl/regulator-cdev";

cti6 = "/soc/cti@6016000";

bcm_sh0 = "/soc/ad-hoc-bus/bcm-sh0";

pm6150_l6 = "/soc/rpmh-regulator-ldoa6/regulator-pm6150-l6";

qupv3_se1_i2c_active = "/soc/pinctrl@3400000/qupv3_se1_i2c_pins/qupv3_se1_i2c_active";

slv_qhs_emmc_cfg = "/soc/ad-hoc-bus/slv-qhs-emmc-cfg";

cpu0_cpu_ddr_latfloor = "/soc/qcom,cpu0-cpu-ddr-latfloor";

slv_qns_camnoc_uncomp = "/soc/ad-hoc-bus/slv-qns-camnoc-uncomp";

pwm_lpg2 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,pwms@b100/lpg2";

mccc_debug = "/soc/syscon@90b0000";

pm6150l_flash0 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,flash_0";

hlos1_vote_aggre_noc_mmu_tbu2_gdsc = "/soc/qcom,gdsc@17d038";

gpu_trip = "/soc/thermal-zones/gpuss-max-step/trips/gpu-trip";

funnel_ddr_0 = "/soc/funnel@6a05000";

L16A = "/soc/rpmh-regulator-ldoa16/regulator-pm6150-l16";

qupv3_se3_spi = "/soc/spi@0x88c000";

funnel_turing_1_in_turing_etm0 = "/soc/funnel_1@6861000/ports/port@1/endpoint";

pm6150_bcl = "/soc/qcom,spmi@c440000/qcom,pm6150@0/bcl@1d00";

disp_pins_default = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/pinctrl@c000/disp_pins/disp_pins_default";

slv_qhs_qdss_cfg = "/soc/ad-hoc-bus/slv-qhs-qdss-cfg";

qupv3_se7_spi_active = "/soc/pinctrl@3400000/qupv3_se7_spi_pins/qupv3_se7_spi_active";

spmi_bus = "/soc/qcom,spmi@c440000";

proxy_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-proxy-tx";

tpda_olc_out_funnel_apss_merg = "/soc/tpda@7832000/ports/port@0/endpoint";

qupv3_se4_tx = "/soc/pinctrl@3400000/qupv3_se4_4uart_pins/qupv3_se4_tx";

dai_quat_auxpcm = "/soc/qcom,msm-quat-auxpcm";

cdsp_mem = "/reserved-memory/cdsp_region";

pm6150l_l7 = "/soc/rpmh-regulator-ldoc7/regulator-pm6150l-l7";

iommu_slim_aud_ctrl_cb = "/soc/slim@62dc0000/qcom,iommu_slim_ctrl_cb";

etm0_out_funnel_apss = "/soc/etm@7040000/port/endpoint";

usb_qmp_dp_phy = "/soc/ssphy@88e8000";

cwlan_trip = "/soc/thermal-zones/cwlan-lowf/trips/cwlan-trip";

LLCC_1 = "/soc/qcom,llcc@9200000/llcc_1_dcache";

funnel_apss_in_etm0 = "/soc/funnel@7800000/ports/port@1/endpoint";

bcl_lvl1 = "/soc/thermal-zones/pm6150-bcl-lvl1/trips/bcl-lvl1";

rx_cdc_dma_5_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-5-rx";

bcm_mm2_display = "/soc/ad-hoc-bus/bcm-mm2_display";

cpu0_cpu_l3_latmon = "/soc/qcom,cpu0-cpu-l3-latmon";

ibb_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled/ibb@dc00";

afe_proxy_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-rx";

modem_pa = "/soc/qmi-tmd-devices/modem/modem_pa";

slv_qhs_venus_cvp_throttle_cfg = "/soc/ad-hoc-bus/slv-qhs-venus-cvp-throttle-cfg";

cam_cci0 = "/soc/qcom,cci@ac4a000";

pri_i2s_data0_active = "/soc/pinctrl@3400000/pri_i2s_data0/pri_i2s_data0_active";

S3A_LEVEL = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3";

qupv3_se6_i2c_active = "/soc/pinctrl@3400000/qupv3_se6_i2c_pins/qupv3_se6_i2c_active";

L15A = "/soc/rpmh-regulator-ldoa15/regulator-pm6150-l15";

mas_qxm_camnoc_hf = "/soc/ad-hoc-bus/mas-qxm-camnoc-hf";

usb_audio_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-tx";

cdsp_vdd = "/soc/qmi-tmd-devices/cdsp/cdsp_vdd";

slv_qhs_camera_cfg = "/soc/ad-hoc-bus/slv-qhs-camera-cfg";

ddr_trip = "/soc/thermal-zones/ddr-lowf/trips/ddr-trip";

mas_qhm_spdm = "/soc/ad-hoc-bus/mas-qhm-spdm";

fab_mmss_noc = "/soc/ad-hoc-bus/fab-mmss_noc";

slv_qhs_imem_cfg = "/soc/ad-hoc-bus/slv-qhs-imem-cfg";

qupv3_se8_i2c_pins = "/soc/pinctrl@3400000/qupv3_se8_i2c_pins";

qupv3_se7_spi = "/soc/spi@0xa84000";

sdc2_clk_on = "/soc/pinctrl@3400000/sdc2_clk_on";

rx_cdc_dma_2_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-2-rx";

qupv3_se3_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se3_i2c_pins/qupv3_se3_i2c_sleep";

audio_apr = "/soc/qcom,msm-audio-apr";

pm6150_vib = "/soc/qcom,spmi@c440000/qcom,pm6150@1/qcom,vibrator@5300";

tpdm_swao1 = "/soc/tpdm@6b03000";

cci1_suspend = "/soc/pinctrl@3400000/cci1_suspend";

pm6150l_lpg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,pwms@b100";

slv_qns_a2noc_snoc = "/soc/ad-hoc-bus/slv-qns-a2noc-snoc";

dai_slim = "/soc/slim@62dc0000/msm_dai_slim";

qupv3_se3_spi_pins = "/soc/pinctrl@3400000/qupv3_se3_spi_pins";

tpda_in_tpdm_pimem = "/soc/tpda@6004000/ports/port@11/endpoint";

qupv3_se8_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se8_i2c_pins/qupv3_se8_i2c_sleep";

funnel_dl_south = "/soc/funnel@6b53000";

funnel_qatb = "/soc/funnel@6005000";

audio_etm0_out_funnel_in0 = "/soc/audio_etm0/port/endpoint";

compute_dsp_0_tbu = "/soc/apps-smmu@0x15000000/compute_dsp_0_tbu@0x15199000";

L11C = "/soc/rpmh-regulator-ldoc11/regulator-pm6150l-l11";

sde_dp_aux_suspend = "/soc/pinctrl@3400000/sde_dp_aux_suspend";

cam_csiphy2 = "/soc/qcom,csiphy@ace4000";

slv_qns2_mem_noc_display = "/soc/ad-hoc-bus/slv-qns2-mem-noc_display";

wsa_swr_data_sleep = "/soc/pinctrl@3400000/wsa_swr_data_pin/wsa_swr_data_sleep";

mas_qnm_snoc_gc = "/soc/ad-hoc-bus/mas-qnm-snoc-gc";

L3_0 = "/cpus/cpu@0/l2-cache/l3-cache";

cam_sensor_mclk3_suspend = "/soc/pinctrl@3400000/cam_sensor_mclk3_suspend";

etm7_out_funnel_apss = "/soc/etm@7740000/port/endpoint";

S8C = "/soc/rpmh-regulator-smpc8/regulator-pm6150l-s8";

modem_smp2p_in = "/soc/qcom,smp2p-modem/slave-kernel";

qcom_crypto = "/soc/qcrypto@1de0000";

routing = "/soc/qcom,msm-pcm-routing";

qupv3_se9_i2c = "/soc/i2c@0xa8c000";

cti13 = "/soc/cti@601d000";

dai_mi2s2 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-tert";

camera_trip = "/soc/thermal-zones/camera-lowf/trips/camera-trip";

bcm_acv = "/soc/ad-hoc-bus/bcm-acv";

pm6150l_clkdiv = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/clock-controller@5b00";

L14A = "/soc/rpmh-regulator-ldoa14/regulator-pm6150-l14";

jtag_mm0 = "/soc/jtagmm@7040000";

msm_bus = "/soc/qcom,kgsl-busmon";

smmu_sde_sec = "/soc/qcom,mdss_mdp@ae00000/qcom,smmu_sde_sec_cb";

mvs0_gdsc = "/soc/qcom,gdsc@ab00874";

L1_I_300 = "/cpus/cpu@300/l1-icache";

afe_pcm_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-tx";

slv_qhs_gpuss_cfg = "/soc/ad-hoc-bus/slv-qhs-gpuss-cfg";

proxy_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-proxy-rx";

pm6150_charger = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,qpnp-smb5";

cam_bps = "/soc/qcom,bps";

pm6150_l13 = "/soc/rpmh-regulator-ldoa13/regulator-pm6150-l13";

bcm_qup0 = "/soc/ad-hoc-bus/bcm-qup0";

gpu_cx_hw_ctrl = "/soc/syscon@5091540";

funnel_in2_out_funnel_merg = "/soc/funnel@6043000/ports/port@0/endpoint";

cpu_0_0_trip = "/soc/thermal-zones/cpu-0-0-lowf/trips/cpu-0-0-trip";

cpu0_computemon = "/soc/qcom,cpu0-computemon";

CPU2 = "/cpus/cpu@200";

cpu_pmu = "/soc/cpu-pmu";

tpdm_qdss = "/soc/tpdm@6006000";

L1_D_200 = "/cpus/cpu@200/l1-dcache";

cpu0_llcc_ddr_latmon = "/soc/qcom,cpu0-llcc-ddr-latmon";

L10C = "/soc/rpmh-regulator-ldoc10/regulator-pm6150l-l10";

slv_qns_mem_noc_hf_display = "/soc/ad-hoc-bus/slv-qns-mem-noc-hf_display";

pm6150_trip1 = "/soc/thermal-zones/pm6150-tz/trips/trip1";

dcc = "/soc/dcc_v2@10a2000";

slv_qhs_tlmm_north = "/soc/ad-hoc-bus/slv-qhs-tlmm-north";

nfc_int_active = "/soc/pinctrl@3400000/nfc/nfc_int_active";

funnel_apss_merg_in_tpda_apss = "/soc/funnel@7810000/ports/port@5/endpoint";

clock_gcc = "/soc/qcom,gcc@100000";

pri_i2s_data1_active = "/soc/pinctrl@3400000/pri_i2s_data1/pri_i2s_data1_active";

tpdm_dl_south_out_funnel_dl_south = "/soc/tpdm@6b52000/port/endpoint";

sb_7_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-tx";

tdm_sen_tx = "/soc/qcom,msm-dai-tdm-sen-tx";

ext_disp = "/soc/qcom,msm-ext-disp";

L13A = "/soc/rpmh-regulator-ldoa13/regulator-pm6150-l13";

usb_audio_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-rx";

modem_etm0_out_funnel_in1 = "/soc/modem_etm0/port/endpoint";

bps_gdsc = "/soc/qcom,gdsc@ad07004";

cti4 = "/soc/cti@6014000";

pm6150_l4 = "/soc/rpmh-regulator-ldoa4/regulator-pm6150-l4";

mdss_mdp = "/soc/qcom,mdss_mdp@ae00000";

cti_aop_m3 = "/soc/cti@6b21000";

cti2_apss = "/soc/cti@7900000";

pm8009_l1 = "/soc/rpmh-regulator-ldof1/regulator-pm8009-l1";

qupv3_se3_spi_sleep = "/soc/pinctrl@3400000/qupv3_se3_spi_pins/qupv3_se3_spi_sleep";

dai_sec_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-sec-rx/qcom,msm-dai-q6-tdm-sec-rx-0";

funnel_in1_in_funnel_modem = "/soc/funnel@6042000/ports/port@3/endpoint";

replicator_in_tmc_etf = "/soc/replicator@6046000/ports/port@2/endpoint";

tpda_llm_silver_in_tpdm_llm_silver = "/soc/tpda@78c0000/ports/port@1/endpoint";

qupv3_se8_spi_sleep = "/soc/pinctrl@3400000/qupv3_se8_spi_pins/qupv3_se8_spi_sleep";

i2c_freq_custom_cci1 = "/soc/qcom,cci@ac4b000/qcom,i2c_custom_mode";

cam_csid0 = "/soc/qcom,csid0@acb3000";

slv_qhs_pimem_cfg = "/soc/ad-hoc-bus/slv-qhs-pimem-cfg";

mdss_rotator = "/soc/qcom,mdss_rotator@ae00000";

pm6150l_flashlight = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,flashlight";

tpda_swao_in_tpdm_swao1 = "/soc/tpda@6b01000/ports/port@2/endpoint";

tdm_quin_tx = "/soc/qcom,msm-dai-tdm-quin-tx";

snoc_cnoc_keepalive = "/soc/qcom,snoc_cnoc_keepalive";

funnel_modem = "/soc/funnel@6832000";

audio_trip = "/soc/thermal-zones/audio-lowf/trips/audio-trip";

sb_4_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-4-tx";

clock_debug = "/soc/qcom,cc-debug";

slv_qns_mem_noc_hf = "/soc/ad-hoc-bus/slv-qns-mem-noc-hf";

cti1_dlct = "/soc/cti@6c2a000";

qupv3_se4_4uart_pins = "/soc/pinctrl@3400000/qupv3_se4_4uart_pins";

clock_cpucc = "/soc/qcom,cpucc@18321000";

fab_gem_noc_display = "/soc/ad-hoc-bus/fab-gem_noc_display";

mas_qnm_npu = "/soc/ad-hoc-bus/mas-qnm-npu";

pm6150l_l5 = "/soc/rpmh-regulator-ldoc5/regulator-pm6150l-l5";

pil_ipa_fw_mem = "/reserved-memory/ips_fw_region@97f00000";

smp2p_rdbg5_in = "/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-in";

pil_video_mem = "/reserved-memory/pil_video_region@93400000";

npu_core_gdsc = "/soc/qcom,gdsc@9911028";

funnel_apss = "/soc/funnel@7800000";

L12A = "/soc/rpmh-regulator-ldoa12/regulator-pm6150-l12";

fab_mmss_noc_display = "/soc/ad-hoc-bus/fab-mmss_noc_display";

afe_pcm_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-rx";

pm6150_revid = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,revid@100";

clock_camcc = "/soc/qcom,camcc";

mas_qnm_pcie = "/soc/ad-hoc-bus/mas-qnm-pcie";

ufsphy_mem = "/soc/ufsphy_mem@1d87000";

qupv3_se3_rts = "/soc/pinctrl@3400000/qupv3_se3_4uart_pins/qupv3_se3_rts";

cpu_1_0_trip = "/soc/thermal-zones/cpu-1-0-lowf/trips/cpu-1-0-trip";

dummy_eud = "/soc/dummy_sink";

sb_1_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-1-tx";

ipa_smmu_ap = "/soc/ipa_smmu_ap";

pm6150l_tz = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/qcom,temp-alarm@2400";

tpdm_swao1_out_tpda_swao = "/soc/tpdm@6b03000/port/endpoint";

smp2p_rdbg2_in = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-in";

L2_100 = "/cpus/cpu@100/l2-cache";

tpda_in_tpdm_npu = "/soc/tpda@6004000/ports/port@12/endpoint";

pm6150l_switch1 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,led_switch_1";

tpdm_llm_gold_out_tpda_llm_gold = "/soc/tpdm@78b0000/port/endpoint";

tpda_apss_out_funnel_apss_merg = "/soc/tpda@7862000/ports/port@0/endpoint";

qupv3_se8_spi_pins = "/soc/pinctrl@3400000/qupv3_se8_spi_pins";

cam_sensor_mclk0_active = "/soc/pinctrl@3400000/cam_sensor_mclk0_active";

mas_qnm_cmpnoc = "/soc/ad-hoc-bus/mas-qnm-cmpnoc";

mas_qnm_mnoc_sf_display = "/soc/ad-hoc-bus/mas-qnm-mnoc-sf_display";

tpda_modem_1_out_funnel_modem = "/soc/tpda@6833000/ports/port@0/endpoint";

sb_7_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-rx";

mas_qxm_venus0 = "/soc/ad-hoc-bus/mas-qxm-venus0";

pm6150l_pwm = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,pwms@bc00";

q6_hvx_trip2 = "/soc/thermal-zones/q6-hvx-step/trips/q6-hvx-trip2";

pm6150_temp_alarm = "/soc/thermal-zones/pm6150-tz";

mdss_dsi1 = "/soc/qcom,mdss_dsi_ctrl1@ae96000";

bcm_ce0 = "/soc/ad-hoc-bus/bcm-ce0";

tdm_sen_rx = "/soc/qcom,msm-dai-tdm-sen-rx";

L11A = "/soc/rpmh-regulator-ldoa11/regulator-pm6150-l11";

slv_qns_llcc_display = "/soc/ad-hoc-bus/slv-qns-llcc_display";

dai_sec_spdif_tx = "/soc/qcom,msm-dai-q6-spdif-sec-tx";

cam_csiphy0 = "/soc/qcom,csiphy@ace0000";

clock_gpucc = "/soc/qcom,gpucc";

slv_qhs_gemnoc = "/soc/ad-hoc-bus/slv-qhs-gemnoc";

video_trip = "/soc/thermal-zones/video-lowf/trips/video-trip";

pm6150l_lcdb = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00";

dai_tert_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-tert-tx/qcom,msm-dai-q6-tdm-tert-tx-0";

mas_qnm_aggre2_noc = "/soc/ad-hoc-bus/mas-qnm-aggre2-noc";

tpda_swao = "/soc/tpda@6b01000";

funnel_in0_in_funnel_qatb = "/soc/funnel@0x6041000/ports/port@3/endpoint";

i2c_freq_1Mhz_cci0 = "/soc/qcom,cci@ac4a000/qcom,i2c_fast_plus_mode";

cti11 = "/soc/cti@601b000";

dai_mi2s0 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-prim";

L1_I_600 = "/cpus/cpu@600/l1-icache";

tdm_quin_rx = "/soc/qcom,msm-dai-tdm-quin-rx";

qupv3_se0_spi_active = "/soc/pinctrl@3400000/qupv3_se0_spi_pins/qupv3_se0_spi_active";

dai_quat_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-quat-tx/qcom,msm-dai-q6-tdm-quat-tx-0";

hlos1_vote_aggre_noc_mmu_tbu1_gdsc = "/soc/qcom,gdsc@17d034";

tsens1 = "/soc/tsens@c223000";

sb_4_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-4-rx";

bcm_mc0 = "/soc/ad-hoc-bus/bcm-mc0";

lsm = "/soc/qcom,msm-lsm-client";

L2_TLB_300 = "/cpus/cpu@300/l2-tlb";

pm6150_l11 = "/soc/rpmh-regulator-ldoa11/regulator-pm6150-l11";

eud = "/soc/qcom,msm-eud@88e0000";

dai_pri_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-pri-rx/qcom,msm-dai-q6-tdm-pri-rx-0";

L1_D_500 = "/cpus/cpu@500/l1-dcache";

dai_quin_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-quin-tx/qcom,msm-dai-q6-tdm-quin-tx-0";

mas_qxm_camnoc_sf = "/soc/ad-hoc-bus/mas-qxm-camnoc-sf";

qupv3_se4_i2c_pins = "/soc/pinctrl@3400000/qupv3_se4_i2c_pins";

ts_release = "/soc/pinctrl@3400000/pmx_ts_release/ts_release";

bcm_sn11 = "/soc/ad-hoc-bus/bcm-sn11";

CPU0 = "/cpus/cpu@0";

cpu6_llcc_ddr_lat = "/soc/qcom,cpu6-llcc-ddr-lat";

sdc1_data_on = "/soc/pinctrl@3400000/sdc1_data_on";

mas_qhm_mnoc_cfg = "/soc/ad-hoc-bus/mas-qhm-mnoc-cfg";

L10A = "/soc/rpmh-regulator-ldoa10/regulator-pm6150-l10";

msm_dai_mi2s = "/soc/qcom,msm-dai-mi2s";

slv_qhs_aop = "/soc/ad-hoc-bus/slv-qhs-aop";

ipa_hw = "/soc/qcom,ipa@1e00000";

tmc_etf_swao_out_replicator_swao = "/soc/tmc@6b09000/ports/port@0/endpoint";

sdcc1_ice = "/soc/sdcc1ice@7C8000";

gfx3d_user = "/soc/qcom,kgsl-iommu@5040000/gfx3d_user";

qupv3_se10_ctsrx = "/soc/pinctrl@3400000/qupv3_se10_4uart_pins/qupv3_se10_ctsrx";

wdog = "/soc/qcom,wdt@17c10000";

tx_cdc_dma_4_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-4-tx";

qupv3_se10_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se10_i2c_pins/qupv3_se10_i2c_sleep";

ad_hoc_bus = "/soc/ad-hoc-bus";

sb_1_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-1-rx";

tpdm_qm = "/soc/tpdm@69d0000";

funnel_turing_out_tpda = "/soc/funnel@6861000/ports/port@0/endpoint";

incall_music_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-rx";

slv_qhs_snoc_cfg = "/soc/ad-hoc-bus/slv-qhs-snoc-cfg";

fpc_reset_low = "/soc/pinctrl@3400000/fpc_reset_int/reset_low";

cpu0_cpu_llcc_latmon = "/soc/qcom,cpu0-cpu-llcc-latmon";

funnel_apss_in_etm7 = "/soc/funnel@7800000/ports/port@8/endpoint";

cti2 = "/soc/cti@6012000";

wsa_cdc_dma_0_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-0-tx";

pm6150_l2 = "/soc/rpmh-regulator-ldoa2/regulator-pm6150-l2";

cam_sensor_mclk1_active = "/soc/pinctrl@3400000/cam_sensor_mclk1_active";

etm6_out_funnel_apss = "/soc/etm@7640000/port/endpoint";

vph_lvl2 = "/soc/thermal-zones/pm6150l-vph-lvl2/trips/vph-lvl2";

funnel_apss_merg_in_tpda_llm_gold = "/soc/funnel@7810000/ports/port@4/endpoint";

oledb_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled/oledb@e000";

mas_xm_sdc4 = "/soc/ad-hoc-bus/mas-xm-sdc4";

funnel_turing = "/soc/funnel@6861000";

tpdm_llm_gold = "/soc/tpdm@78b0000";

gmu_kernel = "/soc/qcom,gmu@506a000/gmu_kernel";

slv_ebi = "/soc/ad-hoc-bus/slv-ebi";

slv_qns_cdsp_gemnoc = "/soc/ad-hoc-bus/slv-qns-cdsp-gemnoc";

tpda_in_tpdm_vsense = "/soc/tpda@6004000/ports/port@7/endpoint";

sde_dp_aux_active = "/soc/pinctrl@3400000/sde_dp_aux_active";

pdc = "/soc/interrupt-controller@b220000";

tx_cdc_dma_1_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-1-tx";

dai_sec_spdif_rx = "/soc/qcom,msm-dai-q6-spdif-sec-rx";

cam_fd = "/soc/qcom,fd@ac5a000";

etm6 = "/soc/etm@7640000";

skin_gpu_trip = "/soc/thermal-zones/quiet-therm-step/trips/skin-gpu-trip";

mdm_core_trip = "/soc/thermal-zones/mdm-core-lowf/trips/mdm-core-trip";

funnel_in0_in_stm = "/soc/funnel@0x6041000/ports/port@4/endpoint";

slv_qhs_qupv3_center = "/soc/ad-hoc-bus/slv-qhs-qupv3-center";

glink_spi_xprt_wdsp = "/soc/qcom,glink/wdsp";

cti1_ddr0 = "/soc/cti@6a03000";

pm6150_s3_level_ao = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3-level-ao";

pm6150l_l3 = "/soc/rpmh-regulator-ldoc3/regulator-pm6150l-l3";

pcie_0_gdsc = "/soc/qcom,gdsc@16b004";

funnel_in1_out_funnel_merg = "/soc/funnel@6042000/ports/port@0/endpoint";

CPU_COST_1 = "/energy-costs/core-cost1";

slv_qhs_sdc4 = "/soc/ad-hoc-bus/slv-qhs-sdc4";

sdc1_rclk_on = "/soc/pinctrl@3400000/sdc1_rclk_on";

slv_srvc_cnoc = "/soc/ad-hoc-bus/slv-srvc-cnoc";

funnel_turing1 = "/soc/funnel_1@6861000";

sleepstate_smp2p_in = "/soc/qcom,smp2p-adsp/qcom,sleepstate-in";

dai_pri_spdif_tx = "/soc/qcom,msm-dai-q6-spdif-pri-tx";

funnel_apss_merg_in_tpda_llm_silver = "/soc/funnel@7810000/ports/port@3/endpoint";

qupv3_se4_i2c_active = "/soc/pinctrl@3400000/qupv3_se4_i2c_pins/qupv3_se4_i2c_active";

mas_qhm_gemnoc_cfg = "/soc/ad-hoc-bus/mas-qhm-gemnoc-cfg";

spkr_1_sd_n_active = "/soc/pinctrl@3400000/spkr_1_sd_n/spkr_1_sd_n_active";

hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = "/soc/qcom,gdsc@17d044";

L2_400 = "/cpus/cpu@400/l2-cache";

pri_i2s_ws_active = "/soc/pinctrl@3400000/pri_i2s_sck_ws/pri_i2s_ws_active";

qupv3_se10_4uart_pins = "/soc/pinctrl@3400000/qupv3_se10_4uart_pins";

tpdm_gfx = "/soc/tpdm@6940000";

jtag_mm7 = "/soc/jtagmm@7740000";

pm6150l_torch1 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,torch_1";

funnel_apss_merg_out_funnel_in2 = "/soc/funnel@7810000/ports/port@0/endpoint";

slv_srvc_aggre1_noc = "/soc/ad-hoc-bus/slv-srvc-aggre1-noc";

qupv3_se4_4uart = "/soc/qcom,qup_uart@0x890000";

tpda_in_funnel_turing = "/soc/tpda@6004000/ports/port@4/endpoint";

cpu_llcc_ddr_bw = "/soc/qcom,cpu-llcc-ddr-bw";

qupv3_se0_spi = "/soc/spi@0x880000";

qupv3_se10_spi_sleep = "/soc/pinctrl@3400000/qupv3_se10_spi_pins/qupv3_se10_spi_sleep";

S5A = "/soc/rpmh-regulator-smpa5/regulator-pm6150-s5";

keepalive_opp_table = "/soc/keepalive-opp-table";

slv_qns_gemnoc_sf = "/soc/ad-hoc-bus/slv-qns-gemnoc-sf";

q6_hvx_trip0 = "/soc/thermal-zones/q6-hvx-step/trips/q6-hvx-trip0";

qupv3_se11_tx = "/soc/pinctrl@3400000/qupv3_se11_4uart_pins/qupv3_se11_tx";

cam_sensor_mclk2_active = "/soc/pinctrl@3400000/cam_sensor_mclk2_active";

pil_adsp_mem = "/reserved-memory/pil_adsp_region@95700000";

qupv3_se11_i2c = "/soc/i2c@0xa94000";

qupv3_se1_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se1_i2c_pins/qupv3_se1_i2c_sleep";

i2c_freq_100Khz_cci0 = "/soc/qcom,cci@ac4a000/qcom,i2c_standard_mode";

bcm_mm3 = "/soc/ad-hoc-bus/bcm-mm3";

apcs = "/soc/syscon@17c0000c";

wsa_cdc_dma_0_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-0-rx";

funnel_turing_1_out_funnel_qatb = "/soc/funnel_1@6861000/ports/port@0/endpoint";

qupv3_se6_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se6_i2c_pins/qupv3_se6_i2c_sleep";

fab_system_noc = "/soc/ad-hoc-bus/fab-system_noc";

apps_rsc = "/soc/mailbox@18220000";

blue_led = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d000/blue";

S1C = "/soc/rpmh-regulator-smpc1/regulator-pm6150l-s1";

qupv3_se2_i2c = "/soc/i2c@0x888000";

dai_meta_mi2s0 = "/soc/qcom,msm-dai-q6-meta-mi2s-prim";

bluetooth = "/soc/bt_wcn3990";

cti1_apss = "/soc/cti@78f0000";

cpu6_llcc_ddr_latmon = "/soc/qcom,cpu6-llcc-ddr-latmon";

pm6150_s3_level = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3";

L2_TLB_600 = "/cpus/cpu@600/l2-tlb";

sde_dp = "/soc/qcom,dp_display@0";

mdss_core_gdsc = "/soc/qcom,gdsc@0f03000";

bcm_sh5 = "/soc/ad-hoc-bus/bcm-sh5";

lmh_dcvs0 = "/soc/qcom,cpucc@18321000/qcom,limits-dcvs@18358800";

qupv3_se9_i2c_active = "/soc/pinctrl@3400000/qupv3_se9_i2c_pins/qupv3_se9_i2c_active";

disp_rsc = "/soc/mailbox@af20000";

qupv3_se9_i2c_pins = "/soc/pinctrl@3400000/qupv3_se9_i2c_pins";

mdm_dsp_trip = "/soc/thermal-zones/mdm-dsp-lowf/trips/mdm-dsp-lowf-trip";

hostless = "/soc/qcom,msm-pcm-hostless";

reserved_memory = "/reserved-memory";

qupv3_se4_spi_pins = "/soc/pinctrl@3400000/qupv3_se4_spi_pins";

pm6150l_bcl = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/bcl@3d00";

cam_lrme = "/soc/qcom,lrme@ac6b000";

dai_hdmi_ms = "/soc/qcom,msm-dai-q6-hdmi_ms";

cti1_dlmm = "/soc/cti@69C2000";

tpdm_pimem = "/soc/tpdm@6850000";

cti0_dlct = "/soc/cti@6c29000";

qupv3_se4_spi = "/soc/spi@0x890000";

cti3_swao = "/soc/cti@6b07000";

replicator1_out_funnel_swao = "/soc/replicator@604a000/ports/port@0/endpoint";

dai_pri_spdif_rx = "/soc/qcom,msm-dai-q6-spdif-pri-rx";

gold_trip = "/soc/thermal-zones/quiet-therm-step/trips/gold-trip";

tpda_modem1 = "/soc/tpda@6833000";

gpi_dma1 = "/soc/qcom,gpi-dma@0xa00000";

dai_sec_auxpcm = "/soc/qcom,msm-sec-auxpcm";

tpdm_turing_out_funnel_turing = "/soc/tpdm@6860000/port/endpoint";

funnel_modem_in_tpda_modem_0 = "/soc/funnel@6832000/ports/port@1/endpoint";

batt_trip3 = "/soc/thermal-zones/quiet-therm-step/trips/batt-trip3";

tpdm_dl_south = "/soc/tpdm@6b52000";

suspendable_ddr_bw_opp_table = "/soc/suspendable-ddr-bw-opp-table";

tpdm_dl_center_out_tpda = "/soc/tpdm@6c28000/port/endpoint";

pm6150l_wled = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800";

funnel_dl_south_out_tpda = "/soc/funnel@6b53000/ports/port@0/endpoint";

funnel_apss_in_etm5 = "/soc/funnel@7800000/ports/port@6/endpoint";

pil_modem_mem = "/reserved-memory/modem_region@8b000000";

bcm_sn1 = "/soc/ad-hoc-bus/bcm-sn1";

qupv3_se6_i2c = "/soc/i2c@0xa80000";

tmc_etf_out_replicator = "/soc/tmc@6047000/ports/port@0/endpoint";

pm6150l_gpios = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/pinctrl@c000";

cti0 = "/soc/cti@6010000";

tpdm_lpass_out_funnel_in0 = "/soc/dummy_source/port/endpoint";

cti_venus_arm9 = "/soc/cti@6c20000";

llcc = "/soc/qcom,llcc@9200000/qcom,sdmmagpie-llcc";

mas_qxm_camnoc_sf_uncomp = "/soc/ad-hoc-bus/mas-qxm-camnoc-sf-uncomp";

vph_lvl0 = "/soc/thermal-zones/pm6150l-vph-lvl0/trips/vph-lvl0";

dai_dp = "/soc/qcom,msm-dai-q6-dp";

mas_xm_sdc2 = "/soc/ad-hoc-bus/mas-xm-sdc2";

cam_sensor_mclk3_active = "/soc/pinctrl@3400000/cam_sensor_mclk3_active";

tdm_tert_tx = "/soc/qcom,msm-dai-tdm-tert-tx";

qupv3_se1_spi_sleep = "/soc/pinctrl@3400000/qupv3_se1_spi_pins/qupv3_se1_spi_sleep";

qupv3_se0_i2c_pins = "/soc/pinctrl@3400000/qupv3_se0_i2c_pins";

vbat_lvl2 = "/soc/thermal-zones/pm6150-vbat-lvl2/trips/vbat-lvl2";

qupv3_se6_spi_sleep = "/soc/pinctrl@3400000/qupv3_se6_spi_pins/qupv3_se6_spi_sleep";

cpu0_llcc_ddr_lat = "/soc/qcom,cpu0-llcc-ddr-lat";

swr1 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/rx-macro@62ee0000/rx_swr_master";

replicator_out_tmc_etr = "/soc/replicator@6046000/ports/port@0/endpoint";

slv_xs_qdss_stm = "/soc/ad-hoc-bus/slv-xs-qdss-stm";

qupv3_se8_spi = "/soc/spi@0xa88000";

pcm1 = "/soc/qcom,msm-pcm-low-latency";

etm4 = "/soc/etm@7440000";

funnel_dl_mm = "/soc/funnel@69C3000";

VDD_GFX_LEVEL = "/soc/rpmh-regulator-gfxlvl/regulator-pm6150-s2-level";

bcm_alc_display = "/soc/ad-hoc-bus/bcm-alc_display";

qupv3_se8_2uart_pins = "/soc/pinctrl@3400000/qupv3_se8_2uart_pins";

l_bcl_lvl1 = "/soc/thermal-zones/pm6150l-bcl-lvl1/trips/l-bcl-lvl1";

pm6150l_l1 = "/soc/rpmh-regulator-ldoc1/regulator-pm6150l-l1";

va_cdc_dma_1_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-1-tx";

slv_qhs_sdc2 = "/soc/ad-hoc-bus/slv-qhs-sdc2";

tpdm_qm_out_tpda = "/soc/tpdm@69d0000/port/endpoint";

slv_qhs_spdm = "/soc/ad-hoc-bus/slv-qhs-spdm";

qupv3_se11_spi_active = "/soc/pinctrl@3400000/qupv3_se11_spi_pins/qupv3_se11_spi_active";

tpdm_modem_1_out_tpda_modem_1 = "/soc/tpdm@6834000/port/endpoint";

L2_700 = "/cpus/cpu@700/l2-cache";

mas_xm_qdss_etr = "/soc/ad-hoc-bus/mas-xm-qdss-etr";

sde_dp_usbplug_cc_suspend = "/soc/pinctrl@3400000/sde_dp_usbplug_cc_suspend";

firmware = "/firmware";

cpu_llcc_ddr_bwmon = "/soc/qcom,cpu-llcc-ddr-bwmon@90cd000";

mdss_dsi_phy1 = "/soc/qcom,mdss_dsi_phy1@ae96400";

jtag_mm5 = "/soc/jtagmm@7540000";

cti_titan = "/soc/cti@6c13000";

msm_vidc0 = "/soc/qcom,vidc0";

anoc_1_pcie_tbu = "/soc/apps-smmu@0x15000000/anoc_1_pcie_tbu@0x151a1000";

slv_xs_sys_tcu_cfg = "/soc/ad-hoc-bus/slv-xs-sys-tcu-cfg";

pm6150_l18 = "/soc/rpmh-regulator-ldoa18/regulator-pm6150-l18";

etm5_out_funnel_apss = "/soc/etm@7540000/port/endpoint";

llcc_pmu = "/soc/llcc-pmu@90cc000";

ab_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled/ab@de00";

tpdm_llm_silver_out_tpda_llm_silver = "/soc/tpdm@78a0000/port/endpoint";

qupv3_se10_i2c_active = "/soc/pinctrl@3400000/qupv3_se10_i2c_pins/qupv3_se10_i2c_active";

mas_llcc_mc_display = "/soc/ad-hoc-bus/mas-llcc-mc_display";

CPU7 = "/cpus/cpu@700";

pm8009_s1 = "/soc/rpmh-regulator-smpf1/regulator-pm8009-s1";

bcm_mm1 = "/soc/ad-hoc-bus/bcm-mm1";

L1_DTLB_700 = "/cpus/cpu@700/l1-dtlb";

tpdm_wcss = "/soc/tpdm@699c000";

ufshc_mem = "/soc/ufshc@1d84000";

rx_cdc_dma_7_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-7-rx";

pil_cdsp_mem = "/reserved-memory/cdsp_regions@93900000";

tdm_tert_rx = "/soc/qcom,msm-dai-tdm-tert-rx";

funnel_in0_out_funnel_merg = "/soc/funnel@0x6041000/ports/port@0/endpoint";

sdc1_clk_off = "/soc/pinctrl@3400000/sdc1_clk_off";

BOB_AO = "/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob-ao";

tpda_modem_0_in_tpdm_modem_0 = "/soc/tpda@6831000/ports/port@1/endpoint";

slv_qhs_aoss = "/soc/ad-hoc-bus/slv-qhs-aoss";

sdc1_data_off = "/soc/pinctrl@3400000/sdc1_data_off";

cti9 = "/soc/cti@6019000";

bcm_sh3 = "/soc/ad-hoc-bus/bcm-sh3";

pm6150_l9 = "/soc/rpmh-regulator-ldoa9/regulator-pm6150-l9";

qupv3_se3_tx = "/soc/pinctrl@3400000/qupv3_se3_4uart_pins/qupv3_se3_tx";

pm8009_l6 = "/soc/rpmh-regulator-ldof6/regulator-pm8009-l6";

L2_0 = "/cpus/cpu@0/l2-cache";

cam_sensor_mclk0_suspend = "/soc/pinctrl@3400000/cam_sensor_mclk0_suspend";

ufs_dev_reset_deassert = "/soc/pinctrl@3400000/ufs_dev_reset_deassert";

rsc_disp = "/soc/ad-hoc-bus/rsc-disp";

refgen = "/soc/refgen-regulator@ff1000";

cpu6_cpu_llcc_latmon = "/soc/qcom,cpu6-cpu-llcc-latmon";

L9C = "/soc/rpmh-regulator-ldoc9/regulator-pm6150l-l9";

qmp_aop = "/soc/qcom,qmp-aop@c300000";

tpda_in_tpdm_prng = "/soc/tpda@6004000/ports/port@8/endpoint";

funnel_gfx_in_tpdm_gfx = "/soc/funnel@6943000/ports/port@1/endpoint";

rx_cdc_dma_4_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-4-rx";

fpc_reset_high = "/soc/pinctrl@3400000/fpc_reset_int/reset_high";

tpdm_dl_mm = "/soc/tpdm@69c0000";

msm_audio_ion = "/soc/qcom,msm-audio-apr/qcom,msm-audio-ion";

modem_skin = "/soc/qmi-tmd-devices/modem/modem_skin";

npu_trip = "/soc/thermal-zones/npu-lowf/trips/npu-trip";

ife_1_gdsc = "/soc/qcom,gdsc@ad0b004";

cti0_ddr0 = "/soc/cti@6a02000";

mas_qxm_mdp1 = "/soc/ad-hoc-bus/mas-qxm-mdp1";

slim_qca = "/soc/slim@62e40000";

bolero = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc";

tpdm_npu_out_tpda = "/soc/tpdm@69e1000/port/endpoint";

L1_I_200 = "/cpus/cpu@200/l1-icache";

smartpa_int_suspend = "/soc/pinctrl@3400000/smartpa_int_suspend";

loopback1 = "/soc/qcom,msm-pcm-loopback-low-latency";

funnel_dl_mm_out_tpda = "/soc/funnel@69C3000/ports/port@0/endpoint";

tpdm_lpass = "/soc/dummy_source";

batt_trip1 = "/soc/thermal-zones/quiet-therm-step/trips/batt-trip1";

slv_qhs_mnoc_cfg = "/soc/ad-hoc-bus/slv-qhs-mnoc-cfg";

slv_qhs_cpr_mx = "/soc/ad-hoc-bus/slv-qhs-cpr-mx";

tpdm_qdss_out_tpda = "/soc/tpdm@6006000/port/endpoint";

tpda_in_funnel_ddr_0 = "/soc/tpda@6004000/ports/port@5/endpoint";

tpdm_modem_0_out_tpda_modem_0 = "/soc/tpdm@6830000/port/endpoint";

sm6150_snd = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/sound";

qcom_seecom = "/soc/qseecom@86d00000";

funnel_apss_in_etm3 = "/soc/funnel@7800000/ports/port@4/endpoint";

tpdm_center_out_tpda = "/soc/tpdm@6b44000/port/endpoint";

tpdm_vsense_out_tpda = "/soc/tpdm@6840000/port/endpoint";

L1_D_100 = "/cpus/cpu@100/l1-dcache";

qupv3_se3_spi_active = "/soc/pinctrl@3400000/qupv3_se3_spi_pins/qupv3_se3_spi_active";

rx_cdc_dma_1_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-1-rx";

sdc1_cmd_off = "/soc/pinctrl@3400000/sdc1_cmd_off";

qupv3_se4_rts = "/soc/pinctrl@3400000/qupv3_se4_4uart_pins/qupv3_se4_rts";

usb30_prim_gdsc = "/soc/qcom,gdsc@10f004";

tpda_in_tpdm_qm = "/soc/tpda@6004000/ports/port@10/endpoint";

usb0 = "/soc/ssusb@a600000";

L8C = "/soc/rpmh-regulator-ldoc8/regulator-pm6150l-l8";

smb5_vbus = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,qpnp-smb5/qcom,smb5-vbus";

CLUSTER_COST_1 = "/energy-costs/cluster-cost1";

slv_qns_gem_noc_snoc = "/soc/ad-hoc-bus/slv-qns-gem-noc-snoc";

qupv3_se0_spi_pins = "/soc/pinctrl@3400000/qupv3_se0_spi_pins";

cpu6_cpu_l3_lat = "/soc/qcom,cpu6-cpu-l3-lat";

vbat_lvl0 = "/soc/thermal-zones/pm6150-vbat-lvl0/trips/vbat-lvl0";

usb_nop_phy = "/soc/usb_nop_phy";

cpu0_config = "/soc/thermal-zones/cpu-0-0-step/trips/cpu0-config";

etm2 = "/soc/etm@7240000";

cam_ipe1 = "/soc/qcom,ipe1";

iommu_qupv3_0_geni_se_cb = "/soc/qcom,qupv3_0_geni_se@0x8c0000/qcom,iommu_qupv3_0_geni_se_cb";

replicator_swao_out_eud = "/soc/replicator@6b0a000/ports/port@0/endpoint";

turing_etm0_out_funnel_turing_1 = "/soc/turing_etm0/port/endpoint";

funnel_merg_in_funnel_in2 = "/soc/funnel@6045000/ports/port@3/endpoint";

mas_qxm_mdp0_display = "/soc/ad-hoc-bus/mas-qxm-mdp0_display";

energy_costs = "/energy-costs";

sdc2_cd_on = "/soc/pinctrl@3400000/cd_on";

qupv3_se2_i2c_active = "/soc/pinctrl@3400000/qupv3_se2_i2c_pins/qupv3_se2_i2c_active";

pri_i2s_sck_active = "/soc/pinctrl@3400000/pri_i2s_sck_ws/pri_i2s_sck_active";

sb_9_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-9-tx";

msm_dai_cdc_dma = "/soc/qcom,msm-dai-cdc-dma";

mas_qnm_cnoc = "/soc/ad-hoc-bus/mas-qnm-cnoc";

secure_display_memory = "/reserved-memory/secure_display_region";

funnel_dl_mm_in_tpdm_dl_mm = "/soc/funnel@69C3000/ports/port@1/endpoint";

cti0_apss = "/soc/cti@78e0000";

VDD_MX_LEVEL = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3";

glink_adsp = "/soc/qcom,glink/adsp";

mas_xm_ufs_mem = "/soc/ad-hoc-bus/mas-xm-ufs-mem";

pm6150l_bob = "/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob";

pm6150l_adc_tm = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/adc_tm@3500";

mas_qhm_qup_north = "/soc/ad-hoc-bus/mas-qhm-qup-north";

L7C = "/soc/rpmh-regulator-ldoc7/regulator-pm6150l-l7";

dai_mi2s5 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-senary";

dai_sec_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-sec-tx/qcom,msm-dai-q6-tdm-sec-tx-0";

xbl_aop_mem = "/reserved-memory/xbl_aop_mem@85e00000";

cdsp_smp2p_out = "/soc/qcom,smp2p-cdsp/master-kernel";

slv_qhs_ddrss_cfg = "/soc/ad-hoc-bus/slv-qhs-ddrss-cfg";

compress = "/soc/qcom,msm-compress-dsp";

qupv3_se8_spi_active = "/soc/pinctrl@3400000/qupv3_se8_spi_pins/qupv3_se8_spi_active";

jtag_mm3 = "/soc/jtagmm@7340000";

smp2p_wlan_1_in = "/soc/qcom,smp2p-modem/qcom,smp2p-wlan-1-in";

pm6150l_l11 = "/soc/rpmh-regulator-ldoc11/regulator-pm6150l-l11";

slv_qhs_display_throttle_cfg = "/soc/ad-hoc-bus/slv-qhs-display-throttle-cfg";

qupv3_1 = "/soc/qcom,qupv3_1_geni_se@0xac0000";

pm6150_gpios = "/soc/qcom,spmi@c440000/qcom,pm6150@0/pinctrl@c000";

cti0_dlmm = "/soc/cti@69C1000";

funnel_qatb_in_funnel_turing_1 = "/soc/funnel@6005000/ports/port@3/endpoint";

cam_csid_lite0 = "/soc/qcom,csid-lite0@acc8000";

cti2_swao = "/soc/cti@6b06000";

sdhc_1 = "/soc/sdhci@7c4000";

sec_apps_mem = "/reserved-memory/sec_apps_region@85fff000";

trans_loopback = "/soc/qcom,msm-transcode-loopback";

pm6150_l16 = "/soc/rpmh-regulator-ldoa16/regulator-pm6150-l16";

gpu_gx_domain_addr = "/soc/syscon@0x5091508";

funnel_apss_merg = "/soc/funnel@7810000";

bt_sco_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-tx";

stub_codec = "/soc/qcom,msm-stub-codec";

mas_qxm_venus_arm9 = "/soc/ad-hoc-bus/mas-qxm-venus-arm9";

funnel_dl_south_1_in_tpdm_wcss = "/soc/funnel_1@6b53000/ports/port@1/endpoint";

CPU5 = "/cpus/cpu@500";

sde_rscc = "/soc/qcom,sde_rscc@af20000";

gmu = "/soc/qcom,gmu@506a000";

pm6150l_bob_ao = "/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob-ao";

funnel_in1 = "/soc/funnel@6042000";

slv_qhs_pcie_cfg = "/soc/ad-hoc-bus/slv-qhs-pcie-cfg";

tpdm_modem0 = "/soc/tpdm@6830000";

sp_mem = "/reserved-memory/sp_region";

smartpa_enable_suspend = "/soc/pinctrl@3400000/smartpa_enable_suspend";

qupv3_se7_i2c_active = "/soc/pinctrl@3400000/qupv3_se7_i2c_pins/qupv3_se7_i2c_active";

L6C = "/soc/rpmh-regulator-ldoc6/regulator-pm6150l-l6";

qupv3_se4_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se4_i2c_pins/qupv3_se4_i2c_sleep";

mas_qxm_rot = "/soc/ad-hoc-bus/mas-qxm-rot";

spkr_1_sd_n_sleep = "/soc/pinctrl@3400000/spkr_1_sd_n/spkr_1_sd_n_sleep";

i2c_freq_400Khz_cci0 = "/soc/qcom,cci@ac4a000/qcom,i2c_fast_mode";

npu_mem = "/reserved-memory/npu_region@97e80000";

nfc_enable_suspend = "/soc/pinctrl@3400000/nfc/nfc_enable_suspend";

sde_te_active = "/soc/pinctrl@3400000/pmx_sde_te/sde_te_active";

sb_3_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-3-tx";

qupv3_se9_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se9_i2c_pins/qupv3_se9_i2c_sleep";

funnel_swao = "/soc/funnel@6b08000";

cpu1_config = "/soc/thermal-zones/cpu-0-1-step/trips/cpu1-config";

cti7 = "/soc/cti@6017000";

anoc_1_tbu = "/soc/apps-smmu@0x15000000/anoc_1_tbu@0x15185000";

pm8009_l4 = "/soc/rpmh-regulator-ldof4/regulator-pm8009-l4";

bus_proxy_client = "/soc/qcom,bus_proxy_client";

bcm_ip0 = "/soc/ad-hoc-bus/bcm-ip0";

pwm_lpg3 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,pwms@b100/lpg3";

L9A = "/soc/rpmh-regulator-ldoa9/regulator-pm6150-l9";

pm6150l_flash1 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,flash_1";

qupv3_se11_ctsrx = "/soc/pinctrl@3400000/qupv3_se11_4uart_pins/qupv3_se11_ctsrx";

bcm_mm1_display = "/soc/ad-hoc-bus/bcm-mm1_display";

L1_I_500 = "/cpus/cpu@500/l1-icache";

cdsp_cdsp_l3_lat = "/soc/qcom,cdsp-cdsp-l3-lat";

sb_9_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-9-rx";

msm_npu = "/soc/qcom,msm_npu@9800000";

mas_acm_sys_tcu = "/soc/ad-hoc-bus/mas-acm-sys-tcu";

slv_qxs_imem = "/soc/ad-hoc-bus/slv-qxs-imem";

ts_active = "/soc/pinctrl@3400000/pmx_ts_active/ts_active";

sleep_clk = "/soc/clocks/sleep-clk";

sb_0_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-0-tx";

etm4_out_funnel_apss = "/soc/etm@7440000/port/endpoint";

L2_TLB_200 = "/cpus/cpu@200/l2-tlb";

pm6150l_l8 = "/soc/rpmh-regulator-ldoc8/regulator-pm6150l-l8";

L1_D_400 = "/cpus/cpu@400/l1-dcache";

L5C = "/soc/rpmh-regulator-ldoc5/regulator-pm6150l-l5";

mas_qhm_qup_center = "/soc/ad-hoc-bus/mas-qhm-qup-center";

LLCC_2 = "/soc/qcom,llcc@9200000/llcc_2_dcache";

L1_D_0 = "/cpus/cpu@0/l1-dcache";

funnel_apss_in_etm1 = "/soc/funnel@7800000/ports/port@2/endpoint";

bcl_lvl2 = "/soc/thermal-zones/pm6150-bcl-lvl2/trips/bcl-lvl2";

slv_qhs_tlmm_south = "/soc/ad-hoc-bus/slv-qhs-tlmm-south";

VDD_MSS_LEVEL = "/soc/rpmh-regulator-modemlvl/regulator-pm6150l-s7";

slv_qhs_ahb2phy_north = "/soc/ad-hoc-bus/slv-qhs-ahb2phy-north";

cci0_suspend = "/soc/pinctrl@3400000/cci0_suspend";

slv_qns_a1noc_snoc = "/soc/ad-hoc-bus/slv-qns-a1noc-snoc";

cpu6_0_config = "/soc/thermal-zones/cpu-1-0-step/trips/cpu6-0-config";

tpdm_gfx_out_funnel_gfx = "/soc/tpdm@6940000/port/endpoint";

fd_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_fd/iova-mem-map";

qcom_cedev = "/soc/qcedev@1de0000";

tpdm_ddr = "/soc/tpdm@6a00000";

sb_6_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-6-rx";

cam_cci1 = "/soc/qcom,cci@ac4b000";

mas_qxm_crypto = "/soc/ad-hoc-bus/mas-qxm-crypto";

loopback = "/soc/qcom,msm-pcm-loopback";

bt_sco_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-rx";

LPI_MX_LEVEL = "/soc/rpmh-regulator-lmxlvl/regulator-pm6150-l7";

qupv3_se10_spi = "/soc/spi@0xa90000";

wsa_swr_clk_sleep = "/soc/pinctrl@3400000/wsa_swr_clk_pin/wsa_swr_clk_sleep";

fab_aggre1_noc = "/soc/ad-hoc-bus/fab-aggre1_noc";

mas_qhm_tsif = "/soc/ad-hoc-bus/mas-qhm-tsif";

dai_pri_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-pri-tx/qcom,msm-dai-q6-tdm-pri-tx-0";

rsc_apps = "/soc/ad-hoc-bus/rsc-apps";

slv_srvc_aggre2_noc = "/soc/ad-hoc-bus/slv-srvc-aggre2-noc";

cam_sensor_mclk2_suspend = "/soc/pinctrl@3400000/cam_sensor_mclk2_suspend";

pm6150l_trip0 = "/soc/thermal-zones/pm6150l-tz/trips/trip0";

tpda_in_funnel_dl_south = "/soc/tpda@6004000/ports/port@3/endpoint";

wled_flash = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800/qcom,wled-flash";

qupv3_se1_spi = "/soc/spi@0x884000";

slv_qhs_mdsp_ms_mpu_cfg = "/soc/ad-hoc-bus/slv-qhs-mdsp-ms-mpu-cfg";

etm0 = "/soc/etm@7040000";

cti2_wcss = "/soc/cti@69a6000";

slv_qxs_pimem = "/soc/ad-hoc-bus/slv-qxs-pimem";

qupv3_se4_spi_sleep = "/soc/pinctrl@3400000/qupv3_se4_spi_pins/qupv3_se4_spi_sleep";

cam_vfe0 = "/soc/qcom,vfe0@acaf000";

dai_sen_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-sen-rx/qcom,msm-dai-q6-tdm-sen-rx-0";

funnel_merg_in_funnel_in0 = "/soc/funnel@6045000/ports/port@1/endpoint";

L4C = "/soc/rpmh-regulator-ldoc4/regulator-pm6150l-l4";

pm6150_l7_level = "/soc/rpmh-regulator-lmxlvl/regulator-pm6150-l7";

qmp_npu0 = "/soc/qcom,qmp-npu-low@9818000";

funnel_in0_in_audio_etm0 = "/soc/funnel@0x6041000/ports/port@2/endpoint";

cpu2_config = "/soc/thermal-zones/cpu-0-2-step/trips/cpu2-config";

dump_mem = "/reserved-memory/mem_dump_region";

slv_srvc_snoc = "/soc/ad-hoc-bus/slv-srvc-snoc";

replicator_qdss = "/soc/replicator@6046000";

sb_3_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-3-rx";

smb5_vconn = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,qpnp-smb5/qcom,smb5-vconn";

cam_csiphy3 = "/soc/qcom,csiphy@ace6000";

cti2_ddr1 = "/soc/cti@6a12000";

tpda_in_tpdm_center = "/soc/tpda@6004000/ports/port@13/endpoint";

pil_gpu = "/soc/qcom,kgsl-hyp";

qupv3_se10_4uart = "/soc/qcom,qup_uart@0xa90000";

qupv3_se3_i2c = "/soc/i2c@0x88c000";

wsa_cdc_dma_2_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-2-tx";

qupv3_se10_i2c_pins = "/soc/pinctrl@3400000/qupv3_se10_i2c_pins";

ibat_lvl0 = "/soc/thermal-zones/pm6150-ibat-lvl0/trips/ibat-lvl0";

slv_qhs_a2_noc_cfg = "/soc/ad-hoc-bus/slv-qhs-a2-noc-cfg";

tpda_in_tpdm_north = "/soc/tpda@6004000/ports/port@9/endpoint";

cam_jpeg_enc = "/soc/qcom,jpegenc@ac4e000";

cti14 = "/soc/cti@601e000";

dai_mi2s3 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quat";

modem_trip2 = "/soc/thermal-zones/quiet-therm-step/trips/modem-trip2";

funnel_qatb_out_funnel_in0 = "/soc/funnel@6005000/ports/port@0/endpoint";

cci0_active = "/soc/pinctrl@3400000/cci0_active";

mas_qxm_pimem = "/soc/ad-hoc-bus/mas-qxm-pimem";

aoss0_trip = "/soc/thermal-zones/aoss-0-lowf/trips/aoss0-trip";

mas_qnm_snoc_sf = "/soc/ad-hoc-bus/mas-qnm-snoc-sf";

qupv3_se1_i2c_pins = "/soc/pinctrl@3400000/qupv3_se1_i2c_pins";

WCSS_CX = "/soc/rpmh-regulator-ldoa9/regulator-pm6150-l9";

jtag_mm1 = "/soc/jtagmm@7140000";

pm6150l_s2_level = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2";

mnoc_hf_0_tbu = "/soc/apps-smmu@0x15000000/mnoc_hf_0_tbu@0x1518d000";

cam_vfe_lite0 = "/soc/qcom,vfe-lite0@acc4000";

slv_qhs_camera_nrt_throttle_cfg = "/soc/ad-hoc-bus/slv-qhs-camera-nrt-thrott-cfg";

slv_qhs_ufs_mem_cfg = "/soc/ad-hoc-bus/slv-qhs-ufs-mem-cfg";

cmd_db = "/soc/qcom,cmd-db@c3f000c";

cpu6_computemon = "/soc/qcom,cpu6-computemon";

nfc_clk_req_active = "/soc/pinctrl@3400000/nfc/nfc_clk_req_active";

tpdm_apss_out_tpda_apss = "/soc/tpdm@7860000/port/endpoint";

tx_cdc_dma_3_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-3-tx";

ife_0_gdsc = "/soc/qcom,gdsc@ad0a004";

pm6150_l14 = "/soc/rpmh-regulator-ldoa14/regulator-pm6150-l14";

sb_0_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-0-rx";

slv_qns2_mem_noc = "/soc/ad-hoc-bus/slv-qns2-mem-noc";

L3C = "/soc/rpmh-regulator-ldoc3/regulator-pm6150l-l3";

slv_srvc_gemnoc = "/soc/ad-hoc-bus/slv-srvc-gemnoc";

bcm_sn14 = "/soc/ad-hoc-bus/bcm-sn14";

L2_300 = "/cpus/cpu@300/l2-cache";

CPU3 = "/cpus/cpu@300";

cpu6_1_config = "/soc/thermal-zones/cpu-1-1-step/trips/cpu6-1-config";

pm8009_gpios = "/soc/qcom,spmi@c440000/qcom,pm8009@a/pinctrl@c000";

soc_trip = "/soc/thermal-zones/soc/trips/soc-trip";

pm6150l_vadc = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/vadc@3100";

gpuss_0_trip = "/soc/thermal-zones/gpuss-0-lowf/trips/gpuss-0-trip";

S2C_LEVEL = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2";

npu_npu_ddr_bwmon = "/soc/qcom,npu-npu-ddr-bwmon@9960300";

qusb_phy0 = "/soc/qusb@88e2000";

replicator_out_replicator1_in = "/soc/replicator@6046000/ports/port@1/endpoint";

L6A = "/soc/rpmh-regulator-ldoa6/regulator-pm6150-l6";

tlmm = "/soc/pinctrl@3400000";

bcm_sh10 = "/soc/ad-hoc-bus/bcm-sh10";

int_fm_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-tx";

qupv3_se7_i2c = "/soc/i2c@0xa84000";

tx_cdc_dma_0_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-0-tx";

cti5 = "/soc/cti@6015000";

apps_smmu = "/soc/apps-smmu@0x15000000";

pm6150_l5 = "/soc/rpmh-regulator-ldoa5/regulator-pm6150-l5";

pm8009_l2 = "/soc/rpmh-regulator-ldof2/regulator-pm8009-l2";

pm6150l_s1 = "/soc/rpmh-regulator-smpc1/regulator-pm6150l-s1";

tmc_etf_in_funnel_merg = "/soc/tmc@6047000/ports/port@1/endpoint";

cpu3_config = "/soc/thermal-zones/cpu-0-3-step/trips/cpu3-config";

cam_csid1 = "/soc/qcom,csid1@acba000";

msm_cam_smmu = "/soc/qcom,cam_smmu";

L2C = "/soc/rpmh-regulator-ldoc2/regulator-pm6150l-l2";

ipe_1_gdsc = "/soc/qcom,gdsc@ad09004";

removed_region = "/reserved-memory/removed_region@86200000";

slv_qns_llcc = "/soc/ad-hoc-bus/slv-qns-llcc";

gfx3d_secure = "/soc/qcom,kgsl-iommu@5040000/gfx3d_secure";

cpu6_cpu_llcc_lat = "/soc/qcom,cpu6-cpu-llcc-lat";

pcm_dtmf = "/soc/qcom,msm-pcm-dtmf";

L2_TLB_500 = "/cpus/cpu@500/l2-tlb";

L1_D_700 = "/cpus/cpu@700/l1-dcache";

nfc_clk_req_suspend = "/soc/pinctrl@3400000/nfc/nfc_clk_req_suspend";

csr = "/soc/csr@6001000";

gpu_cx_gdsc = "/soc/qcom,gdsc@509106c";

cont_splash_memory = "/reserved-memory/cont_splash_region@9c000000";

pm6150_tz = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,temp-alarm@2400";

cci1_active = "/soc/pinctrl@3400000/cci1_active";

clock_videocc = "/soc/qcom,videocc@ab00000";

pm6150l_l6 = "/soc/rpmh-regulator-ldoc6/regulator-pm6150l-l6";

L5A = "/soc/rpmh-regulator-ldoa5/regulator-pm6150-l5";

qupv3_se1_spi_active = "/soc/pinctrl@3400000/qupv3_se1_spi_pins/qupv3_se1_spi_active";

gpu_bw_tbl = "/soc/gpu-bw-tbl";

dai_hdmi = "/soc/qcom,msm-dai-q6-hdmi";

funnel_modem_out_funnel_in1 = "/soc/funnel@6832000/ports/port@0/endpoint";

sdc2_data_off = "/soc/pinctrl@3400000/sdc2_data_off";

bcl_lvl0 = "/soc/thermal-zones/pm6150-bcl-lvl0/trips/bcl-lvl0";

slv_qhs_camera_rt_throttle_cfg = "/soc/ad-hoc-bus/slv-qhs-camera-rt-throttle-cfg";

cpas_cdm_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_cpas_cdm/iova-mem-map";

fab_compute_noc = "/soc/ad-hoc-bus/fab-compute_noc";

cpucc_debug = "/soc/syscon@182a0018";

S2F = "/soc/rpmh-regulator-smpf2/regulator-pm8009-s2";

pm6150_clkdiv = "/soc/qcom,spmi@c440000/qcom,pm6150@0/clock-controller@5b00";

wsa_macro = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/wsa-macro@62f00000";

tpda_llm_gold = "/soc/tpda@78d0000";

qupv3_se10_tx = "/soc/pinctrl@3400000/qupv3_se10_4uart_pins/qupv3_se10_tx";

replicator_qdss1 = "/soc/replicator@604a000";

L1C = "/soc/rpmh-regulator-ldoc1/regulator-pm6150l-l1";

cti1_swao = "/soc/cti@6b05000";

qupv3_se11_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se11_i2c_pins/qupv3_se11_i2c_sleep";

tpdm_dl_center = "/soc/tpdm@6c28000";

smp2p_qvrexternal5_out = "/soc/qcom,smp2p-cdsp/qcom,smp2p-qvrexternal5-out";

mnoc_sf_0_tbu = "/soc/apps-smmu@0x15000000/mnoc_sf_0_tbu@0x15195000";

pm6150l_switch2 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,led_switch_2";

qcom_tzlog = "/soc/tz-log@146aa720";

msm_gpu = "/soc/qcom,kgsl-3d0@5000000";

sde_dp_usbplug_cc_active = "/soc/pinctrl@3400000/sde_dp_usbplug_cc_active";

bcm_mm3_display = "/soc/ad-hoc-bus/bcm-mm3_display";

gmu_user = "/soc/qcom,gmu@506a000/gmu_user";

gpu_gx_sw_reset = "/soc/syscon@0x5091008";

qupv3_se0_i2c_active = "/soc/pinctrl@3400000/qupv3_se0_i2c_pins/qupv3_se0_i2c_active";

tpdm_swao0 = "/soc/tpdm@6b02000";

L4A = "/soc/rpmh-regulator-ldoa4/regulator-pm6150-l4";

mas_qxm_venus1 = "/soc/ad-hoc-bus/mas-qxm-venus1";

int_fm_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-rx";

tpda_olc_in_tpdm_olc = "/soc/tpda@7832000/ports/port@1/endpoint";

L1_ITLB_700 = "/cpus/cpu@700/l1-itlb";

modem_trip1_hvx_trip = "/soc/thermal-zones/quiet-therm-step/trips/modem-trip1-hvx-trip";

ext_disp_audio_codec = "/soc/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx";

cam_csiphy1 = "/soc/qcom,csiphy@ace2000";

qupv3_se10_rts = "/soc/pinctrl@3400000/qupv3_se10_4uart_pins/qupv3_se10_rts";

hdmi_dba = "/soc/qcom,msm-hdmi-dba-codec-rx";

cpu4_config = "/soc/thermal-zones/cpu-0-4-step/trips/cpu4-config";

clock_rpmh = "/soc/qcom,rpmh";

tpda_in_tpdm_qdss = "/soc/tpda@6004000/ports/port@14/endpoint";

slv_qhs_vsense_ctrl_cfg = "/soc/ad-hoc-bus/slv-qhs-vsense-ctrl-cfg";

incall_music_2_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-2-rx";

qupv3_se10_spi_pins = "/soc/pinctrl@3400000/qupv3_se10_spi_pins";

qupv3_se6_spi_active = "/soc/pinctrl@3400000/qupv3_se6_spi_pins/qupv3_se6_spi_active";

S1F = "/soc/rpmh-regulator-smpf1/regulator-pm8009-s1";

qupv3_se6_i2c_pins = "/soc/pinctrl@3400000/qupv3_se6_i2c_pins";

etm3_out_funnel_apss = "/soc/etm@7340000/port/endpoint";

i2c_freq_1Mhz_cci1 = "/soc/qcom,cci@ac4b000/qcom,i2c_fast_plus_mode";

pcm_noirq = "/soc/qcom,msm-pcm-dsp-noirq";

cti12 = "/soc/cti@601c000";

dai_mi2s1 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-sec";

modem_trip0 = "/soc/thermal-zones/quiet-therm-step/trips/modem-trip0";

pil_modem = "/soc/qcom,mss@4080000";

qupv3_se1_spi_pins = "/soc/pinctrl@3400000/qupv3_se1_spi_pins";

cci2_suspend = "/soc/pinctrl@3400000/cci2_suspend";

icnss = "/soc/qcom,icnss@18800000";

ipa_smmu_wlan = "/soc/ipa_smmu_wlan";

mvsc_gdsc = "/soc/qcom,gdsc@0b00814";

modem_current = "/soc/qmi-tmd-devices/modem/modem_current";

bcm_sh8 = "/soc/ad-hoc-bus/bcm-sh8";

tpdm_llm_silver = "/soc/tpdm@78a0000";

bcm_acv_display = "/soc/ad-hoc-bus/bcm-acv_display";

tmc_etf_swao_in_funnel_swao = "/soc/tmc@6b09000/ports/port@1/endpoint";

cci2_active = "/soc/pinctrl@3400000/cci2_active";

wcd934x_mclk_default = "/soc/qcom,spmi@c440000/qcom,pm6150@0/pinctrl@c000/wcd934x_mclk/wcd934x_mclk_default";

L2_600 = "/cpus/cpu@600/l2-cache";

pm6150_l12 = "/soc/rpmh-regulator-ldoa12/regulator-pm6150-l12";

pm6150l_s2_level_ao = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2-level-ao";

mas_qhm_a1noc_cfg = "/soc/ad-hoc-bus/mas-qhm-a1noc-cfg";

qupv3_se8_2uart_active = "/soc/pinctrl@3400000/qupv3_se8_2uart_pins/qupv3_se8_2uart_active";

pil_camera_mem = "/reserved-memory/camera_region@8ab00000";

S3A_LEVEL_AO = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3-level-ao";

npu_trip0 = "/soc/thermal-zones/npu-step/trips/npu-trip0";

L3A = "/soc/rpmh-regulator-ldoa3/regulator-pm6150-l3";

tpdm_vsense = "/soc/tpdm@6840000";

bcm_sn12 = "/soc/ad-hoc-bus/bcm-sn12";

CPU1 = "/cpus/cpu@100";

pri_i2s_ws_sleep = "/soc/pinctrl@3400000/pri_i2s_sck_ws/pri_i2s_ws_sleep";

pm6150_trip0 = "/soc/thermal-zones/pm6150-tz/trips/trip0";

qupv3_se3_ctsrx = "/soc/pinctrl@3400000/qupv3_se3_4uart_pins/qupv3_se3_ctsrx";

cti_turing = "/soc/cti@6867000";

};

reserved-memory {

#address-cells = <0x02>;

#size-cells = <0x02>;

ranges;

phandle = <0x4d7>;

linux,cma {

linux,cma-default;

alignment = <0x00 0x400000>;

alloc-ranges = <0x00 0x00 0x00 0xffffffff>;

compatible = "shared-dma-pool";

size = <0x00 0x2000000>;

reusable;

};

pil_adsp_region@95700000 {

compatible = "removed-dma-pool";

reg = <0x00 0x95700000 0x00 0x2600000>;

phandle = <0xa1>;

no-map;

};

cdsp_region {

alignment = <0x00 0x400000>;

alloc-ranges = <0x00 0x00 0x00 0xffffffff>;

compatible = "shared-dma-pool";

size = <0x00 0x400000>;

phandle = <0x1a4>;

reusable;

};

xbl_aop_mem@85e00000 {

compatible = "removed-dma-pool";

reg = <0x00 0x85e00000 0x00 0x1ff000>;

phandle = <0x4d9>;

no-map;

};

cont_splash_region@9c000000 {

label = "cont_splash_region";

reg = <0x00 0x9c000000 0x00 0x1700000>;

phandle = <0x4de>;

};

secure_display_region {

alignment = <0x00 0x400000>;

alloc-ranges = <0x00 0x00 0x00 0xffffffff>;

compatible = "shared-dma-pool";

size = <0x00 0x8c00000>;

phandle = <0x1c3>;

reusable;

};

adsp_region {

alignment = <0x00 0x400000>;

alloc-ranges = <0x00 0x00 0x00 0xffffffff>;

compatible = "shared-dma-pool";

size = <0x00 0xc00000>;

phandle = <0x92>;

reusable;

};

gpu_region@97f15000 {

compatible = "removed-dma-pool";

reg = <0x00 0x97f15000 0x00 0x2000>;

phandle = <0x4dd>;

no-map;

};

pil_video_region@93400000 {

compatible = "removed-dma-pool";

reg = <0x00 0x93400000 0x00 0x500000>;

phandle = <0xb5>;

no-map;

};

dfps_data_region@9d700000 {

label = "dfps_data_region";

reg = <0x00 0x9d700000 0x00 0x100000>;

phandle = <0x1a5>;

};

smem@86000000 {

compatible = "removed-dma-pool";

reg = <0x00 0x86000000 0x00 0x200000>;

phandle = <0x90>;

no-map;

};

hyp_region@85700000 {

compatible = "removed-dma-pool";

reg = <0x00 0x85700000 0x00 0x600000>;

phandle = <0x4d8>;

no-map;

};

disp_rdump_region@9c000000 {

label = "disp_rdump_region";

reg = <0x00 0x9c000000 0x00 0x1800000>;

phandle = <0x4df>;

};

cdsp_sec_regions@0x9f800000 {

compatible = "removed-dma-pool";

reg = <0x00 0x9f800000 0x00 0x1e00000>;

phandle = <0x1c4>;

no-map;

};

npu_region@97e80000 {

compatible = "removed-dma-pool";

reg = <0x00 0x97e80000 0x00 0x80000>;

phandle = <0xb6>;

no-map;

};

removed_region@86200000 {

compatible = "removed-dma-pool";

reg = <0x00 0x86200000 0x00 0x4900000>;

phandle = <0x4db>;

no-map;

};

qseecom_region@9e400000 {

compatible = "shared-dma-pool";

reg = <0x00 0x9e400000 0x00 0x1400000>;

phandle = <0x9a>;

no-map;

};

ramdump_fb_region@af000000 {

compatible = "removed-dma-pool";

reg = <0x00 0xaf000000 0x00 0x1000000>;

phandle = <0x59f>;

no-map;

};

xbl_dump_mem@85d00000 {

compatible = "removed-dma-pool";

reg = <0x00 0x85d00000 0x00 0x100000>;

phandle = <0x5a0>;

no-map;

};

sec_apps_region@85fff000 {

compatible = "removed-dma-pool";

reg = <0x00 0x85fff000 0x00 0x1000>;

phandle = <0x4da>;

no-map;

};

sp_region {

alignment = <0x00 0x400000>;

alloc-ranges = <0x00 0x00 0x00 0xffffffff>;

compatible = "shared-dma-pool";

size = <0x00 0x800000>;

phandle = <0x1c2>;

reusable;

};

ips_fw_region@97f00000 {

compatible = "removed-dma-pool";

reg = <0x00 0x97f00000 0x00 0x10000>;

phandle = <0xc9>;

no-map;

};

qseecom_ta_region {

alignment = <0x00 0x400000>;

alloc-ranges = <0x00 0x00 0x00 0xffffffff>;

compatible = "shared-dma-pool";

size = <0x00 0x1000000>;

phandle = <0x1c1>;

reusable;

};

ipa_gsi_region@97f10000 {

compatible = "removed-dma-pool";

reg = <0x00 0x97f10000 0x00 0x5000>;

phandle = <0x4dc>;

no-map;

};

wlan_msa_region@97d00000 {

compatible = "removed-dma-pool";

reg = <0x00 0x97d00000 0x00 0x180000>;

phandle = <0xb7>;

no-map;

};

camera_region@8ab00000 {

compatible = "removed-dma-pool";

reg = <0x00 0x8ab00000 0x00 0x500000>;

phandle = <0x1b6>;

no-map;

};

modem_region@8b000000 {

compatible = "removed-dma-pool";

reg = <0x00 0x8b000000 0x00 0x8400000>;

phandle = <0xb1>;

no-map;

};

cdsp_regions@93900000 {

compatible = "removed-dma-pool";

reg = <0x00 0x93900000 0x00 0x1e00000>;

phandle = <0xad>;

no-map;

};

mem_dump_region {

compatible = "shared-dma-pool";

size = <0x00 0x2400000>;

phandle = <0x53>;

reusable;

};

};

memory {

ddr_device_type = <0x07>;

device_type = "memory";

reg = <0x00 0x80000000 0x01 0x00 0x01 0x80000000 0x00 0xfbb00000>;

};

};

Author

Title

Language

Your paste - Paste your paste here

/dts-v1/;

/ {
	#address-cells = &lt;0x02&gt;;
	model = &quot;SWEET&quot;;
	qcom,board-id = &lt;0x2e 0x00&gt;;
	#size-cells = &lt;0x02&gt;;
	interrupt-parent = &lt;0x01&gt;;
	qcom,msm-name = &quot;SDMMAGPIE&quot;;
	compatible = &quot;qcom,sdmmagpie-qrd\0qcom,sdmmagpie\0qcom,qrd&quot;;
	qcom,pmic-name = &quot;PM6150&quot;;
	qcom,msm-id = &lt;0x16d 0x00&gt;;

energy-costs {
		compatible = &quot;sched-energy&quot;;
		phandle = &lt;0x4d5&gt;;

core-cost0 {
			busy-cost-data = &lt;0x493e0 0x0a 0x8ca00 0x12 0xbb800 0x17 0xf8700 0x24 0x130b00 0x34 0x143700 0x43 0x16da00 0x4c 0x189c00 0x5c 0x1a1300 0x71 0x1b8a00 0x77&gt;;
			idle-cost-data = &lt;0x10 0x0c 0x08 0x06&gt;;
			phandle = &lt;0x02&gt;;
		};

cluster-cost0 {
			busy-cost-data = &lt;0x493e0 0x05 0x8ca00 0x05 0xbb800 0x05 0xf8700 0x07 0x130b00 0x08 0x143700 0x0a 0x16da00 0x0a 0x189c00 0x0c 0x1a1300 0x0e 0x1b8a00 0x0e&gt;;
			idle-cost-data = &lt;0x05 0x04 0x03 0x02 0x01&gt;;
			phandle = &lt;0x03&gt;;
		};

core-cost1 {
			busy-cost-data = &lt;0x493e0 0xa6 0x9f600 0xf2 0xc4e00 0x125 0xef100 0x1a8 0x10b300 0x1d6 0x127500 0x26d 0x143700 0x2a4 0x17bb00 0x3cd 0x1a1300 0x424 0x1c2000 0x512 0x1d9700 0x552 0x211b00 0x709 0x21b100 0x7d0 0x240900 0x916 0x249f00 0xa08&gt;;
			idle-cost-data = &lt;0x64 0x50 0x3c 0x28&gt;;
			phandle = &lt;0x0c&gt;;
		};

cluster-cost1 {
			busy-cost-data = &lt;0x493e0 0x13 0x9f600 0x15 0xc4e00 0x15 0xef100 0x19 0x10b300 0x1a 0x127500 0x20 0x143700 0x21 0x17bb00 0x29 0x1a1300 0x2b 0x1c2000 0x31 0x1d9700 0x32 0x211b00 0x3c 0x21b100 0x3d 0x240900 0x3e 0x249f00 0x3f&gt;;
			idle-cost-data = &lt;0x05 0x04 0x03 0x02 0x01&gt;;
			phandle = &lt;0x0d&gt;;
		};
	};

soc {
		#address-cells = &lt;0x01&gt;;
		#size-cells = &lt;0x01&gt;;
		compatible = &quot;simple-bus&quot;;
		ranges = &lt;0x00 0x00 0x00 0xffffffff&gt;;
		phandle = &lt;0x2a7&gt;;

qcom,wb-display@0 {
			cell-index = &lt;0x00&gt;;
			label = &quot;wb_display&quot;;
			compatible = &quot;qcom,wb-display&quot;;
			phandle = &lt;0x55e&gt;;
		};

funnel@6a05000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-ddr-0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6a05000 0x1000&gt;;
			phandle = &lt;0x453&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x24b&gt;;
						phandle = &lt;0x233&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x24c&gt;;
						phandle = &lt;0x24d&gt;;
					};
				};
			};
		};

mailbox@af20000 {
			interrupts = &lt;0x00 0x81 0x00&gt;;
			#mbox-cells = &lt;0x01&gt;;
			label = &quot;display_rsc&quot;;
			qcom,drv-id = &lt;0x00&gt;;
			compatible = &quot;qcom,tcs-drv&quot;;
			reg = &lt;0xaf20000 0x100 0xaf21c00 0x3000&gt;;
			phandle = &lt;0xcf&gt;;
			qcom,tcs-config = &lt;0x00 0x01 0x01 0x01 0x02 0x02 0x03 0x00&gt;;
		};

qcom,npu-npu-ddr-bwmon@9960300 {
			reg-names = &quot;base\0global_base&quot;;
			interrupts = &lt;0x00 0x16d 0x04&gt;;
			compatible = &quot;qcom,bimc-bwmon4&quot;;
			qcom,hw-timer-hz = &lt;0x124f800&gt;;
			qcom,mport = &lt;0x00&gt;;
			qcom,count-unit = &lt;0x10000&gt;;
			reg = &lt;0x9960300 0x300 0x9960200 0x200&gt;;
			phandle = &lt;0x31b&gt;;
			qcom,target-dev = &lt;0xc8&gt;;
		};

qcom,mdss_dsi_xiaomi_f4_41_06_0a_fhd_cmd {
			qcom,ulps-enabled;
			qcom,disp-doze-backlight-threshold = &lt;0x08&gt;;
			qcom,mdss-dsi-bl-min-level = &lt;0x02&gt;;
			qcom,mdss-pan-physical-width-dimension = &lt;0x45&gt;;
			qcom,mdss-dsi-panel-name = &quot;xiaomi f4 41 06 0a fhd cmd dsi panel&quot;;
			qcom,mdss-pan-physical-height-dimension = &lt;0x95&gt;;
			qcom,mdss-dsi-bl-xiaomi-f4-41-flag;
			qcom,mdss-dsi-te-using-te-pin;
			qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
			qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
			qcom,mdss-dsi-t-clk-post = &lt;0x0e&gt;;
			qcom,mdss-dsi-lane-2-state;
			qcom,mdss-dsi-te-check-enable;
			qcom,mdss-dsi-bllp-eof-power-mode;
			qcom,mdss-dsi-panel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-panel-fod-dimlayer-enabled;
			qcom,mdss-dsi-mode-sel-gpio-state = &quot;single_port&quot;;
			qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
			qcom,mdss-dsi-bl-max-level = &lt;0x7ff&gt;;
			qcom,bl-update-flag = &quot;delay_until_first_frame&quot;;
			qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
			qcom,mdss-dsi-panel-dc-demura-threshold = &lt;0x106&gt;;
			qcom,disp-fod-off-dimming-delay = &lt;0x55&gt;;
			qcom,dispparam-enabled;
			qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
			qcom,mdss-dsi-panel-peak-brightness = &lt;0x419ce0&gt;;
			qcom,mdss-dsi-lane-3-state;
			qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
			qcom,mdss-dsi-bl-default-level = &lt;0x218&gt;;
			qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-bl-dcs-type-ss-ea;
			qcom,mdss-dsi-reset-sequence = &lt;0x00 0x01 0x01 0x0a&gt;;
			qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
			qcom,mdss-dsi-lane-0-state;
			qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
			qcom,mdss-panel-on-dimming-delay = &lt;0xc8&gt;;
			qcom,mdss-dsi-t-clk-pre = &lt;0x33&gt;;
			qcom,mdss-dsi-panel-hdr-enabled;
			qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
			phandle = &lt;0x53a&gt;;
			qcom,mdss-dsi-bllp-power-mode;
			qcom,mdss-dsi-panel-sleepwrmod = &lt;0x00&gt;;
			qcom,panel-supply-entries = &lt;0x521&gt;;
			qcom,mdss-dsi-stream = &lt;0x00&gt;;
			qcom,mdss-dsi-lp11-init;
			qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
			qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
			qcom,mdss-dsi-tx-eot-append;
			qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
			qcom,mdss-dsi-border-color = &lt;0x00&gt;;
			qcom,mdss-dsi-lane-1-state;
			qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
			qcom,platform-te-gpio = &lt;0x174 0x0a 0x00&gt;;
			qcom,esd-err-irq-gpio = &lt;0x174 0x20 0x2002&gt;;
			qcom,mdss-dsi-bpp = &lt;0x18&gt;;
			qcom,mdss-brightness-max-level = &lt;0x7ff&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
					qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-demura-level8-command-state = &quot;dsi_lp_mode&quot;;
					qcom,display-topology = &lt;0x01 0x00 0x01&gt;;
					qcom,mdss-dsi-dispparam-hbm-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
					qcom,mdss-dsi-h-pulse-width = &lt;0x04&gt;;
					qcom,mdss-dsi-nolp-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dc-demura-l1-command = [39 01 00 00 00 00 02 fe 20 39 01 00 00 00 00 02 bc 00 39 01 00 00 00 00 02 fe 00];
					qcom,mdss-dsi-panel-jitter = &lt;0x05 0x01&gt;;
					qcom,mdss-dsi-nolp-command = [39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 25 06 39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 1f 08 39 01 00 00 00 00 02 2f 15 39 01 00 00 00 00 02 29 c0 39 01 00 00 00 00 02 fe 22 39 01 00 00 00 00 02 77 00 39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 38 00];
					qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-dispparam-demura-leveld-command = [39 01 00 00 00 00 02 fe 20 39 01 00 00 00 00 02 bc 0d 39 01 00 00 00 00 02 fe 00];
					qcom,mdss-dsi-dispparam-dc-off-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-dispparam-dc-on-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-doze-hbm-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-doze-lbm-command = [39 00 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 39 00 39 01 00 00 00 00 02 fe 72 39 01 00 00 00 00 02 69 0a 39 01 00 00 00 00 02 fe 22 39 01 00 00 00 00 02 77 02 39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 1f 00 39 01 00 00 00 00 02 2f 05 39 01 00 00 00 00 02 29 c1 39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 25 16];
					qcom,mdss-dsi-dispparam-hbm-fod-on-command = &lt;0x39010000 0x30002fe 0xa0390000 0x02 0x25063900 0x00 0x2fea039 0x00 0x21f08 0x39000000 0x22f 0x15390000 0x02 0x29c03900 0x00 0x2fe2239 0x00 0x27700 0x39000000 0x2fe 0x390000 0x02 0x38003900 0x00 0x2fe0039 0x1000000 0x253e0&gt;;
					qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 e8];
					qcom,mdss-dsi-dispparam-dimmingoff-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-hbm-fod-off-command = [39 01 00 00 03 00 02 fe 00 39 01 00 00 00 00 02 53 20];
					qcom,mdss-dsi-dispparam-dimmingon-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 28];
					qcom,mdss-dsi-dispparam-demura-level2-command = [39 01 00 00 00 00 02 fe 20 39 01 00 00 00 00 02 bc 02 39 01 00 00 00 00 02 fe 00];
					qcom,mdss-dsi-dispparam-dc-on-command = &lt;0x39000000 0x2fe 0x40390000 0x02 0x1db83900 0x00 0x2fed039 0x00 0x27101 0x39010000 0x10002fb 0xaa390000 0x02 0xfe743900 0x00 0x20e6039 0x00 0x21001 0x39000000 0x211 0x390000 0x02 0x12003900 0x00 0x2130039 0x00 0x21400 0x39000000 0x215 0x390000 0x02 0x22603900 0x00 0x2430039 0x00 0x2451f 0x39000000 0x24a 0xff390000 0x02 0x61603900 0x00 0x2fe4039 0x00 0x21df8 0x39000000 0x2fe 0xd0390000 0x02 0x71023901 0x1400 0x2fbaa39 0x1000000 0x2fe00&gt;;
					qcom,mdss-dsi-dispparam-dc-off-command = &lt;0x39000000 0x2fe 0x40390000 0x02 0x1db83900 0x00 0x2fed039 0x00 0x27101 0x39010000 0x10002fb 0xaa390000 0x02 0xfe743900 0x00 0x20e7f39 0x00 0x21008 0x39000000 0x211 0x8390000 0x02 0x12073900 0x00 0x2130639 0x00 0x21405 0x39000000 0x215 0x2390000 0x02 0x227f3900 0x00 0x2433f39 0x00 0x24511 0x39000000 0x24a 0x6f390000 0x02 0x617f3900 0x00 0x2fe4039 0x00 0x21df8 0x39000000 0x2fe 0xd0390000 0x02 0x71023901 0x1400 0x2fbaa39 0x1000000 0x2fe00&gt;;
					qcom,mdss-dsi-panel-height = &lt;0x924&gt;;
					qcom,mdss-dsi-on-command = [39 00 00 00 00 00 02 fe 40 39 00 00 00 00 00 02 70 04 39 01 00 00 00 00 02 4d 32 39 00 00 00 00 00 02 fe 40 39 00 00 00 00 00 02 be 17 39 00 00 00 00 00 02 bf bb 39 00 00 00 00 00 02 c0 dd 39 01 00 00 00 00 02 c1 ff 39 00 00 00 00 00 02 fe d0 39 00 00 00 00 00 02 03 24 39 01 00 00 00 00 02 04 03 39 00 00 00 00 00 02 fe 00 39 00 00 00 00 00 02 c2 08 39 00 00 00 00 00 02 fe 00 39 00 00 00 00 00 02 35 00 39 01 00 00 00 00 03 51 00 00 05 01 00 00 64 00 02 11 00 05 01 00 00 00 00 02 29 00];
					qcom,mdss-dsi-h-front-porch = &lt;0x1c&gt;;
					qcom,mdss-dsi-dispparam-demura-level2-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-h-back-porch = &lt;0x24&gt;;
					qcom,mdss-dsi-dispparam-dc-demura-l1-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-demura-leveld-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-hbm-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
					qcom,mdss-dsi-panel-clockrate = &lt;0x4190ab00&gt;;
					qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
					qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
					qcom,mdss-dsi-v-pulse-width = &lt;0x04&gt;;
					qcom,mdss-dsi-doze-hbm-command = [39 00 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 39 00 39 01 00 00 00 00 02 fe 72 39 01 00 00 00 00 02 69 ff 39 01 00 00 00 00 02 fe 22 39 01 00 00 00 00 02 77 02 39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 1f 00 39 01 00 00 00 00 02 2f 05 39 01 00 00 00 00 02 29 c1 39 01 00 00 00 00 02 fe a0 39 01 00 00 00 00 02 25 16];
					qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dc-demura-l2-command = [39 01 00 00 00 00 02 fe 20 39 01 00 00 00 00 02 bc 04 39 01 00 00 00 00 02 fe 00];
					qcom,mdss-dsi-dispparam-dimmingoff-command = [15 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 20];
					qcom,mdss-dsi-panel-phy-timings = &lt;0x220808 0x25220908 0x6020400&gt;;
					qcom,mdss-dsi-v-back-porch = &lt;0x04&gt;;
					qcom,mdss-dsi-doze-lbm-command-state = &quot;dsi_lp_mode&quot;;
					qcom,default-topology-index = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-demura-level8-command = [39 01 00 00 00 00 02 fe 20 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 fe 00];
					qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
					qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 14 00 02 10 00];
					qcom,mdss-dsi-dispparam-dc-demura-l2-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingon-command = [15 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 28];
					qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
					qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
				};
			};
		};

qcom,msm-sen-auxpcm {
			qcom,msm-cpudai-auxpcm-quant = &lt;0x02 0x02&gt;;
			qcom,msm-cpudai-auxpcm-frame = &lt;0x05 0x04&gt;;
			qcom,msm-cpudai-auxpcm-sync = &lt;0x01 0x01&gt;;
			qcom,msm-auxpcm-interface = &quot;senary&quot;;
			qcom,msm-cpudai-auxpcm-slot-mapping = &lt;0x01 0x01&gt;;
			qcom,msm-cpudai-auxpcm-data = &lt;0x00 0x00&gt;;
			qcom,msm-cpudai-afe-clk-ver = &lt;0x02&gt;;
			qcom,msm-cpudai-auxpcm-num-slots = &lt;0x01 0x01&gt;;
			compatible = &quot;qcom,msm-auxpcm-dev&quot;;
			qcom,msm-cpudai-auxpcm-mode = &lt;0x00 0x00&gt;;
			phandle = &lt;0x4b8&gt;;
			qcom,msm-cpudai-auxpcm-pcm-clk-rate = &lt;0x1f4000 0x1f4000&gt;;
		};

cti@601e000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti14&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x601e000 0x1000&gt;;
			phandle = &lt;0x483&gt;;
		};

hwlock {
			syscon = &lt;0x8f 0x00 0x1000&gt;;
			compatible = &quot;qcom,tcsr-mutex&quot;;
			phandle = &lt;0x91&gt;;
			#hwlock-cells = &lt;0x01&gt;;
		};

tmc@6b09000 {
			arm,primecell-periphid = &lt;0x3b961&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tmc-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tmc-etf-swao&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b09000 0x1000&gt;;
			phandle = &lt;0x42b&gt;;
			coresight-csr = &lt;0x1d6&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1f6&gt;;
						phandle = &lt;0x1f5&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1f7&gt;;
						phandle = &lt;0x1f8&gt;;
					};
				};
			};
		};

qcom,lpass@62400000 {
			qcom,smem-state-names = &quot;qcom,force-stop&quot;;
			qcom,smem-id = &lt;0x1a7&gt;;
			qcom,sysmon-id = &lt;0x01&gt;;
			qcom,vdd_mx-uV-uA = &lt;0x181 0x00&gt;;
			qcom,ssctl-instance-id = &lt;0x14&gt;;
			clock-names = &quot;xo&quot;;
			qcom,proxy-timeout-ms = &lt;0x2710&gt;;
			memory-region = &lt;0xa1&gt;;
			clocks = &lt;0x2f 0x00&gt;;
			qcom,signal-aop;
			qcom,complete-ramdump;
			qcom,pas-id = &lt;0x01&gt;;
			interrupts-extended = &lt;0x01 0x00 0xa2 0x01 0xa2 0x00 0x00 0xa2 0x01 0x00 0xa2 0x02 0x00 0xa2 0x03 0x00&gt;;
			vdd_lpi_mx-supply = &lt;0xa0&gt;;
			compatible = &quot;qcom,pil-tz-generic&quot;;
			qcom,vdd_cx-uV-uA = &lt;0x181 0x00&gt;;
			interrupt-names = &quot;qcom,wdog\0qcom,err-fatal\0qcom,err-ready\0qcom,proxy-unvote\0qcom,stop-ack&quot;;
			reg = &lt;0x62400000 0x100&gt;;
			qcom,smem-states = &lt;0xa3 0x00&gt;;
			mboxes = &lt;0x1c 0x00&gt;;
			qcom,proxy-clock-names = &quot;xo&quot;;
			qcom,proxy-reg-names = &quot;vdd_lpi_cx\0vdd_lpi_mx&quot;;
			qcom,firmware-name = &quot;adsp&quot;;
			vdd_lpi_cx-supply = &lt;0x9f&gt;;
			mbox-names = &quot;adsp-pil&quot;;
		};

qcom,gpucc {
			#reset-cells = &lt;0x01&gt;;
			qcom,gpu_cc_gmu_clk_src-opp-handle = &lt;0x22&gt;;
			reg-names = &quot;cc_base&quot;;
			qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = &lt;0x21&gt;;
			#clock-cells = &lt;0x01&gt;;
			vdd_mx-supply = &lt;0x1f&gt;;
			compatible = &quot;qcom,gpucc-sdmmagpie\0syscon&quot;;
			reg = &lt;0x5090000 0x9000&gt;;
			phandle = &lt;0x2b&gt;;
			vdd_cx-supply = &lt;0x1d&gt;;
			vdd_gfx-supply = &lt;0x20&gt;;
		};

rpmh-regulator-lcxlvl {
			compatible = &quot;qcom,rpmh-arc-regulator&quot;;
			qcom,resource-name = &quot;lcx.lvl&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm6150-l8 {
				regulator-max-microvolt = &lt;0x10000&gt;;
				regulator-min-microvolt = &lt;0x11&gt;;
				regulator-name = &quot;pm6150_l8_level&quot;;
				qcom,init-voltage-level = &lt;0x11&gt;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x9f&gt;;
			};
		};

qcom,rpm-stats@c300000 {
			reg-names = &quot;phys_addr_base\0offset_addr&quot;;
			qcom,num-records = &lt;0x03&gt;;
			compatible = &quot;qcom,rpm-stats&quot;;
			reg = &lt;0xc300000 0x1000 0xc3f0004 0x04&gt;;
		};

gpu-bw-tbl {
			compatible = &quot;operating-points-v2&quot;;
			phandle = &lt;0x2a3&gt;;

opp-1017 {
				opp-hz = &lt;0x00 0xf27&gt;;
			};

opp-300 {
				opp-hz = &lt;0x00 0x478&gt;;
			};

opp-451 {
				opp-hz = &lt;0x00 0x6b8&gt;;
			};

opp-1353 {
				opp-hz = &lt;0x00 0x1429&gt;;
			};

opp-1804 {
				opp-hz = &lt;0x00 0x1ae1&gt;;
			};

opp-200 {
				opp-hz = &lt;0x00 0x2fa&gt;;
			};

opp-681 {
				opp-hz = &lt;0x00 0xa25&gt;;
			};

opp-1555 {
				opp-hz = &lt;0x00 0x172b&gt;;
			};

opp-547 {
				opp-hz = &lt;0x00 0x826&gt;;
			};

opp-100 {
				opp-hz = &lt;0x00 0x17d&gt;;
			};

opp-0 {
				opp-hz = &lt;0x00 0x00&gt;;
			};

opp-825 {
				opp-hz = &lt;0x00 0xc4b&gt;;
			};
		};

qcom,dsi-display@10 {
			qcom,dsi-phy-num = &lt;0x00 0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x52c&gt;;
			qcom,dsi-ctrl-num = &lt;0x00 0x01&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_dual_sharp_wqhd_cmd_display&quot;;
			phandle = &lt;0x549&gt;;
		};

tmc@6047000 {
			arm,primecell-periphid = &lt;0x3b961&gt;;
			coresight-ctis = &lt;0x1d5 0x1d5&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tmc-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tmc-etf&quot;;
			arm,default-sink;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6047000 0x1000&gt;;
			phandle = &lt;0x420&gt;;
			coresight-csr = &lt;0x1d6&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1d8&gt;;
						phandle = &lt;0x1d2&gt;;
					};
				};

port@1 {
					reg = &lt;0x01&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1d9&gt;;
						phandle = &lt;0x1da&gt;;
					};
				};
			};
		};

etm@7640000 {
			arm,primecell-periphid = &lt;0xbb95d&gt;;
			clock-names = &quot;apb_pclk&quot;;
			clocks = &lt;0x19 0x00&gt;;
			cpu = &lt;0x17&gt;;
			qcom,tupwr-disable;
			coresight-name = &quot;coresight-etm6&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7640000 0x1000&gt;;
			phandle = &lt;0x442&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x223&gt;;
					phandle = &lt;0x21b&gt;;
				};
			};
		};

interrupt-controller@17a00000 {
			#redistributor-regions = &lt;0x01&gt;;
			interrupts = &lt;0x01 0x09 0x04&gt;;
			interrupt-parent = &lt;0x1a&gt;;
			redistributor-stride = &lt;0x00 0x20000&gt;;
			compatible = &quot;arm,gic-v3&quot;;
			#interrupt-cells = &lt;0x03&gt;;
			reg = &lt;0x17a00000 0x10000 0x17a60000 0x100000&gt;;
			phandle = &lt;0x1a&gt;;
			interrupt-controller;
		};

usbpd_pm {
			mi,pd-bus-curr-compensate = &lt;0x64&gt;;
			mi,pd-ffc-bat-volt-max = &lt;0x1176&gt;;
			mi,pd-bat-curr-max = &lt;0x1770&gt;;
			mi,pd-bat-volt-max = &lt;0x1162&gt;;
			compatible = &quot;xiaomi,usbpd-pm&quot;;
			status = &quot;ok&quot;;
			mi,pd-bus-curr-max = &lt;0xbb8&gt;;
			mi,pd-bus-volt-max = &lt;0x2ee0&gt;;
		};

cti@601b000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti11&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x601b000 0x1000&gt;;
			phandle = &lt;0x480&gt;;
		};

cti@6a12000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-ddr_dl_1_cti2&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6a12000 0x1000&gt;;
			phandle = &lt;0x465&gt;;
		};

tpdm@684c000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-prng&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x684c000 0x1000&gt;;
			phandle = &lt;0x458&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x253&gt;;
					phandle = &lt;0x236&gt;;
				};
			};
		};

qcom,gdsc@17d03c {
			qcom,no-status-check-on-disable;
			qcom,gds-timeout = &lt;0x1f4&gt;;
			regulator-name = &quot;hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x17d03c 0x04&gt;;
			phandle = &lt;0x1cc&gt;;
		};

jtagmm@7740000 {
			clock-names = &quot;core_clk&quot;;
			reg-names = &quot;etm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			compatible = &quot;qcom,jtagv8-mm&quot;;
			qcom,coresight-jtagmm-cpu = &lt;0x18&gt;;
			reg = &lt;0x7740000 0x1000&gt;;
			phandle = &lt;0x2af&gt;;
		};

tpdm@6940000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			vddcx-supply = &lt;0x1c5&gt;;
			clock-names = &quot;apb_pclk\0gpu_apb_clk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00 0x2b 0x08&gt;;
			coresight-name = &quot;coresight-tpdm-gpu&quot;;
			vdd-supply = &lt;0x24e&gt;;
			compatible = &quot;arm,primecell&quot;;
			status = &quot;disabled&quot;;
			qcom,tpdm-regs = &quot;vddcx\0vdd&quot;;
			reg = &lt;0x6940000 0x1000&gt;;
			regulator-names = &quot;vddcx\0vdd&quot;;
			phandle = &lt;0x456&gt;;
			qcom,tpdm-clks = &quot;gpu_apb_clk&quot;;
			qcom,msr-fix-req;

port {

endpoint {
					remote-endpoint = &lt;0x251&gt;;
					phandle = &lt;0x250&gt;;
				};
			};
		};

qcom,msm-dai-tdm-sec-tx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9011&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9111&gt;;
			phandle = &lt;0x4bd&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-sec-tx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9011&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x289&gt;;
			};
		};

rpmh-regulator-ldoa15 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa15&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l15 {
				regulator-max-microvolt = &lt;0x1d0d80&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x19e100&gt;;
				regulator-min-microvolt = &lt;0x19e100&gt;;
				regulator-name = &quot;pm6150_l15&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x40a&gt;;
			};
		};

qcom,msm-pcm-loopback-low-latency {
			qcom,msm-pcm-loopback-low-latency;
			compatible = &quot;qcom,msm-pcm-loopback&quot;;
			phandle = &lt;0x48f&gt;;
		};

spi@0x88c000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x17c&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			interrupts = &lt;0x00 0x25c 0x00&gt;;
			clocks = &lt;0x27 0x4a 0x27 0x67 0x27 0x68&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x168&gt;;
			spi-max-frequency = &lt;0x2faf080&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,spi-geni&quot;;
			pinctrl-1 = &lt;0x17d&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0x88c000 0x4000&gt;;
			phandle = &lt;0x356&gt;;
			dmas = &lt;0x165 0x00 0x03 0x01 0x40 0x00 0x165 0x01 0x03 0x01 0x40 0x00&gt;;
		};

qcom,ipe1 {
			clock-control-debugfs = &quot;true&quot;;
			clock-names = &quot;ipe_1_ahb_clk\0ipe_1_areg_clk\0ipe_1_axi_clk\0ipe_1_clk_src\0ipe_1_clk&quot;;
			reg-names = &quot;ipe1_top&quot;;
			reg-cam-base = &lt;0x91000&gt;;
			cell-index = &lt;0x01&gt;;
			clocks = &lt;0x29 0x48 0x29 0x49 0x29 0x4a 0x29 0x47 0x29 0x4b&gt;;
			ipe1-vdd-supply = &lt;0x1ba&gt;;
			clock-cntl-level = &quot;lowsvs\0svs\0svs_l1\0nominal\0turbo&quot;;
			compatible = &quot;qcom,cam-ipe&quot;;
			src-clock-name = &quot;ipe_1_clk_src&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xac91000 0x3000&gt;;
			regulator-names = &quot;ipe1-vdd&quot;;
			phandle = &lt;0x395&gt;;
			qcom,cam-cx-ipeak = &lt;0x1a3 0x03&gt;;
			clock-rates = &lt;0x00 0x00 0x00 0x1443fd00 0x00 0x00 0x00 0x00 0x19a14780 0x00 0x00 0x00 0x00 0x1efe9200 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600 0x00&gt;;
		};

qcom,csiphy@ace6000 {
			clock-names = &quot;cphy_rx_clk_src\0csiphy0_clk\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk&quot;;
			reg-names = &quot;csiphy&quot;;
			reg-cam-base = &lt;0xe6000&gt;;
			csi-vdd-voltage = &lt;0x124f80&gt;;
			cell-index = &lt;0x03&gt;;
			interrupts = &lt;0x00 0x25f 0x00&gt;;
			clocks = &lt;0x29 0x1b 0x29 0x24 0x29 0x27 0x29 0x23 0x29 0x22&gt;;
			gdscr-supply = &lt;0x1ae&gt;;
			clock-cntl-level = &quot;svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,csiphy-v1.2\0qcom,csiphy&quot;;
			src-clock-name = &quot;csi3phytimer_clk_src&quot;;
			mipi-csi-vdd-supply = &lt;0x1a8&gt;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;csiphy&quot;;
			reg = &lt;0xace6000 0x2000&gt;;
			regulator-names = &quot;gdscr\0refgen&quot;;
			phandle = &lt;0x37b&gt;;
			refgen-supply = &lt;0x1af&gt;;
			clock-rates = &lt;0x16e36000 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00&gt;;
		};

rpmh-regulator-smpa5 {
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;smpa5&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm6150-s5 {
				regulator-max-microvolt = &lt;0x1f20c0&gt;;
				qcom,init-voltage = &lt;0x1a9c80&gt;;
				regulator-min-microvolt = &lt;0x1a9c80&gt;;
				regulator-name = &quot;pm6150_s5&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x3fe&gt;;
			};
		};

qcom,cci@ac4a000 {
			pinctrl-names = &quot;cam_default\0cam_suspend&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x1b0 0x1b1&gt;;
			clock-names = &quot;cci_0_clk\0cci_0_clk_src&quot;;
			reg-names = &quot;cci&quot;;
			reg-cam-base = &lt;0x4a000&gt;;
			cell-index = &lt;0x00&gt;;
			gpio-req-tbl-num = &lt;0x00 0x01 0x02 0x03&gt;;
			interrupts = &lt;0x00 0x1cc 0x00&gt;;
			clocks = &lt;0x29 0x15 0x29 0x16&gt;;
			gdscr-supply = &lt;0x1ae&gt;;
			#size-cells = &lt;0x00&gt;;
			gpio-req-tbl-label = &quot;CCI_I2C_DATA0\0CCI_I2C_CLK0\0CCI_I2C_DATA1\0CCI_I2C_CLK1&quot;;
			clock-cntl-level = &quot;lowsvs&quot;;
			compatible = &quot;qcom,cci&quot;;
			src-clock-name = &quot;cci_0_clk_src&quot;;
			pinctrl-1 = &lt;0x1b2 0x1b3&gt;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;cci&quot;;
			reg = &lt;0xac4a000 0x1000&gt;;
			regulator-names = &quot;gdscr&quot;;
			phandle = &lt;0x37c&gt;;
			clock-rates = &lt;0x00 0x23c3460&gt;;
			gpio-req-tbl-flags = &lt;0x01 0x01 0x01 0x01&gt;;
			gpios = &lt;0x174 0x11 0x00 0x174 0x12 0x00 0x174 0x13 0x00 0x174 0x14 0x00&gt;;

qcom,eeprom@2 {
				rgltr-max-voltage = &lt;0x1b7740&gt;;
				cell-index = &lt;0x02&gt;;
				cci-device = &lt;0x00&gt;;
				rgltr-load-current = &lt;0x2bf20&gt;;
				cam_vio-supply = &lt;0x562&gt;;
				rgltr-cntrl-support;
				cci-master = &lt;0x01&gt;;
				compatible = &quot;qcom,eeprom&quot;;
				rgltr-min-voltage = &lt;0x1b7740&gt;;
				status = &quot;ok&quot;;
				reg = &lt;0x02&gt;;
				regulator-names = &quot;cam_vio&quot;;
				phandle = &lt;0x56a&gt;;
			};

qcom,i2c_custom_mode {
				hw-tsu-sto = &lt;0x28&gt;;
				cci-clk-src = &lt;0x23c3460&gt;;
				hw-tsp = &lt;0x03&gt;;
				hw-trdhld = &lt;0x06&gt;;
				hw-thigh = &lt;0x26&gt;;
				hw-tlow = &lt;0x38&gt;;
				status = &quot;ok&quot;;
				hw-thd-dat = &lt;0x16&gt;;
				hw-tsu-sta = &lt;0x28&gt;;
				hw-scl-stretch-en = &lt;0x01&gt;;
				phandle = &lt;0x37f&gt;;
				hw-tbuf = &lt;0x3e&gt;;
				hw-thd-sta = &lt;0x23&gt;;
			};

qcom,cam-sensor@3 {
				rgltr-max-voltage = &lt;0x1b7740 0x2ab980 0x00&gt;;
				pinctrl-names = &quot;cam_default\0cam_suspend&quot;;
				eeprom-src = &lt;0x571&gt;;
				pinctrl-0 = &lt;0x573 0x574 0x575&gt;;
				clock-names = &quot;cam_clk&quot;;
				cell-index = &lt;0x03&gt;;
				gpio-req-tbl-num = &lt;0x00 0x01 0x02&gt;;
				sensor-position-yaw = &lt;0xb4&gt;;
				cci-device = &lt;0x00&gt;;
				clocks = &lt;0x29 0x56&gt;;
				rgltr-load-current = &lt;0x2bf20 0x1d4c0 0x00&gt;;
				actuator-src = &lt;0x572&gt;;
				cam_vio-supply = &lt;0x562&gt;;
				rgltr-cntrl-support;
				cam_vana-supply = &lt;0x56b&gt;;
				gpio-req-tbl-label = &quot;CAMIF_MCLK1\0CAMM_RESET\0CAMD_CUSTOM1&quot;;
				gpio-reset = &lt;0x01&gt;;
				csiphy-sd-index = &lt;0x03&gt;;
				clock-cntl-level = &quot;turbo&quot;;
				gpio-custom1 = &lt;0x02&gt;;
				cci-master = &lt;0x01&gt;;
				gpio-no-mux = &lt;0x00&gt;;
				compatible = &quot;qcom,cam-sensor&quot;;
				rgltr-min-voltage = &lt;0x1b7740 0x2ab980 0x00&gt;;
				led-flash-src = &lt;0x570&gt;;
				sensor-position-roll = &lt;0x5a&gt;;
				pinctrl-1 = &lt;0x576 0x577 0x578&gt;;
				status = &quot;ok&quot;;
				reg = &lt;0x03&gt;;
				regulator-names = &quot;cam_vio\0cam_vana\0cam_clk&quot;;
				sensor-position-pitch = &lt;0x00&gt;;
				cam_clk-supply = &lt;0x1ae&gt;;
				clock-rates = &lt;0x124f800&gt;;
				gpio-req-tbl-flags = &lt;0x01 0x00 0x00&gt;;
				gpios = &lt;0x174 0x10 0x00 0x174 0x18 0x00 0x174 0x58 0x00&gt;;
			};

qcom,eeprom@0 {
				cam_v_custom1-supply = &lt;0x406&gt;;
				rgltr-max-voltage = &lt;0x1b7740 0x10c8e0 0x10c8e0 0x00&gt;;
				pinctrl-names = &quot;cam_default\0cam_suspend&quot;;
				pinctrl-0 = &lt;0x563 0x564&gt;;
				clock-names = &quot;cam_clk&quot;;
				cell-index = &lt;0x00&gt;;
				gpio-req-tbl-num = &lt;0x00 0x01&gt;;
				cci-device = &lt;0x00&gt;;
				clocks = &lt;0x29 0x54&gt;;
				rgltr-load-current = &lt;0x2bf20 0x1d4c0 0x1d4c0 0x00&gt;;
				cam_vio-supply = &lt;0x562&gt;;
				rgltr-cntrl-support;
				gpio-req-tbl-label = &quot;CAMIF_MCLK0\0CAMW_RESET&quot;;
				gpio-reset = &lt;0x01&gt;;
				csiphy-sd-index = &lt;0x00&gt;;
				clock-cntl-level = &quot;turbo&quot;;
				cam_vdig-supply = &lt;0x406&gt;;
				sensor-mode = &lt;0x00&gt;;
				cci-master = &lt;0x00&gt;;
				gpio-no-mux = &lt;0x00&gt;;
				compatible = &quot;qcom,eeprom&quot;;
				rgltr-min-voltage = &lt;0x1b7740 0x10c8e0 0x10c8e0 0x00&gt;;
				pinctrl-1 = &lt;0x565 0x566&gt;;
				status = &quot;ok&quot;;
				reg = &lt;0x00&gt;;
				regulator-names = &quot;cam_vio\0cam_vdig\0cam_v_custom1\0cam_clk&quot;;
				phandle = &lt;0x569&gt;;
				cam_clk-supply = &lt;0x1ae&gt;;
				clock-rates = &lt;0x124f800&gt;;
				gpio-req-tbl-flags = &lt;0x01 0x00&gt;;
				gpios = &lt;0x174 0x0f 0x00 0x174 0x1a 0x00&gt;;
			};

qcom,i2c_standard_mode {
				hw-tsu-sto = &lt;0xcc&gt;;
				cci-clk-src = &lt;0x23c3460&gt;;
				hw-tsp = &lt;0x03&gt;;
				hw-trdhld = &lt;0x06&gt;;
				hw-thigh = &lt;0xc9&gt;;
				hw-tlow = &lt;0xae&gt;;
				status = &quot;ok&quot;;
				hw-thd-dat = &lt;0x16&gt;;
				hw-tsu-sta = &lt;0xe7&gt;;
				hw-scl-stretch-en = &lt;0x00&gt;;
				phandle = &lt;0x37d&gt;;
				hw-tbuf = &lt;0xe3&gt;;
				hw-thd-sta = &lt;0xa2&gt;;
			};

qcom,actuator@0 {
				rgltr-max-voltage = &lt;0x2ab980&gt;;
				cell-index = &lt;0x00&gt;;
				cci-device = &lt;0x00&gt;;
				rgltr-load-current = &lt;0x35b60&gt;;
				rgltr-cntrl-support;
				cam_vaf-supply = &lt;0x40b&gt;;
				cci-master = &lt;0x00&gt;;
				compatible = &quot;qcom,actuator&quot;;
				rgltr-min-voltage = &lt;0x2ab980&gt;;
				reg = &lt;0x00&gt;;
				regulator-names = &quot;cam_vaf&quot;;
				phandle = &lt;0x568&gt;;
			};

qcom,cam-res-mgr {
				compatible = &quot;qcom,cam-res-mgr&quot;;
				status = &quot;ok&quot;;
			};

qcom,eeprom@3 {
				rgltr-max-voltage = &lt;0x1b7740&gt;;
				cell-index = &lt;0x03&gt;;
				cci-device = &lt;0x00&gt;;
				rgltr-load-current = &lt;0x2bf20&gt;;
				cam_vio-supply = &lt;0x562&gt;;
				rgltr-cntrl-support;
				cci-master = &lt;0x01&gt;;
				compatible = &quot;qcom,eeprom&quot;;
				rgltr-min-voltage = &lt;0x1b7740&gt;;
				status = &quot;ok&quot;;
				reg = &lt;0x03&gt;;
				regulator-names = &quot;cam_vio&quot;;
				phandle = &lt;0x571&gt;;
			};

qcom,cam-sensor@2 {
				rgltr-max-voltage = &lt;0x1b7740 0x2ab980 0x00&gt;;
				pinctrl-names = &quot;cam_default\0cam_suspend&quot;;
				eeprom-src = &lt;0x56a&gt;;
				pinctrl-0 = &lt;0x56c 0x56d&gt;;
				clock-names = &quot;cam_clk&quot;;
				cell-index = &lt;0x02&gt;;
				gpio-req-tbl-num = &lt;0x00 0x01&gt;;
				sensor-position-yaw = &lt;0x00&gt;;
				cci-device = &lt;0x00&gt;;
				clocks = &lt;0x29 0x50&gt;;
				rgltr-load-current = &lt;0x2bf20 0x1d4c0 0x00&gt;;
				cam_vio-supply = &lt;0x562&gt;;
				rgltr-cntrl-support;
				cam_vana-supply = &lt;0x56b&gt;;
				gpio-req-tbl-label = &quot;CAMIF_MCLK0\0CAMF_RESET&quot;;
				gpio-reset = &lt;0x01&gt;;
				csiphy-sd-index = &lt;0x01&gt;;
				clock-cntl-level = &quot;turbo&quot;;
				sensor-mode = &lt;0x00&gt;;
				cci-master = &lt;0x01&gt;;
				gpio-no-mux = &lt;0x00&gt;;
				compatible = &quot;qcom,cam-sensor&quot;;
				rgltr-min-voltage = &lt;0x1b7740 0x2ab980 0x00&gt;;
				sensor-position-roll = &lt;0x10e&gt;;
				pinctrl-1 = &lt;0x56e 0x56f&gt;;
				status = &quot;ok&quot;;
				reg = &lt;0x02&gt;;
				regulator-names = &quot;cam_vio\0cam_vana\0cam_clk&quot;;
				sensor-position-pitch = &lt;0x00&gt;;
				cam_clk-supply = &lt;0x1ae&gt;;
				clock-rates = &lt;0x124f800&gt;;
				gpio-req-tbl-flags = &lt;0x01 0x00&gt;;
				gpios = &lt;0x174 0x0d 0x00 0x174 0x17 0x00&gt;;
			};

qcom,i2c_fast_plus_mode {
				hw-tsu-sto = &lt;0x11&gt;;
				cci-clk-src = &lt;0x23c3460&gt;;
				hw-tsp = &lt;0x03&gt;;
				hw-trdhld = &lt;0x03&gt;;
				hw-thigh = &lt;0x12&gt;;
				hw-tlow = &lt;0x14&gt;;
				status = &quot;ok&quot;;
				hw-thd-dat = &lt;0x0e&gt;;
				hw-tsu-sta = &lt;0x12&gt;;
				hw-scl-stretch-en = &lt;0x00&gt;;
				phandle = &lt;0x5b0&gt;;
				hw-tbuf = &lt;0x18&gt;;
				hw-thd-sta = &lt;0x0f&gt;;
			};

qcom,cam-sensor@0 {
				cam_v_custom1-supply = &lt;0x406&gt;;
				rgltr-max-voltage = &lt;0x1b7740 0x100590 0x10c8e0 0x00&gt;;
				pinctrl-names = &quot;cam_default\0cam_suspend&quot;;
				eeprom-src = &lt;0x569&gt;;
				pinctrl-0 = &lt;0x563 0x564&gt;;
				clock-names = &quot;cam_clk&quot;;
				cell-index = &lt;0x00&gt;;
				gpio-req-tbl-num = &lt;0x00 0x01&gt;;
				sensor-position-yaw = &lt;0xb4&gt;;
				cci-device = &lt;0x00&gt;;
				clocks = &lt;0x29 0x54&gt;;
				rgltr-load-current = &lt;0x2bf20 0x1d4c0 0x1d4c0 0x00&gt;;
				actuator-src = &lt;0x568&gt;;
				cam_vio-supply = &lt;0x562&gt;;
				rgltr-cntrl-support;
				gpio-req-tbl-label = &quot;CAMIF_MCLK0\0CAMW_RESET&quot;;
				gpio-reset = &lt;0x01&gt;;
				csiphy-sd-index = &lt;0x00&gt;;
				clock-cntl-level = &quot;turbo&quot;;
				cam_vdig-supply = &lt;0x406&gt;;
				sensor-mode = &lt;0x00&gt;;
				cci-master = &lt;0x00&gt;;
				gpio-no-mux = &lt;0x00&gt;;
				compatible = &quot;qcom,cam-sensor&quot;;
				rgltr-min-voltage = &lt;0x1b7740 0x100590 0x10c8e0 0x00&gt;;
				led-flash-src = &lt;0x567&gt;;
				sensor-position-roll = &lt;0x5a&gt;;
				pinctrl-1 = &lt;0x565 0x566&gt;;
				status = &quot;ok&quot;;
				reg = &lt;0x00&gt;;
				regulator-names = &quot;cam_vio\0cam_vdig\0cam_v_custom1\0cam_clk&quot;;
				sensor-position-pitch = &lt;0x00&gt;;
				cam_clk-supply = &lt;0x1ae&gt;;
				clock-rates = &lt;0x124f800&gt;;
				gpio-req-tbl-flags = &lt;0x01 0x00&gt;;
				gpios = &lt;0x174 0x0f 0x00 0x174 0x1a 0x00&gt;;
			};

qcom,actuator@1 {
				rgltr-max-voltage = &lt;0x2ab980&gt;;
				cell-index = &lt;0x01&gt;;
				cci-device = &lt;0x00&gt;;
				rgltr-load-current = &lt;0x35b60&gt;;
				rgltr-cntrl-support;
				cam_vaf-supply = &lt;0x40b&gt;;
				cci-master = &lt;0x01&gt;;
				compatible = &quot;qcom,actuator&quot;;
				rgltr-min-voltage = &lt;0x2ab980&gt;;
				reg = &lt;0x01&gt;;
				regulator-names = &quot;cam_vaf&quot;;
				phandle = &lt;0x572&gt;;
			};

qcom,i2c_fast_mode {
				hw-tsu-sto = &lt;0x28&gt;;
				cci-clk-src = &lt;0x23c3460&gt;;
				hw-tsp = &lt;0x03&gt;;
				hw-trdhld = &lt;0x06&gt;;
				hw-thigh = &lt;0x26&gt;;
				hw-tlow = &lt;0x38&gt;;
				status = &quot;ok&quot;;
				hw-thd-dat = &lt;0x16&gt;;
				hw-tsu-sta = &lt;0x28&gt;;
				hw-scl-stretch-en = &lt;0x00&gt;;
				phandle = &lt;0x37e&gt;;
				hw-tbuf = &lt;0x3e&gt;;
				hw-thd-sta = &lt;0x23&gt;;
			};
		};

qcom,cam-cdm-intf {
			cdm-client-names = &quot;vfe\0jpegdma\0jpegenc\0fd\0lrmecdm&quot;;
			num-hw-cdm = &lt;0x01&gt;;
			cell-index = &lt;0x00&gt;;
			label = &quot;cam-cdm-intf&quot;;
			compatible = &quot;qcom,cam-cdm-intf&quot;;
			status = &quot;ok&quot;;
		};

qcom,rpmh-master-stats@b221200 {
			compatible = &quot;qcom,rpmh-master-stats-v1&quot;;
			reg = &lt;0xb221200 0x60&gt;;
		};

qcom,cpucc@18321000 {
			#address-cells = &lt;0x01&gt;;
			reg-names = &quot;osm_l3_base\0osm_pwrcl_base\0osm_perfcl_base&quot;;
			#size-cells = &lt;0x01&gt;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,clk-cpu-osm-sdmmagpie&quot;;
			reg = &lt;0x18321000 0x1400 0x18323000 0x1400 0x18325800 0x1400&gt;;
			phandle = &lt;0xc0&gt;;
			l3-devs = &lt;0x24 0x25 0x26&gt;;

qcom,limits-dcvs@18350800 {
				qcom,affinity = &lt;0x01&gt;;
				interrupts = &lt;0x00 0x21 0x04&gt;;
				#thermal-sensor-cells = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-hw-limits&quot;;
				reg = &lt;0x18350800 0x1000 0x18325800 0x1000&gt;;
				phandle = &lt;0x0f&gt;;
			};

qcom,limits-dcvs@18358800 {
				qcom,affinity = &lt;0x00&gt;;
				interrupts = &lt;0x00 0x20 0x04&gt;;
				#thermal-sensor-cells = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-hw-limits&quot;;
				reg = &lt;0x18358800 0x1000 0x18323000 0x1000&gt;;
				phandle = &lt;0x05&gt;;
			};
		};

qcom,gmu@506a000 {
			vddcx-supply = &lt;0x1c5&gt;;
			clock-names = &quot;gmu_clk\0cxo_clk\0axi_clk\0memnoc_clk&quot;;
			reg-names = &quot;kgsl_gmu_reg\0kgsl_gmu_pdc_cfg\0kgsl_gmu_pdc_seq&quot;;
			qcom,msm-bus,name = &quot;cnoc&quot;;
			interrupts = &lt;0x00 0x130 0x04 0x00 0x131 0x04&gt;;
			clocks = &lt;0x2b 0x0b 0x2b 0x0e 0x27 0x1b 0x27 0x2b&gt;;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x02&gt;;
			label = &quot;kgsl-gmu&quot;;
			vdd-supply = &lt;0x24e&gt;;
			compatible = &quot;qcom,gpu-gmu&quot;;
			interrupt-names = &quot;kgsl_hfi_irq\0kgsl_gmu_irq&quot;;
			reg = &lt;0x506a000 0x31000 0xb290000 0x10000 0xb490000 0x10000&gt;;
			regulator-names = &quot;vddcx\0vdd&quot;;
			phandle = &lt;0x22&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x1a 0x2734 0x00 0x00 0x1a 0x2734 0x00 0x64&gt;;

qcom,gmu-pwrlevels {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;
				compatible = &quot;qcom,gmu-pwrlevels&quot;;

qcom,gmu-pwrlevel@0 {
					reg = &lt;0x00&gt;;
					qcom,gmu-freq = &lt;0x00&gt;;
				};

qcom,gmu-pwrlevel@1 {
					reg = &lt;0x01&gt;;
					qcom,gmu-freq = &lt;0xbebc200&gt;;
				};
			};

gmu_kernel {
				iommus = &lt;0x1cd 0x05&gt;;
				compatible = &quot;qcom,smmu-gmu-kernel-cb&quot;;
				phandle = &lt;0x4d4&gt;;
			};

gmu_user {
				iommus = &lt;0x1cd 0x04&gt;;
				compatible = &quot;qcom,smmu-gmu-user-cb&quot;;
				phandle = &lt;0x4d3&gt;;
			};
		};

qcom,mdss_dsi_ctrl1@ae96000 {
			clock-names = &quot;byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk&quot;;
			reg-names = &quot;dsi_ctrl\0disp_cc_base&quot;;
			cell-index = &lt;0x01&gt;;
			interrupts = &lt;0x05 0x00&gt;;
			clocks = &lt;0x2a 0x07 0x2a 0x08 0x2a 0x0a 0x2a 0x20 0x2a 0x21 0x2a 0x18&gt;;
			interrupt-parent = &lt;0x1a6&gt;;
			label = &quot;dsi-ctrl-1&quot;;
			vdda-1p2-supply = &lt;0x1a8&gt;;
			compatible = &quot;qcom,dsi-ctrl-hw-v2.3&quot;;
			reg = &lt;0xae96000 0x400 0xaf08000 0x04&gt;;
			phandle = &lt;0x373&gt;;

qcom,ctrl-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

qcom,ctrl-supply-entry@0 {
					qcom,supply-disable-load = &lt;0x00&gt;;
					qcom,supply-enable-load = &lt;0x5528&gt;;
					qcom,supply-name = &quot;vdda-1p2&quot;;
					qcom,supply-max-voltage = &lt;0x12cc80&gt;;
					reg = &lt;0x00&gt;;
					qcom,supply-min-voltage = &lt;0x1174c0&gt;;
				};
			};

qcom,core-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

qcom,core-supply-entry@0 {
					qcom,supply-disable-load = &lt;0x00&gt;;
					qcom,supply-enable-load = &lt;0x00&gt;;
					qcom,supply-name = &quot;refgen&quot;;
					qcom,supply-max-voltage = &lt;0x00&gt;;
					reg = &lt;0x00&gt;;
					qcom,supply-min-voltage = &lt;0x00&gt;;
				};
			};
		};

hwevent@0x014066f0 {
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;ddr-ch0-cfg\0ddr-ch23-cfg\0ddr-ch0-ctrl\0ddr-ch23-ctrl&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-hwevent&quot;;
			compatible = &quot;qcom,coresight-hwevent&quot;;
			reg = &lt;0x14066f0 0x04 0x14166f0 0x04 0x1406038 0x04 0x1416038 0x04&gt;;
			phandle = &lt;0x45d&gt;;
			coresight-csr = &lt;0x1d6&gt;;
		};

qcom,dsi-display@29 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x53d&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_g7b_37_02_0b_video_display&quot;;
			phandle = &lt;0x555&gt;;
		};

qcom,cpu6-cpu-llcc-lat {
			qcom,src-dst-ports = &lt;0x01 0x302&gt;;
			governor = &quot;performance&quot;;
			compatible = &quot;qcom,devbw&quot;;
			phandle = &lt;0xc2&gt;;
			qcom,active-only;
			operating-points-v2 = &lt;0xbc&gt;;
		};

qcom,cam_smmu {
			compatible = &quot;qcom,msm-cam-smmu&quot;;
			status = &quot;ok&quot;;
			phandle = &lt;0x386&gt;;

msm_cam_smmu_ife {
				iommus = &lt;0x30 0x900 0x460 0x30 0xd00 0x460 0x30 0x880 0x460 0x30 0xc80 0x460 0x30 0x820 0x440 0x30 0xc20 0x440 0x30 0x920 0x460 0x30 0xd20 0x460 0x30 0x8a0 0x460 0x30 0xca0 0x460 0x30 0x940 0x460 0x30 0xd40 0x460 0x30 0x8c0 0x460 0x30 0xcc0 0x460&gt;;
				label = &quot;ife&quot;;
				compatible = &quot;qcom,msm-cam-smmu-cb&quot;;

iova-mem-map {
					phandle = &lt;0x387&gt;;

iova-mem-region-io {
						iova-region-len = &lt;0xd8c00000&gt;;
						iova-region-name = &quot;io&quot;;
						status = &quot;ok&quot;;
						iova-region-id = &lt;0x03&gt;;
						iova-region-start = &lt;0x7400000&gt;;
					};
				};
			};

msm_cam_smmu_lrme {
				iommus = &lt;0x30 0x11c0 0x00 0x30 0x1240 0x00&gt;;
				label = &quot;lrme&quot;;
				compatible = &quot;qcom,msm-cam-smmu-cb&quot;;

iova-mem-map {
					phandle = &lt;0x38c&gt;;

iova-mem-region-io {
						iova-region-len = &lt;0xd2800000&gt;;
						iova-region-name = &quot;io&quot;;
						status = &quot;ok&quot;;
						iova-region-id = &lt;0x03&gt;;
						iova-region-start = &lt;0xd800000&gt;;
					};

iova-mem-region-shared {
						iova-region-len = &lt;0x6400000&gt;;
						iova-region-name = &quot;shared&quot;;
						status = &quot;ok&quot;;
						iova-region-id = &lt;0x01&gt;;
						iova-region-start = &lt;0x7400000&gt;;
					};
				};
			};

msm_cam_smmu_cpas_cdm {
				iommus = &lt;0x30 0x1000 0x00&gt;;
				label = &quot;cpas-cdm0&quot;;
				compatible = &quot;qcom,msm-cam-smmu-cb&quot;;

iova-mem-map {
					phandle = &lt;0x38a&gt;;

msm_cam_smmu_fd {
				iommus = &lt;0x30 0x12c0 0x20 0x30 0x12e0 0x20&gt;;
				label = &quot;fd&quot;;
				compatible = &quot;qcom,msm-cam-smmu-cb&quot;;

iova-mem-map {
					phandle = &lt;0x38b&gt;;

msm_cam_smmu_icp {
				iommus = &lt;0x30 0x1180 0x00 0x30 0x11e0 0x00 0x30 0x11a0 0x00 0x30 0x1200 0x00 0x30 0x1260 0x00 0x30 0x1220 0x00 0x30 0x1042 0x00 0x30 0x1300 0x60 0x30 0x1320 0x60&gt;;
				label = &quot;icp&quot;;
				compatible = &quot;qcom,msm-cam-smmu-cb&quot;;

iova-mem-map {
					phandle = &lt;0x389&gt;;

iova-mem-qdss-region {
						iova-region-len = &lt;0x100000&gt;;
						qdss-phy-addr = &lt;0x16790000&gt;;
						iova-region-name = &quot;qdss&quot;;
						status = &quot;ok&quot;;
						iova-region-id = &lt;0x05&gt;;
						iova-region-start = &lt;0x10b00000&gt;;
					};

iova-mem-region-secondary-heap {
						iova-region-len = &lt;0x100000&gt;;
						iova-region-name = &quot;secheap&quot;;
						status = &quot;ok&quot;;
						iova-region-id = &lt;0x04&gt;;
						iova-region-start = &lt;0x10a00000&gt;;
					};

iova-mem-region-firmware {
						iova-region-len = &lt;0x500000&gt;;
						iova-region-name = &quot;firmware&quot;;
						status = &quot;ok&quot;;
						iova-region-id = &lt;0x00&gt;;
						iova-region-start = &lt;0x00&gt;;
					};

iova-mem-region-io {
						iova-region-len = &lt;0xa9c00000&gt;;
						iova-region-name = &quot;io&quot;;
						status = &quot;ok&quot;;
						iova-region-id = &lt;0x03&gt;;
						iova-region-start = &lt;0x10c00000&gt;;
					};

iova-mem-region-shared {
						iova-region-len = &lt;0x9600000&gt;;
						iova-region-name = &quot;shared&quot;;
						status = &quot;ok&quot;;
						iova-region-id = &lt;0x01&gt;;
						iova-region-start = &lt;0x7400000&gt;;
					};
				};
			};

msm_cam_smmu_jpeg {
				iommus = &lt;0x30 0x1280 0x20 0x30 0x12a0 0x20&gt;;
				label = &quot;jpeg&quot;;
				compatible = &quot;qcom,msm-cam-smmu-cb&quot;;

iova-mem-map {
					phandle = &lt;0x388&gt;;

msm_cam_smmu_secure {
				qcom,secure-cb;
				label = &quot;cam-secure&quot;;
				compatible = &quot;qcom,msm-cam-smmu-cb&quot;;
			};

msm_cam_icp_fw {
				memory-region = &lt;0x1b6&gt;;
				label = &quot;icp&quot;;
				compatible = &quot;qcom,msm-cam-smmu-fw-dev&quot;;
			};
		};

syscon@0x5091008 {
			compatible = &quot;syscon&quot;;
			reg = &lt;0x5091008 0x04&gt;;
			phandle = &lt;0xce&gt;;
		};

qcom,smp2p_interrupt_rdbg_5_out {
			qcom,smem-state-names = &quot;rdbg-smp2p-out&quot;;
			compatible = &quot;qcom,smp2p-interrupt-rdbg-5-out&quot;;
			qcom,smem-states = &lt;0x1be 0x00&gt;;
		};

funnel@0x6041000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-in0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6041000 0x1000&gt;;
			phandle = &lt;0x422&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1de&gt;;
						phandle = &lt;0x1db&gt;;
					};
				};

port@3 {
					reg = &lt;0x06&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1e1&gt;;
						phandle = &lt;0x226&gt;;
					};
				};

port@1 {
					reg = &lt;0x04&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1df&gt;;
						phandle = &lt;0x22c&gt;;
					};
				};

port@4 {
					reg = &lt;0x07&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1e2&gt;;
						phandle = &lt;0x225&gt;;
					};
				};

port@2 {
					reg = &lt;0x04&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1e0&gt;;
						phandle = &lt;0x1e3&gt;;
					};
				};
			};
		};

qcom,gdsc@16b004 {
			qcom,poll-cfg-gdscr;
			regulator-name = &quot;pcie_0_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x16b004 0x04&gt;;
			phandle = &lt;0x321&gt;;
		};

qcom,dsi-display@7 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x529&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_sim_dsc_375_cmd_display&quot;;
			phandle = &lt;0x546&gt;;
		};

sdcc1ice@7C8000 {
			clock-names = &quot;ice_core_clk_src\0ice_core_clk\0bus_clk\0iface_clk&quot;;
			qcom,bus-vector-names = &quot;MIN\0MAX&quot;;
			qcom,msm-bus,name = &quot;sdcc_ice_noc&quot;;
			qcom,instance-type = &quot;sdcc&quot;;
			clocks = &lt;0x27 0x6f 0x27 0x6e 0x27 0x6b 0x27 0x6c&gt;;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x02&gt;;
			qcom,op-freq-hz = &lt;0x11e1a300 0x00 0x00 0x00&gt;;
			compatible = &quot;qcom,ice&quot;;
			reg = &lt;0x7c8000 0x8000&gt;;
			phandle = &lt;0x2d7&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x01 0x2f5 0x00 0x00 0x01 0x2f5 0x3e8 0x00&gt;;
			qcom,enable-ice-clk;
		};

cx_ipeak@01fed000 {
			compatible = &quot;qcom,cx-ipeak-v2&quot;;
			reg = &lt;0x1fed000 0x8008&gt;;
			phandle = &lt;0x1a3&gt;;
		};

qcom,csiphy@ace0000 {
			clock-names = &quot;cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk&quot;;
			reg-names = &quot;csiphy&quot;;
			reg-cam-base = &lt;0xe0000&gt;;
			csi-vdd-voltage = &lt;0x124f80&gt;;
			cell-index = &lt;0x00&gt;;
			interrupts = &lt;0x00 0x1dd 0x00&gt;;
			clocks = &lt;0x29 0x1b 0x29 0x24 0x29 0x1d 0x29 0x1c&gt;;
			gdscr-supply = &lt;0x1ae&gt;;
			clock-cntl-level = &quot;svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,csiphy-v1.2\0qcom,csiphy&quot;;
			src-clock-name = &quot;csi0phytimer_clk_src&quot;;
			mipi-csi-vdd-supply = &lt;0x1a8&gt;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;csiphy&quot;;
			reg = &lt;0xace0000 0x2000&gt;;
			regulator-names = &quot;gdscr\0refgen&quot;;
			phandle = &lt;0x378&gt;;
			refgen-supply = &lt;0x1af&gt;;
			clock-rates = &lt;0x16e36000 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x11e1a300 0x00&gt;;
		};

qcom,dsi-display@19 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x531&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_rm69299_visionox_amoled_vid_display&quot;;
			phandle = &lt;0x54f&gt;;
		};

qcom,gdsc@ab008b4 {
			clock-names = &quot;ahb_clk&quot;;
			qcom,support-hw-trigger;
			clocks = &lt;0x27 0x9b&gt;;
			regulator-name = &quot;mvs1_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xab008b4 0x04&gt;;
			phandle = &lt;0x1a2&gt;;
		};

tpdm@6b03000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-swao-1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b03000 0x1000&gt;;
			phandle = &lt;0x430&gt;;
			qcom,msr-fix-req;

port {

endpoint {
					remote-endpoint = &lt;0x1ff&gt;;
					phandle = &lt;0x1fd&gt;;
				};
			};
		};

qcom,msm-dai-tdm-sec-rx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9010&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9110&gt;;
			phandle = &lt;0x4bc&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-sec-rx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9010&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x288&gt;;
			};
		};

qcom,qupv3_0_geni_se@0x8c0000 {
			qcom,iommu-s1-bypass;
			qcom,bus-mas-id = &lt;0x97&gt;;
			qcom,bus-slv-id = &lt;0x200&gt;;
			compatible = &quot;qcom,qupv3-geni-se&quot;;
			reg = &lt;0x8c0000 0x2000&gt;;
			phandle = &lt;0x168&gt;;

qcom,iommu_qupv3_0_geni_se_cb {
				iommus = &lt;0x30 0x203 0x00&gt;;
				compatible = &quot;qcom,qupv3-geni-se-cb&quot;;
				phandle = &lt;0x34c&gt;;
			};
		};

rpmh-regulator-ldoc8 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoc8&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150l-l8 {
				regulator-max-microvolt = &lt;0x1cfde0&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x1b7740&gt;;
				regulator-min-microvolt = &lt;0x1b7740&gt;;
				regulator-name = &quot;pm6150l_l8&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x412&gt;;
			};
		};

qcom,cc-debug {
			qcom,gpucc = &lt;0x2b&gt;;
			clock-names = &quot;xo_clk_src&quot;;
			clocks = &lt;0x2f 0x00&gt;;
			#clock-cells = &lt;0x01&gt;;
			qcom,cc-count = &lt;0x08&gt;;
			qcom,gcc = &lt;0x27&gt;;
			qcom,dispcc = &lt;0x2a&gt;;
			compatible = &quot;qcom,debugcc-sdmmagpie&quot;;
			qcom,mccc = &lt;0x2e&gt;;
			phandle = &lt;0x2b2&gt;;
			qcom,videocc = &lt;0x28&gt;;
			qcom,npucc = &lt;0x2c&gt;;
			qcom,cpucc = &lt;0x2d&gt;;
			qcom,camcc = &lt;0x29&gt;;
		};

qcom,gdsc@509106c {
			hw-ctrl-addr = &lt;0xcc&gt;;
			qcom,no-status-check-on-disable;
			qcom,gds-timeout = &lt;0x1f4&gt;;
			parent-supply = &lt;0x1d&gt;;
			qcom,clk-dis-wait-val = &lt;0x08&gt;;
			regulator-name = &quot;gpu_cx_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x509106c 0x04&gt;;
			phandle = &lt;0x1c5&gt;;
		};

qcom,icnss@18800000 {
			iommus = &lt;0x30 0x240 0x01&gt;;
			qcom,smmu-s1-bypass;
			vdd-1.8-xo-supply = &lt;0x34&gt;;
			qcom,wlan-msa-memory = &lt;0x100000&gt;;
			reg-names = &quot;membase\0smmu_iova_base\0smmu_iova_ipa&quot;;
			qcom,vdd-cx-mx-config = &lt;0x9c400 0x9c400&gt;;
			interrupts = &lt;0x00 0x19e 0x00 0x00 0x19f 0x00 0x00 0x1a0 0x00 0x00 0x1a1 0x00 0x00 0x1a2 0x00 0x00 0x1a3 0x00 0x00 0x1a4 0x00 0x00 0x1a5 0x00 0x00 0x1a6 0x00 0x00 0x1a7 0x00 0x00 0x1a8 0x00 0x00 0x1a9 0x00&gt;;
			vdd-3.3-ch0-supply = &lt;0x33&gt;;
			compatible = &quot;qcom,icnss&quot;;
			qcom,wlan-msa-fixed-region = &lt;0xb7&gt;;
			reg = &lt;0x18800000 0x800000 0xa0000000 0x10000000 0xb0000000 0x10000&gt;;
			phandle = &lt;0x30e&gt;;
			vdd-1.3-rfa-supply = &lt;0x32&gt;;
			vdd-cx-mx-supply = &lt;0xb8&gt;;

qcom,smp2p_map_wlan_1_in {
				interrupts-extended = &lt;0xb9 0x00 0x00 0xb9 0x01 0x00&gt;;
				interrupt-names = &quot;qcom,smp2p-force-fatal-error\0qcom,smp2p-early-crash-ind&quot;;
			};
		};

ipa_smmu_uc {
			iommus = &lt;0x30 0x522 0x00&gt;;
			qcom,smmu-s1-bypass;
			qcom,iova-mapping = &lt;0x40400000 0x1fc00000&gt;;
			compatible = &quot;qcom,ipa-smmu-uc-cb&quot;;
			phandle = &lt;0x31e&gt;;
		};

qcom,chd_gold {
			qcom,config-arr = &lt;0x18060060 0x18070060&gt;;
			label = &quot;gold&quot;;
			qcom,threshold-arr = &lt;0x18060058 0x18070058&gt;;
			compatible = &quot;qcom,core-hang-detect&quot;;
		};

i2c@0xa84000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x186&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			interrupts = &lt;0x00 0x162 0x00&gt;;
			clocks = &lt;0x27 0x59 0x27 0x69 0x27 0x6a&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,i2c-geni&quot;;
			pinctrl-1 = &lt;0x187&gt;;
			status = &quot;ok&quot;;
			reg = &lt;0xa84000 0x4000&gt;;
			phandle = &lt;0x35b&gt;;
			dmas = &lt;0x183 0x00 0x01 0x03 0x40 0x00 0x183 0x01 0x01 0x03 0x40 0x00&gt;;

gt9896@5d {
				pinctrl-names = &quot;pmx_ts_active\0pmx_ts_suspend&quot;;
				goodix,power-off-delay-us = &lt;0x1388&gt;;
				goodix,input-max-y = &lt;0x95f&gt;;
				goodix,vdd-gpio = &lt;0x174 0x5a 0x00&gt;;
				goodix,reset-gpio = &lt;0x174 0x08 0x00&gt;;
				pinctrl-0 = &lt;0x58f&gt;;
				tpd-filter-custom-speed = &lt;0x00 0x00 0x00&gt;;
				goodix,firmware-version = &quot;6885b1&quot;;
				tpd-filter-custom-prameters = &lt;0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00&gt;;
				goodix,panel-max-x = &lt;0x437&gt;;
				interrupts = &lt;0x09 0x00&gt;;
				goodix,touch-game-param-config3 = &lt;0x04 0x04 0x03 0x01&gt;;
				interrupt-parent = &lt;0x174&gt;;
				goodix,touch-game-param-config1 = &lt;0x03 0x03 0x01 0x03&gt;;
				vtouch-supply = &lt;0x414&gt;;
				goodix,avdd-name = &quot;vtouch&quot;;
				compatible = &quot;goodix,gt9896&quot;;
				tpd-filter-enable = &lt;0x01&gt;;
				pinctrl-1 = &lt;0x590 0x591&gt;;
				status = &quot;ok&quot;;
				goodix,panel-max-p = &lt;0x100&gt;;
				goodix,irq-flags = &lt;0x02&gt;;
				goodix,input-max-x = &lt;0x437&gt;;
				goodix,power-on-delay-us = &lt;0x64&gt;;
				goodix,panel-max-y = &lt;0x95f&gt;;
				reg = &lt;0x5d&gt;;
				goodix,panel-max-id = &lt;0x0a&gt;;
				tpd-filter-pixel-density = &lt;0xa1&gt;;
				goodix,panel-max-w = &lt;0x100&gt;;
				goodix,touch-game-param-config2 = &lt;0x02 0x04 0x02 0x03&gt;;
				goodix,config-version = &quot;6885v9c&quot;;
				goodix,irq-gpio = &lt;0x174 0x09 0x00&gt;;

sensor0 {
					normal-cfg;
				};
			};
		};

rpmh-regulator-smpf1 {
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;smpf1&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm8009-s1 {
				regulator-max-microvolt = &lt;0x14c080&gt;;
				qcom,init-voltage = &lt;0x103c40&gt;;
				regulator-min-microvolt = &lt;0x103c40&gt;;
				regulator-name = &quot;pm8009_s1&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x400&gt;;
			};
		};

qcom,cpu6-cpu-llcc-latmon {
			qcom,cachemiss-ev = &lt;0x2a&gt;;
			qcom,core-dev-table = &lt;0xc4c70 0x11e1 0x10b170 0x1bc6 0x1433e0 0x23c3 0x1a1300 0x300a 0x253500 0x379c&gt;;
			qcom,cpulist = &lt;0x17 0x18&gt;;
			compatible = &quot;qcom,arm-memlat-mon&quot;;
			phandle = &lt;0x316&gt;;
			qcom,target-dev = &lt;0xc2&gt;;
		};

rpmh-regulator-ldof6 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldof6&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm8009-l6 {
				regulator-max-microvolt = &lt;0x2c4fc0&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x292340&gt;;
				regulator-min-microvolt = &lt;0x292340&gt;;
				regulator-name = &quot;pm8009_l6&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x41b&gt;;
			};
		};

qcom,dispcc@af00000 {
			#reset-cells = &lt;0x01&gt;;
			reg-names = &quot;cc_base&quot;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,dispcc-sdmmagpie\0syscon&quot;;
			reg = &lt;0xaf00000 0x20000&gt;;
			phandle = &lt;0x2a&gt;;
			vdd_cx-supply = &lt;0x1d&gt;;
		};

qcom,qup_uart@0x890000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			pinctrl-0 = &lt;0x175 0x176 0x177&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			clocks = &lt;0x27 0x4c 0x27 0x67 0x27 0x68&gt;;
			qcom,wrapper-core = &lt;0x168&gt;;
			interrupts-extended = &lt;0x01 0x00 0x25d 0x00 0x174 0x38 0x00&gt;;
			compatible = &quot;qcom,msm-geni-serial-hs&quot;;
			pinctrl-1 = &lt;0x175 0x176 0x177&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0x890000 0x4000&gt;;
			phandle = &lt;0x353&gt;;
			qcom,wakeup-byte = &lt;0xfd&gt;;
		};

qcom,venus@aae0000 {
			qcom,ahb-freq = &lt;0xbebc200&gt;;
			clock-names = &quot;xo\0core\0ahb&quot;;
			qcom,msm-bus,name = &quot;pil-venus&quot;;
			qcom,proxy-timeout-ms = &lt;0x64&gt;;
			memory-region = &lt;0xb5&gt;;
			clocks = &lt;0x28 0x0a 0x28 0x07 0x28 0x01&gt;;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x02&gt;;
			qcom,core-freq = &lt;0xbebc200&gt;;
			qcom,pas-id = &lt;0x09&gt;;
			vdd-supply = &lt;0xb4&gt;;
			compatible = &quot;qcom,pil-tz-generic&quot;;
			reg = &lt;0xaae0000 0x4000&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x3f 0x200 0x00 0x00 0x3f 0x200 0x00 0x4a380&gt;;
			qcom,proxy-clock-names = &quot;xo\0core\0ahb&quot;;
			qcom,proxy-reg-names = &quot;vdd&quot;;
			qcom,firmware-name = &quot;venus&quot;;
		};

qcom,vidc1 {
			qcom,allowed-clock-rates = &lt;0xbebc200&gt;;
			iris-ctl-supply = &lt;0xb4&gt;;
			sku-index = &lt;0x01&gt;;
			clock-names = &quot;video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk&quot;;
			vcodec-supply = &lt;0x1a1&gt;;
			interrupts = &lt;0x00 0xae 0x04&gt;;
			cvp-supply = &lt;0x1a2&gt;;
			clocks = &lt;0x28 0x08 0x28 0x03 0x28 0x05 0x28 0x07 0x28 0x04 0x28 0x06 0x28 0x09&gt;;
			compatible = &quot;qcom,msm-vidc\0qcom,sdmmagpie-vidc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xaa00000 0x200000&gt;;
			phandle = &lt;0x369&gt;;
			qcom,proxy-clock-names = &quot;video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk&quot;;
			qcom,clock-configs = &lt;0x00 0x00 0x00 0x01 0x01 0x01 0x00&gt;;

venus_bus_ddr {
				qcom,bus-governor = &quot;msm-vidc-ddr&quot;;
				label = &quot;venus-ddr&quot;;
				compatible = &quot;qcom,msm-vidc,bus&quot;;
				qcom,bus-slave = &lt;0x200&gt;;
				qcom,bus-master = &lt;0x3f&gt;;
				qcom,bus-range-kbps = &lt;0x3e8 0x63af88&gt;;
			};

qcom,msm-vidc,mem_cdsp {
				memory-region = &lt;0x1a4&gt;;
				compatible = &quot;qcom,msm-vidc,mem-cdsp&quot;;
			};

non_secure_cb {
				iommus = &lt;0x30 0x1080 0x60&gt;;
				virtual-addr-pool = &lt;0x25800000 0xba800000&gt;;
				label = &quot;venus_ns&quot;;
				compatible = &quot;qcom,msm-vidc,context-bank&quot;;
				buffer-types = &lt;0xfff&gt;;
			};

secure_non_pixel_cb {
				iommus = &lt;0x30 0x1084 0x60&gt;;
				qcom,secure-context-bank;
				virtual-addr-pool = &lt;0x1000000 0x24800000&gt;;
				label = &quot;venus_sec_non_pixel&quot;;
				compatible = &quot;qcom,msm-vidc,context-bank&quot;;
				buffer-types = &lt;0x480&gt;;
			};

arm9_bus_ddr {
				qcom,bus-governor = &quot;performance&quot;;
				label = &quot;venus-arm9-ddr&quot;;
				compatible = &quot;qcom,msm-vidc,bus&quot;;
				qcom,bus-slave = &lt;0x200&gt;;
				qcom,bus-master = &lt;0x3f&gt;;
				qcom,bus-range-kbps = &lt;0x3e8 0x3e8&gt;;
			};

bus_cnoc {
				qcom,bus-governor = &quot;performance&quot;;
				label = &quot;cnoc&quot;;
				compatible = &quot;qcom,msm-vidc,bus&quot;;
				qcom,bus-slave = &lt;0x254&gt;;
				qcom,bus-master = &lt;0x01&gt;;
				qcom,bus-range-kbps = &lt;0x3e8 0x3e8&gt;;
			};

secure_bitstream_cb {
				iommus = &lt;0x30 0x1081 0x04&gt;;
				qcom,secure-context-bank;
				virtual-addr-pool = &lt;0x500000 0xdfb00000&gt;;
				label = &quot;venus_sec_bitstream&quot;;
				compatible = &quot;qcom,msm-vidc,context-bank&quot;;
				buffer-types = &lt;0x241&gt;;
			};

secure_pixel_cb {
				iommus = &lt;0x30 0x1083 0x20&gt;;
				qcom,secure-context-bank;
				virtual-addr-pool = &lt;0x500000 0xdfb00000&gt;;
				label = &quot;venus_sec_pixel&quot;;
				compatible = &quot;qcom,msm-vidc,context-bank&quot;;
				buffer-types = &lt;0x106&gt;;
			};
		};

qcom,ipa_fws {
			qcom,pil-force-shutdown;
			memory-region = &lt;0xc9&gt;;
			qcom,pas-id = &lt;0x0f&gt;;
			compatible = &quot;qcom,pil-tz-generic&quot;;
			qcom,firmware-name = &quot;ipa_fws&quot;;
		};

qcom,aopclk {
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,aop-qmp-clk&quot;;
			phandle = &lt;0x19&gt;;
			mboxes = &lt;0x1c 0x00&gt;;
			mbox-names = &quot;qdss_clk&quot;;
		};

qcom,wcd-dsp-glink {
			compatible = &quot;qcom,wcd-dsp-glink&quot;;
			qcom,wdsp-channels = &quot;g_glink_ctrl\0g_glink_persistent_data_nild\0g_glink_persistent_data_ild\0g_glink_audio_data&quot;;
			status = &quot;disabled&quot;;
			phandle = &lt;0x599&gt;;
		};

funnel@7810000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-apss-merg&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7810000 0x1000&gt;;
			phandle = &lt;0x432&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x202&gt;;
						phandle = &lt;0x201&gt;;
					};
				};

port@5 {
					reg = &lt;0x05&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x207&gt;;
						phandle = &lt;0x20b&gt;;
					};
				};

port@3 {
					reg = &lt;0x03&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x205&gt;;
						phandle = &lt;0x20e&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x203&gt;;
						phandle = &lt;0x214&gt;;
					};
				};

port@4 {
					reg = &lt;0x04&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x206&gt;;
						phandle = &lt;0x211&gt;;
					};
				};

port@2 {
					reg = &lt;0x02&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x204&gt;;
						phandle = &lt;0x208&gt;;
					};
				};
			};
		};

tpda@6833000 {
			arm,primecell-periphid = &lt;0x3b969&gt;;
			qcom,cmb-elem-size = &lt;0x00 0x40&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpda-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpda-modem-1&quot;;
			qcom,dsb-elem-size = &lt;0x00 0x20&gt;;
			compatible = &quot;arm,primecell&quot;;
			qcom,tpda-atid = &lt;0x62&gt;;
			reg = &lt;0x6833000 0x1000&gt;;
			phandle = &lt;0x426&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1ed&gt;;
						phandle = &lt;0x1ea&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1ee&gt;;
						phandle = &lt;0x1f0&gt;;
					};
				};
			};
		};

cti@6018000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti8&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6018000 0x1000&gt;;
			phandle = &lt;0x47d&gt;;
		};

dsi_panel_pwr_supply_labibb_amoled {
			#address-cells = &lt;0x01&gt;;
			#size-cells = &lt;0x00&gt;;
			phandle = &lt;0x521&gt;;

qcom,panel-supply-entry@1 {
				qcom,supply-disable-load = &lt;0x50&gt;;
				qcom,supply-enable-load = &lt;0x3390&gt;;
				qcom,supply-name = &quot;vdda-3p3&quot;;
				qcom,supply-max-voltage = &lt;0x2dc6c0&gt;;
				qcom,supply-pre-off-sleep = &lt;0x0a&gt;;
				reg = &lt;0x01&gt;;
				qcom,supply-min-voltage = &lt;0x2dc6c0&gt;;
			};

qcom,panel-supply-entry@0 {
				qcom,supply-disable-load = &lt;0x50&gt;;
				qcom,supply-enable-load = &lt;0x7d00&gt;;
				qcom,supply-name = &quot;vddio&quot;;
				qcom,supply-max-voltage = &lt;0x1cfde0&gt;;
				qcom,supply-pre-off-sleep = &lt;0x14&gt;;
				reg = &lt;0x00&gt;;
				qcom,supply-min-voltage = &lt;0x1cfde0&gt;;
			};
		};

jtagmm@7040000 {
			clock-names = &quot;core_clk&quot;;
			reg-names = &quot;etm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			compatible = &quot;qcom,jtagv8-mm&quot;;
			qcom,coresight-jtagmm-cpu = &lt;0x11&gt;;
			reg = &lt;0x7040000 0x1000&gt;;
			phandle = &lt;0x2a8&gt;;
		};

rpmh-regulator-ldoa13 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa13&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l13 {
				regulator-max-microvolt = &lt;0x1d0d80&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x19e100&gt;;
				regulator-min-microvolt = &lt;0x19e100&gt;;
				regulator-name = &quot;pm6150_l13&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x408&gt;;
			};
		};

ufsphy_mem@1d87000 {
			clock-names = &quot;ref_clk_src\0ref_clk\0ref_aux_clk&quot;;
			reg-names = &quot;phy_mem&quot;;
			lanes-per-direction = &lt;0x01&gt;;
			clocks = &lt;0x2f 0x00 0x27 0x7c 0x27 0x84&gt;;
			vdda-phy-supply = &lt;0x1a9&gt;;
			#phy-cells = &lt;0x00&gt;;
			vdda-pll-supply = &lt;0x1a8&gt;;
			compatible = &quot;qcom,ufs-phy-qmp-v3&quot;;
			status = &quot;ok&quot;;
			vdda-phy-max-microamp = &lt;0xf5b4&gt;;
			reg = &lt;0x1d87000 0xddc&gt;;
			phandle = &lt;0x9c&gt;;
			vdda-phy-always-on;
			vdda-pll-max-microamp = &lt;0x477c&gt;;
		};

wsa_swr_clk_data_pinctrl {
			pinctrl-names = &quot;aud_active\0aud_sleep&quot;;
			pinctrl-0 = &lt;0x3cd 0x3cf&gt;;
			compatible = &quot;qcom,msm-cdc-pinctrl&quot;;
			pinctrl-1 = &lt;0x3cc 0x3ce&gt;;
			status = &quot;disabled&quot;;
			phandle = &lt;0x4e8&gt;;
		};

tpda@78d0000 {
			arm,primecell-periphid = &lt;0x3b969&gt;;
			qcom,cmb-elem-size = &lt;0x00 0x20&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpda-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpda-llm-gold&quot;;
			compatible = &quot;arm,primecell&quot;;
			qcom,tpda-atid = &lt;0x49&gt;;
			reg = &lt;0x78d0000 0x1000&gt;;
			phandle = &lt;0x439&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x211&gt;;
						phandle = &lt;0x206&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x212&gt;;
						phandle = &lt;0x213&gt;;
					};
				};
			};
		};

funnel@6005000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-qatb&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6005000 0x1000&gt;;
			phandle = &lt;0x445&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x226&gt;;
						phandle = &lt;0x1e1&gt;;
					};
				};

port@3 {
					reg = &lt;0x05&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x229&gt;;
						phandle = &lt;0x247&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x227&gt;;
						phandle = &lt;0x22e&gt;;
					};
				};

port@2 {
					reg = &lt;0x03&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x228&gt;;
						phandle = &lt;0x22a&gt;;
					};
				};
			};
		};

tpdm@78a0000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-llm-silver&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x78a0000 0x1000&gt;;
			phandle = &lt;0x438&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x210&gt;;
					phandle = &lt;0x20f&gt;;
				};
			};
		};

qcom,msm-voip-dsp {
			compatible = &quot;qcom,msm-voip-dsp&quot;;
			phandle = &lt;0x261&gt;;
		};

cti@6015000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti5&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6015000 0x1000&gt;;
			phandle = &lt;0x47a&gt;;
		};

qcom,turing@8300000 {
			qcom,smem-state-names = &quot;qcom,force-stop&quot;;
			qcom,smem-id = &lt;0x259&gt;;
			qcom,sysmon-id = &lt;0x07&gt;;
			qcom,vdd_mx-uV-uA = &lt;0x181 0x186a0&gt;;
			qcom,ssctl-instance-id = &lt;0x17&gt;;
			clock-names = &quot;xo&quot;;
			qcom,proxy-timeout-ms = &lt;0x2710&gt;;
			memory-region = &lt;0xad&gt;;
			clocks = &lt;0x2f 0x00&gt;;
			qcom,signal-aop;
			qcom,complete-ramdump;
			vdd_mx-supply = &lt;0x1f&gt;;
			qcom,pas-id = &lt;0x12&gt;;
			interrupts-extended = &lt;0x01 0x00 0x242 0x01 0xae 0x00 0x00 0xae 0x01 0x00 0xae 0x02 0x00 0xae 0x03 0x00&gt;;
			compatible = &quot;qcom,pil-tz-generic&quot;;
			qcom,vdd_cx-uV-uA = &lt;0x181 0x186a0&gt;;
			interrupt-names = &quot;qcom,wdog\0qcom,err-fatal\0qcom,err-ready\0qcom,proxy-unvote\0qcom,stop-ack&quot;;
			reg = &lt;0x8300000 0x100000&gt;;
			qcom,smem-states = &lt;0xaf 0x00&gt;;
			mboxes = &lt;0x1c 0x00&gt;;
			vdd_cx-supply = &lt;0x1d&gt;;
			qcom,proxy-clock-names = &quot;xo&quot;;
			qcom,proxy-reg-names = &quot;vdd_cx\0vdd_mx&quot;;
			qcom,firmware-name = &quot;cdsp&quot;;
			mbox-names = &quot;cdsp-pil&quot;;
		};

qcom,dsi-display@27 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x53b&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_xiaomi_f4_36_02_0b_fhd_cmd_display&quot;;
			phandle = &lt;0x552&gt;;
		};

replicator@6b0a000 {
			arm,primecell-periphid = &lt;0x3b909&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;replicator-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-replicator-swao&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b0a000 0x1000&gt;;
			phandle = &lt;0x42a&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x01&gt;;

endpoint {
						remote-endpoint = &lt;0x1f3&gt;;
						phandle = &lt;0x1f2&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1f4&gt;;
						phandle = &lt;0x1e6&gt;;
					};
				};

port@2 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1f5&gt;;
						phandle = &lt;0x1f6&gt;;
					};
				};
			};
		};

gpio-regulator@3 {
			regulator-max-microvolt = &lt;0x2ab980&gt;;
			gpio = &lt;0x2ec 0x0b 0x00&gt;;
			regulator-enable-ramp-delay = &lt;0x64&gt;;
			enable-active-high;
			regulator-min-microvolt = &lt;0x2ab980&gt;;
			regulator-name = &quot;camera_d_vdda_regulator&quot;;
			compatible = &quot;regulator-fixed&quot;;
			reg = &lt;0x03 0x00&gt;;
			phandle = &lt;0x56b&gt;;
			vin-supply = &lt;0x415&gt;;
		};

tpdm@699c000 {
			qcom,dummy-source;
			coresight-name = &quot;coresight-tpdm-wcss&quot;;
			compatible = &quot;qcom,coresight-dummy&quot;;
			phandle = &lt;0x448&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x22d&gt;;
					phandle = &lt;0x22b&gt;;
				};
			};
		};

qcom,gdsc@10f004 {
			qcom,poll-cfg-gdscr;
			regulator-name = &quot;usb30_prim_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x10f004 0x04&gt;;
			phandle = &lt;0x259&gt;;
		};

qcom,mdss_dsi_ctrl0@ae94000 {
			clock-names = &quot;byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk&quot;;
			reg-names = &quot;dsi_ctrl\0disp_cc_base&quot;;
			cell-index = &lt;0x00&gt;;
			interrupts = &lt;0x04 0x00&gt;;
			clocks = &lt;0x2a 0x03 0x2a 0x04 0x2a 0x06 0x2a 0x1e 0x2a 0x1f 0x2a 0x16&gt;;
			interrupt-parent = &lt;0x1a6&gt;;
			label = &quot;dsi-ctrl-0&quot;;
			vdda-1p2-supply = &lt;0x1a8&gt;;
			compatible = &quot;qcom,dsi-ctrl-hw-v2.3&quot;;
			reg = &lt;0xae94000 0x400 0xaf08000 0x04&gt;;
			phandle = &lt;0x372&gt;;

qcom,ctrl-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

qcom,core-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

cti@6012000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti2&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6012000 0x1000&gt;;
			phandle = &lt;0x477&gt;;
		};

rpmh-regulator-ldoc10 {
			qcom,mode-threshold-currents = &lt;0x00 0x2710&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoc10&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150l-l10 {
				regulator-max-microvolt = &lt;0x328980&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x30d400&gt;;
				regulator-min-microvolt = &lt;0x30d400&gt;;
				regulator-name = &quot;pm6150l_l10&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x33&gt;;
			};
		};

cti@6c2a000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-dlct_cti1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6c2a000 0x1000&gt;;
			phandle = &lt;0x469&gt;;
		};

funnel_1@6861000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base-dummy\0funnel-base-real&quot;;
			qcom,duplicate-funnel;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-turing1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6867010 0x10 0x6861000 0x1000&gt;;
			phandle = &lt;0x451&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x247&gt;;
						phandle = &lt;0x229&gt;;
					};
				};

port@1 {
					reg = &lt;0x01&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x248&gt;;
						phandle = &lt;0x249&gt;;
					};
				};
			};
		};

funnel@6045000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-merg&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6045000 0x1000&gt;;
			phandle = &lt;0x421&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1da&gt;;
						phandle = &lt;0x1d9&gt;;
					};
				};

port@3 {
					reg = &lt;0x02&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1dd&gt;;
						phandle = &lt;0x200&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1db&gt;;
						phandle = &lt;0x1de&gt;;
					};
				};

port@2 {
					reg = &lt;0x01&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1dc&gt;;
						phandle = &lt;0x1e4&gt;;
					};
				};
			};
		};

qcom,cpu0-cpu-l3-latmon {
			qcom,cachemiss-ev = &lt;0x17&gt;;
			qcom,core-dev-table = &lt;0xbb800 0x11e1a300 0xf8700 0x21301800 0x130b00 0x2dc6c000 0x16d7a8 0x38137800 0x1b8a00 0x56f9a000&gt;;
			qcom,cpulist = &lt;0x11 0x12 0x13 0x14 0x15 0x16&gt;;
			compatible = &quot;qcom,arm-memlat-mon&quot;;
			phandle = &lt;0x313&gt;;
			qcom,target-dev = &lt;0x24&gt;;
		};

qcom,msm-pcm-loopback {
			compatible = &quot;qcom,msm-pcm-loopback&quot;;
			phandle = &lt;0x263&gt;;
		};

qcom,dsi-display@5 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x527&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_sim_cmd_display&quot;;
			phandle = &lt;0x544&gt;;
		};

msm_cdc_pinctrl@24 {
			pinctrl-names = &quot;aud_active\0aud_sleep&quot;;
			pinctrl-0 = &lt;0x50b&gt;;
			compatible = &quot;qcom,msm-cdc-pinctrl&quot;;
			qcom,lpi-gpios;
			pinctrl-1 = &lt;0x50c&gt;;
			phandle = &lt;0x4ec&gt;;
		};

etm@7540000 {
			arm,primecell-periphid = &lt;0xbb95d&gt;;
			clock-names = &quot;apb_pclk&quot;;
			clocks = &lt;0x19 0x00&gt;;
			cpu = &lt;0x16&gt;;
			qcom,tupwr-disable;
			coresight-name = &quot;coresight-etm5&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7540000 0x1000&gt;;
			phandle = &lt;0x441&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x222&gt;;
					phandle = &lt;0x21a&gt;;
				};
			};
		};

rpmh-regulator-smpc1 {
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;smpc1&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm6150l-s1 {
				regulator-max-microvolt = &lt;0x124f80&gt;;
				qcom,init-voltage = &lt;0xf4240&gt;;
				regulator-min-microvolt = &lt;0xf4240&gt;;
				regulator-name = &quot;pm6150l_s1&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x3fd&gt;;
			};
		};

qcom,jpegdma@ac52000 {
			clock-names = &quot;jpegdma_clk_src\0jpegdma_clk&quot;;
			reg-names = &quot;jpegdma_hw&quot;;
			reg-cam-base = &lt;0x52000&gt;;
			cell-index = &lt;0x00&gt;;
			camss-vdd-supply = &lt;0x1ae&gt;;
			interrupts = &lt;0x00 0x1db 0x00&gt;;
			clocks = &lt;0x29 0x4d 0x29 0x4c&gt;;
			clock-cntl-level = &quot;nominal&quot;;
			compatible = &quot;qcom,cam_jpeg_dma&quot;;
			src-clock-name = &quot;jpegdma_clk_src&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;jpegdma&quot;;
			reg = &lt;0xac52000 0x4000&gt;;
			regulator-names = &quot;camss-vdd&quot;;
			phandle = &lt;0x398&gt;;
			clock-rates = &lt;0x23c34600 0x00&gt;;
		};

qcom,gcc@100000 {
			#reset-cells = &lt;0x01&gt;;
			reg-names = &quot;cc_base&quot;;
			vdd_cx_ao-supply = &lt;0x1e&gt;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,gcc-sdmmagpie\0syscon&quot;;
			reg = &lt;0x100000 0x1f0000&gt;;
			phandle = &lt;0x27&gt;;
			vdd_cx-supply = &lt;0x1d&gt;;
		};

qcom,dsi-display@17 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x532&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_ss_fhd_ea_f10_cmd_display&quot;;
			phandle = &lt;0x54e&gt;;
		};

qcom,vfe1@acb6000 {
			camss-supply = &lt;0x1ae&gt;;
			clock-control-debugfs = &quot;true&quot;;
			clock-names = &quot;ife_clk_src\0ife_clk\0ife_axi_clk&quot;;
			clocks-option = &lt;0x29 0x3d&gt;;
			reg-names = &quot;ife&quot;;
			clock-rates-option = &lt;0x2d4cae00&gt;;
			reg-cam-base = &lt;0xb6000&gt;;
			cell-index = &lt;0x01&gt;;
			ife1-supply = &lt;0x1b8&gt;;
			interrupts = &lt;0x00 0x1d3 0x00&gt;;
			clocks = &lt;0x29 0x39 0x29 0x38 0x29 0x37&gt;;
			clock-cntl-level = &quot;lowsvs\0svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,vfe175_130&quot;;
			src-clock-name = &quot;ife_clk_src&quot;;
			status = &quot;ok&quot;;
			clock-names-option = &quot;ife_dsp_clk&quot;;
			interrupt-names = &quot;ife&quot;;
			reg = &lt;0xacb6000 0x5200&gt;;
			regulator-names = &quot;camss\0ife1&quot;;
			phandle = &lt;0x390&gt;;
			qcom,cam-cx-ipeak = &lt;0x1a3 0x03&gt;;
			clock-rates = &lt;0x16a65700 0x00 0x00 0x1e65fb80 0x00 0x00 0x25f7d940 0x00 0x00 0x2d4cae00 0x00 0x00&gt;;
		};

i2c@0x88c000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x16d&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			interrupts = &lt;0x00 0x25c 0x00&gt;;
			clocks = &lt;0x27 0x4a 0x27 0x67 0x27 0x68&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x168&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,i2c-geni&quot;;
			pinctrl-1 = &lt;0x16e&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0x88c000 0x4000&gt;;
			phandle = &lt;0x350&gt;;
			dmas = &lt;0x165 0x00 0x03 0x03 0x40 0x00 0x165 0x01 0x03 0x03 0x40 0x00&gt;;
		};

qcom,cpu0-cpu-llcc-lat {
			qcom,src-dst-ports = &lt;0x01 0x302&gt;;
			governor = &quot;performance&quot;;
			compatible = &quot;qcom,devbw&quot;;
			phandle = &lt;0xc1&gt;;
			qcom,active-only;
			operating-points-v2 = &lt;0xbc&gt;;
		};

rpmh-regulator-ldoc6 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoc6&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150l-l6 {
				regulator-max-microvolt = &lt;0x2f4d60&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x192580&gt;;
				regulator-min-microvolt = &lt;0x192580&gt;;
				regulator-name = &quot;pm6150l_l6&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x410&gt;;
			};
		};

jtagmm@7640000 {
			clock-names = &quot;core_clk&quot;;
			reg-names = &quot;etm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			compatible = &quot;qcom,jtagv8-mm&quot;;
			qcom,coresight-jtagmm-cpu = &lt;0x17&gt;;
			reg = &lt;0x7640000 0x1000&gt;;
			phandle = &lt;0x2ae&gt;;
		};

tpdm@6840000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-vsense&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6840000 0x1000&gt;;
			phandle = &lt;0x457&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x252&gt;;
					phandle = &lt;0x235&gt;;
				};
			};
		};

qcom,gdsc@9911028 {
			clock-names = &quot;ahb_clk&quot;;
			clocks = &lt;0x27 0x2f&gt;;
			regulator-name = &quot;npu_core_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x9911028 0x04&gt;;
			phandle = &lt;0x23&gt;;
		};

funnel_1@6b53000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-dl-south-1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b58000 0x10 0x6b53000 0x1000&gt;;
			phandle = &lt;0x446&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x22a&gt;;
						phandle = &lt;0x228&gt;;
					};
				};

port@1 {
					reg = &lt;0x02&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x22b&gt;;
						phandle = &lt;0x22d&gt;;
					};
				};
			};
		};

cti@69a5000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-wcss_cti1&quot;;
			compatible = &quot;arm,primecell&quot;;
			status = &quot;disabled&quot;;
			reg = &lt;0x69a5000 0x1000&gt;;
			phandle = &lt;0x46b&gt;;
		};

funnel@6042000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-in1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6042000 0x1000&gt;;
			phandle = &lt;0x423&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1e4&gt;;
						phandle = &lt;0x1dc&gt;;
					};
				};

port@3 {
					reg = &lt;0x05&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1e7&gt;;
						phandle = &lt;0x1e8&gt;;
					};
				};

port@1 {
					reg = &lt;0x03&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1e5&gt;;
						phandle = &lt;0x1f1&gt;;
					};
				};

port@2 {
					reg = &lt;0x04&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1e6&gt;;
						phandle = &lt;0x1f4&gt;;
					};
				};
			};
		};

spi@0x880000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x178&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			interrupts = &lt;0x00 0x259 0x00&gt;;
			clocks = &lt;0x27 0x44 0x27 0x67 0x27 0x68&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x168&gt;;
			spi-max-frequency = &lt;0x2faf080&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,spi-geni&quot;;
			pinctrl-1 = &lt;0x179&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0x880000 0x4000&gt;;
			phandle = &lt;0x354&gt;;
			dmas = &lt;0x165 0x00 0x00 0x01 0x40 0x00 0x165 0x01 0x00 0x01 0x40 0x00&gt;;
		};

rpmh-regulator-ldof4 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldof4&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm8009-l4 {
				regulator-max-microvolt = &lt;0x13e5c0&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x10b940&gt;;
				regulator-min-microvolt = &lt;0x10b940&gt;;
				regulator-name = &quot;pm8009_l4&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x419&gt;;
			};
		};

syscon@17c0000c {
			compatible = &quot;syscon&quot;;
			reg = &lt;0x17c0000c 0x04&gt;;
			phandle = &lt;0x99&gt;;
		};

qcom,memshare {
			compatible = &quot;qcom,memshare&quot;;

qcom,client_2 {
				qcom,peripheral-size = &lt;0x00&gt;;
				qcom,client-id = &lt;0x02&gt;;
				label = &quot;modem&quot;;
				compatible = &quot;qcom,memshare-peripheral&quot;;
			};

qcom,client_3 {
				qcom,peripheral-size = &lt;0x500000&gt;;
				qcom,client-id = &lt;0x01&gt;;
				qcom,allocate-on-request;
				label = &quot;modem&quot;;
				compatible = &quot;qcom,memshare-peripheral&quot;;
				phandle = &lt;0x2b0&gt;;
			};

qcom,client_1 {
				qcom,peripheral-size = &lt;0x00&gt;;
				qcom,client-id = &lt;0x00&gt;;
				label = &quot;modem&quot;;
				qcom,allocate-boot-time;
				compatible = &quot;qcom,memshare-peripheral&quot;;
			};
		};

tpdm@7830000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-olc&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7830000 0x1000&gt;;
			phandle = &lt;0x434&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x20a&gt;;
					phandle = &lt;0x209&gt;;
				};
			};
		};

spi@0xa94000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x19f&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			interrupts = &lt;0x00 0x166 0x00&gt;;
			clocks = &lt;0x27 0x61 0x27 0x69 0x27 0x6a&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			spi-max-frequency = &lt;0x2faf080&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,spi-geni&quot;;
			pinctrl-1 = &lt;0x1a0&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0xa94000 0x4000&gt;;
			phandle = &lt;0x367&gt;;
			dmas = &lt;0x183 0x00 0x05 0x01 0x40 0x00 0x183 0x01 0x05 0x01 0x40 0x00&gt;;
		};

qcom,gdsc@ad09004 {
			qcom,poll-cfg-gdscr;
			clock-names = &quot;ahb_clk&quot;;
			qcom,support-hw-trigger;
			clocks = &lt;0x27 0x0e&gt;;
			regulator-name = &quot;ipe_1_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xad09004 0x04&gt;;
			phandle = &lt;0x1ba&gt;;
		};

qcom,vfe0@acaf000 {
			camss-supply = &lt;0x1ae&gt;;
			clock-control-debugfs = &quot;true&quot;;
			clock-names = &quot;ife_clk_src\0ife_clk\0ife_axi_clk&quot;;
			clocks-option = &lt;0x29 0x36&gt;;
			reg-names = &quot;ife&quot;;
			clock-rates-option = &lt;0x2d4cae00&gt;;
			reg-cam-base = &lt;0xaf000&gt;;
			ife0-supply = &lt;0x1b7&gt;;
			cell-index = &lt;0x00&gt;;
			interrupts = &lt;0x00 0x1d1 0x00&gt;;
			clocks = &lt;0x29 0x32 0x29 0x31 0x29 0x30&gt;;
			clock-cntl-level = &quot;lowsvs\0svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,vfe175_130&quot;;
			src-clock-name = &quot;ife_clk_src&quot;;
			status = &quot;ok&quot;;
			clock-names-option = &quot;ife_dsp_clk&quot;;
			interrupt-names = &quot;ife&quot;;
			reg = &lt;0xacaf000 0x5200&gt;;
			regulator-names = &quot;camss\0ife0&quot;;
			phandle = &lt;0x38e&gt;;
			qcom,cam-cx-ipeak = &lt;0x1a3 0x03&gt;;
			clock-rates = &lt;0x16a65700 0x00 0x00 0x1e65fb80 0x00 0x00 0x25f7d940 0x00 0x00 0x2d4cae00 0x00 0x00&gt;;
		};

qcom,qup_uart@0xa90000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			pinctrl-0 = &lt;0x191 0x192 0x193&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			clocks = &lt;0x27 0x4c 0x27 0x69 0x27 0x6a&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			interrupts-extended = &lt;0x01 0x00 0x165 0x00 0x174 0x71 0x00&gt;;
			compatible = &quot;qcom,msm-geni-serial-hs&quot;;
			pinctrl-1 = &lt;0x191 0x192 0x193&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0xa90000 0x4000&gt;;
			phandle = &lt;0x361&gt;;
			qcom,wakeup-byte = &lt;0xfd&gt;;
		};

qcom,smp2p_sleepstate {
			interrupts = &lt;0x00 0x00&gt;;
			interrupt-parent = &lt;0x98&gt;;
			compatible = &quot;qcom,smp2p-sleepstate&quot;;
			interrupt-names = &quot;smp2p-sleepstate-in&quot;;
			qcom,smem-states = &lt;0x97 0x00&gt;;
		};

qcom,a5@ac00000 {
			clock-names = &quot;soc_fast_ahb\0icp_ahb_clk\0icp_clk_src\0icp_clk&quot;;
			fw_name = &quot;CAMERA_ICP.elf&quot;;
			reg-names = &quot;a5_qgic\0a5_sierra\0a5_csr&quot;;
			reg-cam-base = &lt;0x00 0x10000 0x18000&gt;;
			cell-index = &lt;0x00&gt;;
			camss-vdd-supply = &lt;0x1ae&gt;;
			interrupts = &lt;0x00 0x1cf 0x00&gt;;
			clocks = &lt;0x29 0x28 0x29 0x2d 0x29 0x2f 0x29 0x2e&gt;;
			ubwc-cfg = &lt;0x73 0x1cf&gt;;
			clock-cntl-level = &quot;svs\0turbo&quot;;
			compatible = &quot;qcom,cam-a5&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;a5&quot;;
			reg = &lt;0xac00000 0x6000 0xac10000 0x8000 0xac18000 0x3000&gt;;
			regulator-names = &quot;camss-vdd&quot;;
			phandle = &lt;0x393&gt;;
			clock-rates = &lt;0xbebc200 0x00 0x17d78400 0x00 0x17d78400 0x00 0x23c34600 0x00&gt;;
		};

rpmh-regulator-ldoa11 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa11&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l11 {
				regulator-max-microvolt = &lt;0x1e4600&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x19e100&gt;;
				regulator-min-microvolt = &lt;0x19e100&gt;;
				regulator-name = &quot;pm6150_l11&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x1cf&gt;;
			};
		};

rpmh-regulator-cxlvl {
			compatible = &quot;qcom,rpmh-arc-regulator&quot;;
			pm6150l-s2-level_ao-parent-supply = &lt;0x1ce&gt;;
			qcom,resource-name = &quot;cx.lvl&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			pm6150l-s2-level-parent-supply = &lt;0x1f&gt;;

regulator-pm6150l-s2 {
				regulator-max-microvolt = &lt;0x10000&gt;;
				regulator-min-microvolt = &lt;0x11&gt;;
				regulator-name = &quot;pm6150l_s2_level&quot;;
				qcom,init-voltage-level = &lt;0x11&gt;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x1d&gt;;
				qcom,min-dropout-voltage-level = &lt;0xffffffff&gt;;
			};

regulator-cdev {
				qcom,reg-resource-name = &quot;cx&quot;;
				compatible = &quot;qcom,rpmh-reg-cdev&quot;;
				phandle = &lt;0x67&gt;;
				mboxes = &lt;0x1c 0x00&gt;;
				#cooling-cells = &lt;0x02&gt;;
			};

regulator-pm6150l-s2-level-ao {
				regulator-max-microvolt = &lt;0x10000&gt;;
				regulator-min-microvolt = &lt;0x11&gt;;
				regulator-name = &quot;pm6150l_s2_level_ao&quot;;
				qcom,init-voltage-level = &lt;0x11&gt;;
				qcom,set = &lt;0x01&gt;;
				phandle = &lt;0x1e&gt;;
				qcom,min-dropout-voltage-level = &lt;0xffffffff&gt;;
			};
		};

wsa_core_clk {
			qcom,codec-ext-clk-src = &lt;0x03&gt;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,audio-ref-clk&quot;;
			phandle = &lt;0x4e6&gt;;
			qcom,codec-lpass-clk-id = &lt;0x309&gt;;
			qcom,codec-lpass-ext-clk-freq = &lt;0x124f800&gt;;
		};

tpdm@69c0000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-dl-mm&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x69c0000 0x1000&gt;;
			phandle = &lt;0x44c&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x240&gt;;
					phandle = &lt;0x23f&gt;;
				};
			};
		};

qcom,spmi@c440000 {
			#address-cells = &lt;0x01&gt;;
			reg-names = &quot;core\0chnls\0obsrvr\0intr\0cnfg&quot;;
			qcom,channel = &lt;0x00&gt;;
			cell-index = &lt;0x00&gt;;
			interrupts = &lt;0x00 0x1e1 0x00&gt;;
			#size-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,spmi-pmic-arb&quot;;
			#interrupt-cells = &lt;0x04&gt;;
			interrupt-names = &quot;periph_irq&quot;;
			reg = &lt;0xc440000 0x1100 0xc600000 0x2000000 0xe600000 0x100000 0xe700000 0xa0000 0xc40a000 0x26000&gt;;
			phandle = &lt;0x2e3&gt;;
			qcom,ee = &lt;0x00&gt;;
			interrupt-controller;

qcom,pm6150@1 {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x01&gt;;
				compatible = &quot;qcom,spmi-pmic&quot;;
				reg = &lt;0x01 0x00&gt;;

qcom,vibrator@5300 {
					qcom,disable-overdrive;
					compatible = &quot;qcom,qpnp-vibrator-ldo&quot;;
					reg = &lt;0x5300 0x100&gt;;
					phandle = &lt;0x2e9&gt;;
					qcom,vib-ldo-volt-uv = &lt;0x2dc6c0&gt;;
				};
			};

qcom,pm6150l@5 {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x01&gt;;
				compatible = &quot;qcom,spmi-pmic&quot;;
				reg = &lt;0x05 0x00&gt;;

qcom,pwms@bc00 {
					qcom,num-lpg-channels = &lt;0x02&gt;;
					reg-names = &quot;lpg-base&quot;;
					#pwm-cells = &lt;0x02&gt;;
					compatible = &quot;qcom,pwm-lpg&quot;;
					status = &quot;disabled&quot;;
					reg = &lt;0xbc00 0x200&gt;;
					phandle = &lt;0x303&gt;;
				};

qcom,amoled {
					compatible = &quot;qcom,qpnp-amoled-regulator&quot;;
					status = &quot;disabled&quot;;
					phandle = &lt;0x308&gt;;

ab@de00 {
						regulator-max-microvolt = &lt;0x5d1420&gt;;
						reg-names = &quot;ab_base&quot;;
						regulator-min-microvolt = &lt;0x4630c0&gt;;
						regulator-name = &quot;ab&quot;;
						reg = &lt;0xde00 0x100&gt;;
						phandle = &lt;0x30a&gt;;
						qcom,swire-control;
					};

oledb@e000 {
						regulator-max-microvolt = &lt;0x7b98a0&gt;;
						reg-names = &quot;oledb_base&quot;;
						regulator-min-microvolt = &lt;0x4b2648&gt;;
						regulator-name = &quot;oledb&quot;;
						reg = &lt;0xe000 0x100&gt;;
						phandle = &lt;0x309&gt;;
						qcom,swire-control;
					};

ibb@dc00 {
						regulator-max-microvolt = &lt;0x5265c0&gt;;
						reg-names = &quot;ibb_base&quot;;
						regulator-min-microvolt = &lt;0xc3500&gt;;
						regulator-name = &quot;ibb&quot;;
						reg = &lt;0xdc00 0x100&gt;;
						phandle = &lt;0x30b&gt;;
						qcom,swire-control;
					};
				};

qcom,lcdb@ec00 {
					#address-cells = &lt;0x01&gt;;
					interrupts = &lt;0x05 0xec 0x01 0x01&gt;;
					#size-cells = &lt;0x01&gt;;
					compatible = &quot;qcom,qpnp-lcdb-regulator&quot;;
					status = &quot;disabled&quot;;
					interrupt-names = &quot;sc-irq&quot;;
					qcom,pmic-revid = &lt;0xab&gt;;
					reg = &lt;0xec00 0x100&gt;;
					phandle = &lt;0x2ee&gt;;

bst {
						regulator-max-microvolt = &lt;0x5fbfb8&gt;;
						label = &quot;bst&quot;;
						regulator-min-microvolt = &lt;0x47b760&gt;;
						regulator-name = &quot;lcdb_bst&quot;;
						phandle = &lt;0x2f1&gt;;
					};

ldo {
						regulator-max-microvolt = &lt;0x5b8d80&gt;;
						label = &quot;ldo&quot;;
						regulator-min-microvolt = &lt;0x3d0900&gt;;
						regulator-name = &quot;lcdb_ldo&quot;;
						phandle = &lt;0x2ef&gt;;
					};

ncp {
						regulator-max-microvolt = &lt;0x5b8d80&gt;;
						label = &quot;ncp&quot;;
						regulator-min-microvolt = &lt;0x3d0900&gt;;
						regulator-name = &quot;lcdb_ncp&quot;;
						phandle = &lt;0x2f0&gt;;
					};
				};

qcom,leds@d000 {
					compatible = &quot;qcom,tri-led&quot;;
					reg = &lt;0xd000 0x100&gt;;
					phandle = &lt;0x304&gt;;

green {
						linux,default-trigger = &quot;timer&quot;;
						label = &quot;green&quot;;
						led-sources = &lt;0x01&gt;;
						phandle = &lt;0x306&gt;;
						pwms = &lt;0xac 0x01 0xf4240&gt;;
					};

led {
						linux,default-trigger = &quot;timer&quot;;
						label = &quot;red&quot;;
						led-sources = &lt;0x00&gt;;
						phandle = &lt;0x305&gt;;
						pwms = &lt;0xac 0x00 0xf4240&gt;;
					};

blue {
						linux,default-trigger = &quot;timer&quot;;
						label = &quot;blue&quot;;
						led-sources = &lt;0x02&gt;;
						phandle = &lt;0x307&gt;;
						pwms = &lt;0xac 0x02 0xf4240&gt;;
					};
				};

qcom,leds@d300 {
					qcom,hdrm-auto-mode;
					qcom,open-circuit-det;
					qcom,vph-droop-det;
					interrupts = &lt;0x05 0xd3 0x00 0x01 0x05 0xd3 0x03 0x01 0x05 0xd3 0x04 0x01&gt;;
					label = &quot;flash&quot;;
					compatible = &quot;qcom,qpnp-flash-led-v2&quot;;
					status = &quot;okay&quot;;
					interrupt-names = &quot;led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq&quot;;
					qcom,thermal-derate-en;
					qcom,pmic-revid = &lt;0xab&gt;;
					reg = &lt;0xd300 0x100&gt;;
					phandle = &lt;0x2f2&gt;;
					qcom,short-circuit-det;
					qcom,thermal-derate-current = &lt;0xc8 0x1f4 0x3e8&gt;;
					qcom,isc-delay = &lt;0xc0&gt;;

qcom,flashlight {
						qcom,led-name = &quot;flashlight&quot;;
						qcom,ires-ua = &lt;0x30d4&gt;;
						qcom,id = &lt;0x03&gt;;
						qcom,current-ma = &lt;0x1f4&gt;;
						qcom,duration-ms = &lt;0x500&gt;;
						qcom,hdrm-vol-hi-lo-win-mv = &lt;0x64&gt;;
						label = &quot;flash&quot;;
						qcom,hdrm-voltage-mv = &lt;0x145&gt;;
						phandle = &lt;0x2fc&gt;;
						qcom,max-current = &lt;0x2ee&gt;;
						qcom,default-led-trigger = &quot;flashlight_trigger&quot;;
					};

qcom,torch_2 {
						qcom,led-name = &quot;led:torch_2&quot;;
						qcom,ires-ua = &lt;0x30d4&gt;;
						qcom,id = &lt;0x02&gt;;
						qcom,current-ma = &lt;0x12c&gt;;
						qcom,hdrm-vol-hi-lo-win-mv = &lt;0x64&gt;;
						label = &quot;torch&quot;;
						status = &quot;disabled&quot;;
						qcom,hdrm-voltage-mv = &lt;0x145&gt;;
						phandle = &lt;0x2f8&gt;;
						qcom,max-current = &lt;0x1f4&gt;;
						qcom,default-led-trigger = &quot;torch2_trigger&quot;;
					};

qcom,flash_1 {
						qcom,led-name = &quot;led:flash_1&quot;;
						qcom,ires-ua = &lt;0x30d4&gt;;
						qcom,id = &lt;0x01&gt;;
						qcom,current-ma = &lt;0x3e8&gt;;
						qcom,duration-ms = &lt;0x500&gt;;
						qcom,hdrm-vol-hi-lo-win-mv = &lt;0x64&gt;;
						label = &quot;flash&quot;;
						qcom,hdrm-voltage-mv = &lt;0x145&gt;;
						phandle = &lt;0x2f4&gt;;
						qcom,max-current = &lt;0x5dc&gt;;
						qcom,default-led-trigger = &quot;flash1_trigger&quot;;
					};

qcom,torch_0 {
						qcom,led-name = &quot;led:torch_0&quot;;
						qcom,ires-ua = &lt;0x30d4&gt;;
						qcom,id = &lt;0x00&gt;;
						qcom,current-ma = &lt;0x12c&gt;;
						qcom,hdrm-vol-hi-lo-win-mv = &lt;0x64&gt;;
						label = &quot;torch&quot;;
						qcom,hdrm-voltage-mv = &lt;0x145&gt;;
						phandle = &lt;0x2f6&gt;;
						qcom,max-current = &lt;0x1f4&gt;;
						qcom,default-led-trigger = &quot;torch0_trigger&quot;;
					};

qcom,led_switch_1 {
						qcom,led-name = &quot;led:switch_1&quot;;
						qcom,led-mask = &lt;0x02&gt;;
						label = &quot;switch&quot;;
						phandle = &lt;0x2fa&gt;;
						qcom,default-led-trigger = &quot;switch1_trigger&quot;;
					};

qcom,flash_2 {
						qcom,led-name = &quot;led:flash_2&quot;;
						qcom,ires-ua = &lt;0x30d4&gt;;
						qcom,id = &lt;0x02&gt;;
						qcom,current-ma = &lt;0x1f4&gt;;
						qcom,duration-ms = &lt;0x500&gt;;
						qcom,hdrm-vol-hi-lo-win-mv = &lt;0x64&gt;;
						label = &quot;flash&quot;;
						status = &quot;disabled&quot;;
						qcom,hdrm-voltage-mv = &lt;0x145&gt;;
						phandle = &lt;0x2f5&gt;;
						qcom,max-current = &lt;0x2ee&gt;;
						qcom,default-led-trigger = &quot;flash2_trigger&quot;;
					};

qcom,torch_1 {
						qcom,led-name = &quot;led:torch_1&quot;;
						qcom,ires-ua = &lt;0x30d4&gt;;
						qcom,id = &lt;0x01&gt;;
						qcom,current-ma = &lt;0x12c&gt;;
						qcom,hdrm-vol-hi-lo-win-mv = &lt;0x64&gt;;
						label = &quot;torch&quot;;
						qcom,hdrm-voltage-mv = &lt;0x145&gt;;
						phandle = &lt;0x2f7&gt;;
						qcom,max-current = &lt;0x1f4&gt;;
						qcom,default-led-trigger = &quot;torch1_trigger&quot;;
					};

qcom,flash_0 {
						qcom,led-name = &quot;led:flash_0&quot;;
						qcom,ires-ua = &lt;0x30d4&gt;;
						qcom,id = &lt;0x00&gt;;
						qcom,current-ma = &lt;0x3e8&gt;;
						qcom,duration-ms = &lt;0x500&gt;;
						qcom,hdrm-vol-hi-lo-win-mv = &lt;0x64&gt;;
						label = &quot;flash&quot;;
						qcom,hdrm-voltage-mv = &lt;0x145&gt;;
						phandle = &lt;0x2f3&gt;;
						qcom,max-current = &lt;0x5dc&gt;;
						qcom,default-led-trigger = &quot;flash0_trigger&quot;;
					};

qcom,led_switch_2 {
						qcom,led-name = &quot;led:switch_2&quot;;
						qcom,led-mask = &lt;0x03&gt;;
						label = &quot;switch&quot;;
						phandle = &lt;0x2fb&gt;;
						qcom,default-led-trigger = &quot;switch2_trigger&quot;;
					};

qcom,led_switch_0 {
						qcom,led-name = &quot;led:switch_0&quot;;
						qcom,led-mask = &lt;0x01&gt;;
						label = &quot;switch&quot;;
						phandle = &lt;0x2f9&gt;;
						qcom,default-led-trigger = &quot;switch0_trigger&quot;;
					};
				};

qcom,pwms@b100 {
					qcom,num-lpg-channels = &lt;0x03&gt;;
					reg-names = &quot;lpg-base\0lut-base&quot;;
					#pwm-cells = &lt;0x02&gt;;
					compatible = &quot;qcom,pwm-lpg&quot;;
					qcom,lut-patterns = &lt;0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00&gt;;
					reg = &lt;0xb100 0x300 0xb000 0x100&gt;;
					phandle = &lt;0xac&gt;;

lpg3 {
						qcom,ramp-pattern-repeat;
						qcom,ramp-pause-hi-count = &lt;0x02&gt;;
						qcom,ramp-step-ms = &lt;0x64&gt;;
						qcom,ramp-from-low-to-high;
						qcom,ramp-low-index = &lt;0x00&gt;;
						qcom,ramp-high-index = &lt;0x14&gt;;
						phandle = &lt;0x302&gt;;
						qcom,lpg-chan-id = &lt;0x03&gt;;
						qcom,ramp-pause-lo-count = &lt;0x02&gt;;
					};

lpg1 {
						qcom,ramp-pattern-repeat;
						qcom,ramp-pause-hi-count = &lt;0x02&gt;;
						qcom,ramp-step-ms = &lt;0x64&gt;;
						qcom,ramp-from-low-to-high;
						qcom,ramp-low-index = &lt;0x00&gt;;
						qcom,ramp-high-index = &lt;0x14&gt;;
						qcom,lpg-chan-id = &lt;0x01&gt;;
						qcom,ramp-pause-lo-count = &lt;0x02&gt;;
					};

lpg2 {
						qcom,ramp-pattern-repeat;
						qcom,ramp-pause-hi-count = &lt;0x02&gt;;
						qcom,ramp-step-ms = &lt;0x64&gt;;
						qcom,ramp-from-low-to-high;
						qcom,ramp-low-index = &lt;0x00&gt;;
						qcom,ramp-high-index = &lt;0x14&gt;;
						phandle = &lt;0x301&gt;;
						qcom,lpg-chan-id = &lt;0x02&gt;;
						qcom,ramp-pause-lo-count = &lt;0x02&gt;;
					};
				};

qcom,wled@d800 {
					reg-names = &quot;wled-ctrl-base\0wled-sink-base&quot;;
					interrupts = &lt;0x05 0xd8 0x01 0x01 0x05 0xd8 0x04 0x03 0x05 0xd8 0x05 0x03&gt;;
					label = &quot;backlight&quot;;
					qcom,auto-calibration;
					compatible = &quot;qcom,pm6150l-spmi-wled&quot;;
					status = &quot;disabled&quot;;
					interrupt-names = &quot;ovp-irq\0pre-flash-irq\0flash-irq&quot;;
					qcom,pmic-revid = &lt;0xab&gt;;
					reg = &lt;0xd800 0x100 0xd900 0x100&gt;;
					phandle = &lt;0x2fd&gt;;

qcom,wled-torch {
						label = &quot;torch&quot;;
						phandle = &lt;0x2ff&gt;;
						qcom,wled-torch-timer = &lt;0x4b0&gt;;
						qcom,default-led-trigger = &quot;wled_torch&quot;;
					};

qcom,wled-switch {
						label = &quot;switch&quot;;
						phandle = &lt;0x300&gt;;
						qcom,default-led-trigger = &quot;wled_switch&quot;;
					};

qcom,wled-flash {
						label = &quot;flash&quot;;
						phandle = &lt;0x2fe&gt;;
						qcom,default-led-trigger = &quot;wled_flash&quot;;
					};
				};
			};

qcom,pm8009@a {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x01&gt;;
				compatible = &quot;qcom,spmi-pmic&quot;;
				reg = &lt;0x0a 0x00&gt;;

pinctrl@c000 {
					qcom,gpios-disallowed = &lt;0x03&gt;;
					gpio-controller;
					interrupts = &lt;0x00 0xc0 0x00 0x00 0x00 0xc1 0x00 0x00 0x00 0xc3 0x00 0x00&gt;;
					compatible = &quot;qcom,spmi-gpio&quot;;
					interrupt-names = &quot;pm8009_gpio1\0pm8009_gpio2\0pm8009_gpio4&quot;;
					reg = &lt;0xc000 0x400&gt;;
					phandle = &lt;0x30c&gt;;
					#gpio-cells = &lt;0x02&gt;;
				};

qcom,revid@100 {
					compatible = &quot;qcom,qpnp-revid&quot;;
					reg = &lt;0x100 0x100&gt;;
				};
			};

qcom,pm6150@0 {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x01&gt;;
				compatible = &quot;qcom,spmi-pmic&quot;;
				reg = &lt;0x00 0x00&gt;;

qcom,power-on@800 {
					interrupts = &lt;0x00 0x08 0x00 0x00 0x00 0x08 0x01 0x00 0x00 0x08 0x04 0x00 0x00 0x08 0x05 0x00&gt;;
					qcom,pon-dbc-delay = &lt;0xf424&gt;;
					compatible = &quot;qcom,qpnp-power-on&quot;;
					qcom,system-reset;
					interrupt-names = &quot;kpdpwr\0resin\0resin-bark\0kpdpwr-resin-bark&quot;;
					reg = &lt;0x800 0x100&gt;;
					qcom,kpdpwr-sw-debounce;
					qcom,store-hard-reset-reason;

qcom,pon_3 {
						qcom,s2-type = &lt;0x01&gt;;
						qcom,pull-up = &lt;0x01&gt;;
						qcom,pon-type = &lt;0x03&gt;;
						qcom,s1-timer = &lt;0x548&gt;;
						qcom,support-reset = &lt;0x01&gt;;
						qcom,use-bark;
						qcom,s2-timer = &lt;0x7d0&gt;;
					};

qcom,pon_1 {
						qcom,s2-type = &lt;0x07&gt;;
						qcom,pull-up = &lt;0x01&gt;;
						qcom,pon-type = &lt;0x00&gt;;
						qcom,s1-timer = &lt;0x1180&gt;;
						qcom,support-reset = &lt;0x01&gt;;
						qcom,s2-timer = &lt;0x7d0&gt;;
						linux,code = &lt;0x74&gt;;
					};

qcom,pon_2 {
						qcom,pull-up;
						qcom,pon-type = &lt;0x01&gt;;
						linux,code = &lt;0x72&gt;;
					};
				};

qcom,qpnp-smb5 {
					qcom,thermal-mitigation-icl = &lt;0x2dc6c0 0x2dc6c0 0x2dc6c0 0x249f00 0x2191c0 0x200b20 0x1e8480 0x1e8480 0x1e8480 0x1cfde0 0x1b7740 0x186a00 0x16e360 0x13d620 0x13d620 0xb71b0&gt;;
					mi,ffc-low-tbat = &lt;0x96&gt;;
					mi,support-qc3p5-without-smb;
					qcom,thermal-mitigation-pd-base = &lt;0x5b8d80 0x4c4b40 0x44aa20 0x3d0900 0x33e140 0x325aa0 0x30d400 0x2f4d60 0x2dc6c0 0x2ab980 0x27ac40 0x249f00 0x2191c0 0x1e8480 0xf4240 0xaae60&gt;;
					#address-cells = &lt;0x01&gt;;
					mi,fcc-batt-unverify-ua = &lt;0x1e8480&gt;;
					qcom,reg-dump-enable;
					qcom,thermal-fcc-qc3-normal = &lt;0x5b8d80 0x4c4b40 0x44aa20 0x3d0900 0x3567e0 0x2dc6c0 0x2c4020 0x2ab980 0x2932e0 0x27ac40 0x249f00 0x2191c0 0x1e8480 0x1e8480 0xb71b0 0xaae60&gt;;
					mi,ffc-high-tbat = &lt;0x1e0&gt;;
					qcom,disable-suspend-on-collapse;
					qcom,fv-max-uv = &lt;0x4434f0&gt;;
					qcom,chg-term-current-ma = &lt;0xffffff38&gt;;
					qcom,sec-charger-config = &lt;0x00&gt;;
					io-channels = &lt;0xa8 0x08 0xa8 0x07 0xa8 0x09 0xa8 0x06 0x2ea 0x4d 0xa8 0x99 0xa8 0x83&gt;;
					mi,early-status-report;
					qcom,fcc-max-ua = &lt;0x5b8d80&gt;;
					mi,use-bq-pump;
					#size-cells = &lt;0x01&gt;;
					dpdm-supply = &lt;0x25a&gt;;
					mi,support-ffc;
					qcom,usbpd-phandle = &lt;0x25b&gt;;
					qcom,thermal-fcc-pps-cp = &lt;0x5b8d80 0x53ec60 0x4c4b40 0x44aa20 0x3e8fa0 0x3b8260 0x3567e0 0x30d400 0x2f4d60 0x2ab980 0x27ac40 0x249f00 0x2191c0 0x1e8480 0xf4240 0xaae60&gt;;
					qcom,battery-data = &lt;0x58e&gt;;
					qcom,distinguish-qc-class-ab;
					qcom,usb-icl-ua = &lt;0x2dc6c0&gt;;
					qcom,thermal-mitigation = &lt;0x5b8d80 0x4c4b40 0x44aa20 0x3d0900 0x3567e0 0x2dc6c0 0x2c4020 0x2ab980 0x27ac40 0x249f00 0x2191c0 0x1e8480 0x1b7740 0x16e360 0xf4240 0x7a120&gt;;
					compatible = &quot;qcom,qpnp-smb5&quot;;
					qcom,step-charging-enable;
					qcom,chg-term-src = &lt;0x01&gt;;
					qcom,sw-jeita-enable;
					qcom,pmic-revid = &lt;0xa4&gt;;
					qcom,thermal-mitigation-dcp = &lt;0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x19f0a0 0x186a00 0x155cc0 0x124f80 0x10c8e0 0x10c8e0 0xf4240&gt;;
					qcom,auto-recharge-soc = &lt;0x63&gt;;
					phandle = &lt;0x8a&gt;;
					qcom,thermal-fcc-qc3-cp = &lt;0x5b8d80 0x4c4b40 0x44aa20 0x3d0900 0x3567e0 0x325aa0 0x30d400 0x2f4d60 0x2dc6c0 0x2ab980 0x27ac40 0x249f00 0x2191c0 0x1e8480 0x1e8480 0x30d40&gt;;
					qcom,lpd-disable;
					qcom,thermal-mitigation-qc2 = &lt;0x16e360 0x16e360 0x16e360 0x16e360 0x162010 0x155cc0 0x149970 0x13d620 0x118c30 0x10c8e0 0xf4240 0xdbba0 0xcf850 0xb71b0 0x9eb10 0x7a120&gt;;
					io-channel-names = &quot;usb_in_voltage\0usb_in_current\0chg_temp\0die_temp\0conn_temp\0sbux_res\0vph_voltage&quot;;
					#cooling-cells = &lt;0x02&gt;;

qcom,chgr@1000 {
						interrupts = &lt;0x00 0x10 0x00 0x01 0x00 0x10 0x01 0x01 0x00 0x10 0x02 0x01 0x00 0x10 0x03 0x01 0x00 0x10 0x04 0x01 0x00 0x10 0x05 0x01 0x00 0x10 0x06 0x01 0x00 0x10 0x07 0x01&gt;;
						interrupt-names = &quot;chgr-error\0chg-state-change\0step-chg-state-change\0step-chg-soc-update-fail\0step-chg-soc-update-req\0fg-fvcal-qualified\0vph-alarm\0vph-drop-prechg&quot;;
						reg = &lt;0x1000 0x100&gt;;
					};

qcom,batif@1200 {
						interrupts = &lt;0x00 0x12 0x00 0x01 0x00 0x12 0x02 0x03 0x00 0x12 0x03 0x03 0x00 0x12 0x04 0x03 0x00 0x12 0x05 0x03 0x00 0x12 0x06 0x03 0x00 0x12 0x07 0x03&gt;;
						interrupt-names = &quot;bat-temp\0bat-ov\0bat-low\0bat-therm-or-id-missing\0bat-terminal-missing\0buck-oc\0vph-ov&quot;;
						reg = &lt;0x1200 0x100&gt;;
					};

qcom,typec@1500 {
						interrupts = &lt;0x00 0x15 0x00 0x01 0x00 0x15 0x01 0x01 0x00 0x15 0x02 0x01 0x00 0x15 0x03 0x01 0x00 0x15 0x04 0x01 0x00 0x15 0x05 0x01 0x00 0x15 0x06 0x01 0x00 0x15 0x07 0x01&gt;;
						interrupt-names = &quot;typec-or-rid-detect-change\0typec-vpd-detect\0typec-cc-state-change\0typec-vconn-oc\0typec-vbus-change\0typec-attach-detach\0typec-legacy-cable-detect\0typec-try-snk-src-detect&quot;;
						reg = &lt;0x1500 0x100&gt;;
					};

qcom,dc@1400 {
						interrupts = &lt;0x00 0x14 0x01 0x03 0x00 0x14 0x02 0x03 0x00 0x14 0x03 0x03 0x00 0x14 0x04 0x03 0x00 0x14 0x05 0x01 0x00 0x14 0x06 0x01 0x00 0x14 0x07 0x01&gt;;
						interrupt-names = &quot;dcin-vashdn\0dcin-uv\0dcin-ov\0dcin-plugin\0dcin-revi\0dcin-pon\0dcin-en&quot;;
						reg = &lt;0x1400 0x100&gt;;
					};

qcom,misc@1600 {
						interrupts = &lt;0x00 0x16 0x00 0x01 0x00 0x16 0x01 0x01 0x00 0x16 0x02 0x01 0x00 0x16 0x03 0x01 0x00 0x16 0x04 0x03 0x00 0x16 0x05 0x01 0x00 0x16 0x06 0x01 0x00 0x16 0x07 0x01&gt;;
						interrupt-names = &quot;wdog-snarl\0wdog-bark\0aicl-fail\0aicl-done\0smb-en\0imp-trigger\0temp-change\0temp-change-smb&quot;;
						reg = &lt;0x1600 0x100&gt;;
					};

qcom,dcdc@1100 {
						interrupts = &lt;0x00 0x11 0x00 0x01 0x00 0x11 0x01 0x01 0x00 0x11 0x02 0x01 0x00 0x11 0x03 0x03 0x00 0x11 0x04 0x03 0x00 0x11 0x05 0x03 0x00 0x11 0x06 0x01 0x00 0x11 0x07 0x03&gt;;
						interrupt-names = &quot;otg-fail\0otg-oc-disable-sw\0otg-oc-hiccup\0bsm-active\0high-duty-cycle\0input-current-limiting\0concurrent-mode-disable\0switcher-power-ok&quot;;
						reg = &lt;0x1100 0x100&gt;;
					};

qcom,usb@1300 {
						interrupts = &lt;0x00 0x13 0x00 0x03 0x00 0x13 0x01 0x03 0x00 0x13 0x02 0x03 0x00 0x13 0x03 0x03 0x00 0x13 0x04 0x03 0x00 0x13 0x05 0x01 0x00 0x13 0x06 0x01 0x00 0x13 0x07 0x01&gt;;
						interrupt-names = &quot;usbin-collapse\0usbin-vashdn\0usbin-uv\0usbin-ov\0usbin-plugin\0usbin-revi-change\0usbin-src-change\0usbin-icl-change&quot;;
						reg = &lt;0x1300 0x100&gt;;
					};

qcom,sdam@b100 {
						interrupts = &lt;0x00 0xb1 0x01 0x01&gt;;
						interrupt-names = &quot;sdam-sts&quot;;
						reg = &lt;0xb100 0x100&gt;;
					};

qcom,smb5-vbus {
						regulator-name = &quot;smb5-vbus&quot;;
						phandle = &lt;0xa6&gt;;
					};

qcom,smb5-vconn {
						regulator-name = &quot;smb5-vconn&quot;;
						phandle = &lt;0xa7&gt;;
					};
				};

qcom,misc@900 {
					compatible = &quot;qcom,qpnp-misc&quot;;
					reg = &lt;0x900 0x100&gt;;
					phandle = &lt;0x2e4&gt;;
				};

vadc@3100 {
					io-channel-ranges;
					#address-cells = &lt;0x01&gt;;
					reg-names = &quot;adc5-usr-base\0adc5-cal-base&quot;;
					interrupts = &lt;0x00 0x31 0x00 0x01&gt;;
					#io-channel-cells = &lt;0x01&gt;;
					#size-cells = &lt;0x00&gt;;
					compatible = &quot;qcom,spmi-adc5&quot;;
					qcom,adc-vdd-reference = &lt;0x753&gt;;
					interrupt-names = &quot;eoc-int-en-set&quot;;
					qcom,pmic-revid = &lt;0xa4&gt;;
					reg = &lt;0x3100 0x100 0x3700 0x100&gt;;
					phandle = &lt;0xa8&gt;;

xo_therm {
						label = &quot;xo_therm&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x4c&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

ref_gnd {
						label = &quot;ref_gnd&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						reg = &lt;0x00&gt;;
					};

chg_temp {
						label = &quot;chg_temp&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						reg = &lt;0x09&gt;;
					};

v_i_int_ext {
						label = &quot;v_i_int_vbat_vdata&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						reg = &lt;0xb0&gt;;
					};

vph_pwr {
						label = &quot;vph_pwr&quot;;
						qcom,pre-scaling = &lt;0x01 0x03&gt;;
						reg = &lt;0x83&gt;;
					};

chg_sbux {
						label = &quot;chg_sbux&quot;;
						qcom,pre-scaling = &lt;0x01 0x03&gt;;
						reg = &lt;0x99&gt;;
					};

vcoin {
						label = &quot;vcoin&quot;;
						qcom,pre-scaling = &lt;0x01 0x03&gt;;
						reg = &lt;0x85&gt;;
					};

bat_therm {
						label = &quot;bat_therm&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x4a&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

bat_therm_400k {
						label = &quot;bat_therm_400k&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x6a&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

cpu_therm {
						label = &quot;cpu_therm&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x4f&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

vref_1p25 {
						label = &quot;vref_1p25&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						reg = &lt;0x01&gt;;
					};

v_i_parallel {
						label = &quot;v_i_parallel_vbat_vdata&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						reg = &lt;0xb4&gt;;
					};

die_temp {
						label = &quot;die_temp&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						reg = &lt;0x06&gt;;
					};

pa_therm0 {
						label = &quot;pa_therm0&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x4e&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

usb_in_i_uv {
						label = &quot;usb_in_i_uv&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						reg = &lt;0x07&gt;;
					};

mid_chg_div6 {
						label = &quot;chg_mid&quot;;
						qcom,pre-scaling = &lt;0x01 0x06&gt;;
						reg = &lt;0x1e&gt;;
					};

usb_in_v_div_16 {
						label = &quot;usb_in_v_div_16&quot;;
						qcom,pre-scaling = &lt;0x01 0x10&gt;;
						reg = &lt;0x08&gt;;
					};

vbat_sns {
						label = &quot;vbat_sns&quot;;
						qcom,pre-scaling = &lt;0x01 0x03&gt;;
						reg = &lt;0x84&gt;;
					};

bat_therm_30k {
						label = &quot;bat_therm_30k&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x2a&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

quiet_therm {
						label = &quot;quiet_therm&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x50&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

bat_id {
						label = &quot;bat_id&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x4b&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};
				};

qpnp,qg {
					qcom,bass-enable;
					qcom,cl-feedback-on;
					mi,software-optimize-ffc-qg-iterm;
					#address-cells = &lt;0x01&gt;;
					qcom,vbatt-empty-mv = &lt;0xc1c&gt;;
					qcom,vbatt-empty-cold-mv = &lt;0xbb8&gt;;
					qcom,vbatt-cutoff-mv = &lt;0xd48&gt;;
					io-channels = &lt;0xa8 0x4a 0xa8 0x4b&gt;;
					qcom,qg-iterm-ma = &lt;0x15e&gt;;
					qcom,s3-entry-fifo-length = &lt;0x02&gt;;
					#size-cells = &lt;0x01&gt;;
					qcom,vbatt-low-mv = &lt;0xdac&gt;;
					qcom,vbatt-low-cold-mv = &lt;0xed8&gt;;
					qcom,s3-entry-ibat-ua = &lt;0x61a8&gt;;
					qcom,tcss-enable;
					qcom,hold-soc-while-full;
					qcom,battery-data = &lt;0x58e&gt;;
					qcom,linearize-soc;
					qcom,tcss-entry-soc = &lt;0x5a&gt;;
					compatible = &quot;qcom,qpnp-qg&quot;;
					qcom,soc_decimal_rate = &lt;0x00 0x20 0x0a 0x1e 0x14 0x1c 0x1e 0x1c 0x28 0x1c 0x32 0x1c 0x3c 0x1c 0x46 0x1c 0x50 0x1c 0x5a 0x1a 0x5f 0x0a 0x63 0x05&gt;;
					qcom,pmic-revid = &lt;0xa4&gt;;
					qcom,qg-ext-sns;
					phandle = &lt;0x2e5&gt;;
					qcom,shutdown-delay-enable;
					qcom,shutdown-soc-threshold = &lt;0x0a&gt;;
					qcom,s3-exit-ibat-ua = &lt;0xafc8&gt;;
					io-channel-names = &quot;batt-therm\0batt-id&quot;;

qcom,qg-sdam@b600 {
						status = &quot;okay&quot;;
						reg = &lt;0xb600 0x100&gt;;
					};

qcom,qgauge@4800 {
						interrupts = &lt;0x00 0x48 0x00 0x03 0x00 0x48 0x01 0x03 0x00 0x48 0x02 0x01 0x00 0x48 0x03 0x01 0x00 0x48 0x04 0x01&gt;;
						status = &quot;okay&quot;;
						interrupt-names = &quot;qg-batt-missing\0qg-vbat-low\0qg-vbat-empty\0qg-fifo-done\0qg-good-ocv&quot;;
						reg = &lt;0x4800 0x100&gt;;
					};
				};

pinctrl@c000 {
					qcom,gpios-disallowed = &lt;0x05 0x06 0x09 0x0a&gt;;
					gpio-controller;
					interrupts = &lt;0x00 0xc0 0x00 0x00 0x00 0xc1 0x00 0x00 0x00 0xc2 0x00 0x00 0x00 0xc3 0x00 0x00 0x00 0xc6 0x00 0x00 0x00 0xc7 0x00 0x00&gt;;
					compatible = &quot;qcom,spmi-gpio&quot;;
					interrupt-names = &quot;pm6150_gpio1\0pm6150_gpio2\0pm6150_gpio3\0pm6150_gpio4\0pm6150_gpio7\0pm6150_gpio8&quot;;
					reg = &lt;0xc000 0xa00&gt;;
					phandle = &lt;0x2e6&gt;;
					#gpio-cells = &lt;0x02&gt;;

smb_stat {

smb_stat_default {
							function = &quot;normal&quot;;
							pins = &quot;gpio3&quot;;
							qcom,pull-up-strength = &lt;0x00&gt;;
							phandle = &lt;0x5b3&gt;;
							bias-pull-up;
							power-source = &lt;0x00&gt;;
							input-enable;
						};
					};

wcd934x_mclk {

wcd934x_mclk_default {
							function = &quot;func1&quot;;
							pins = &quot;gpio8&quot;;
							qcom,drive-strength = &lt;0x02&gt;;
							bias-disable;
							phandle = &lt;0x2e7&gt;;
							power-source = &lt;0x00&gt;;
							output-low;
						};
					};
				};

qcom,usb-pdphy@1700 {
					mi,limit_pd_unverified_pps_vbus = &lt;0x01&gt;;
					vdd-pdphy-supply = &lt;0xa5&gt;;
					mi,non-qcom-pps-ctrl;
					interrupts = &lt;0x00 0x17 0x00 0x01 0x00 0x17 0x01 0x01 0x00 0x17 0x02 0x01 0x00 0x17 0x03 0x01 0x00 0x17 0x04 0x01 0x00 0x17 0x05 0x01 0x00 0x17 0x06 0x01 0x00 0x17 0x07 0x01&gt;;
					vconn-supply = &lt;0xa7&gt;;
					vbus-supply = &lt;0xa6&gt;;
					mi,pd_unverified_pps_max_vbus_limit = &lt;0x90f560&gt;;
					qcom,default-sink-caps = &lt;0x1388 0xbb8 0x2328 0xbb8 0x2ee0 0x8ca&gt;;
					compatible = &quot;qcom,qpnp-pdphy&quot;;
					interrupt-names = &quot;sig-tx\0sig-rx\0msg-tx\0msg-rx\0msg-tx-failed\0msg-tx-discarded\0msg-rx-discarded\0fr-swap&quot;;
					mi,pd_max_curr_limit = &lt;0x3d0900&gt;;
					reg = &lt;0x1700 0x100&gt;;
					phandle = &lt;0x25b&gt;;
					mi,pd_curr_limit = &lt;0x01&gt;;
				};

clock-controller@5b00 {
					clock-output-names = &quot;pm6150_div_clk1&quot;;
					clock-names = &quot;xo&quot;;
					assigned-clocks = &lt;0xa9 0x01&gt;;
					assigned-clock-rates = &lt;0x124f800&gt;;
					clocks = &lt;0x2f 0x00&gt;;
					#clock-cells = &lt;0x01&gt;;
					compatible = &quot;qcom,spmi-clkdiv&quot;;
					qcom,num-clkdivs = &lt;0x01&gt;;
					reg = &lt;0x5b00 0x100&gt;;
					phandle = &lt;0xa9&gt;;
				};

adc_tm@3500 {
					#address-cells = &lt;0x01&gt;;
					interrupts = &lt;0x00 0x35 0x00 0x01&gt;;
					io-channels = &lt;0xa8 0x4c 0xa8 0x4e 0xa8 0x4f 0xa8 0x50&gt;;
					#size-cells = &lt;0x00&gt;;
					#thermal-sensor-cells = &lt;0x01&gt;;
					compatible = &quot;qcom,adc-tm5&quot;;
					interrupt-names = &quot;thr-int-en&quot;;
					reg = &lt;0x3500 0x100&gt;;
					phandle = &lt;0x7f&gt;;

xo_therm {
						qcom,ratiometric;
						reg = &lt;0x4c&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

cpu_therm {
						qcom,ratiometric;
						reg = &lt;0x4f&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

pa_therm0 {
						qcom,ratiometric;
						reg = &lt;0x4e&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

quiet_therm {
						qcom,ratiometric;
						reg = &lt;0x50&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};
				};

bcl@1d00 {
					interrupts = &lt;0x00 0x1d 0x00 0x00 0x00 0x1d 0x01 0x00 0x00 0x1d 0x02 0x00&gt;;
					#thermal-sensor-cells = &lt;0x01&gt;;
					compatible = &quot;qcom,bcl-v5&quot;;
					interrupt-names = &quot;bcl-lvl0\0bcl-lvl1\0bcl-lvl2&quot;;
					reg = &lt;0x1d00 0x100&gt;;
					phandle = &lt;0x55&gt;;
				};

qcom,pm6150_rtc {
					#address-cells = &lt;0x01&gt;;
					#size-cells = &lt;0x01&gt;;
					qcom,qpnp-rtc-alarm-pwrup = &lt;0x00&gt;;
					compatible = &quot;qcom,qpnp-rtc&quot;;
					phandle = &lt;0x2e8&gt;;
					qcom,qpnp-rtc-write = &lt;0x00&gt;;

qcom,pm6150_rtc_rw@6000 {
						reg = &lt;0x6000 0x100&gt;;
					};

qcom,pm6150_rtc_alarm@6100 {
						interrupts = &lt;0x00 0x61 0x01 0x00&gt;;
						reg = &lt;0x6100 0x100&gt;;
					};
				};

qcom,revid@100 {
					compatible = &quot;qcom,qpnp-revid&quot;;
					reg = &lt;0x100 0x100&gt;;
					phandle = &lt;0xa4&gt;;
				};

qcom,temp-alarm@2400 {
					qcom,temperature-threshold-set = &lt;0x01&gt;;
					interrupts = &lt;0x00 0x24 0x00 0x01&gt;;
					#thermal-sensor-cells = &lt;0x00&gt;;
					compatible = &quot;qcom,spmi-temp-alarm&quot;;
					reg = &lt;0x2400 0x100&gt;;
					phandle = &lt;0x54&gt;;
				};

bcl-soc {
					#thermal-sensor-cells = &lt;0x00&gt;;
					compatible = &quot;qcom,msm-bcl-soc&quot;;
					phandle = &lt;0x56&gt;;
				};
			};

qcom,pm6150l@4 {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x01&gt;;
				compatible = &quot;qcom,spmi-pmic&quot;;
				reg = &lt;0x04 0x00&gt;;

qcom,power-on@800 {
					compatible = &quot;qcom,qpnp-power-on&quot;;
					reg = &lt;0x800 0x100&gt;;
				};

bcl@3d00 {
					interrupts = &lt;0x04 0x3d 0x00 0x00 0x04 0x3d 0x01 0x00 0x04 0x3d 0x02 0x00&gt;;
					#thermal-sensor-cells = &lt;0x01&gt;;
					compatible = &quot;qcom,bcl-v5&quot;;
					interrupt-names = &quot;bcl-lvl0\0bcl-lvl1\0bcl-lvl2&quot;;
					reg = &lt;0x3d00 0x100&gt;;
					phandle = &lt;0x58&gt;;
				};

vadc@3100 {
					io-channel-ranges;
					#address-cells = &lt;0x01&gt;;
					interrupts = &lt;0x04 0x31 0x00 0x01&gt;;
					#io-channel-cells = &lt;0x01&gt;;
					#size-cells = &lt;0x00&gt;;
					compatible = &quot;qcom,spmi-adc5&quot;;
					qcom,adc-vdd-reference = &lt;0x753&gt;;
					interrupt-names = &quot;eoc-int-en-set&quot;;
					reg = &lt;0x3100 0x100&gt;;
					phandle = &lt;0x2ea&gt;;

ref_gnd {
						label = &quot;ref_gnd&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						reg = &lt;0x00&gt;;
					};

smb_therm {
						label = &quot;smb_therm&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						reg = &lt;0x0e&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

vph_pwr {
						label = &quot;vph_pwr&quot;;
						qcom,pre-scaling = &lt;0x01 0x03&gt;;
						reg = &lt;0x83&gt;;
					};

charger_therm0 {
						label = &quot;charger_therm0&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x4e&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

vref_1p25 {
						label = &quot;vref_1p25&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						reg = &lt;0x01&gt;;
					};

conn_therm {
						label = &quot;conn_therm&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x4d&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

wifi_therm {
						label = &quot;wifi_therm&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x4f&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

die_temp {
						label = &quot;die_temp&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						reg = &lt;0x06&gt;;
					};

nvm_therm {
						label = &quot;nvm_therm&quot;;
						qcom,pre-scaling = &lt;0x01 0x01&gt;;
						qcom,ratiometric;
						reg = &lt;0x55&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};
				};

pinctrl@c000 {
					gpio-controller;
					interrupts = &lt;0x04 0xc0 0x00 0x00 0x04 0xc1 0x00 0x00 0x04 0xc2 0x00 0x00 0x04 0xc3 0x00 0x00 0x04 0xc4 0x00 0x00 0x04 0xc5 0x00 0x00 0x04 0xc6 0x00 0x00 0x04 0xc7 0x00 0x00 0x04 0xc8 0x00 0x00 0x04 0xc9 0x00 0x00 0x04 0xca 0x00 0x00 0x04 0xcb 0x00 0x00&gt;;
					compatible = &quot;qcom,spmi-gpio&quot;;
					interrupt-names = &quot;pm6150l_gpio1\0pm6150l_gpio2\0pm6150l_gpio3\0pm6150l_gpio4\0pm6150l_gpio5\0pm6150l_gpio6\0pm6150l_gpio7\0pm6150l_gpio8\0pm6150l_gpio9\0pm6150l_gpio10\0pm6150l_gpio11\0pm6150l_gpio12&quot;;
					reg = &lt;0xc000 0xc00&gt;;
					phandle = &lt;0x2ec&gt;;
					#gpio-cells = &lt;0x02&gt;;

disp_pins {

disp_pins_default {
							function = &quot;func1&quot;;
							pins = &quot;gpio9&quot;;
							qcom,drive-strength = &lt;0x02&gt;;
							bias-disable;
							phandle = &lt;0x2ed&gt;;
							power-source = &lt;0x01&gt;;
							output-low;
						};
					};

cam_sensor_w_vdda_vddd_disable {
						function = &quot;normal&quot;;
						pins = &quot;gpio3&quot;;
						phandle = &lt;0x5a8&gt;;
						power-source = &lt;0x00&gt;;
						output-low;
					};

key_vol_up {

key_vol_up_default {
							function = &quot;normal&quot;;
							pins = &quot;gpio2&quot;;
							phandle = &lt;0x561&gt;;
							bias-pull-up;
							power-source = &lt;0x00&gt;;
							input-enable;
						};
					};

aw3644_pwm_default {
						function = &quot;normal&quot;;
						pins = &quot;gpio4&quot;;
						phandle = &lt;0x5af&gt;;
						power-source = &lt;0x00&gt;;
						output-low;
					};

cam_sensor_w_vdda_vddd_enable {
						function = &quot;normal&quot;;
						pins = &quot;gpio3&quot;;
						phandle = &lt;0x5a7&gt;;
						power-source = &lt;0x00&gt;;
						output-low;
					};

cam_sensor_u_vdda_vddd_enable {
						function = &quot;normal&quot;;
						pins = &quot;gpio11&quot;;
						phandle = &lt;0x5ab&gt;;
						power-source = &lt;0x01&gt;;
						output-low;
					};

cam_sensor_u_vdda_vddd_disable {
						function = &quot;normal&quot;;
						pins = &quot;gpio11&quot;;
						phandle = &lt;0x5ac&gt;;
						power-source = &lt;0x01&gt;;
						output-low;
					};

cam_sensor_d_vdda_vddd_disable {
						function = &quot;normal&quot;;
						pins = &quot;gpio8&quot;;
						phandle = &lt;0x5aa&gt;;
						power-source = &lt;0x01&gt;;
						output-low;
					};

aw8624_interrupt_pin {

aw8624_interrupt_pin {
							function = &quot;normal&quot;;
							pins = &quot;gpio10&quot;;
							qcom,pull-up-strength = &lt;0x02&gt;;
							phandle = &lt;0x58d&gt;;
							bias-pull-up;
							power-source = &lt;0x01&gt;;
							input-enable;
						};
					};

aw3644_led_hwen_suspend {
						function = &quot;normal&quot;;
						pins = &quot;gpio12&quot;;
						phandle = &lt;0x5ae&gt;;
						power-source = &lt;0x00&gt;;
						output-low;
					};

aw3644_led_hwen_active {
						function = &quot;normal&quot;;
						pins = &quot;gpio12&quot;;
						phandle = &lt;0x5ad&gt;;
						power-source = &lt;0x00&gt;;
						output-low;
					};

cam_sensor_d_vdda_vddd_enable {
						function = &quot;normal&quot;;
						pins = &quot;gpio8&quot;;
						phandle = &lt;0x5a9&gt;;
						power-source = &lt;0x01&gt;;
						output-low;
					};
				};

clock-controller@5b00 {
					clock-output-names = &quot;pm6150l_div_clk1&quot;;
					clock-names = &quot;xo&quot;;
					assigned-clocks = &lt;0xaa 0x01&gt;;
					assigned-clock-rates = &lt;0x927c00&gt;;
					clocks = &lt;0x2f 0x00&gt;;
					#clock-cells = &lt;0x01&gt;;
					compatible = &quot;qcom,spmi-clkdiv&quot;;
					qcom,num-clkdivs = &lt;0x01&gt;;
					reg = &lt;0x5b00 0x100&gt;;
					phandle = &lt;0xaa&gt;;
				};

adc_tm@3500 {
					#address-cells = &lt;0x01&gt;;
					interrupts = &lt;0x04 0x35 0x00 0x01&gt;;
					io-channels = &lt;0x2ea 0x4d 0x2ea 0x4e 0x2ea 0x4f 0x2ea 0x55&gt;;
					#size-cells = &lt;0x00&gt;;
					#thermal-sensor-cells = &lt;0x01&gt;;
					compatible = &quot;qcom,adc-tm5&quot;;
					interrupt-names = &quot;thr-int-en&quot;;
					reg = &lt;0x3500 0x100&gt;;
					phandle = &lt;0x2eb&gt;;

charger_therm0 {
						qcom,ratiometric;
						reg = &lt;0x4e&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

conn_therm {
						qcom,ratiometric;
						reg = &lt;0x4d&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

wifi_therm {
						qcom,ratiometric;
						reg = &lt;0x4f&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};

nvm_therm {
						qcom,ratiometric;
						reg = &lt;0x55&gt;;
						qcom,hw-settle-time = &lt;0xc8&gt;;
					};
				};

qcom,revid@100 {
					compatible = &quot;qcom,qpnp-revid&quot;;
					reg = &lt;0x100 0x100&gt;;
					phandle = &lt;0xab&gt;;
				};

qcom,temp-alarm@2400 {
					qcom,temperature-threshold-set = &lt;0x01&gt;;
					interrupts = &lt;0x04 0x24 0x00 0x01&gt;;
					#thermal-sensor-cells = &lt;0x00&gt;;
					compatible = &quot;qcom,spmi-temp-alarm&quot;;
					reg = &lt;0x2400 0x100&gt;;
					phandle = &lt;0x57&gt;;
				};
			};

qcom,pm8009@b {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x01&gt;;
				compatible = &quot;qcom,spmi-pmic&quot;;
				reg = &lt;0x0b 0x00&gt;;
			};
		};

qcom,msm-ultra-low-latency {
			qcom,msm-pcm-dsp-id = &lt;0x02&gt;;
			qcom,latency-level = &quot;ultra&quot;;
			compatible = &quot;qcom,msm-pcm-dsp&quot;;
			phandle = &lt;0x260&gt;;
			qcom,msm-pcm-low-latency;
		};

qcom,mss@4080000 {
			qcom,smem-state-names = &quot;qcom,force-stop&quot;;
			qcom,smem-id = &lt;0x1a5&gt;;
			qcom,sysmon-id = &lt;0x00&gt;;
			qcom,ssctl-instance-id = &lt;0x12&gt;;
			clock-names = &quot;xo&quot;;
			qcom,msm-bus,name = &quot;pil-modem&quot;;
			qcom,proxy-timeout-ms = &lt;0x2710&gt;;
			memory-region = &lt;0xb1&gt;;
			clocks = &lt;0x2f 0x00&gt;;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x02&gt;;
			qcom,vdd_mss-uV-uA = &lt;0x181 0x186a0&gt;;
			qcom,signal-aop;
			qcom,complete-ramdump;
			qcom,pas-id = &lt;0x04&gt;;
			qcom,minidump-id = &lt;0x03&gt;;
			qcom,aux-minidump-ids = &lt;0x04&gt;;
			interrupts-extended = &lt;0x01 0x00 0x10a 0x01 0xb2 0x00 0x00 0xb2 0x01 0x00 0xb2 0x02 0x00 0xb2 0x03 0x00 0xb2 0x07 0x00&gt;;
			compatible = &quot;qcom,pil-tz-generic&quot;;
			qcom,vdd_cx-uV-uA = &lt;0x181 0x186a0&gt;;
			interrupt-names = &quot;qcom,wdog\0qcom,err-fatal\0qcom,err-ready\0qcom,proxy-unvote\0qcom,stop-ack\0qcom,shutdown-ack&quot;;
			reg = &lt;0x4080000 0x100&gt;;
			vdd_mss-supply = &lt;0xb0&gt;;
			phandle = &lt;0x30d&gt;;
			qcom,smem-states = &lt;0xb3 0x00&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x81 0x200 0x00 0x00 0x81 0x200 0x00 0x6acfc0&gt;;
			mboxes = &lt;0x1c 0x00&gt;;
			vdd_cx-supply = &lt;0x1d&gt;;
			qcom,proxy-clock-names = &quot;xo&quot;;
			qcom,proxy-reg-names = &quot;vdd_cx\0vdd_mss&quot;;
			qcom,firmware-name = &quot;modem&quot;;
			mbox-names = &quot;mss-pil&quot;;
		};

qcom,qup_uart@0xa88000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			pinctrl-0 = &lt;0x180&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			interrupts = &lt;0x00 0x163 0x00&gt;;
			clocks = &lt;0x27 0x5b 0x27 0x69 0x27 0x6a&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			compatible = &quot;qcom,msm-geni-console&quot;;
			pinctrl-1 = &lt;0x181&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0xa88000 0x4000&gt;;
			phandle = &lt;0x359&gt;;
		};

rpmh-regulator-ldoa6 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa6&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l6 {
				regulator-max-microvolt = &lt;0x13e5c0&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x10b940&gt;;
				regulator-min-microvolt = &lt;0x100590&gt;;
				regulator-name = &quot;pm6150_l6&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x406&gt;;
			};
		};

qcom,msm-dai-q6 {
			compatible = &quot;qcom,msm-dai-q6&quot;;

qcom,msm-dai-q6-int-fm-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x3004&gt;;
				phandle = &lt;0x4aa&gt;;
			};

qcom,msm-dai-q6-usb-audio-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x7000&gt;;
				phandle = &lt;0x284&gt;;
			};

qcom,msm-dai-q6-sb-8-tx {
				qcom,msm-dai-q6-slim-dev-id = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4011&gt;;
				phandle = &lt;0x280&gt;;
			};

qcom,msm-dai-q6-sb-5-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x400b&gt;;
				phandle = &lt;0x4a3&gt;;
			};

qcom,msm-dai-q6-sb-2-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4005&gt;;
				phandle = &lt;0x49e&gt;;
			};

qcom,msm-dai-q6-sb-8-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4010&gt;;
				phandle = &lt;0x281&gt;;
			};

qcom,msm-dai-q6-sb-5-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x400a&gt;;
				phandle = &lt;0x4a4&gt;;
			};

qcom,msm-dai-q6-sb-2-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4004&gt;;
				phandle = &lt;0x49d&gt;;
			};

qcom,msm-dai-q6-incall-record-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x8004&gt;;
				phandle = &lt;0x27b&gt;;
			};

qcom,msm-dai-q6-incall-record-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x8003&gt;;
				phandle = &lt;0x27a&gt;;
			};

qcom,msm-dai-q6-incall-music-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x8005&gt;;
				phandle = &lt;0x27c&gt;;
			};

qcom,msm-dai-q6-incall-music-2-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x8002&gt;;
				phandle = &lt;0x27d&gt;;
			};

qcom,msm-dai-q6-proxy-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x2003&gt;;
				phandle = &lt;0x283&gt;;
			};

qcom,msm-dai-q6-sb-7-tx {
				qcom,msm-dai-q6-slim-dev-id = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x400f&gt;;
				phandle = &lt;0x27f&gt;;
			};

qcom,msm-dai-q6-sb-4-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4009&gt;;
				phandle = &lt;0x4a2&gt;;
			};

qcom,msm-dai-q6-proxy-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x2002&gt;;
				phandle = &lt;0x282&gt;;
			};

qcom,msm-dai-q6-sb-1-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4003&gt;;
				phandle = &lt;0x49c&gt;;
			};

qcom,msm-dai-q6-sb-7-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x400e&gt;;
				phandle = &lt;0x27e&gt;;
			};

qcom,msm-dai-q6-sb-4-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4008&gt;;
				phandle = &lt;0x4a1&gt;;
			};

qcom,msm-dai-q6-sb-1-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4002&gt;;
				phandle = &lt;0x49b&gt;;
			};

qcom,msm-dai-q6-be-afe-pcm-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0xe1&gt;;
				phandle = &lt;0x277&gt;;
			};

qcom,msm-dai-q6-be-afe-pcm-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0xe0&gt;;
				phandle = &lt;0x276&gt;;
			};

qcom,msm-dai-q6-sb-9-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4013&gt;;
				phandle = &lt;0x4a7&gt;;
			};

qcom,msm-dai-q6-sb-3-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4007&gt;;
				phandle = &lt;0x4a0&gt;;
			};

qcom,msm-dai-q6-sb-9-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4012&gt;;
				phandle = &lt;0x4a6&gt;;
			};

qcom,msm-dai-q6-sb-0-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4001&gt;;
				phandle = &lt;0x49a&gt;;
			};

qcom,msm-dai-q6-sb-6-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x400c&gt;;
				phandle = &lt;0x4a5&gt;;
			};

qcom,msm-dai-q6-sb-3-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4006&gt;;
				phandle = &lt;0x49f&gt;;
			};

qcom,msm-dai-q6-bt-sco-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x3001&gt;;
				phandle = &lt;0x4a9&gt;;
			};

qcom,msm-dai-q6-sb-0-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x4000&gt;;
				phandle = &lt;0x499&gt;;
			};

qcom,msm-dai-q6-bt-sco-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x3000&gt;;
				phandle = &lt;0x4a8&gt;;
			};

qcom,msm-dai-q6-afe-proxy-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0xf0&gt;;
				phandle = &lt;0x279&gt;;
			};

qcom,msm-dai-q6-int-fm-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x3005&gt;;
				phandle = &lt;0x4ab&gt;;
			};

qcom,msm-dai-q6-afe-proxy-rx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0xf1&gt;;
				phandle = &lt;0x278&gt;;
			};

qcom,msm-dai-q6-usb-audio-tx {
				compatible = &quot;qcom,msm-dai-q6-dev&quot;;
				qcom,msm-dai-q6-dev-id = &lt;0x7001&gt;;
				phandle = &lt;0x285&gt;;
			};
		};

qcom,avtimer@62CF7000 {
			reg-names = &quot;avtimer_lsb_addr\0avtimer_msb_addr&quot;;
			qcom,clk-div = &lt;0xc0&gt;;
			compatible = &quot;qcom,avtimer&quot;;
			qcom,clk-mult = &lt;0x0a&gt;;
			reg = &lt;0x62cf700c 0x04 0x62cf7010 0x04&gt;;
		};

dummy_source {
			qcom,dummy-source;
			coresight-name = &quot;coresight-tpdm-lpass&quot;;
			compatible = &quot;qcom,coresight-dummy&quot;;
			phandle = &lt;0x447&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x22c&gt;;
					phandle = &lt;0x1df&gt;;
				};
			};
		};

qcom,dsi-display@25 {
			qcom,dsi-phy-num = &lt;0x00 0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x539&gt;;
			qcom,dsi-ctrl-num = &lt;0x00 0x01&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_sharp_qsync_fhd_cmd_display&quot;;
			phandle = &lt;0x55a&gt;;
		};

cti@6b06000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-swao_cti2&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b06000 0x1000&gt;;
			phandle = &lt;0x471&gt;;
		};

qcom,rmtfs_sharedmem@0 {
			reg-names = &quot;rmtfs&quot;;
			qcom,client-id = &lt;0x01&gt;;
			qcom,guard-memory;
			compatible = &quot;qcom,sharedmem-uio&quot;;
			reg = &lt;0x00 0x200000&gt;;
		};

sdhci@7c4000 {
			pinctrl-names = &quot;active\0sleep&quot;;
			qcom,large-address-bus;
			qcom,vdd-voltage-level = &lt;0x2d0370 0x2d0370&gt;;
			qcom,pm-qos-cmdq-latency-us = &lt;0x43 0x43 0x43 0x43&gt;;
			pinctrl-0 = &lt;0x3dd 0x3df 0x3e1 0x3e3&gt;;
			clock-names = &quot;iface_clk\0core_clk\0ice_core_clk&quot;;
			qcom,bus-width = &lt;0x08&gt;;
			reg-names = &quot;hc_mem\0cmdq_mem\0cmdq_ice&quot;;
			qcom,msm-bus,name = &quot;sdhc1&quot;;
			qcom,pm-qos-irq-latency = &lt;0x43 0x43&gt;;
			qcom,pm-qos-legacy-latency-us = &lt;0x43 0x43 0x43 0x43&gt;;
			interrupts = &lt;0x00 0x281 0x00 0x00 0x284 0x00&gt;;
			qcom,clk-rates = &lt;0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xb71b000 0x16e36000&gt;;
			clocks = &lt;0x27 0x6b 0x27 0x6c 0x27 0x6e&gt;;
			qcom,msm-bus,num-paths = &lt;0x02&gt;;
			qcom,msm-bus,num-cases = &lt;0x09&gt;;
			qcom,vdd-io-current-level = &lt;0x00 0x4f588&gt;;
			qcom,bus-bw-vectors-bps = &lt;0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x60152b0 0xbebc200 0x17d78400 0xffffffff&gt;;
			qcom,pm-qos-cpu-groups = &lt;0x3f 0xc0&gt;;
			qcom,pm-qos-irq-type = &quot;affine_irq&quot;;
			qcom,ice-clk-rates = &lt;0x11e1a300 0x47868c0&gt;;
			vdd-supply = &lt;0x40d&gt;;
			compatible = &quot;qcom,sdhci-msm-v5&quot;;
			qcom,devfreq,freq-table = &lt;0x2faf080 0xbebc200&gt;;
			qcom,vdd-io-lpm-sup;
			vdd-io-supply = &lt;0x407&gt;;
			pinctrl-1 = &lt;0x3de 0x3e0 0x3e2 0x3e4&gt;;
			qcom,vdd-current-level = &lt;0x00 0x8b290&gt;;
			status = &quot;ok&quot;;
			qcom,dll-hsr-list = &lt;0xf642c 0x00 0x00 0x10800 0x80040868&gt;;
			interrupt-names = &quot;hc_irq\0pwr_irq&quot;;
			reg = &lt;0x7c4000 0x1000 0x7c5000 0x1000 0x7c8000 0x8000&gt;;
			phandle = &lt;0x2d8&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x96 0x200 0x00 0x00 0x01 0x326 0x00 0x00 0x96 0x200 0x3e8 0x7d0 0x01 0x326 0x7d0 0xfa0 0x96 0x200 0x61a8 0xc350 0x01 0x326 0x4e20 0x9c40 0x96 0x200 0xc350 0x186a0 0x01 0x326 0x7530 0xea60 0x96 0x200 0x13880 0x249f0 0x01 0x326 0x9c40 0x13880 0x96 0x200 0x186a0 0x30d40 0x01 0x326 0xc350 0x186a0 0x96 0x200 0x249f0 0x3d090 0x01 0x326 0x13880 0x1d4c0 0x96 0x200 0x3fd3e 0x297c66 0x01 0x326 0x493e0 0x14be33 0x96 0x200 0x146cc2 0x3e8000 0x01 0x326 0x146cc2 0x3e8000&gt;;
			qcom,vdd-io-always-on;
			qcom,bus-speed-mode = &quot;HS400_1p8v\0HS200_1p8v\0DDR_1p8v&quot;;
			qcom,scaling-lower-bus-speed-mode = &quot;DDR52&quot;;
			qcom,vdd-io-voltage-level = &lt;0x1b7740 0x1b7740&gt;;
			qcom,nonremovable;
		};

wsa_spkr_en2_pinctrl {
			pinctrl-names = &quot;aud_active\0aud_sleep&quot;;
			pinctrl-0 = &lt;0x3d3&gt;;
			compatible = &quot;qcom,msm-cdc-pinctrl&quot;;
			pinctrl-1 = &lt;0x3d2&gt;;
			status = &quot;disabled&quot;;
			phandle = &lt;0x4ea&gt;;
		};

va_core_clk {
			qcom,codec-ext-clk-src = &lt;0x02&gt;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,audio-ref-clk&quot;;
			phandle = &lt;0x4eb&gt;;
			qcom,codec-lpass-clk-id = &lt;0x30b&gt;;
			qcom,codec-lpass-ext-clk-freq = &lt;0x124f800&gt;;
		};

gpio-regulator@1 {
			regulator-max-microvolt = &lt;0x1b7740&gt;;
			gpio = &lt;0x2ec 0x08 0x00&gt;;
			regulator-enable-ramp-delay = &lt;0x64&gt;;
			enable-active-high;
			regulator-min-microvolt = &lt;0x1b7740&gt;;
			regulator-name = &quot;camera_vddio_depth_regulator&quot;;
			compatible = &quot;regulator-fixed&quot;;
			reg = &lt;0x01 0x00&gt;;
			phandle = &lt;0x579&gt;;
			vin-supply = &lt;0x3fe&gt;;
		};

qcom,gdsc@509100c {
			qcom,poll-cfg-gdscr;
			clock-names = &quot;core_root_clk&quot;;
			parent-supply = &lt;0x20&gt;;
			clocks = &lt;0x2b 0x12&gt;;
			domain-addr = &lt;0xcd&gt;;
			regulator-name = &quot;gpu_gx_gdsc&quot;;
			qcom,reset-aon-logic;
			compatible = &quot;qcom,gdsc&quot;;
			qcom,force-enable-root-clk;
			status = &quot;ok&quot;;
			reg = &lt;0x509100c 0x04&gt;;
			sw-reset = &lt;0xce&gt;;
			phandle = &lt;0x24e&gt;;
		};

apps-smmu@0x15000000 {
			#global-interrupts = &lt;0x01&gt;;
			#address-cells = &lt;0x01&gt;;
			reg-names = &quot;base\0tcu-base&quot;;
			qcom,msm-bus,name = &quot;apps_smmu&quot;;
			qcom,msm-bus,active-only;
			interrupts = &lt;0x00 0x41 0x04 0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0xb5 0x04 0x00 0xb6 0x04 0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x13e 0x04 0x00 0x13f 0x04 0x00 0x140 0x04 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04 0x00 0x18e 0x04 0x00 0x18f 0x04 0x00 0x190 0x04 0x00 0x191 0x04 0x00 0x192 0x04 0x00 0x193 0x04 0x00 0x194 0x04 0x00 0x195 0x04 0x00 0x196 0x04 0x00 0x197 0x04 0x00 0x198 0x04 0x00 0x199 0x04 0x00 0x19a 0x04 0x00 0x19b 0x04 0x00 0x19c 0x04 0x00 0x19d 0x04&gt;;
			qcom,actlr = &lt;0x800 0x7ff 0x103 0x1000 0x3ff 0x103 0x1460 0x1f 0x303&gt;;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			#size-cells = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x02&gt;;
			qcom,skip-init;
			qcom,use-3-lvl-tables;
			#iommu-cells = &lt;0x02&gt;;
			compatible = &quot;qcom,qsmmu-v500&quot;;
			ranges;
			reg = &lt;0x15000000 0x100000 0x15182000 0x20&gt;;
			phandle = &lt;0x30&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8&gt;;

anoc_1_tbu@0x15185000 {
				reg-names = &quot;base\0status-reg&quot;;
				qcom,msm-bus,name = &quot;apps_smmu&quot;;
				qcom,msm-bus,active-only;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x02&gt;;
				qcom,stream-id-range = &lt;0x00 0x400&gt;;
				qcom,regulator-names = &quot;vdd&quot;;
				vdd-supply = &lt;0x1c6&gt;;
				compatible = &quot;qcom,qsmmuv500-tbu&quot;;
				reg = &lt;0x15185000 0x1000 0x15182200 0x08&gt;;
				phandle = &lt;0x39c&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8&gt;;
			};

mnoc_sf_0_tbu@0x15195000 {
				reg-names = &quot;base\0status-reg&quot;;
				qcom,msm-bus,name = &quot;mnoc_sf_0_tbu&quot;;
				qcom,msm-bus,active-only;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x02&gt;;
				qcom,stream-id-range = &lt;0x1000 0x400&gt;;
				qcom,regulator-names = &quot;vdd&quot;;
				vdd-supply = &lt;0x1ca&gt;;
				compatible = &quot;qcom,qsmmuv500-tbu&quot;;
				reg = &lt;0x15195000 0x1000 0x15182220 0x08&gt;;
				phandle = &lt;0x3a0&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0x89 0x304 0x00 0x00 0x89 0x304 0x00 0x3e8&gt;;
			};

mnoc_hf_0_tbu@0x1518d000 {
				reg-names = &quot;base\0status-reg&quot;;
				qcom,msm-bus,name = &quot;mnoc_hf_0_tbu&quot;;
				qcom,msm-bus,active-only;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x02&gt;;
				qcom,stream-id-range = &lt;0x800 0x400&gt;;
				qcom,regulator-names = &quot;vdd&quot;;
				vdd-supply = &lt;0x1c8&gt;;
				compatible = &quot;qcom,qsmmuv500-tbu&quot;;
				reg = &lt;0x1518d000 0x1000 0x15182210 0x08&gt;;
				phandle = &lt;0x39e&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8&gt;;
			};

mnoc_hf_1_tbu@0x15191000 {
				reg-names = &quot;base\0status-reg&quot;;
				qcom,msm-bus,name = &quot;mnoc_hf_1_tbu&quot;;
				qcom,msm-bus,active-only;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x02&gt;;
				qcom,stream-id-range = &lt;0xc00 0x400&gt;;
				qcom,regulator-names = &quot;vdd&quot;;
				vdd-supply = &lt;0x1c9&gt;;
				compatible = &quot;qcom,qsmmuv500-tbu&quot;;
				reg = &lt;0x15191000 0x1000 0x15182218 0x08&gt;;
				phandle = &lt;0x39f&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8&gt;;
			};

compute_dsp_0_tbu@0x15199000 {
				reg-names = &quot;base\0status-reg&quot;;
				qcom,msm-bus,name = &quot;apps_smmu&quot;;
				qcom,msm-bus,active-only;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x02&gt;;
				qcom,stream-id-range = &lt;0x1400 0x400&gt;;
				compatible = &quot;qcom,qsmmuv500-tbu&quot;;
				reg = &lt;0x15199000 0x1000 0x15182228 0x08&gt;;
				phandle = &lt;0x3a1&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0x9a 0x275c 0x00 0x00 0x9a 0x275c 0x00 0x3e8&gt;;
			};

anoc_2_tbu@0x15189000 {
				reg-names = &quot;base\0status-reg&quot;;
				qcom,msm-bus,name = &quot;apps_smmu&quot;;
				qcom,msm-bus,active-only;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x02&gt;;
				qcom,stream-id-range = &lt;0x400 0x400&gt;;
				qcom,regulator-names = &quot;vdd&quot;;
				vdd-supply = &lt;0x1c7&gt;;
				compatible = &quot;qcom,qsmmuv500-tbu&quot;;
				reg = &lt;0x15189000 0x1000 0x15182208 0x08&gt;;
				phandle = &lt;0x39d&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8&gt;;
			};

adsp_tbu@0x1519d000 {
				reg-names = &quot;base\0status-reg&quot;;
				qcom,msm-bus,name = &quot;apps_smmu&quot;;
				qcom,msm-bus,active-only;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x02&gt;;
				qcom,stream-id-range = &lt;0x1800 0x400&gt;;
				qcom,regulator-names = &quot;vdd&quot;;
				vdd-supply = &lt;0x1cb&gt;;
				compatible = &quot;qcom,qsmmuv500-tbu&quot;;
				reg = &lt;0x1519d000 0x1000 0x15182230 0x08&gt;;
				phandle = &lt;0x3a2&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8&gt;;
			};

anoc_1_pcie_tbu@0x151a1000 {
				clock-names = &quot;gcc_aggre_noc_pcie_tbu_clk&quot;;
				reg-names = &quot;base\0status-reg&quot;;
				qcom,msm-bus,name = &quot;apps_smmu&quot;;
				qcom,msm-bus,active-only;
				clocks = &lt;0x27 0x08&gt;;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x02&gt;;
				qcom,stream-id-range = &lt;0x1c00 0x400&gt;;
				qcom,regulator-names = &quot;vdd&quot;;
				vdd-supply = &lt;0x1cc&gt;;
				compatible = &quot;qcom,qsmmuv500-tbu&quot;;
				reg = &lt;0x151a1000 0x1000 0x15182238 0x08&gt;;
				phandle = &lt;0x3a3&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8&gt;;
			};
		};

cpu-pmu {
			interrupts = &lt;0x01 0x05 0x04&gt;;
			qcom,irq-is-percpu;
			compatible = &quot;arm,armv8-pmuv3&quot;;
			phandle = &lt;0x2b3&gt;;
		};

tpda@6004000 {
			arm,primecell-periphid = &lt;0x3b969&gt;;
			qcom,cmb-elem-size = &lt;0x03 0x40 0x07 0x40 0x0d 0x40&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpda-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpda&quot;;
			qcom,dsb-elem-size = &lt;0x00 0x20 0x02 0x20 0x03 0x20 0x05 0x20 0x06 0x20 0x0a 0x20 0x0b 0x20 0x0d 0x20&gt;;
			qcom,tc-elem-size = &lt;0x0d 0x20&gt;;
			compatible = &quot;arm,primecell&quot;;
			qcom,tpda-atid = &lt;0x41&gt;;
			qcom,bc-elem-size = &lt;0x0a 0x20 0x0d 0x20&gt;;
			reg = &lt;0x6004000 0x1000&gt;;
			phandle = &lt;0x449&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x22e&gt;;
						phandle = &lt;0x227&gt;;
					};
				};

port@14 {
					reg = &lt;0x11&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x23c&gt;;
						phandle = &lt;0x23d&gt;;
					};
				};

port@9 {
					reg = &lt;0x0b&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x237&gt;;
						phandle = &lt;0x254&gt;;
					};
				};

port@12 {
					reg = &lt;0x0e&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x23a&gt;;
						phandle = &lt;0x258&gt;;
					};
				};

port@7 {
					reg = &lt;0x08&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x235&gt;;
						phandle = &lt;0x252&gt;;
					};
				};

port@10 {
					reg = &lt;0x0c&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x238&gt;;
						phandle = &lt;0x255&gt;;
					};
				};

port@5 {
					reg = &lt;0x06&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x233&gt;;
						phandle = &lt;0x24b&gt;;
					};
				};

port@3 {
					reg = &lt;0x03&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x231&gt;;
						phandle = &lt;0x242&gt;;
					};
				};

port@1 {
					reg = &lt;0x01&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x22f&gt;;
						phandle = &lt;0x23e&gt;;
					};
				};

port@13 {
					reg = &lt;0x0f&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x23b&gt;;
						phandle = &lt;0x257&gt;;
					};
				};

port@8 {
					reg = &lt;0x0a&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x236&gt;;
						phandle = &lt;0x253&gt;;
					};
				};

port@11 {
					reg = &lt;0x0d&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x239&gt;;
						phandle = &lt;0x256&gt;;
					};
				};

port@6 {
					reg = &lt;0x07&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x234&gt;;
						phandle = &lt;0x24f&gt;;
					};
				};

port@4 {
					reg = &lt;0x05&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x232&gt;;
						phandle = &lt;0x245&gt;;
					};
				};

port@2 {
					reg = &lt;0x02&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x230&gt;;
						phandle = &lt;0x241&gt;;
					};
				};
			};
		};

tpdm@6a00000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-ddr&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6a00000 0x1000&gt;;
			phandle = &lt;0x454&gt;;
			qcom,msr-fix-req;

port {

endpoint {
					remote-endpoint = &lt;0x24d&gt;;
					phandle = &lt;0x24c&gt;;
				};
			};
		};

qcom,msm-quin-auxpcm {
			qcom,msm-cpudai-auxpcm-quant = &lt;0x02 0x02&gt;;
			qcom,msm-cpudai-auxpcm-frame = &lt;0x05 0x04&gt;;
			qcom,msm-cpudai-auxpcm-sync = &lt;0x01 0x01&gt;;
			qcom,msm-auxpcm-interface = &quot;quinary&quot;;
			qcom,msm-cpudai-auxpcm-slot-mapping = &lt;0x01 0x01&gt;;
			qcom,msm-cpudai-auxpcm-data = &lt;0x00 0x00&gt;;
			qcom,msm-cpudai-afe-clk-ver = &lt;0x02&gt;;
			qcom,msm-cpudai-auxpcm-num-slots = &lt;0x01 0x01&gt;;
			compatible = &quot;qcom,msm-auxpcm-dev&quot;;
			qcom,msm-cpudai-auxpcm-mode = &lt;0x00 0x00&gt;;
			phandle = &lt;0x275&gt;;
			qcom,msm-cpudai-auxpcm-pcm-clk-rate = &lt;0x1f4000 0x1f4000&gt;;
		};

qcom,dsi-display@3 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x525&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,dsi-display-active;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_sim_vid_display&quot;;
			phandle = &lt;0x542&gt;;
		};

ufshc@1d84000 {
			vcc-max-microamp = &lt;0x927c0&gt;;
			pinctrl-names = &quot;dev-reset-assert\0dev-reset-deassert&quot;;
			freq-table-hz = &lt;0x2faf080 0xbebc200 0x00 0x00 0x00 0x00 0x23c3460 0x8f0d180 0x47868c0 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00&gt;;
			qcom,pm-qos-cpu-group-latency-us = &lt;0x43 0x43&gt;;
			spm-level = &lt;0x03&gt;;
			phy-names = &quot;ufsphy&quot;;
			pinctrl-0 = &lt;0x9d&gt;;
			clock-names = &quot;core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk&quot;;
			reg-names = &quot;ufs_mem\0ufs_ice&quot;;
			qcom,bus-vector-names = &quot;MIN\0PWM_G1_L1\0PWM_G2_L1\0PWM_G3_L1\0PWM_G4_L1\0HS_RA_G1_L1\0HS_RA_G2_L1\0HS_RA_G3_L1\0HS_RB_G1_L1\0HS_RB_G2_L1\0HS_RB_G3_L1\0MAX&quot;;
			vcc-voltage-level = &lt;0x2d0370 0x2d2a80&gt;;
			qcom,msm-bus,name = &quot;ufshc_mem&quot;;
			non-removable;
			lanes-per-direction = &lt;0x01&gt;;
			qcom,vddp-ref-clk-max-microamp = &lt;0x64&gt;;
			resets = &lt;0x27 0x03&gt;;
			interrupts = &lt;0x00 0x109 0x00&gt;;
			clocks = &lt;0x27 0x7e 0x27 0x09 0x27 0x7d 0x27 0x89 0x27 0x81 0x2f 0x00 0x27 0x88 0x27 0x87&gt;;
			dev-ref-clk-freq = &lt;0x00&gt;;
			vccq2-supply = &lt;0x407&gt;;
			qcom,msm-bus,num-paths = &lt;0x02&gt;;
			qcom,msm-bus,num-cases = &lt;0x0c&gt;;
			vdd-hba-fixed-regulator;
			qcom,pm-qos-cpu-groups = &lt;0x3f 0xc0&gt;;
			rpm-level = &lt;0x03&gt;;
			compatible = &quot;qcom,ufshc&quot;;
			pinctrl-1 = &lt;0x9e&gt;;
			status = &quot;ok&quot;;
			phys = &lt;0x9c&gt;;
			vdd-hba-supply = &lt;0x9b&gt;;
			reg = &lt;0x1d84000 0x3000 0x1d90000 0x8000&gt;;
			phandle = &lt;0x2de&gt;;
			vccq2-voltage-level = &lt;0x1b7740 0x1dc130&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x7b 0x200 0x00 0x00 0x01 0x2f5 0x00 0x00 0x7b 0x200 0x39a 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x734 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0xe68 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1cd0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1f334 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x3e667 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x247ae 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x48ccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x74a000 0x00 0x01 0x2f5 0x4b000 0x00&gt;;
			vccq2-max-microamp = &lt;0x927c0&gt;;
			reset-names = &quot;core_reset&quot;;
			vcc-supply = &lt;0x40d&gt;;
			qcom,pm-qos-default-cpu = &lt;0x00&gt;;
			qcom,vddp-ref-clk-supply = &lt;0x1a8&gt;;
		};

wsa_npl_clk {
			qcom,codec-ext-clk-src = &lt;0x04&gt;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,audio-ref-clk&quot;;
			phandle = &lt;0x4e7&gt;;
			qcom,codec-lpass-clk-id = &lt;0x30a&gt;;
			qcom,codec-lpass-ext-clk-freq = &lt;0x124f800&gt;;
		};

qcom,smp2p-adsp {
			qcom,local-pid = &lt;0x00&gt;;
			interrupts = &lt;0x00 0xac 0x01&gt;;
			qcom,remote-pid = &lt;0x02&gt;;
			compatible = &quot;qcom,smp2p&quot;;
			qcom,smem = &lt;0x1bb 0x1ad&gt;;
			qcom,ipc = &lt;0x99 0x00 0x1a&gt;;

qcom,smp2p-rdbg2-out {
				qcom,entry-name = &quot;rdbg&quot;;
				#qcom,smem-state-cells = &lt;0x01&gt;;
				phandle = &lt;0x1bc&gt;;
			};

slave-kernel {
				qcom,entry-name = &quot;slave-kernel&quot;;
				#interrupt-cells = &lt;0x02&gt;;
				phandle = &lt;0xa2&gt;;
				interrupt-controller;
			};

qcom,sleepstate-in {
				qcom,entry-name = &quot;sleepstate_see&quot;;
				#interrupt-cells = &lt;0x02&gt;;
				phandle = &lt;0x98&gt;;
				interrupt-controller;
			};

sleepstate-out {
				qcom,entry-name = &quot;sleepstate&quot;;
				#qcom,smem-state-cells = &lt;0x01&gt;;
				phandle = &lt;0x97&gt;;
			};

master-kernel {
				qcom,entry-name = &quot;master-kernel&quot;;
				#qcom,smem-state-cells = &lt;0x01&gt;;
				phandle = &lt;0xa3&gt;;
			};

qcom,smp2p-rdbg2-in {
				qcom,entry-name = &quot;rdbg&quot;;
				#interrupt-cells = &lt;0x02&gt;;
				phandle = &lt;0x1bd&gt;;
				interrupt-controller;
			};
		};

qcom,dsi-display@15 {
			qcom,dsi-phy-num = &lt;0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk1\0mux_pixel_clk1&quot;;
			qcom,dsi-panel = &lt;0x52f&gt;;
			qcom,dsi-ctrl-num = &lt;0x01&gt;;
			qcom,display-type = &quot;secondary&quot;;
			label = &quot;dsi_nt35695b_truly_fhd_video_sec_display&quot;;
			phandle = &lt;0x55c&gt;;
		};

cdc_dmic01_pinctrl {
			pinctrl-names = &quot;aud_active\0aud_sleep&quot;;
			pinctrl-0 = &lt;0x4f7 0x4f8&gt;;
			compatible = &quot;qcom,msm-cdc-pinctrl&quot;;
			qcom,lpi-gpios;
			pinctrl-1 = &lt;0x4f9 0x4fa&gt;;
			phandle = &lt;0x4ef&gt;;
		};

qcom,mdss_dsi_phy1@ae96400 {
			qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00];
			reg-names = &quot;dsi_phy\0dyn_refresh_base&quot;;
			cell-index = &lt;0x01&gt;;
			label = &quot;dsi-phy-1&quot;;
			qcom,platform-lane-config = &lt;0x00 0x00 0x00 0x00 0x80&gt;;
			compatible = &quot;qcom,dsi-phy-v3.0&quot;;
			vdda-0p9-supply = &lt;0x1a9&gt;;
			qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
			reg = &lt;0xae96400 0x7c0 0xae96200 0x100&gt;;
			phandle = &lt;0x375&gt;;

qcom,phy-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

qcom,phy-supply-entry@0 {
					qcom,supply-disable-load = &lt;0x00&gt;;
					qcom,supply-enable-load = &lt;0x8ca0&gt;;
					qcom,supply-name = &quot;vdda-0p9&quot;;
					qcom,supply-max-voltage = &lt;0xe09c0&gt;;
					reg = &lt;0x00&gt;;
					qcom,supply-min-voltage = &lt;0xc92c0&gt;;
				};
			};
		};

qcom,kgsl-hyp {
			qcom,pas-id = &lt;0x0d&gt;;
			compatible = &quot;qcom,pil-tz-generic&quot;;
			phandle = &lt;0x4ce&gt;;
			qcom,firmware-name = &quot;a615_zap&quot;;
		};

tsens@c222000 {
			reg-names = &quot;tsens_srot_physical\0tsens_tm_physical&quot;;
			interrupts = &lt;0x00 0x1fa 0x00 0x00 0x1fc 0x00&gt;;
			#thermal-sensor-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,tsens24xx&quot;;
			interrupt-names = &quot;tsens-upper-lower\0tsens-critical&quot;;
			reg = &lt;0xc222000 0x08 0xc263000 0x1ff&gt;;
			phandle = &lt;0x59&gt;;
			tsens-reinit-wa;
		};

qcom,cpu6-cpu-l3-lat {
			clock-names = &quot;devfreq_clk&quot;;
			clocks = &lt;0xc0 0x01&gt;;
			governor = &quot;performance&quot;;
			compatible = &quot;devfreq-simple-dev&quot;;
			phandle = &lt;0x25&gt;;
		};

rpmh-regulator-ldoc4 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoc4&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150l-l4 {
				regulator-max-microvolt = &lt;0x2d0370&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x192580&gt;;
				regulator-min-microvolt = &lt;0x192580&gt;;
				regulator-name = &quot;pm6150l_l4&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x40e&gt;;
			};
		};

usb_audio_qmi_dev {
			iommus = &lt;0x30 0x1b2f 0x00&gt;;
			qcom,usb-audio-intr-num = &lt;0x02&gt;;
			compatible = &quot;qcom,usb-audio-qmi-dev&quot;;
			qcom,usb-audio-stream-id = &lt;0x0f&gt;;
		};

qcom,msm-adsprpc-mem {
			restrict-access;
			memory-region = &lt;0x92&gt;;
			compatible = &quot;qcom,msm-adsprpc-mem-region&quot;;
		};

qcom,msm_hdcp {
			compatible = &quot;qcom,msm-hdcp&quot;;
			phandle = &lt;0x2e0&gt;;
		};

ad-hoc-bus {
			reg-names = &quot;aggre1_noc-base\0aggre2_noc-base\0config_noc-base\0dc_noc-base\0gem_noc-base\0mc_virt-base\0mmss_noc-base\0system_noc-base\0ipa_virt-base\0camnoc_virt-base\0compute_noc-base&quot;;
			compatible = &quot;qcom,msm-bus-device&quot;;
			reg = &lt;0x16e0000 0x11080 0x1700000 0x1f080 0x1500000 0x28000 0x9160000 0x3200 0x9680000 0x3e200 0x1380000 0x40000 0x1740000 0x1c100 0x1620000 0x18080 0x1620000 0x40000 0x1620000 0x40000 0x80a8000 0x1400&gt;;
			phandle = &lt;0x322&gt;;
			mboxes = &lt;0x1b 0x00 0xcf 0x00&gt;;
			mbox-names = &quot;apps_rsc\0disp_rsc&quot;;

mas-qhm-gemnoc-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x9d&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-qhm-gemnoc-cfg&quot;;
				qcom,connections = &lt;0x11b 0x11c&gt;;
				phandle = &lt;0x14b&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

slv-qns-gemnoc-gc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2758&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;slv-qns-gemnoc-gc&quot;;
				qcom,connections = &lt;0x157&gt;;
				phandle = &lt;0x133&gt;;
				qcom,bcms = &lt;0x158&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

mas-qhm-mnoc-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x67&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-qhm-mnoc-cfg&quot;;
				qcom,connections = &lt;0x121&gt;;
				phandle = &lt;0x148&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

bcm-mm3_display {
				qcom,rscs = &lt;0xd1&gt;;
				cell-id = &lt;0x697d&gt;;
				label = &quot;MM3_DISPLAY&quot;;
				qcom,bcm-name = &quot;MM3&quot;;
				phandle = &lt;0x13e&gt;;
				qcom,bcm-dev;
			};

mas-qnm-gemnoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0xa1&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-qnm-gemnoc&quot;;
				qcom,connections = &lt;0x12a 0x12b 0x12c 0x12d 0x130 0x12e&gt;;
				phandle = &lt;0x14c&gt;;
				qcom,bcms = &lt;0x132&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

mas-qhm-tsif {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x52&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-qhm-tsif&quot;;
				qcom,connections = &lt;0xd4&gt;;
				phandle = &lt;0x325&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xd3&gt;;
			};

bcm-alc {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b7f&gt;;
				label = &quot;ALC&quot;;
				qcom,bcm-name = &quot;ALC&quot;;
				phandle = &lt;0x135&gt;;
				qcom,bcm-dev;
			};

slv-qhs-snoc-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x282&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-snoc-cfg&quot;;
				qcom,connections = &lt;0x149&gt;;
				phandle = &lt;0xf8&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

bcm-sn12 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b76&gt;;
				label = &quot;SN12&quot;;
				qcom,bcm-name = &quot;SN12&quot;;
				phandle = &lt;0x134&gt;;
				qcom,bcm-dev;
			};

bcm-sn0 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b6a&gt;;
				label = &quot;SN0&quot;;
				qcom,bcm-name = &quot;SN0&quot;;
				phandle = &lt;0x15a&gt;;
				qcom,bcm-dev;
			};

slv-qns2-mem-noc_display {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x5022&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;slv-qns2-mem-noc_display&quot;;
				qcom,connections = &lt;0x161&gt;;
				phandle = &lt;0x13d&gt;;
				qcom,bcms = &lt;0x162&gt;;
				qcom,bus-dev = &lt;0x13b&gt;;
			};

bcm-acv_display {
				qcom,rscs = &lt;0xd1&gt;;
				cell-id = &lt;0x697e&gt;;
				label = &quot;ACV_DISPLAY&quot;;
				qcom,bcm-name = &quot;ACV&quot;;
				phandle = &lt;0x160&gt;;
				qcom,bcm-dev;
			};

slv-qns-a2noc-snoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2751&gt;;
				qcom,buswidth = &lt;0x10&gt;;
				label = &quot;slv-qns-a2noc-snoc&quot;;
				qcom,connections = &lt;0x140&gt;;
				phandle = &lt;0xd9&gt;;
				qcom,bcms = &lt;0x131&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;
			};

mas-qnm-mnoc-sf {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0x85&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qnm-mnoc-sf&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x116 0x117&gt;;
				qcom,qport = &lt;0x140&gt;;
				phandle = &lt;0x153&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

slv-srvc-cnoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x286&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-srvc-cnoc&quot;;
				phandle = &lt;0x101&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qhs-venus-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x254&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-venus-cfg&quot;;
				phandle = &lt;0xfa&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
				qcom,disable-ports = &lt;0x4b 0x4c&gt;;
			};

slv-qhs-pdm {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x267&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-pdm&quot;;
				phandle = &lt;0xec&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

bcm-mm0 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b63&gt;;
				label = &quot;MM0&quot;;
				qcom,bcm-name = &quot;MM0&quot;;
				phandle = &lt;0x155&gt;;
				qcom,bcm-dev;
			};

slv-qns-llcc {
				qcom,agg-ports = &lt;0x02&gt;;
				cell-id = &lt;0x302&gt;;
				qcom,buswidth = &lt;0x10&gt;;
				label = &quot;slv-qns-llcc&quot;;
				qcom,connections = &lt;0x14e&gt;;
				phandle = &lt;0x116&gt;;
				qcom,bcms = &lt;0x14f&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

slv-qhs-ipa {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2a4&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-ipa&quot;;
				phandle = &lt;0x105&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qhs-ahb2phy-north {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x327&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-ahb2phy-north&quot;;
				phandle = &lt;0xf7&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

bcm-cn0 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b7c&gt;;
				label = &quot;CN0&quot;;
				qcom,bcm-name = &quot;CN0&quot;;
				phandle = &lt;0xd6&gt;;
				qcom,bcm-dev;
			};

slv-qhs-camera-nrt-thrott-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x328&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-camera-nrt-throttle-cfg&quot;;
				phandle = &lt;0xed&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

bcm-sn9 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b73&gt;;
				label = &quot;SN9&quot;;
				qcom,bcm-name = &quot;SN9&quot;;
				phandle = &lt;0x12f&gt;;
				qcom,bcm-dev;
			};

bcm-sh2 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b5d&gt;;
				label = &quot;SH2&quot;;
				qcom,bcm-name = &quot;SH2&quot;;
				phandle = &lt;0x14d&gt;;
				qcom,bcm-dev;
			};

slv-qhs-ufs-mem-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2f5&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-ufs-mem-cfg&quot;;
				phandle = &lt;0xe9&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qhs-tlmm-west {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2dc&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-tlmm-west&quot;;
				phandle = &lt;0x107&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

fab-mc_virt {
				qcom,base-name = &quot;mc_virt-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				cell-id = &lt;0x1807&gt;;
				qcom,bypass-qos-prg;
				clocks;
				label = &quot;fab-mc_virt&quot;;
				qcom,base-offset = &lt;0x00&gt;;
				qcom,fab-dev;
				phandle = &lt;0x120&gt;;
				qcom,qos-off = &lt;0x00&gt;;
			};

slv-qhs-camera-rt-throttle-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x329&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-camera-rt-throttle-cfg&quot;;
				phandle = &lt;0xf0&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

bcm-mc0_display {
				qcom,rscs = &lt;0xd1&gt;;
				cell-id = &lt;0x6978&gt;;
				label = &quot;MC0_DISPLAY&quot;;
				qcom,bcm-name = &quot;MC0&quot;;
				phandle = &lt;0x15f&gt;;
				qcom,bcm-dev;
			};

mas-qxm-mdp0_display {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x4e23&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-mdp0_display&quot;;
				qcom,connections = &lt;0x13a&gt;;
				qcom,qport = &lt;0x60&gt;;
				phandle = &lt;0x349&gt;;
				qcom,bcms = &lt;0x13c&gt;;
				qcom,bus-dev = &lt;0x13b&gt;;
			};

slv-qhs-usb3-0 {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x247&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-usb3-0&quot;;
				phandle = &lt;0x103&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-qhm-qup-north {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x98&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-qhm-qup-north&quot;;
				qcom,connections = &lt;0xd9&gt;;
				qcom,qport = &lt;0x00&gt;;
				phandle = &lt;0x32b&gt;;
				qcom,bcms = &lt;0xd5&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;
			};

slv-qns-mem-noc-hf {
				qcom,agg-ports = &lt;0x02&gt;;
				cell-id = &lt;0x305&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;slv-qns-mem-noc-hf&quot;;
				qcom,connections = &lt;0x154&gt;;
				phandle = &lt;0x123&gt;;
				qcom,bcms = &lt;0x155&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

slv-qns2-mem-noc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x304&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;slv-qns2-mem-noc&quot;;
				qcom,connections = &lt;0x153&gt;;
				phandle = &lt;0x124&gt;;
				qcom,bcms = &lt;0x125&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

mas-qxm-camnoc-rt {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0xac&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-camnoc-rt&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x123&gt;;
				qcom,qport = &lt;0x101&gt;;
				phandle = &lt;0x33e&gt;;
				qcom,bcms = &lt;0xde&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

fab-ipa_virt {
				qcom,base-name = &quot;ipa_virt-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				cell-id = &lt;0x1809&gt;;
				qcom,bypass-qos-prg;
				clocks;
				label = &quot;fab-ipa_virt&quot;;
				qcom,base-offset = &lt;0x00&gt;;
				qcom,fab-dev;
				phandle = &lt;0x11e&gt;;
				qcom,qos-off = &lt;0x00&gt;;
			};

slv-qns-cnoc-a2noc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2d5&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;slv-qns-cnoc-a2noc&quot;;
				qcom,connections = &lt;0x14a&gt;;
				phandle = &lt;0xe2&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-xm-ufs-mem {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x7b&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-xm-ufs-mem&quot;;
				qcom,connections = &lt;0xd4&gt;;
				qcom,qport = &lt;0x04&gt;;
				phandle = &lt;0x329&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd3&gt;;

qcom,node-qos-clks {
					clock-names = &quot;clk-aggre-ufs-phy-axi-no-rate&quot;;
					clocks = &lt;0x27 0x09&gt;;
				};
			};

mas-xm-qdss-dap {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x4c&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-xm-qdss-dap&quot;;
				qcom,connections = &lt;0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xe2 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109 0x10a 0x10b 0x10c 0x10d 0x10e 0x10f 0x110 0x111 0x112&gt;;
				phandle = &lt;0x337&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

fab-gem_noc {
				qcom,base-name = &quot;gem_noc-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				qcom,bus-type = &lt;0x01&gt;;
				cell-id = &lt;0x180c&gt;;
				clocks;
				label = &quot;fab-gem_noc&quot;;
				qcom,base-offset = &lt;0x2b000&gt;;
				qcom,fab-dev;
				phandle = &lt;0x118&gt;;
				qcom,qos-off = &lt;0x80&gt;;
			};

bcm-sh0 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b5b&gt;;
				label = &quot;SH0&quot;;
				qcom,bcm-name = &quot;SH0&quot;;
				phandle = &lt;0x14f&gt;;
				qcom,bcm-dev;
			};

mas-qnm-snoc-gc {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x86&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-qnm-snoc-gc&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x116&gt;;
				qcom,qport = &lt;0xc0&gt;;
				phandle = &lt;0x157&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

slv-qhs-qupv3-center {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x313&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-qupv3-center&quot;;
				phandle = &lt;0xea&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qns-cnoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2734&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;slv-qns-cnoc&quot;;
				qcom,connections = &lt;0x156&gt;;
				phandle = &lt;0x12d&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

slv-qhs-mnoc-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x280&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-mnoc-cfg&quot;;
				qcom,connections = &lt;0x148&gt;;
				phandle = &lt;0xe8&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-srvc-gemnoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x316&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-srvc-gemnoc&quot;;
				phandle = &lt;0x11b&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

slv-qhs-a2-noc-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2b0&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-a2-noc-cfg&quot;;
				qcom,connections = &lt;0x146&gt;;
				phandle = &lt;0xee&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-qnm-snoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2733&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-qnm-snoc&quot;;
				qcom,connections = &lt;0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109 0x10a 0x10b 0x10c 0x10d 0x10e 0x10f 0x110 0x111 0x112&gt;;
				phandle = &lt;0x156&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

fab-camnoc_virt {
				qcom,base-name = &quot;camnoc_virt-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				cell-id = &lt;0x180a&gt;;
				qcom,bypass-qos-prg;
				clocks;
				label = &quot;fab-camnoc_virt&quot;;
				qcom,base-offset = &lt;0x00&gt;;
				qcom,fab-dev;
				phandle = &lt;0xdd&gt;;
				qcom,qos-off = &lt;0x00&gt;;
			};

mas-qnm-npu {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x9a&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qnm-npu&quot;;
				qcom,connections = &lt;0xdf&gt;;
				qcom,qport = &lt;0x01&gt;;
				phandle = &lt;0x335&gt;;
				qcom,bcms = &lt;0xe1&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0xe0&gt;;
			};

mas-xm-gic {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x95&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-xm-gic&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x133 0x12b&gt;;
				qcom,qport = &lt;0x00&gt;;
				phandle = &lt;0x347&gt;;
				qcom,bcms = &lt;0x134&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

bcm-acv {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b7e&gt;;
				label = &quot;ACV&quot;;
				qcom,bcm-name = &quot;ACV&quot;;
				phandle = &lt;0x152&gt;;
				qcom,bcm-dev;
			};

fab-system_noc {
				qcom,base-name = &quot;system_noc-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				qcom,bus-type = &lt;0x01&gt;;
				cell-id = &lt;0x400&gt;;
				clocks;
				label = &quot;fab-system_noc&quot;;
				qcom,base-offset = &lt;0xa000&gt;;
				qcom,fab-dev;
				phandle = &lt;0x128&gt;;
				qcom,qos-off = &lt;0x1000&gt;;
			};

slv-qhs-prng {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x26a&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-prng&quot;;
				phandle = &lt;0x10a&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-qxm-camnoc-hf {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x02&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0x88&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-camnoc-hf&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x123&gt;;
				qcom,qport = &lt;0x20 0x40&gt;;
				phandle = &lt;0x33c&gt;;
				qcom,bcms = &lt;0xde&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

slv-qhs-pcie-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x28d&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-pcie-cfg&quot;;
				phandle = &lt;0xf2&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qns-gem-noc-snoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2757&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;slv-qns-gem-noc-snoc&quot;;
				qcom,connections = &lt;0x14c&gt;;
				phandle = &lt;0x117&gt;;
				qcom,bcms = &lt;0x14d&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

slv-qhs-tsif {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x23f&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-tsif&quot;;
				phandle = &lt;0xfb&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qhs-aop {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2eb&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-aop&quot;;
				phandle = &lt;0xfe&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-ebi_display {
				qcom,agg-ports = &lt;0x02&gt;;
				cell-id = &lt;0x5020&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-ebi_display&quot;;
				phandle = &lt;0x138&gt;;
				qcom,bcms = &lt;0x15f 0x160&gt;;
				qcom,bus-dev = &lt;0x139&gt;;
			};

mas-qxm-camnoc-sf-uncomp {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x94&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-camnoc-sf-uncomp&quot;;
				qcom,connections = &lt;0xdc&gt;;
				phandle = &lt;0x333&gt;;
				qcom,bcms = &lt;0xde&gt;;
				qcom,bus-dev = &lt;0xdd&gt;;
			};

bcm-mm0_display {
				qcom,rscs = &lt;0xd1&gt;;
				cell-id = &lt;0x697a&gt;;
				label = &quot;MM0_DISPLAY&quot;;
				qcom,bcm-name = &quot;MM0&quot;;
				phandle = &lt;0x164&gt;;
				qcom,bcm-dev;
			};

slv-qhs-gpuss-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x256&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;slv-qhs-gpuss-cfg&quot;;
				phandle = &lt;0xf9&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-qnm-mnoc-hf_display {
				qcom,agg-ports = &lt;0x02&gt;;
				cell-id = &lt;0x4e21&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qnm-mnoc-hf_display&quot;;
				qcom,connections = &lt;0x136&gt;;
				qcom,qport = &lt;0x80 0x81&gt;;
				phandle = &lt;0x163&gt;;
				qcom,bus-dev = &lt;0x137&gt;;
			};

slv-srvc-snoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x24b&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-srvc-snoc&quot;;
				phandle = &lt;0x127&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

slv-qns-cdsp-gemnoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x275c&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;slv-qns-cdsp-gemnoc&quot;;
				qcom,connections = &lt;0x143&gt;;
				phandle = &lt;0xdf&gt;;
				qcom,bcms = &lt;0x144&gt;;
				qcom,bus-dev = &lt;0xe0&gt;;
			};

bcm-ce0 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b7a&gt;;
				label = &quot;CE0&quot;;
				qcom,bcm-name = &quot;CE0&quot;;
				phandle = &lt;0xda&gt;;
				qcom,bcm-dev;
			};

fab-mmss_noc_display {
				qcom,base-name = &quot;mmss_noc-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				qcom,bus-type = &lt;0x01&gt;;
				cell-id = &lt;0x6592&gt;;
				qcom,bypass-qos-prg;
				clocks;
				label = &quot;fab-mmss_noc_display&quot;;
				qcom,base-offset = &lt;0x9000&gt;;
				qcom,fab-dev;
				phandle = &lt;0x13b&gt;;
				qcom,qos-off = &lt;0x80&gt;;
			};

slv-qhs-tcsr {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x26f&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-tcsr&quot;;
				phandle = &lt;0xf4&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qhs-tlmm-north {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2db&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-tlmm-north&quot;;
				phandle = &lt;0x110&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qhs-pimem-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2a9&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-pimem-cfg&quot;;
				phandle = &lt;0x10f&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

bcm-mc0 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b58&gt;;
				label = &quot;MC0&quot;;
				qcom,bcm-name = &quot;MC0&quot;;
				phandle = &lt;0x151&gt;;
				qcom,bcm-dev;
			};

slv-qhs-apss {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2a1&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;slv-qhs-apss&quot;;
				phandle = &lt;0x12c&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

slv-qhs-vsense-ctrl-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2f6&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-vsense-ctrl-cfg&quot;;
				phandle = &lt;0x10b&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

bcm-sn15 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b79&gt;;
				label = &quot;SN15&quot;;
				qcom,bcm-name = &quot;SN15&quot;;
				phandle = &lt;0x132&gt;;
				qcom,bcm-dev;
			};

slv-ebi {
				qcom,agg-ports = &lt;0x02&gt;;
				cell-id = &lt;0x200&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-ebi&quot;;
				phandle = &lt;0x11f&gt;;
				qcom,bcms = &lt;0x151 0x152&gt;;
				qcom,bus-dev = &lt;0x120&gt;;
			};

mas-qxm-camnoc-sf {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0x89&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-camnoc-sf&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x124&gt;;
				qcom,qport = &lt;0x00&gt;;
				phandle = &lt;0x33f&gt;;
				qcom,bcms = &lt;0x126&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

bcm-sh0_display {
				qcom,rscs = &lt;0xd1&gt;;
				cell-id = &lt;0x6979&gt;;
				label = &quot;SH0_DISPLAY&quot;;
				qcom,bcm-name = &quot;SH0&quot;;
				phandle = &lt;0x15e&gt;;
				qcom,bcm-dev;
			};

mas-qnm-cmpnoc {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x9e&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qnm-cmpnoc&quot;;
				qcom,connections = &lt;0x116 0x117&gt;;
				qcom,qport = &lt;0x40&gt;;
				phandle = &lt;0x143&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

mas-qxm-venus-arm9 {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0x8a&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-qxm-venus-arm9&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x124&gt;;
				qcom,qport = &lt;0x100&gt;;
				phandle = &lt;0x345&gt;;
				qcom,bcms = &lt;0x126&gt;;
				qcom,prio = &lt;0x05&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

slv-qhs-llcc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2f8&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-llcc&quot;;
				phandle = &lt;0x113&gt;;
				qcom,bus-dev = &lt;0x115&gt;;
			};

mas-qxm-camnoc-nrt {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0xab&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-qxm-camnoc-nrt&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x124&gt;;
				qcom,qport = &lt;0x102&gt;;
				phandle = &lt;0x33d&gt;;
				qcom,bcms = &lt;0x125&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

mas-qxm-venus0 {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0x3f&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-venus0&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x124&gt;;
				qcom,qport = &lt;0xc0&gt;;
				phandle = &lt;0x343&gt;;
				qcom,bcms = &lt;0x126&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

slv-qhs-gemnoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x314&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-gemnoc&quot;;
				qcom,connections = &lt;0x14b&gt;;
				phandle = &lt;0x114&gt;;
				qcom,bus-dev = &lt;0x115&gt;;
			};

slv-qns-mem-noc-hf_display {
				qcom,agg-ports = &lt;0x02&gt;;
				cell-id = &lt;0x5023&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;slv-qns-mem-noc-hf_display&quot;;
				qcom,connections = &lt;0x163&gt;;
				phandle = &lt;0x13a&gt;;
				qcom,bcms = &lt;0x164&gt;;
				qcom,bus-dev = &lt;0x13b&gt;;
			};

bcm-mm3 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b66&gt;;
				label = &quot;MM3&quot;;
				qcom,bcm-name = &quot;MM3&quot;;
				phandle = &lt;0x126&gt;;
				qcom,bcm-dev;
			};

slv-xs-sys-tcu-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2a0&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;slv-xs-sys-tcu-cfg&quot;;
				phandle = &lt;0x130&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

bcm-mm2_display {
				qcom,rscs = &lt;0xd1&gt;;
				cell-id = &lt;0x697c&gt;;
				label = &quot;MM2_DISPLAY&quot;;
				qcom,bcm-name = &quot;MM2&quot;;
				phandle = &lt;0x162&gt;;
				qcom,bcm-dev;
			};

mas-qxm-mdp0 {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0x16&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-mdp0&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x123&gt;;
				qcom,qport = &lt;0x60&gt;;
				phandle = &lt;0x340&gt;;
				qcom,bcms = &lt;0xde&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

bcm-sh5 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b60&gt;;
				label = &quot;SH5&quot;;
				qcom,bcm-name = &quot;SH5&quot;;
				phandle = &lt;0x119&gt;;
				qcom,bcm-dev;
			};

slv-qhs-cpr-mx {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x28c&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-cpr-mx&quot;;
				phandle = &lt;0x111&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qns-gemnoc-sf {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2759&gt;;
				qcom,buswidth = &lt;0x10&gt;;
				label = &quot;slv-qns-gemnoc-sf&quot;;
				qcom,connections = &lt;0x159&gt;;
				phandle = &lt;0x129&gt;;
				qcom,bcms = &lt;0x15a&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

slv-qns-a1noc-snoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x274e&gt;;
				qcom,buswidth = &lt;0x10&gt;;
				label = &quot;slv-qns-a1noc-snoc&quot;;
				qcom,connections = &lt;0x13f&gt;;
				phandle = &lt;0xd4&gt;;
				qcom,bcms = &lt;0x12f&gt;;
				qcom,bus-dev = &lt;0xd3&gt;;
			};

mas-acm-apps {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x01&gt;;
				qcom,buswidth = &lt;0x10&gt;;
				label = &quot;mas-acm-apps&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x116 0x117&gt;;
				qcom,qport = &lt;0x60 0x62&gt;;
				phandle = &lt;0x338&gt;;
				qcom,bcms = &lt;0x119&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

bcm-qup0 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b80&gt;;
				label = &quot;QUP0&quot;;
				qcom,bcm-name = &quot;QUP0&quot;;
				phandle = &lt;0xd5&gt;;
				qcom,bcm-dev;
			};

bcm-sn1 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b6b&gt;;
				label = &quot;SN1&quot;;
				qcom,bcm-name = &quot;SN1&quot;;
				phandle = &lt;0x15b&gt;;
				qcom,bcm-dev;
			};

slv-qhs-ahb2phy-south {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x30b&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-ahb2phy-south&quot;;
				phandle = &lt;0x100&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

fab-mc_virt_display {
				qcom,base-name = &quot;mc_virt-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				cell-id = &lt;0x6590&gt;;
				qcom,bypass-qos-prg;
				clocks;
				label = &quot;fab-mc_virt_display&quot;;
				qcom,base-offset = &lt;0x00&gt;;
				qcom,fab-dev;
				phandle = &lt;0x139&gt;;
				qcom,qos-off = &lt;0x00&gt;;
			};

fab-aggre1_noc {
				qcom,base-name = &quot;aggre1_noc-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				qcom,bus-type = &lt;0x01&gt;;
				cell-id = &lt;0x1802&gt;;
				clocks;
				label = &quot;fab-aggre1_noc&quot;;
				qcom,base-offset = &lt;0x4000&gt;;
				qcom,fab-dev;
				phandle = &lt;0xd3&gt;;
				qcom,qos-off = &lt;0x1000&gt;;
			};

slv-srvc-aggre1-noc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2e8&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-srvc-aggre1-noc&quot;;
				phandle = &lt;0xd2&gt;;
				qcom,bus-dev = &lt;0xd3&gt;;
			};

slv-qhs-crypto0-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x271&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-crypto0-cfg&quot;;
				phandle = &lt;0x10e&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-qxm-camnoc-hf0-uncomp {
				qcom,agg-ports = &lt;0x02&gt;;
				cell-id = &lt;0x92&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-camnoc-hf0-uncomp&quot;;
				qcom,connections = &lt;0xdc&gt;;
				phandle = &lt;0x331&gt;;
				qcom,bcms = &lt;0xde&gt;;
				qcom,bus-dev = &lt;0xdd&gt;;
			};

mas-xm-sdc4 {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x50&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-xm-sdc4&quot;;
				qcom,connections = &lt;0xd4&gt;;
				qcom,qport = &lt;0x02&gt;;
				phandle = &lt;0x328&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd3&gt;;
			};

slv-qhs-compute-dsp-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2ed&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-compute-dsp-cfg&quot;;
				phandle = &lt;0xfc&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-qxm-rot_display {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x4e25&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-rot_display&quot;;
				qcom,connections = &lt;0x13d&gt;;
				qcom,qport = &lt;0xa0&gt;;
				phandle = &lt;0x34b&gt;;
				qcom,bcms = &lt;0x13e&gt;;
				qcom,bus-dev = &lt;0x13b&gt;;
			};

bcm-mm1 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b64&gt;;
				label = &quot;MM1&quot;;
				qcom,bcm-name = &quot;MM1&quot;;
				phandle = &lt;0xde&gt;;
				qcom,bcm-dev;
			};

fab-mmss_noc {
				qcom,base-name = &quot;mmss_noc-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				qcom,bus-type = &lt;0x01&gt;;
				cell-id = &lt;0x800&gt;;
				clocks;
				label = &quot;fab-mmss_noc&quot;;
				qcom,base-offset = &lt;0x9000&gt;;
				qcom,fab-dev;
				phandle = &lt;0x122&gt;;
				qcom,qos-off = &lt;0x80&gt;;
			};

bcm-sh3 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b5e&gt;;
				label = &quot;SH3&quot;;
				qcom,bcm-name = &quot;SH3&quot;;
				phandle = &lt;0x11a&gt;;
				qcom,bcm-dev;
			};

slv-qhs-ahb2phy-west {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x319&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-ahb2phy-west&quot;;
				phandle = &lt;0x102&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-qxm-rot {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0x19&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-rot&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x124&gt;;
				qcom,qport = &lt;0xa0&gt;;
				phandle = &lt;0x342&gt;;
				qcom,bcms = &lt;0x126&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

mas-qhm-spdm {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x24&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-qhm-spdm&quot;;
				qcom,connections = &lt;0xe2&gt;;
				phandle = &lt;0x336&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

bcm-sn11 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b75&gt;;
				label = &quot;SN11&quot;;
				qcom,bcm-name = &quot;SN11&quot;;
				phandle = &lt;0x131&gt;;
				qcom,bcm-dev;
			};

slv-qns-camnoc-uncomp {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x30a&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;slv-qns-camnoc-uncomp&quot;;
				phandle = &lt;0xdc&gt;;
				qcom,bus-dev = &lt;0xdd&gt;;
			};

slv-qxs-pimem {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2c8&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;slv-qxs-pimem&quot;;
				phandle = &lt;0x12a&gt;;
				qcom,bcms = &lt;0x15c&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

fab-dc_noc {
				qcom,base-name = &quot;dc_noc-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				qcom,bus-type = &lt;0x01&gt;;
				cell-id = &lt;0x1806&gt;;
				qcom,bypass-qos-prg;
				clocks;
				label = &quot;fab-dc_noc&quot;;
				qcom,base-offset = &lt;0x00&gt;;
				qcom,fab-dev;
				phandle = &lt;0x115&gt;;
				qcom,qos-off = &lt;0x00&gt;;
			};

mas-qxm-pimem {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x8d&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-qxm-pimem&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x133 0x12b&gt;;
				qcom,qport = &lt;0x03&gt;;
				phandle = &lt;0x346&gt;;
				qcom,bcms = &lt;0x134&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

mas-qnm-mnoc-sf_display {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x4e22&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qnm-mnoc-sf_display&quot;;
				qcom,connections = &lt;0x136&gt;;
				qcom,qport = &lt;0x140&gt;;
				phandle = &lt;0x161&gt;;
				qcom,bus-dev = &lt;0x137&gt;;
			};

mas-xm-sdc2 {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x51&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-xm-sdc2&quot;;
				qcom,connections = &lt;0xd4&gt;;
				qcom,qport = &lt;0x01&gt;;
				phandle = &lt;0x327&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd3&gt;;
			};

slv-qhs-display-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x24e&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-display-cfg&quot;;
				phandle = &lt;0xf1&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
				qcom,disable-ports = &lt;0x48 0x49&gt;;
			};

mas-acm-sys-tcu {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x9c&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-acm-sys-tcu&quot;;
				qcom,connections = &lt;0x116 0x117&gt;;
				qcom,qport = &lt;0x180&gt;;
				phandle = &lt;0x339&gt;;
				qcom,bcms = &lt;0x11a&gt;;
				qcom,prio = &lt;0x06&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

slv-srvc-mnoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x25b&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-srvc-mnoc&quot;;
				phandle = &lt;0x121&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

mas-qxm-camnoc-nrt-uncomp {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0xb3&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-camnoc-nrt-uncomp&quot;;
				qcom,connections = &lt;0xdc&gt;;
				phandle = &lt;0x334&gt;;
				qcom,bcms = &lt;0xde&gt;;
				qcom,bus-dev = &lt;0xdd&gt;;
			};

slv-qhs-a1-noc-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2af&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-a1-noc-cfg&quot;;
				qcom,connections = &lt;0x145&gt;;
				phandle = &lt;0x108&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

bcm-ip0 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b7b&gt;;
				label = &quot;IP0&quot;;
				qcom,bcm-name = &quot;IP0&quot;;
				phandle = &lt;0x150&gt;;
				qcom,bcm-dev;
			};

mas-qnm-pcie {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x9f&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-qnm-pcie&quot;;
				qcom,connections = &lt;0x116 0x117&gt;;
				qcom,qport = &lt;0xe0&gt;;
				phandle = &lt;0x141&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

mas-qhm-cnoc-dc-noc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x7e&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-qhm-cnoc-dc-noc&quot;;
				qcom,connections = &lt;0x113 0x114&gt;;
				phandle = &lt;0x147&gt;;
				qcom,bus-dev = &lt;0x115&gt;;
			};

mas-qnm-snoc-sf {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x87&gt;;
				qcom,buswidth = &lt;0x10&gt;;
				label = &quot;mas-qnm-snoc-sf&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x116&gt;;
				qcom,qport = &lt;0xa0&gt;;
				phandle = &lt;0x159&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

slv-qhs-ddrss-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2ee&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-ddrss-cfg&quot;;
				qcom,connections = &lt;0x147&gt;;
				phandle = &lt;0xf6&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-xs-qdss-stm {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x24c&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-xs-qdss-stm&quot;;
				phandle = &lt;0x12e&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

mas-qnm-aggre1-noc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x274f&gt;;
				qcom,buswidth = &lt;0x10&gt;;
				label = &quot;mas-qnm-aggre1-noc&quot;;
				qcom,connections = &lt;0x129 0x12a 0x12b 0x12c 0x12d 0x12e&gt;;
				phandle = &lt;0x13f&gt;;
				qcom,bcms = &lt;0x12f&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

mas-xm-qdss-etr {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x3c&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-xm-qdss-etr&quot;;
				qcom,connections = &lt;0xd9&gt;;
				qcom,qport = &lt;0x09&gt;;
				phandle = &lt;0x32f&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;
			};

slv-qhs-mdsp-ms-mpu-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2fd&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-mdsp-ms-mpu-cfg&quot;;
				phandle = &lt;0x11c&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

mas-qxm-mdp1_display {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x4e24&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-mdp1_display&quot;;
				qcom,connections = &lt;0x13a&gt;;
				qcom,qport = &lt;0x80&gt;;
				phandle = &lt;0x34a&gt;;
				qcom,bcms = &lt;0x13c&gt;;
				qcom,bus-dev = &lt;0x13b&gt;;
			};

mas-qhm-qup-center {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x97&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-qhm-qup-center&quot;;
				qcom,connections = &lt;0xd4&gt;;
				qcom,qport = &lt;0x05&gt;;
				phandle = &lt;0x324&gt;;
				qcom,bcms = &lt;0xd5&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd3&gt;;
			};

slv-qhs-display-throttle-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2bc&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-display-throttle-cfg&quot;;
				phandle = &lt;0xf3&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

bcm-alc_display {
				qcom,rscs = &lt;0xd1&gt;;
				cell-id = &lt;0x697f&gt;;
				label = &quot;ALC_DISPLAY&quot;;
				qcom,bcm-name = &quot;ALC&quot;;
				phandle = &lt;0x323&gt;;
				qcom,bcm-dev;
			};

slv-qhs-cpr-cx {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x28b&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-cpr-cx&quot;;
				phandle = &lt;0x106&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qhs-tlmm-south {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2f3&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-tlmm-south&quot;;
				phandle = &lt;0xe4&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qhs-sdc4 {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x261&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-sdc4&quot;;
				phandle = &lt;0xe6&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

fab-aggre2_noc {
				qcom,base-name = &quot;aggre2_noc-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				qcom,bus-type = &lt;0x01&gt;;
				cell-id = &lt;0x1803&gt;;
				clocks;
				label = &quot;fab-aggre2_noc&quot;;
				qcom,base-offset = &lt;0x5000&gt;;
				qcom,fab-dev;
				phandle = &lt;0xd8&gt;;
				qcom,qos-off = &lt;0x1000&gt;;
			};

rsc-disp {
				qcom,req_state = &lt;0x02&gt;;
				cell-id = &lt;0x1f41&gt;;
				label = &quot;disp_rsc&quot;;
				qcom,rsc-dev;
				phandle = &lt;0xd1&gt;;
			};

mas-qxm-crypto {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x7d&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-qxm-crypto&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0xd9&gt;;
				qcom,qport = &lt;0x01&gt;;
				phandle = &lt;0x32c&gt;;
				qcom,bcms = &lt;0xda&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;
			};

slv-srvc-aggre2-noc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2ea&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-srvc-aggre2-noc&quot;;
				phandle = &lt;0xd7&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;
			};

mas-xm-pcie3-0 {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2d&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-xm-pcie3-0&quot;;
				qcom,connections = &lt;0xdb&gt;;
				qcom,qport = &lt;0x0b&gt;;
				phandle = &lt;0x32e&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;
			};

mas-llcc-mc_display {
				qcom,agg-ports = &lt;0x02&gt;;
				cell-id = &lt;0x4e20&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-llcc-mc_display&quot;;
				qcom,connections = &lt;0x138&gt;;
				phandle = &lt;0x15d&gt;;
				qcom,bus-dev = &lt;0x139&gt;;
			};

slv-qhs-glm {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2d6&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-glm&quot;;
				phandle = &lt;0xeb&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-qhm-qdss-bam {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x35&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-qhm-qdss-bam&quot;;
				qcom,connections = &lt;0xd9&gt;;
				qcom,qport = &lt;0x08&gt;;
				phandle = &lt;0x32a&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;
			};

bcm-sh8 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b8c&gt;;
				label = &quot;SH8&quot;;
				qcom,bcm-name = &quot;SH8&quot;;
				phandle = &lt;0x144&gt;;
				qcom,bcm-dev;
			};

mas-qhm-snoc-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x36&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-qhm-snoc-cfg&quot;;
				qcom,connections = &lt;0x127&gt;;
				phandle = &lt;0x149&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

slv-qhs-camera-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x24d&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-camera-cfg&quot;;
				phandle = &lt;0xe5&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
				qcom,disable-ports = &lt;0x46 0x47&gt;;
			};

slv-qhs-qupv3-north {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x312&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-qupv3-north&quot;;
				phandle = &lt;0xff&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-llcc-mc {
				qcom,agg-ports = &lt;0x02&gt;;
				cell-id = &lt;0x81&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-llcc-mc&quot;;
				qcom,connections = &lt;0x11f&gt;;
				phandle = &lt;0x14e&gt;;
				qcom,bus-dev = &lt;0x120&gt;;
			};

bcm-sn4 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b6e&gt;;
				label = &quot;SN4&quot;;
				qcom,bcm-name = &quot;SN4&quot;;
				phandle = &lt;0x15c&gt;;
				qcom,bcm-dev;
			};

slv-qhs-emmc-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x326&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-emmc-cfg&quot;;
				phandle = &lt;0x10c&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qns-pcie-gemnoc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2755&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;slv-qns-pcie-gemnoc&quot;;
				qcom,connections = &lt;0x141&gt;;
				phandle = &lt;0xdb&gt;;
				qcom,bcms = &lt;0x142&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;
			};

slv-qhs-sdc2 {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x260&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-sdc2&quot;;
				phandle = &lt;0xe7&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qhs-spdm {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x279&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-spdm&quot;;
				phandle = &lt;0x10d&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qhs-qdss-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x27b&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-qdss-cfg&quot;;
				phandle = &lt;0xef&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-qhm-a1noc-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x79&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-qhm-a1noc-cfg&quot;;
				qcom,connections = &lt;0xd2&gt;;
				phandle = &lt;0x145&gt;;
				qcom,bus-dev = &lt;0xd3&gt;;
			};

mas-qxm-venus1 {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0x40&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-venus1&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x124&gt;;
				qcom,qport = &lt;0xe0&gt;;
				phandle = &lt;0x344&gt;;
				qcom,bcms = &lt;0x126&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

slv-qhs-imem-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x273&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-imem-cfg&quot;;
				phandle = &lt;0x112&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

slv-qns-llcc_display {
				qcom,agg-ports = &lt;0x02&gt;;
				cell-id = &lt;0x5021&gt;;
				qcom,buswidth = &lt;0x10&gt;;
				label = &quot;slv-qns-llcc_display&quot;;
				qcom,connections = &lt;0x15d&gt;;
				phandle = &lt;0x136&gt;;
				qcom,bcms = &lt;0x15e&gt;;
				qcom,bus-dev = &lt;0x137&gt;;
			};

bcm-mm1_display {
				qcom,rscs = &lt;0xd1&gt;;
				cell-id = &lt;0x697b&gt;;
				label = &quot;MM1_DISPLAY&quot;;
				qcom,bcm-name = &quot;MM1&quot;;
				phandle = &lt;0x13c&gt;;
				qcom,bcm-dev;
			};

slv-qhs-aoss {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2ec&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-aoss&quot;;
				phandle = &lt;0x109&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

rsc-apps {
				qcom,req_state = &lt;0x02&gt;;
				cell-id = &lt;0x1f40&gt;;
				label = &quot;apps_rsc&quot;;
				qcom,rsc-dev;
				phandle = &lt;0xd0&gt;;
			};

mas-qxm-mdp1 {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0x17&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-mdp1&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x123&gt;;
				qcom,qport = &lt;0x80&gt;;
				phandle = &lt;0x341&gt;;
				qcom,bcms = &lt;0xde&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x122&gt;;
			};

mas-qnm-mnoc-hf {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x02&gt;;
				qcom,node-qos-bcms = &lt;0x1b64 0x00 0x01&gt;;
				cell-id = &lt;0x84&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qnm-mnoc-hf&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x116&gt;;
				qcom,qport = &lt;0x80 0x81&gt;;
				phandle = &lt;0x154&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

mas-qxm-ipa {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				qcom,node-qos-bcms = &lt;0x1b7b 0x00 0x01&gt;;
				cell-id = &lt;0x5a&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-qxm-ipa&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0xd9&gt;;
				qcom,defer-init-qos;
				qcom,qport = &lt;0x02&gt;;
				phandle = &lt;0x32d&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;
			};

fab-config_noc {
				qcom,base-name = &quot;config_noc-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				qcom,bus-type = &lt;0x01&gt;;
				cell-id = &lt;0x1400&gt;;
				qcom,bypass-qos-prg;
				clocks;
				label = &quot;fab-config_noc&quot;;
				qcom,base-offset = &lt;0x00&gt;;
				qcom,fab-dev;
				phandle = &lt;0xe3&gt;;
				qcom,qos-off = &lt;0x00&gt;;
			};

mas-qhm-a2noc-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x7c&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;mas-qhm-a2noc-cfg&quot;;
				qcom,connections = &lt;0xd7&gt;;
				phandle = &lt;0x146&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;
			};

bcm-sn14 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b78&gt;;
				label = &quot;SN14&quot;;
				qcom,bcm-name = &quot;SN14&quot;;
				phandle = &lt;0x142&gt;;
				qcom,bcm-dev;
			};

fab-gem_noc_display {
				qcom,base-name = &quot;gem_noc-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				qcom,bus-type = &lt;0x01&gt;;
				cell-id = &lt;0x6593&gt;;
				qcom,bypass-qos-prg;
				clocks;
				label = &quot;fab-gem_noc_display&quot;;
				qcom,base-offset = &lt;0x2b000&gt;;
				qcom,fab-dev;
				phandle = &lt;0x137&gt;;
				qcom,qos-off = &lt;0x80&gt;;
			};

bcm-sn2 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b6c&gt;;
				label = &quot;SN2&quot;;
				qcom,bcm-name = &quot;SN2&quot;;
				phandle = &lt;0x158&gt;;
				qcom,bcm-dev;
			};

mas-ipa-core-master {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x8f&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-ipa-core-master&quot;;
				qcom,connections = &lt;0x11d&gt;;
				phandle = &lt;0x33b&gt;;
				qcom,bus-dev = &lt;0x11e&gt;;
			};

mas-qnm-aggre2-noc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2750&gt;;
				qcom,buswidth = &lt;0x10&gt;;
				label = &quot;mas-qnm-aggre2-noc&quot;;
				qcom,connections = &lt;0x129 0x12a 0x12b 0x12c 0x12d 0x130 0x12e&gt;;
				phandle = &lt;0x140&gt;;
				qcom,bcms = &lt;0x131&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

mas-qnm-cnoc {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x76&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-qnm-cnoc&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0xd9&gt;;
				qcom,qport = &lt;0x03&gt;;
				phandle = &lt;0x14a&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;
			};

slv-qhs-venus-throttle-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x2b8&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-venus-throttle-cfg&quot;;
				phandle = &lt;0x104&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

mas-xm-usb3-0 {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x3d&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-xm-usb3-0&quot;;
				qcom,connections = &lt;0xd9&gt;;
				qcom,qport = &lt;0x0c&gt;;
				phandle = &lt;0x330&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd8&gt;;

qcom,node-qos-clks {
					clock-names = &quot;clk-aggre-usb3-prim-axi-no-rate&quot;;
					clocks = &lt;0x27 0x0b&gt;;
				};
			};

bcm-sh10 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b8e&gt;;
				label = &quot;SH10&quot;;
				qcom,bcm-name = &quot;SH10&quot;;
				phandle = &lt;0xe1&gt;;
				qcom,bcm-dev;
			};

mas-alc {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x90&gt;;
				qcom,buswidth = &lt;0x01&gt;;
				label = &quot;mas-alc&quot;;
				phandle = &lt;0x348&gt;;
				qcom,bcms = &lt;0x135&gt;;
				qcom,bus-dev = &lt;0x120&gt;;
			};

slv-ipa-core-slave {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x309&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;slv-ipa-core-slave&quot;;
				phandle = &lt;0x11d&gt;;
				qcom,bcms = &lt;0x150&gt;;
				qcom,bus-dev = &lt;0x11e&gt;;
			};

mas-qxm-gpu {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x02&gt;;
				cell-id = &lt;0x1a&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-gpu&quot;;
				qcom,forwarding;
				qcom,connections = &lt;0x116 0x117&gt;;
				qcom,qport = &lt;0x120 0x121&gt;;
				phandle = &lt;0x33a&gt;;
				qcom,prio = &lt;0x00&gt;;
				qcom,bus-dev = &lt;0x118&gt;;
			};

mas-qxm-camnoc-rt-uncomp {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0xb2&gt;;
				qcom,buswidth = &lt;0x20&gt;;
				label = &quot;mas-qxm-camnoc-rt-uncomp&quot;;
				qcom,connections = &lt;0xdc&gt;;
				phandle = &lt;0x332&gt;;
				qcom,bcms = &lt;0xde&gt;;
				qcom,bus-dev = &lt;0xdd&gt;;
			};

slv-qhs-clk-ctl {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x26c&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-clk-ctl&quot;;
				phandle = &lt;0xfd&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

bcm-mm2 {
				qcom,rscs = &lt;0xd0&gt;;
				cell-id = &lt;0x1b65&gt;;
				label = &quot;MM2&quot;;
				qcom,bcm-name = &quot;MM2&quot;;
				phandle = &lt;0x125&gt;;
				qcom,bcm-dev;
			};

slv-qhs-venus-cvp-throttle-cfg {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x32a&gt;;
				qcom,buswidth = &lt;0x04&gt;;
				label = &quot;slv-qhs-venus-cvp-throttle-cfg&quot;;
				phandle = &lt;0xf5&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,bus-dev = &lt;0xe3&gt;;
			};

fab-compute_noc {
				qcom,base-name = &quot;compute_noc-base&quot;;
				qcom,sbm-offset = &lt;0x00&gt;;
				qcom,bus-type = &lt;0x01&gt;;
				cell-id = &lt;0x180b&gt;;
				qcom,bypass-qos-prg;
				clocks;
				label = &quot;fab-compute_noc&quot;;
				qcom,base-offset = &lt;0x00&gt;;
				qcom,fab-dev;
				phandle = &lt;0xe0&gt;;
				qcom,qos-off = &lt;0x1000&gt;;
			};

slv-qxs-imem {
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x249&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;slv-qxs-imem&quot;;
				phandle = &lt;0x12b&gt;;
				qcom,bcms = &lt;0x15b&gt;;
				qcom,bus-dev = &lt;0x128&gt;;
			};

mas-xm-emmc {
				qcom,ap-owned;
				qcom,agg-ports = &lt;0x01&gt;;
				cell-id = &lt;0x96&gt;;
				qcom,buswidth = &lt;0x08&gt;;
				label = &quot;mas-xm-emmc&quot;;
				qcom,connections = &lt;0xd4&gt;;
				qcom,qport = &lt;0x03&gt;;
				phandle = &lt;0x326&gt;;
				qcom,bcms = &lt;0xd6&gt;;
				qcom,prio = &lt;0x02&gt;;
				qcom,bus-dev = &lt;0xd3&gt;;
			};
		};

qcom,smp2p_interrupt_rdbg_2_out {
			qcom,smem-state-names = &quot;rdbg-smp2p-out&quot;;
			compatible = &quot;qcom,smp2p-interrupt-rdbg-2-out&quot;;
			qcom,smem-states = &lt;0x1bc 0x00&gt;;
		};

cti@683b000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-mss-q6&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x683b000 0x1000&gt;;
			phandle = &lt;0x46d&gt;;
		};

qseecom@86d00000 {
			qcom,hlos-num-ce-hw-instances = &lt;0x01&gt;;
			reg-names = &quot;secapp-region&quot;;
			memory-region = &lt;0x9a&gt;;
			qcom,qsee-reentrancy-support = &lt;0x02&gt;;
			compatible = &quot;qcom,qseecom&quot;;
			qcom,no-clock-support;
			qcom,disk-encrypt-pipe-pair = &lt;0x02&gt;;
			qcom,support-fde;
			qcom,appsbl-qseecom-support;
			qcom,qsee-ce-hw-instance = &lt;0x00&gt;;
			reg = &lt;0x86d00000 0x3e00000&gt;;
			phandle = &lt;0x2da&gt;;
			qcom,commonlib64-loaded-by-uefi;
			qcom,hlos-ce-hw-instance = &lt;0x00&gt;;
			qcom,fde-key-size;
		};

qcom,msm-dai-tdm-sen-tx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9051&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9151&gt;;
			phandle = &lt;0x4c6&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-sen-tx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9051&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x4c7&gt;;
			};
		};

rpmh-regulator-ldof2 {
			compatible = &quot;qcom,rpmh-xob-regulator&quot;;
			qcom,resource-name = &quot;ldof2&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm8009-l2 {
				regulator-max-microvolt = &lt;0x100590&gt;;
				regulator-min-microvolt = &lt;0x100590&gt;;
				regulator-name = &quot;pm8009_l2&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x418&gt;;
			};
		};

i2c@0xa8c000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x18a&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			interrupts = &lt;0x00 0x164 0x00&gt;;
			clocks = &lt;0x27 0x5d 0x27 0x69 0x27 0x6a&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			qcom,clk-freq-in = &lt;0x61a80&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,i2c-geni&quot;;
			pinctrl-1 = &lt;0x18b&gt;;
			status = &quot;ok&quot;;
			reg = &lt;0xa8c000 0x4000&gt;;
			phandle = &lt;0x35d&gt;;
			dmas = &lt;0x183 0x00 0x03 0x03 0x40 0x00 0x183 0x01 0x03 0x03 0x40 0x00&gt;;
			qcom,clk-freq-out = &lt;0x61a80&gt;;

fsa4480@43 {
				pinctrl-names = &quot;default&quot;;
				pinctrl-0 = &lt;0x18c&gt;;
				compatible = &quot;qcom,fsa4480-i2c&quot;;
				status = &quot;disabled&quot;;
				reg = &lt;0x43&gt;;
				phandle = &lt;0x35e&gt;;
			};

wl2866d@28 {
				vin1-supply = &lt;0x3ff&gt;;
				vin2-supply = &lt;0x415&gt;;
				vin2-voltage-level = &lt;0x325aa0 0x325aa0&gt;;
				en-gpio = &lt;0x174 0x1e 0x00&gt;;
				compatible = &quot;xiaomi,wl2866d&quot;;
				status = &quot;ok&quot;;
				reg = &lt;0x28&gt;;
				vin1-voltage-level = &lt;0x149970 0x149970&gt;;
			};

aw8624_haptic@5A {
				vib_f0_cali_percen = &lt;0x07&gt;;
				pinctrl-names = &quot;aw8624_reset_reset\0aw8624_reset_active\0aw8624_interrupt_active&quot;;
				pinctrl-2 = &lt;0x58d&gt;;
				vib_brake_cont_config = &lt;0x01 0x01 0x5a 0x2a 0x14 0x05 0x02 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00&gt;;
				vib_f0_pre = &lt;0x802&gt;;
				irq-gpio = &lt;0x2ec 0x0a 0x00&gt;;
				vib_tset = &lt;0x11&gt;;
				pinctrl-0 = &lt;0x58b&gt;;
				vib_bstdbg = &lt;0x30 0xeb 0xd4 0x00 0x00 0x00&gt;;
				vib_effect_max = &lt;0xaa&gt;;
				vib_bemf_config = &lt;0x00 0x08 0x03 0xf8&gt;;
				vib_td_brake = &lt;0xa6e0 0xa6e0 0xa6e0&gt;;
				vib_duration_time = &lt;0x0f 0x3c 0x00 0x00 0x00&gt;;
				vib_cont_num_brk = &lt;0x03&gt;;
				vib_rtp_time = &lt;0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x6e 0x78 0x82 0x8c 0x96 0xa0 0xaa 0xb4 0xbe 0xc8 0xd2 0xdc 0xe6 0xf0 0xfa 0x104 0x10e 0x118 0x122 0x12c 0x136 0x140 0x14a 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14&gt;;
				vib_r_spare = &lt;0x68&gt;;
				vib_func_parameter1 = &lt;0x01&gt;;
				vib_cont_zc_thr = &lt;0x8f8&gt;;
				vib_effect_id_boundary = &lt;0x0a&gt;;
				vib_cont_drv_lvl_ov = &lt;0x9b&gt;;
				reset-gpio = &lt;0x174 0x04 0x00&gt;;
				vib_sw_brake = &lt;0x2c&gt;;
				vib_cont_td = &lt;0xf06c&gt;;
				compatible = &quot;awinic,aw8624_haptic&quot;;
				vib_brake_ram_config = &lt;0x01 0x01 0x5a 0x3c 0x14 0x03 0x01 0x03 0x01 0x01 0x5a 0x3c 0x1e 0x05 0x01 0x03 0x00 0x00 0x32 0x28 0x19 0x00 0x05 0x03&gt;;
				pinctrl-1 = &lt;0x58c&gt;;
				vib_cont_drv_lev = &lt;0x6a&gt;;
				vib_f0_trace_parameter = &lt;0x09 0x05 0x01 0x0f&gt;;
				reg = &lt;0x5a&gt;;
				vib_f0_coeff = &lt;0x104&gt;;
				vib_gain_flag = &lt;0x01&gt;;
				vib_wavseq = &lt;0x00 0x01 0x01 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00&gt;;
				vib_wavloop = &lt;0x00 0x06 0x01 0x0f 0x00 0x00 0x00 0x00 0x00 0x00&gt;;

wf_7 {
					qcom,wf-play-rate-us = &lt;0x4e20&gt;;
					qcom,wf-brake-pattern = &lt;0x2010000&gt;;
					qcom,effect-id = &lt;0x07&gt;;
					qcom,wf-pattern = [3e 3e];
					qcom,wf-vmax-mv = &lt;0xe10&gt;;
				};

wf_5 {
					qcom,wf-play-rate-us = &lt;0x4e20&gt;;
					qcom,wf-brake-pattern = &lt;0x3030100&gt;;
					qcom,effect-id = &lt;0x05&gt;;
					qcom,wf-pattern = [7e 7e 7e];
					qcom,wf-vmax-mv = &lt;0xe10&gt;;
				};

wf_3 {
					qcom,wf-play-rate-us = &lt;0x4e20&gt;;
					qcom,wf-brake-pattern = &lt;0x2010000&gt;;
					qcom,effect-id = &lt;0x03&gt;;
					qcom,wf-pattern = [3e 3e];
					qcom,wf-vmax-mv = &lt;0xe10&gt;;
				};

wf_1 {
					qcom,wf-play-rate-us = &lt;0x4e20&gt;;
					qcom,wf-brake-pattern = &lt;0x3010000&gt;;
					qcom,effect-id = &lt;0x01&gt;;
					qcom,wf-pattern = [7e 3e];
					qcom,wf-vmax-mv = &lt;0xe10&gt;;
				};

wf_8 {
					qcom,wf-play-rate-us = &lt;0x4e20&gt;;
					qcom,wf-brake-pattern = &lt;0x2010000&gt;;
					qcom,effect-id = &lt;0x08&gt;;
					qcom,wf-pattern = [3e 3e];
					qcom,wf-vmax-mv = &lt;0xe10&gt;;
				};

wf_6 {
					qcom,wf-play-rate-us = &lt;0x4e20&gt;;
					qcom,wf-brake-pattern = &lt;0x2010000&gt;;
					qcom,effect-id = &lt;0x06&gt;;
					qcom,wf-pattern = [3e 3e];
					qcom,wf-vmax-mv = &lt;0xe10&gt;;
				};

wf_4 {
					qcom,wf-play-rate-us = &lt;0x6d60&gt;;
					qcom,wf-brake-pattern = &lt;0x2010000&gt;;
					qcom,effect-id = &lt;0x04&gt;;
					qcom,wf-pattern = [3e 3e];
					qcom,wf-vmax-mv = &lt;0xe10&gt;;
				};

wf_2 {
					qcom,wf-play-rate-us = &lt;0x4e20&gt;;
					qcom,wf-brake-pattern = &lt;0x2010000&gt;;
					qcom,effect-id = &lt;0x02&gt;;
					qcom,wf-pattern = [7e 3e];
					qcom,wf-vmax-mv = &lt;0xe10&gt;;
				};

wf_0 {
					qcom,wf-play-rate-us = &lt;0x4e20&gt;;
					qcom,wf-brake-pattern = &lt;0x2010000&gt;;
					qcom,effect-id = &lt;0x00&gt;;
					qcom,wf-pattern = [3e 3e];
					qcom,wf-vmax-mv = &lt;0xe10&gt;;
				};

wf_9 {
					qcom,wf-play-rate-us = &lt;0x4e20&gt;;
					qcom,wf-brake-pattern = &lt;0x2010000&gt;;
					qcom,effect-id = &lt;0x09&gt;;
					qcom,wf-pattern = [3e 3e];
					qcom,wf-vmax-mv = &lt;0xe10&gt;;
				};
			};

bq25970-standalone@66 {
				ti,bq2597x,bat-ovp-alarm-threshold = &lt;0x11ad&gt;;
				ti,bq2597x,bus-ocp-threshold = &lt;0xea6&gt;;
				pinctrl-names = &quot;default&quot;;
				ti,bq2597x,bat-ocp-alarm-disable;
				ti,bq2597x,die-therm-threshold = &lt;0x91&gt;;
				ti,bq2597x,bat-therm-threshold = &lt;0x15&gt;;
				ti,bq2597x,bat-ovp-threshold = &lt;0x11c6&gt;;
				pinctrl-0 = &lt;0x589 0x58a&gt;;
				ti,bq2597x,bat-therm-disable;
				ti,bq2597x,bus-ovp-threshold = &lt;0x2ee0&gt;;
				ti,bq2597x,bus-therm-disable;
				interrupts = &lt;0x37 0x2002&gt;;
				interrupt-parent = &lt;0x174&gt;;
				ti,bq2597x,die-therm-disable;
				ti,bq2597x,bus-therm-threshold = &lt;0x15&gt;;
				ti,bq2597x,bus-ovp-alarm-threshold = &lt;0x2af8&gt;;
				ti,bq2597x,ac-ovp-threshold = &lt;0x0e&gt;;
				compatible = &quot;ti,bq2597x-standalone&quot;;
				ti,bq2597x,bat-ocp-disable;
				reg = &lt;0x66&gt;;
				ti,bq2597x,bus-ocp-alarm-threshold = &lt;0xdac&gt;;
				ti,bq2597x,bat-ovp-alarm-disable;
				ti,bq2597x,bat-ucp-disable;
				ti,bq2597x,bat-ucp-alarm-disable;
			};
		};

qcom,cmd-db@c3f000c {
			compatible = &quot;qcom,cmd-db&quot;;
			reg = &lt;0xc3f000c 0x08&gt;;
			phandle = &lt;0x2d3&gt;;
		};

qcom,mdss_dsi_ss_fhd_eb_f10_cmd {
			qcom,mdss-dsi-bl-dcs-type-ss-eb;
			qcom,ulps-enabled;
			qcom,disp-doze-backlight-threshold = &lt;0x08&gt;;
			qcom,mdss-pan-physical-width-dimension = &lt;0x44&gt;;
			qcom,mdss-dsi-panel-name = &quot;ss eb fhd cmd dsi panel&quot;;
			qcom,mdss-pan-physical-height-dimension = &lt;0x93&gt;;
			qcom,mdss-dsi-te-using-te-pin;
			qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
			qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
			qcom,mdss-dsi-t-clk-post = &lt;0x0f&gt;;
			qcom,mdss-dsi-lane-2-state;
			qcom,mdss-dsi-te-check-enable;
			qcom,mdss-dsi-bllp-eof-power-mode;
			qcom,mdss-dsi-panel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-panel-fod-dimlayer-enabled;
			qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
			qcom,bl-update-flag = &quot;delay_until_first_frame&quot;;
			qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
			qcom,disp-fod-off-dimming-delay = &lt;0x55&gt;;
			qcom,dispparam-enabled;
			qcom,mdss-dsi-panel-peak-brightness = &lt;0x419ce0&gt;;
			qcom,mdss-dsi-lane-3-state;
			qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
			qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-reset-sequence = &lt;0x00 0x01 0x01 0x0a&gt;;
			qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
			qcom,mdss-dsi-lane-0-state;
			qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
			qcom,mdss-dsi-t-clk-pre = &lt;0x37&gt;;
			qcom,mdss-dsi-panel-hdr-enabled;
			qcom,mdss-dsi-panel-model = &quot;SS FHD EB CMD PANEL&quot;;
			qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
			phandle = &lt;0x533&gt;;
			qcom,mdss-dsi-bllp-power-mode;
			qcom,mdss-dsi-panel-sleepwrmod = &lt;0x00&gt;;
			qcom,mdss-dsi-stream = &lt;0x00&gt;;
			qcom,mdss-dsi-lp11-init;
			qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
			qcom,mdss-dsi-tx-eot-append;
			qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
			qcom,mdss-dsi-border-color = &lt;0x00&gt;;
			qcom,mdss-dsi-lane-1-state;
			qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
			qcom,mdss-brightness-remap;
			qcom,esd-err-irq-gpio = &lt;0x174 0x20 0x2002&gt;;
			qcom,mdss-dsi-bpp = &lt;0x18&gt;;
			qcom,mdss-brightness-max-level = &lt;0x7ff&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
					qcom,mdss-dsi-dispparam-acl-l3-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
					qcom,display-topology = &lt;0x01 0x00 0x01&gt;;
					qcom,mdss-dsi-dispparam-hbm-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
					qcom,mdss-dsi-h-pulse-width = &lt;0x14&gt;;
					qcom,mdss-dsi-nolp-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00];
					qcom,mdss-dsi-panel-jitter = &lt;0x05 0x01&gt;;
					qcom,mdss-dsi-nolp-command = &lt;0x39010000 0x351 0x1003901 0x00 0x2b00039 0x1000000 0x4f0bb 0x2a403901 0x100 0x2532039 0x1000000 0x28800&gt;;
					qcom,mdss-dsi-lp1-command = [39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 88 01];
					qcom,mdss-dsi-dispparam-acl-l1-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-doze-hbm-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-doze-lbm-command = [39 01 00 00 00 00 03 51 00 40 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 04 f0 bb 2a 40 39 01 00 00 00 00 02 53 20];
					qcom,mdss-dsi-dispparam-hbm-fod-on-command = [39 01 00 00 03 00 02 88 00 39 01 00 00 00 00 02 53 e0];
					qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 e8];
					qcom,mdss-dsi-dispparam-hbm-fod-off-command = [39 01 00 00 00 00 02 53 20];
					qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 ff 00 02 53 28 39 01 00 00 00 00 02 53 20];
					qcom,mdss-dsi-panel-height = &lt;0x924&gt;;
					qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 00 00 00 00 00 2c bb 59 ff ff ff ef cf ab 87 63 3f 4a 48 46 44 42 40 3e 3c 3a 64 00 ff ff ff ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00 02 02 42 00 39 00 00 00 00 00 03 d4 00 8d 39 00 00 00 00 00 02 fa 0f 39 01 00 00 00 00 02 b0 80 39 00 00 00 00 00 02 e6 00 39 00 00 00 00 00 02 35 00 39 00 00 00 00 00 05 2a 00 00 04 37 39 00 00 00 00 00 05 2b 00 00 09 23 39 00 00 00 00 00 03 51 01 00 05 01 00 00 6e 00 02 11 00 05 01 00 00 10 00 02 29 00 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 04 f0 cf c3 00 39 01 00 00 00 00 04 f0 cf c4 00];
					qcom,mdss-dsi-h-front-porch = &lt;0x40&gt;;
					qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];
					qcom,mdss-dsi-h-back-porch = &lt;0x40&gt;;
					qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-hbm-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-lp1-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];
					qcom,mdss-dsi-panel-clockrate = &lt;0x4190ab00&gt;;
					qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
					qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
					qcom,mdss-dsi-dispparam-acl-l2-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-v-pulse-width = &lt;0x14&gt;;
					qcom,mdss-dsi-doze-hbm-command = [39 01 00 00 00 00 03 51 00 ff 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 04 f0 bb 2a 40 39 01 00 00 00 00 02 53 20];
					qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-acl-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-panel-phy-timings = &lt;0x240a0a 0x2625090a 0x6020400&gt;;
					qcom,mdss-dsi-v-back-porch = &lt;0x40&gt;;
					qcom,mdss-dsi-doze-lbm-command-state = &quot;dsi_lp_mode&quot;;
					qcom,default-topology-index = &lt;0x00&gt;;
					qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
					qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00];
					qcom,mdss-dsi-v-front-porch = &lt;0x40&gt;;
					qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];
					qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
				};
			};
		};

qcom,fd@ac5a000 {
			clock-control-debugfs = &quot;true&quot;;
			clock-names = &quot;fd_core_clk_src\0fd_core_clk\0fd_core_uar_clk&quot;;
			reg-names = &quot;fd_core\0fd_wrapper&quot;;
			reg-cam-base = &lt;0x5a000 0x5b000&gt;;
			cell-index = &lt;0x00&gt;;
			camss-vdd-supply = &lt;0x1ae&gt;;
			interrupts = &lt;0x00 0x1ce 0x00&gt;;
			clocks = &lt;0x29 0x2a 0x29 0x29 0x29 0x2b&gt;;
			clock-cntl-level = &quot;lowsvs\0svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,fd501&quot;;
			src-clock-name = &quot;fd_core_clk_src&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;fd&quot;;
			reg = &lt;0xac5a000 0x1000 0xac5b000 0x400&gt;;
			regulator-names = &quot;camss-vdd&quot;;
			phandle = &lt;0x399&gt;;
			clock-rates = &lt;0x23c34600 0x00 0x00 0x23c34600 0x00 0x00 0x23c34600 0x00 0x00 0x23c34600 0x00 0x00&gt;;
		};

xiaomi_touch {
			touch,name = &quot;xiaomi-touch&quot;;
			compatible = &quot;xiaomi-touch&quot;;
			status = &quot;ok&quot;;
		};

qcom,msm-dai-q6-hdmi {
			compatible = &quot;qcom,msm-dai-q6-hdmi&quot;;
			qcom,msm-dai-q6-dev-id = &lt;0x08&gt;;
			phandle = &lt;0x48d&gt;;
		};

onewire_gpio {
			pinctrl-names = &quot;onewire_active\0onewire_sleep&quot;;
			mi,onewire-gpio-cfg-addr = &lt;0x395b000 0x04&gt;;
			pinctrl-0 = &lt;0x587&gt;;
			label = &quot;xm_onewire&quot;;
			xiaomi,version = &lt;0x01&gt;;
			compatible = &quot;xiaomi,onewire_gpio&quot;;
			pinctrl-1 = &lt;0x588&gt;;
			status = &quot;ok&quot;;
			xiaomi,ow_gpio = &lt;0x174 0x5b 0x00&gt;;
			phandle = &lt;0x5b1&gt;;
		};

tgu@6b0c000 {
			arm,primecell-periphid = &lt;0x3b999&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tgu-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			tgu-regs = &lt;0x04&gt;;
			tgu-steps = &lt;0x03&gt;;
			coresight-name = &quot;coresight-tgu-ipcb&quot;;
			tgu-conditions = &lt;0x04&gt;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b0c000 0x1000&gt;;
			phandle = &lt;0x485&gt;;
			tgu-timer-counters = &lt;0x08&gt;;
		};

spi@0xa80000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x197&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			interrupts = &lt;0x00 0x161 0x00&gt;;
			clocks = &lt;0x27 0x57 0x27 0x69 0x27 0x6a&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			spi-max-frequency = &lt;0x2faf080&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,spi-geni&quot;;
			pinctrl-1 = &lt;0x198&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0xa80000 0x4000&gt;;
			phandle = &lt;0x363&gt;;
			dmas = &lt;0x183 0x00 0x00 0x01 0x40 0x00 0x183 0x01 0x00 0x01 0x40 0x00&gt;;
		};

qrng@793000 {
			qcom,msm-rng-iface-clk;
			clock-names = &quot;iface_clk&quot;;
			qcom,no-qrng-config;
			qcom,msm-bus,name = &quot;msm-rng-noc&quot;;
			clocks = &lt;0x27 0x41&gt;;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x02&gt;;
			compatible = &quot;qcom,msm-rng&quot;;
			reg = &lt;0x793000 0x1000&gt;;
			phandle = &lt;0x2dc&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x01 0x26a 0x00 0x00 0x01 0x26a 0x00 0x493e0&gt;;
		};

wcd-dsp-mgr@2 {
			compatible = &quot;qcom,wcd-dsp-mgr&quot;;
			status = &quot;disabled&quot;;
			qcom,wdsp-components = &lt;0x50d 0x00 0x50e 0x01 0x2d6 0x02&gt;;
			phandle = &lt;0x59a&gt;;
			qcom,img-filename = &quot;cpe_9340&quot;;
		};

qcom,glinkpkt {
			compatible = &quot;qcom,glinkpkt&quot;;

qcom,glinkpkt-apr-apps2 {
				qcom,glinkpkt-edge = &quot;adsp&quot;;
				qcom,glinkpkt-dev-name = &quot;apr_apps2&quot;;
				qcom,glinkpkt-ch-name = &quot;apr_apps2&quot;;
			};

qcom,glinkpkt-data11 {
				qcom,glinkpkt-edge = &quot;mpss&quot;;
				qcom,glinkpkt-dev-name = &quot;smd11&quot;;
				qcom,glinkpkt-ch-name = &quot;DATA11&quot;;
			};

qcom,glinkpkt-data1 {
				qcom,glinkpkt-edge = &quot;mpss&quot;;
				qcom,glinkpkt-dev-name = &quot;smd7&quot;;
				qcom,glinkpkt-ch-name = &quot;DATA1&quot;;
			};

qcom,glinkpkt-data40-cntl {
				qcom,glinkpkt-edge = &quot;mpss&quot;;
				qcom,glinkpkt-dev-name = &quot;smdcntl8&quot;;
				qcom,glinkpkt-ch-name = &quot;DATA40_CNTL&quot;;
			};

qcom,glinkpkt-data4 {
				qcom,glinkpkt-edge = &quot;mpss&quot;;
				qcom,glinkpkt-dev-name = &quot;smd8&quot;;
				qcom,glinkpkt-ch-name = &quot;DATA4&quot;;
			};

qcom,glinkpkt-at-mdm0 {
				qcom,glinkpkt-edge = &quot;mpss&quot;;
				qcom,glinkpkt-dev-name = &quot;at_mdm0&quot;;
				qcom,glinkpkt-ch-name = &quot;DS&quot;;
			};
		};

qcom,mdss_dsi_xiaomi_f4_36_02_0b_fhd_cmd {
			qcom,ulps-enabled;
			qcom,disp-doze-backlight-threshold = &lt;0x08&gt;;
			qcom,mdss-dsi-bl-min-level = &lt;0x02&gt;;
			qcom,mdss-dsi-bl-xiaomi-f4-36-flag;
			qcom,mdss-pan-physical-width-dimension = &lt;0x45&gt;;
			qcom,mdss-dsi-panel-name = &quot;xiaomi f4 36 02 0b fhd cmd dsi panel&quot;;
			qcom,mdss-pan-physical-height-dimension = &lt;0x95&gt;;
			qcom,mdss-dsi-te-using-te-pin;
			qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
			qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
			qcom,mdss-dsi-panel-hbm-off-51-index = &lt;0x01&gt;;
			qcom,mdss-dsi-t-clk-post = &lt;0x09&gt;;
			qcom,mdss-dsi-lane-2-state;
			qcom,mdss-dsi-te-check-enable;
			qcom,mdss-dsi-bllp-eof-power-mode;
			qcom,mdss-dsi-panel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-panel-fod-dimlayer-enabled;
			qcom,mdss-dsi-mode-sel-gpio-state = &quot;single_port&quot;;
			qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
			qcom,mdss-dsi-bl-max-level = &lt;0x7ff&gt;;
			qcom,bl-update-flag = &quot;delay_until_first_frame&quot;;
			qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
			qcom,mdss-dsi-panel-fod-off-51-index = &lt;0x01&gt;;
			qcom,disp-fod-off-dimming-delay = &lt;0x55&gt;;
			qcom,dispparam-enabled;
			qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
			qcom,mdss-dsi-panel-peak-brightness = &lt;0x419ce0&gt;;
			qcom,mdss-dsi-lane-3-state;
			qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
			qcom,mdss-dsi-bl-default-level = &lt;0x218&gt;;
			qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-bl-dcs-type-ss-ea;
			qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
			qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
			qcom,mdss-dsi-lane-0-state;
			qcom,dispparam-f4-51-ctrl-flag;
			qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
			qcom,mdss-panel-on-dimming-delay = &lt;0xc8&gt;;
			qcom,mdss-dsi-t-clk-pre = &lt;0x1a&gt;;
			qcom,mdss-dsi-panel-hdr-enabled;
			qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
			phandle = &lt;0x53b&gt;;
			qcom,mdss-dsi-bllp-power-mode;
			qcom,mdss-dsi-panel-sleepwrmod = &lt;0x00&gt;;
			qcom,panel-supply-entries = &lt;0x521&gt;;
			qcom,mdss-dsi-stream = &lt;0x00&gt;;
			qcom,mdss-dsi-lp11-init;
			qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
			qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
			qcom,mdss-dsi-tx-eot-append;
			qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
			qcom,mdss-dsi-border-color = &lt;0x00&gt;;
			qcom,disp-backlight-pulse-threshold = &lt;0x40e&gt;;
			qcom,mdss-dsi-lane-1-state;
			qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
			qcom,platform-te-gpio = &lt;0x174 0x0a 0x00&gt;;
			qcom,esd-err-irq-gpio = &lt;0x174 0x20 0x2002&gt;;
			qcom,mdss-dsi-bpp = &lt;0x18&gt;;
			qcom,mdss-brightness-max-level = &lt;0x7ff&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
					qcom,mdss-dsi-dispparam-one-pluse-command = [39 00 00 00 00 00 06 f0 55 aa 52 08 00 39 00 00 00 00 00 02 6f 09 39 01 00 00 00 00 02 b2 00];
					qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
					qcom,mdss-dsc-encoders = &lt;0x02&gt;;
					qcom,display-topology = &lt;0x02 0x02 0x01&gt;;
					qcom,mdss-dsi-dispparam-hbm-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
					qcom,mdss-dsi-dispparam-one-pluse-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-h-pulse-width = &lt;0x04&gt;;
					qcom,mdss-dsi-nolp-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-panel-jitter = &lt;0x08 0x0a&gt;;
					qcom,mdss-dsi-nolp-command = [39 00 00 00 00 00 02 65 00 39 00 00 00 00 00 02 38 00 15 01 00 00 00 00 02 2c 00];
					qcom,compression-mode = &quot;dsc&quot;;
					qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-dispparam-dc-off-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-dispparam-dc-on-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-doze-hbm-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-doze-lbm-command = [39 00 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 1f 39 00 00 00 00 00 02 6f 02 39 00 00 00 00 00 03 51 00 0a 39 00 00 00 00 00 02 39 00 39 00 00 00 00 00 02 65 01 15 01 00 00 00 00 02 2c 00];
					qcom,mdss-dsi-dispparam-hbm-fod-on-command = [39 00 00 00 00 00 02 65 00 39 00 00 00 00 00 02 38 00 15 01 00 00 00 00 02 2c 00 39 00 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 0f ff];
					qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 28 39 01 00 00 00 00 03 51 0f ff];
					qcom,mdss-dsi-dispparam-dimmingoff-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-hbm-fod-off-command = [39 00 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 07 ff];
					qcom,mdss-dsi-dispparam-dimmingon-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28 39 01 00 00 00 00 03 51 07 ff];
					qcom,mdss-dsi-dispparam-four-pluse-command = [39 00 00 00 00 00 06 f0 55 aa 52 08 00 39 00 00 00 00 00 02 6f 09 39 01 00 00 00 00 02 b2 20];
					qcom,lm-split = &lt;0x21c 0x21c&gt;;
					qcom,mdss-dsi-dispparam-dc-on-command = [39 00 00 00 00 00 06 f0 55 aa 52 08 00 39 00 00 00 00 00 0b b2 c9 00 10 10 00 08 08 00 00 00 39 01 00 00 00 00 25 b3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 07 ff 0b ff 0b ff 0f ff 39 00 00 00 00 00 06 f0 55 aa 52 08 04 39 00 00 00 00 00 15 d0 00 1f 00 00 85 0b 17 20 40 80 00 b6 00 f8 01 5c 01 e6 07 ff 39 01 00 00 00 00 4c d2 08 08 08 08 08 20 20 20 20 20 2a 2a 2a 2a 2a 40 40 40 40 40 40 40 40 40 40 08 08 08 08 08 20 20 20 20 20 2a 2a 2a 2a 2a 40 40 40 40 40 40 40 40 40 40 08 08 08 08 08 20 20 20 20 20 2a 2a 2a 2a 2a 40 40 40 40 40 40 40 40 40 40];
					qcom,mdss-dsi-dispparam-dc-off-command = [39 00 00 00 00 00 06 f0 55 aa 52 08 00 39 00 00 00 00 00 0b b2 59 00 10 10 00 08 08 00 00 20 39 01 00 00 00 00 25 b3 00 02 00 0a 00 0a 00 24 00 24 00 5e 00 5e 00 ee 00 ee 01 e6 01 e6 03 b8 03 b8 07 ff 07 ff 0b ff 0b ff 0f ff 39 00 00 00 00 00 06 f0 55 aa 52 08 04 39 00 00 00 00 00 15 d0 00 1f 00 00 85 0b 17 20 40 80 00 0a 00 5e 00 ee 01 e6 07 ff 39 01 00 00 00 00 4c d2 00 08 00 08 08 10 50 40 3c 20 60 60 50 40 2a 60 60 50 50 40 60 60 54 50 40 00 08 00 08 08 10 50 40 3c 20 60 60 50 40 2a 60 60 50 50 40 60 60 54 50 40 00 08 00 08 08 10 50 40 3c 20 60 60 50 40 2a 60 60 50 50 40 60 60 54 50 40];
					qcom,mdss-dsi-panel-height = &lt;0x924&gt;;
					qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
					qcom,mdss-dsc-block-prediction-enable;
					qcom,mdss-dsi-on-command = [39 00 00 00 00 00 05 ff aa 55 a5 80 39 00 00 00 00 00 02 6f 0a 39 01 00 00 00 00 02 fc 02 39 01 00 00 00 00 06 f0 55 aa 52 08 00 39 01 00 00 00 00 05 b2 19 00 10 10 39 00 00 00 00 00 02 6f 09 39 01 00 00 00 00 02 b2 20 15 01 00 00 00 00 02 6f 13 39 01 00 00 00 00 03 b2 03 b8 39 00 00 00 00 00 02 c0 56 39 00 00 00 00 00 02 6f 06 39 00 00 00 00 00 0b b5 2b 1c 00 00 00 2b 1c 00 00 00 39 00 00 00 00 00 03 be 0e 0b 39 00 00 00 00 00 02 6f 05 39 01 00 00 00 00 02 be 8a 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 00 00 00 00 00 02 6f 03 39 00 00 00 00 00 02 cf 09 39 00 00 00 00 00 02 6f 02 39 00 00 00 00 00 02 d2 22 39 00 00 00 00 00 07 b6 00 98 00 98 00 98 39 00 00 00 00 00 05 ff aa 55 a5 81 39 00 00 00 00 00 02 6f 04 39 01 00 00 00 00 02 f5 08 39 01 00 00 00 00 06 f0 55 aa 52 08 00 39 00 00 00 00 00 02 df 81 39 00 00 00 00 00 02 6f 01 39 00 00 00 00 00 04 df 80 80 00 39 00 00 00 00 00 02 6f 04 39 00 00 00 00 00 02 df 02 39 00 00 00 00 00 02 6f 22 39 01 00 00 00 00 06 df 35 80 7f 15 50 39 00 00 00 00 00 03 89 00 0f 39 01 00 00 00 00 05 88 02 1b 07 11 39 00 00 00 00 00 05 ff aa 55 a5 81 39 00 00 00 00 00 02 6f 05 39 01 00 00 00 00 03 fd 00 db 39 00 00 00 00 00 05 ff aa 55 a5 81 39 00 00 00 00 00 02 6f 0d 39 00 00 00 00 00 02 f3 a7 39 01 00 00 00 00 05 3b 00 10 00 0c 39 00 00 00 00 00 02 90 01 39 00 00 00 00 00 13 93 89 28 00 0c 02 00 02 0e 01 1f 00 07 08 bb 08 7a 10 f0 39 00 00 00 00 00 02 03 11 39 01 00 00 00 00 02 2c 00 39 00 00 00 00 00 05 51 00 00 00 00 39 00 00 00 00 00 02 53 20 39 01 00 00 00 00 02 35 00 39 00 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 80 00 02 11 00 05 01 00 00 00 00 02 29 00];
					qcom,mdss-dsi-h-front-porch = &lt;0x08&gt;;
					qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
					qcom,mdss-dsi-h-back-porch = &lt;0x08&gt;;
					qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-hbm-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
					qcom,mdss-dsc-slice-height = &lt;0x0c&gt;;
					qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
					qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
					qcom,mdss-dsi-v-pulse-width = &lt;0x04&gt;;
					qcom,mdss-dsi-doze-hbm-command = [39 00 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 1f 39 00 00 00 00 00 02 6f 02 39 00 00 00 00 00 03 51 00 ee 39 00 00 00 00 00 02 39 00 39 00 00 00 00 00 02 65 01 15 01 00 00 00 00 02 2c 00];
					qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20];
					qcom,mdss-dsi-panel-phy-timings = &lt;0xe0303 0x1e1d0403 0x2020400&gt;;
					qcom,mdss-dsi-v-back-porch = &lt;0x0c&gt;;
					qcom,mdss-dsi-doze-lbm-command-state = &quot;dsi_lp_mode&quot;;
					qcom,default-topology-index = &lt;0x00&gt;;
					qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsc-slice-per-pkt = &lt;0x02&gt;;
					qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
					qcom,mdss-dsc-scr-version = &lt;0x00&gt;;
					qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 66 00 02 10 00];
					qcom,mdss-dsi-dispparam-four-pluse-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
					qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28];
					qcom,mdss-dsi-v-front-porch = &lt;0x0c&gt;;
					qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsc-version = &lt;0x11&gt;;
				};
			};
		};

keepalive-opp-table {
			compatible = &quot;operating-points-v2&quot;;
			phandle = &lt;0xca&gt;;

opp-1 {
				opp-hz = &lt;0x00 0x01&gt;;
			};
		};

qcom,msm-dai-tdm-quat-tx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9031&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9131&gt;;
			phandle = &lt;0x4c1&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-quat-tx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9031&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x28d&gt;;
			};
		};

thermal-zones {
			phandle = &lt;0x2bc&gt;;

xo_therm {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x7f 0x4c&gt;;
				thermal-governor = &quot;user_space&quot;;

trips {

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

mdm-dsp-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x07&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

mdm-dsp-lowf-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x75&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x75&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x75&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x75&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x75&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x75&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x75&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x75&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x75&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

cpu-0-2-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x03&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpuss-0-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x07&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

nvm-therm-adc {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x2eb 0x55&gt;;
				thermal-governor = &quot;user_space&quot;;

trips {

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-1-1-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x0a&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-0-4-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x05&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

cpu4-config {
						temperature = &lt;0x1adb0&gt;;
						hysteresis = &lt;0x2710&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x60&gt;;
					};
				};

cooling-maps {

cpu4_cdev {
						trip = &lt;0x60&gt;;
						cooling-device = &lt;0x15 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

cpu-0-0-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x01&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

cpu-0-0-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x6c&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x6c&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x6c&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x6c&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x6c&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x6c&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x6c&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x6c&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x6c&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

pm6150-ibat-lvl0 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x55 0x00&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

ibat-lvl0 {
						temperature = &lt;0x157c&gt;;
						hysteresis = &lt;0xc8&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2c0&gt;;
					};
				};
			};

pm6150l-vph-lvl1 {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x58 0x03&gt;;
				thermal-governor = &quot;low_limits_cap&quot;;
				wake-capable-sensor;

trips {

vph-lvl1 {
						temperature = &lt;0xabe&gt;;
						hysteresis = &lt;0xc8&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2cd&gt;;
					};
				};
			};

cpu-1-0-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x09&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

cpu-1-0-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x6d&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x6d&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x6d&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x6d&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x6d&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x6d&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x6d&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x6d&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x6d&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

q6-hvx-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x0a&gt;;
				thermal-sensors = &lt;0x5a 0x04&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

q6-hvx-trip2 {
						temperature = &lt;0x19a28&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x7e&gt;;
					};

q6-hvx-trip0 {
						temperature = &lt;0x17318&gt;;
						hysteresis = &lt;0x4e20&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x7a&gt;;
					};

q6-hvx-trip1 {
						temperature = &lt;0x17318&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x7c&gt;;
					};
				};

cooling-maps {

cdsp-cdev0 {
						trip = &lt;0x7c&gt;;
						cooling-device = &lt;0x7d 0xffffffff 0x04&gt;;
					};

cxip-cdev {
						trip = &lt;0x7a&gt;;
						cooling-device = &lt;0x7b 0x01 0x01&gt;;
					};

cdsp-cdev1 {
						trip = &lt;0x7e&gt;;
						cooling-device = &lt;0x7d 0x04 0x04&gt;;
					};
				};
			};

q6-hvx-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x04&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-0-3-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x04&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

cpu3-config {
						temperature = &lt;0x1adb0&gt;;
						hysteresis = &lt;0x2710&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x5f&gt;;
					};
				};

cooling-maps {

cpu3_cdev {
						trip = &lt;0x5f&gt;;
						cooling-device = &lt;0x14 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

mdm-core-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x06&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

mdm-core-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x74&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x74&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x74&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x74&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x74&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x74&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x74&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x74&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x74&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

lmh-dcvs-01 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x0f&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

active-config {
						temperature = &lt;0x17318&gt;;
						hysteresis = &lt;0x7530&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

charger_therm0 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x2eb 0x4e&gt;;
				thermal-governor = &quot;user_space&quot;;

trips {

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-1-3-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x0c&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

cpu7-1-config {
						temperature = &lt;0x1adb0&gt;;
						hysteresis = &lt;0x2710&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x65&gt;;
					};
				};

cooling-maps {

cpu7_cdev {
						trip = &lt;0x65&gt;;
						cooling-device = &lt;0x18 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

pm6150l-tz {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x57&gt;;
				thermal-governor = &quot;step_wise&quot;;
				phandle = &lt;0x2c9&gt;;
				wake-capable-sensor;

trips {

trip2 {
						temperature = &lt;0x23668&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
					};

trip0 {
						temperature = &lt;0x17318&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2ca&gt;;
					};

trip1 {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2cb&gt;;
					};
				};

cooling-maps {

trip1_cpu6 {
						trip = &lt;0x2cb&gt;;
						cooling-device = &lt;0x17 0xfffffffe 0xfffffffe&gt;;
					};

trip1_cpu4 {
						trip = &lt;0x2cb&gt;;
						cooling-device = &lt;0x15 0xfffffffe 0xfffffffe&gt;;
					};

trip0_cpu6 {
						trip = &lt;0x2ca&gt;;
						cooling-device = &lt;0x17 0xfffffffd 0xfffffffd&gt;;
					};

trip1_cpu2 {
						trip = &lt;0x2cb&gt;;
						cooling-device = &lt;0x13 0xfffffffe 0xfffffffe&gt;;
					};

trip0_cpu4 {
						trip = &lt;0x2ca&gt;;
						cooling-device = &lt;0x15 0xfffffffd 0xfffffffd&gt;;
					};

trip0_cpu2 {
						trip = &lt;0x2ca&gt;;
						cooling-device = &lt;0x13 0xfffffffd 0xfffffffd&gt;;
					};

trip0_cpu0 {
						trip = &lt;0x2ca&gt;;
						cooling-device = &lt;0x11 0xfffffffd 0xfffffffd&gt;;
					};

trip1_cpu7 {
						trip = &lt;0x2cb&gt;;
						cooling-device = &lt;0x18 0xfffffffe 0xfffffffe&gt;;
					};

trip1_cpu5 {
						trip = &lt;0x2cb&gt;;
						cooling-device = &lt;0x16 0xfffffffe 0xfffffffe&gt;;
					};

trip0_cpu7 {
						trip = &lt;0x2ca&gt;;
						cooling-device = &lt;0x18 0xfffffffd 0xfffffffd&gt;;
					};

trip1_cpu3 {
						trip = &lt;0x2cb&gt;;
						cooling-device = &lt;0x14 0xfffffffe 0xfffffffe&gt;;
					};

trip0_cpu5 {
						trip = &lt;0x2ca&gt;;
						cooling-device = &lt;0x16 0xfffffffd 0xfffffffd&gt;;
					};

trip1_cpu1 {
						trip = &lt;0x2cb&gt;;
						cooling-device = &lt;0x12 0xfffffffe 0xfffffffe&gt;;
					};

trip0_cpu3 {
						trip = &lt;0x2ca&gt;;
						cooling-device = &lt;0x14 0xfffffffd 0xfffffffd&gt;;
					};

trip0_cpu1 {
						trip = &lt;0x2ca&gt;;
						cooling-device = &lt;0x12 0xfffffffd 0xfffffffd&gt;;
					};
				};
			};

cpu-0-3-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x04&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpuss-1-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x08&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cwlan-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x01&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

aoss-0-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x00&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

aoss0-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x66&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x66&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x66&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x66&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x66&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x66&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x66&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x66&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x66&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

camera-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x05&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-1-2-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x0b&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

pm6150-bcl-lvl2 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x64&gt;;
				thermal-sensors = &lt;0x55 0x07&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

bcl-lvl2 {
						temperature = &lt;0x01&gt;;
						hysteresis = &lt;0x01&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2c7&gt;;
					};
				};

cooling-maps {

ibat_cpu7 {
						trip = &lt;0x2c7&gt;;
						cooling-device = &lt;0x18 0xfffffffe 0xfffffffe&gt;;
					};

ibat_cpu6 {
						trip = &lt;0x2c7&gt;;
						cooling-device = &lt;0x17 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

soc {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				disable-thermal-zone;
				polling-delay-passive = &lt;0x64&gt;;
				thermal-sensors = &lt;0x56&gt;;
				thermal-governor = &quot;low_limits_cap&quot;;
				wake-capable-sensor;

trips {

soc-trip {
						temperature = &lt;0x0a&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2c8&gt;;
					};
				};

cooling-maps {

soc_cpu7 {
						trip = &lt;0x2c8&gt;;
						cooling-device = &lt;0x18 0xfffffffe 0xfffffffe&gt;;
					};

soc_cpu6 {
						trip = &lt;0x2c8&gt;;
						cooling-device = &lt;0x17 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

cpu_therm {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x7f 0x4f&gt;;
				thermal-governor = &quot;user_space&quot;;

trips {

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-0-2-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x03&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

cpu2-config {
						temperature = &lt;0x1adb0&gt;;
						hysteresis = &lt;0x2710&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x5e&gt;;
					};
				};

cooling-maps {

cpu2_cdev {
						trip = &lt;0x5e&gt;;
						cooling-device = &lt;0x13 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

pm6150l-bcl-lvl1 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x64&gt;;
				thermal-sensors = &lt;0x58 0x06&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

l-bcl-lvl1 {
						temperature = &lt;0x01&gt;;
						hysteresis = &lt;0x01&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2d0&gt;;
					};
				};
			};

gpuss-0-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x0d&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

gpuss-0-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x6e&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x6e&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x6e&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x6e&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x6e&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x6e&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x6e&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x6e&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x6e&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

pm6150-bcl-lvl0 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x64&gt;;
				thermal-sensors = &lt;0x55 0x05&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

bcl-lvl0 {
						temperature = &lt;0x01&gt;;
						hysteresis = &lt;0x01&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2c5&gt;;
					};
				};

cooling-maps {

vbat_cpu6 {
						trip = &lt;0x2c5&gt;;
						cooling-device = &lt;0x17 0xfffffffe 0xfffffffe&gt;;
					};

vbat_cpu7 {
						trip = &lt;0x2c5&gt;;
						cooling-device = &lt;0x18 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

pm6150-vbat-lvl1 {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x55 0x03&gt;;
				thermal-governor = &quot;low_limits_cap&quot;;
				wake-capable-sensor;

trips {

vbat-lvl1 {
						temperature = &lt;0xaf0&gt;;
						hysteresis = &lt;0xc8&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2c3&gt;;
					};
				};
			};

cpu-1-2-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x0b&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

cpu7-0-config {
						temperature = &lt;0x1adb0&gt;;
						hysteresis = &lt;0x2710&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x64&gt;;
					};
				};

cooling-maps {

cpu7_cdev {
						trip = &lt;0x64&gt;;
						cooling-device = &lt;0x18 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

cpu-0-max-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

silver-trip {
						temperature = &lt;0x1d4c0&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-0-0-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x01&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

q6-hvx-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x04&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

q6-hvx-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x72&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x72&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x72&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x72&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x72&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x72&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x72&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x72&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x72&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

quiet-therm-step {
				polling-delay = &lt;0x00&gt;;
				disable-thermal-zone;
				polling-delay-passive = &lt;0x3e8&gt;;
				thermal-sensors = &lt;0x7f 0x50&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

batt-trip1 {
						temperature = &lt;0xafc8&gt;;
						hysteresis = &lt;0x7d0&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x8b&gt;;
					};

modem-trip1-hvx-trip {
						temperature = &lt;0xc350&gt;;
						hysteresis = &lt;0x7d0&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x83&gt;;
					};

silver-trip {
						temperature = &lt;0xd2f0&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x81&gt;;
					};

modem-trip2 {
						temperature = &lt;0xcb20&gt;;
						hysteresis = &lt;0x7d0&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x85&gt;;
					};

modem-trip0 {
						temperature = &lt;0xbb80&gt;;
						hysteresis = &lt;0xfa0&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x87&gt;;
					};

batt-trip4 {
						temperature = &lt;0xc738&gt;;
						hysteresis = &lt;0x7d0&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x8e&gt;;
					};

batt-trip2 {
						temperature = &lt;0xb798&gt;;
						hysteresis = &lt;0x7d0&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x8c&gt;;
					};

batt-trip0 {
						temperature = &lt;0xa7f8&gt;;
						hysteresis = &lt;0xfa0&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x89&gt;;
					};

modem-trip3 {
						temperature = &lt;0xe290&gt;;
						hysteresis = &lt;0xfa0&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x86&gt;;
					};

gold-trip {
						temperature = &lt;0xc350&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x80&gt;;
					};

skin-gpu-trip {
						temperature = &lt;0xcb20&gt;;
						hysteresis = &lt;0xfa0&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x82&gt;;
					};

batt-trip3 {
						temperature = &lt;0xbf68&gt;;
						hysteresis = &lt;0x7d0&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x8d&gt;;
					};
				};

cooling-maps {

skin_cpu1 {
						trip = &lt;0x81&gt;;
						cooling-device = &lt;0x12 0xffffffff 0xfffffff7&gt;;
					};

cdsp_cdev1 {
						trip = &lt;0x83&gt;;
						cooling-device = &lt;0x7d 0x04 0x04&gt;;
					};

battery_lvl3 {
						trip = &lt;0x8d&gt;;
						cooling-device = &lt;0x8a 0x05 0x05&gt;;
					};

battery_lvl1 {
						trip = &lt;0x8b&gt;;
						cooling-device = &lt;0x8a 0x02 0x02&gt;;
					};

skin_cpu6 {
						trip = &lt;0x80&gt;;
						cooling-device = &lt;0x17 0xffffffff 0xfffffff5&gt;;
					};

skin_cpu4 {
						trip = &lt;0x81&gt;;
						cooling-device = &lt;0x15 0xffffffff 0xfffffff7&gt;;
					};

modem_proc_lvl3 {
						trip = &lt;0x86&gt;;
						cooling-device = &lt;0x88 0x03 0x03&gt;;
					};

modem_lvl2 {
						trip = &lt;0x85&gt;;
						cooling-device = &lt;0x84 0x02 0x02&gt;;
					};

skin_gpu {
						trip = &lt;0x82&gt;;
						cooling-device = &lt;0x21 0xfffffff9 0xfffffff9&gt;;
					};

skin_cpu2 {
						trip = &lt;0x81&gt;;
						cooling-device = &lt;0x13 0xffffffff 0xfffffff7&gt;;
					};

modem_proc_lvl1 {
						trip = &lt;0x87&gt;;
						cooling-device = &lt;0x88 0x01 0x01&gt;;
					};

skin_cpu0 {
						trip = &lt;0x81&gt;;
						cooling-device = &lt;0x11 0xffffffff 0xfffffff7&gt;;
					};

battery_lvl4 {
						trip = &lt;0x8e&gt;;
						cooling-device = &lt;0x8a 0x06 0x06&gt;;
					};

battery_lvl2 {
						trip = &lt;0x8c&gt;;
						cooling-device = &lt;0x8a 0x04 0x04&gt;;
					};

skin_cpu7 {
						trip = &lt;0x80&gt;;
						cooling-device = &lt;0x18 0xffffffff 0xfffffff5&gt;;
					};

battery_lvl0 {
						trip = &lt;0x89&gt;;
						cooling-device = &lt;0x8a 0x01 0x01&gt;;
					};

skin_cpu5 {
						trip = &lt;0x81&gt;;
						cooling-device = &lt;0x16 0xffffffff 0xfffffff7&gt;;
					};

modem_lvl3 {
						trip = &lt;0x86&gt;;
						cooling-device = &lt;0x84 0x03 0x03&gt;;
					};

skin_cpu3 {
						trip = &lt;0x81&gt;;
						cooling-device = &lt;0x14 0xffffffff 0xfffffff7&gt;;
					};

modem_lvl1 {
						trip = &lt;0x83&gt;;
						cooling-device = &lt;0x84 0x01 0x01&gt;;
					};
				};
			};

cpu-0-1-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x02&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

cpu1-config {
						temperature = &lt;0x1adb0&gt;;
						hysteresis = &lt;0x2710&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x5d&gt;;
					};
				};

cooling-maps {

cpu1_cdev {
						trip = &lt;0x5d&gt;;
						cooling-device = &lt;0x12 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

mdm-core-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x06&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

pm6150-ibat-lvl1 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x55 0x01&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

ibat-lvl1 {
						temperature = &lt;0x1770&gt;;
						hysteresis = &lt;0xc8&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2c1&gt;;
					};
				};
			};

cpu-0-4-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x05&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-1-3-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x0c&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-1-1-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x0a&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

cpu6-1-config {
						temperature = &lt;0x1adb0&gt;;
						hysteresis = &lt;0x2710&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x63&gt;;
					};
				};

cooling-maps {

cpu6_cdev {
						trip = &lt;0x63&gt;;
						cooling-device = &lt;0x17 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

pm6150l-vph-lvl2 {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x58 0x04&gt;;
				thermal-governor = &quot;low_limits_cap&quot;;
				wake-capable-sensor;

trips {

vph-lvl2 {
						temperature = &lt;0x9c4&gt;;
						hysteresis = &lt;0xc8&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2ce&gt;;
					};
				};
			};

npu-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x0a&gt;;
				thermal-sensors = &lt;0x5a 0x08&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

npu-trip0 {
						temperature = &lt;0x17318&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x78&gt;;
					};
				};

cooling-maps {

npu_cdev {
						trip = &lt;0x78&gt;;
						cooling-device = &lt;0x79 0xffffffff 0xffffffff&gt;;
					};
				};
			};

conn_therm {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x2eb 0x4d&gt;;
				thermal-governor = &quot;user_space&quot;;

trips {

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

aoss-0-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x00&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cwlan-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x01&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

cwlan-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x6f&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x6f&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x6f&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x6f&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x6f&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x6f&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x6f&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x6f&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x6f&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

gpuss-0-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x0d&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

ddr-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x03&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

ddr-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x71&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x71&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x71&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x71&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x71&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x71&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x71&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x71&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x71&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

wifi_therm {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x2eb 0x4f&gt;;
				thermal-governor = &quot;user_space&quot;;

trips {

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

camera-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x05&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

camera-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x73&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x73&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x73&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x73&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x73&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x73&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x73&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x73&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x73&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

pm6150l-vph-lvl0 {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x58 0x02&gt;;
				thermal-governor = &quot;low_limits_cap&quot;;
				wake-capable-sensor;

trips {

vph-lvl0 {
						temperature = &lt;0xbb8&gt;;
						hysteresis = &lt;0xc8&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2cc&gt;;
					};
				};
			};

cpu-0-0-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x01&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

cpu0-config {
						temperature = &lt;0x1adb0&gt;;
						hysteresis = &lt;0x2710&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x5c&gt;;
					};
				};

cooling-maps {

cpu0_cdev {
						trip = &lt;0x5c&gt;;
						cooling-device = &lt;0x11 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

npu-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x08&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

pa_therm0 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x7f 0x4e&gt;;
				thermal-governor = &quot;user_space&quot;;

trips {

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

pm6150-tz {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x54&gt;;
				thermal-governor = &quot;step_wise&quot;;
				phandle = &lt;0x2bd&gt;;
				wake-capable-sensor;

trips {

trip2 {
						temperature = &lt;0x23668&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
					};

trip0 {
						temperature = &lt;0x17318&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2be&gt;;
					};

trip1 {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2bf&gt;;
					};
				};

cooling-maps {

trip0_bat {
						trip = &lt;0x2be&gt;;
						cooling-device = &lt;0x8a 0xfffffffd 0xfffffffd&gt;;
					};

trip1_bat {
						trip = &lt;0x2bf&gt;;
						cooling-device = &lt;0x8a 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

audio-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x02&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

audio-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x70&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x70&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x70&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x70&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x70&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x70&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x70&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x70&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x70&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

cpu-1-max-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

gold-trip {
						temperature = &lt;0x1d4c0&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-1-0-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x09&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

cpu6-0-config {
						temperature = &lt;0x1adb0&gt;;
						hysteresis = &lt;0x2710&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x62&gt;;
					};
				};

cooling-maps {

cpu6_cdev {
						trip = &lt;0x62&gt;;
						cooling-device = &lt;0x17 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

video-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x09&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

video-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x77&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x77&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x77&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x77&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x77&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x77&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x77&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x77&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x77&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};

video-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x09&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-0-1-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x02&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

mdm-dsp-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x07&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

lmh-dcvs-00 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x05&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

active-config {
						temperature = &lt;0x17318&gt;;
						hysteresis = &lt;0x7530&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-1-0-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x09&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-0-5-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x06&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

ddr-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x03&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

audio-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x02&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

gpuss-max-step {
				polling-delay = &lt;0x64&gt;;
				polling-delay-passive = &lt;0x0a&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

gpu-trip {
						temperature = &lt;0x17318&gt;;
						hysteresis = &lt;0x00&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x5b&gt;;
					};
				};

cooling-maps {

gpu_cdev {
						trip = &lt;0x5b&gt;;
						cooling-device = &lt;0x21 0xffffffff 0xffffffff&gt;;
					};
				};
			};

pm6150l-bcl-lvl2 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x64&gt;;
				thermal-sensors = &lt;0x58 0x07&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

l-bcl-lvl2 {
						temperature = &lt;0x01&gt;;
						hysteresis = &lt;0x01&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2d1&gt;;
					};
				};
			};

pm6150-bcl-lvl1 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x64&gt;;
				thermal-sensors = &lt;0x55 0x06&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

bcl-lvl1 {
						temperature = &lt;0x01&gt;;
						hysteresis = &lt;0x01&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2c6&gt;;
					};
				};

cooling-maps {

ibat_cpu7 {
						trip = &lt;0x2c6&gt;;
						cooling-device = &lt;0x18 0xfffffffe 0xfffffffe&gt;;
					};

ibat_cpu6 {
						trip = &lt;0x2c6&gt;;
						cooling-device = &lt;0x17 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

quiet_therm {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x7f 0x50&gt;;
				thermal-governor = &quot;user_space&quot;;

trips {

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

pm6150-vbat-lvl2 {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x55 0x04&gt;;
				thermal-governor = &quot;low_limits_cap&quot;;
				wake-capable-sensor;

trips {

vbat-lvl2 {
						temperature = &lt;0xa28&gt;;
						hysteresis = &lt;0xc8&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2c4&gt;;
					};
				};
			};

aoss-1-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x00&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

gpuss-1-usr {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x0e&gt;;
				thermal-governor = &quot;user_space&quot;;
				wake-capable-sensor;

trips {

reset-mon-cfg {
						temperature = &lt;0x1c138&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
					};

active-config0 {
						temperature = &lt;0x1e848&gt;;
						hysteresis = &lt;0x3e8&gt;;
						type = &quot;passive&quot;;
					};
				};
			};

cpu-0-5-step {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x59 0x06&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

cpu5-config {
						temperature = &lt;0x1adb0&gt;;
						hysteresis = &lt;0x2710&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x61&gt;;
					};
				};

cooling-maps {

cpu5_cdev {
						trip = &lt;0x61&gt;;
						cooling-device = &lt;0x16 0xfffffffe 0xfffffffe&gt;;
					};
				};
			};

pm6150l-bcl-lvl0 {
				polling-delay = &lt;0x00&gt;;
				polling-delay-passive = &lt;0x64&gt;;
				thermal-sensors = &lt;0x58 0x05&gt;;
				thermal-governor = &quot;step_wise&quot;;
				wake-capable-sensor;

trips {

l-bcl-lvl0 {
						temperature = &lt;0x01&gt;;
						hysteresis = &lt;0x01&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2cf&gt;;
					};
				};
			};

pm6150-vbat-lvl0 {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x55 0x02&gt;;
				thermal-governor = &quot;low_limits_cap&quot;;
				wake-capable-sensor;

trips {

vbat-lvl0 {
						temperature = &lt;0xbb8&gt;;
						hysteresis = &lt;0xc8&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x2c2&gt;;
					};
				};
			};

npu-lowf {
				polling-delay = &lt;0x00&gt;;
				tracks-low;
				polling-delay-passive = &lt;0x00&gt;;
				thermal-sensors = &lt;0x5a 0x08&gt;;
				thermal-governor = &quot;low_limits_floor&quot;;
				wake-capable-sensor;

trips {

npu-trip {
						temperature = &lt;0x1388&gt;;
						hysteresis = &lt;0x1388&gt;;
						type = &quot;passive&quot;;
						phandle = &lt;0x76&gt;;
					};
				};

cooling-maps {

cdsp_vdd_cdev {
						trip = &lt;0x76&gt;;
						cooling-device = &lt;0x6b 0x00 0x00&gt;;
					};

adsp_vdd_cdev {
						trip = &lt;0x76&gt;;
						cooling-device = &lt;0x6a 0x00 0x00&gt;;
					};

cpu1_cdev {
						trip = &lt;0x76&gt;;
						cooling-device = &lt;0x17 0x04 0x04&gt;;
					};

cx_vdd_cdev {
						trip = &lt;0x76&gt;;
						cooling-device = &lt;0x67 0x00 0x00&gt;;
					};

mx_vdd_cdev {
						trip = &lt;0x76&gt;;
						cooling-device = &lt;0x68 0x00 0x00&gt;;
					};

cpu0_cdev {
						trip = &lt;0x76&gt;;
						cooling-device = &lt;0x11 0x02 0x02&gt;;
					};

modem_vdd_cdev {
						trip = &lt;0x76&gt;;
						cooling-device = &lt;0x69 0x00 0x00&gt;;
					};

gpu_vdd_cdev {
						trip = &lt;0x76&gt;;
						cooling-device = &lt;0x21 0xfffffffb 0xfffffffb&gt;;
					};
				};
			};
		};

qcom,cpu6-computemon {
			qcom,core-dev-table = &lt;0x10b170 0x478 0x1433e0 0x826 0x17af48 0xb71 0x1a0fe0 0xf27 0x253500 0x1ae1&gt;;
			qcom,cpulist = &lt;0x17 0x18&gt;;
			compatible = &quot;qcom,arm-cpu-mon&quot;;
			phandle = &lt;0x31a&gt;;
			qcom,target-dev = &lt;0xc6&gt;;
		};

qcom,cpas-cdm0@ac48000 {
			camss-supply = &lt;0x1ae&gt;;
			clock-names = &quot;cam_cc_cpas_slow_ahb_clk\0cam_cc_cpas_ahb_clk&quot;;
			reg-names = &quot;cpas-cdm&quot;;
			reg-cam-base = &lt;0x48000&gt;;
			cdm-client-names = &quot;ife&quot;;
			cell-index = &lt;0x00&gt;;
			interrupts = &lt;0x00 0x1d4 0x00&gt;;
			clocks = &lt;0x29 0x5a 0x29 0x1a&gt;;
			label = &quot;cpas-cdm&quot;;
			clock-cntl-level = &quot;svs&quot;;
			compatible = &quot;qcom,cam170-cpas-cdm0&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;cpas-cdm&quot;;
			reg = &lt;0xac48000 0x1000&gt;;
			regulator-names = &quot;camss&quot;;
			clock-rates = &lt;0x00 0x00&gt;;
		};

pinctrl@3400000 {
			reg-names = &quot;pinctrl\0spi_cfg&quot;;
			gpio-controller;
			interrupts = &lt;0x00 0xd0 0x00&gt;;
			compatible = &quot;qcom,sdmmagpie-pinctrl&quot;;
			#interrupt-cells = &lt;0x02&gt;;
			reg = &lt;0x3400000 0xdc2000 0x17c000f0 0x60&gt;;
			phandle = &lt;0x174&gt;;
			#gpio-cells = &lt;0x02&gt;;
			interrupt-controller;

sdc1_cmd_on {
				phandle = &lt;0x3df&gt;;

config {
					pins = &quot;sdc1_cmd&quot;;
					drive-strength = &lt;0x0a&gt;;
					bias-pull-up;
				};
			};

qupv3_se11_4uart_pins {
				phandle = &lt;0x3c4&gt;;

qupv3_se11_rts {
					phandle = &lt;0x195&gt;;

mux {
						function = &quot;qup15&quot;;
						pins = &quot;gpio102&quot;;
					};

config {
						pins = &quot;gpio102&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
					};
				};

qupv3_se11_tx {
					phandle = &lt;0x196&gt;;

mux {
						function = &quot;qup15&quot;;
						pins = &quot;gpio103&quot;;
					};

config {
						pins = &quot;gpio103&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

qupv3_se11_ctsrx {
					phandle = &lt;0x194&gt;;

mux {
						function = &quot;qup15&quot;;
						pins = &quot;gpio101\0gpio92&quot;;
					};

config {
						pins = &quot;gpio101\0gpio92&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-no-pull;
					};
				};
			};

pmx_ts_int_suspend {

ts_int_suspend {
					phandle = &lt;0x590&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio9&quot;;
					};

config {
						pins = &quot;gpio9&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
						bias-pull-down;
					};
				};

tp_int_suspend {
					phandle = &lt;0x59c&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio9&quot;;
					};

config {
						pins = &quot;gpio9&quot;;
						drive-strength = &lt;0x10&gt;;
						slew-rate = &lt;0x00&gt;;
						bias-pull-up = &lt;0x00&gt;;
						input-enable;
					};
				};
			};

cam_sensor_wide_active {
				phandle = &lt;0x564&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio26&quot;;
				};

config {
					pins = &quot;gpio26&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

aw8624_gpio_reset_output_high {
				phandle = &lt;0x58c&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio4&quot;;
				};

config {
					pins = &quot;gpio4&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
					output-high;
				};
			};

sdc2_cmd_on {
				phandle = &lt;0x3e7&gt;;

config {
					pins = &quot;sdc2_cmd&quot;;
					drive-strength = &lt;0x0a&gt;;
					bias-pull-up;
				};
			};

cam_sensor_ultra_active {
				phandle = &lt;0x581&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio25&quot;;
				};

config {
					pins = &quot;gpio25&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

onewire_gpio_active {
				phandle = &lt;0x587&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio91&quot;;
				};

config {
					pins = &quot;gpio91&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
				};
			};

qupv3_se6_spi_pins {
				phandle = &lt;0x3b9&gt;;

qupv3_se6_spi_sleep {
					phandle = &lt;0x198&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio59\0gpio60\0gpio61\0gpio62&quot;;
					};

config {
						pins = &quot;gpio59\0gpio60\0gpio61\0gpio62&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};

qupv3_se6_spi_active {
					phandle = &lt;0x197&gt;;

mux {
						function = &quot;qup10&quot;;
						pins = &quot;gpio59\0gpio60\0gpio61\0gpio62&quot;;
					};

config {
						pins = &quot;gpio59\0gpio60\0gpio61\0gpio62&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};
			};

qupv3_se3_4uart_pins {
				phandle = &lt;0x3b0&gt;;

qupv3_se3_rts {
					phandle = &lt;0x172&gt;;

mux {
						function = &quot;qup03&quot;;
						pins = &quot;gpio39&quot;;
					};

config {
						pins = &quot;gpio39&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
					};
				};

qupv3_se3_tx {
					phandle = &lt;0x173&gt;;

mux {
						function = &quot;qup03&quot;;
						pins = &quot;gpio40&quot;;
					};

config {
						pins = &quot;gpio40&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

qupv3_se3_ctsrx {
					phandle = &lt;0x171&gt;;

mux {
						function = &quot;qup03&quot;;
						pins = &quot;gpio38\0gpio41&quot;;
					};

config {
						pins = &quot;gpio38\0gpio41&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-no-pull;
					};
				};
			};

qupv3_se11_i2c_pins {
				phandle = &lt;0x3c3&gt;;

qupv3_se11_i2c_active {
					phandle = &lt;0x18f&gt;;

mux {
						function = &quot;qup15&quot;;
						pins = &quot;gpio101\0gpio102&quot;;
					};

config {
						pins = &quot;gpio101\0gpio102&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};

qupv3_se11_i2c_sleep {
					phandle = &lt;0x190&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio101\0gpio102&quot;;
					};

config {
						pins = &quot;gpio101\0gpio102&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};
			};

qupv3_se2_i2c_pins {
				phandle = &lt;0x3a8&gt;;

qupv3_se2_i2c_sleep {
					phandle = &lt;0x16c&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio34\0gpio35&quot;;
					};

config {
						pins = &quot;gpio34\0gpio35&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

qupv3_se2_i2c_active {
					phandle = &lt;0x16b&gt;;

mux {
						function = &quot;qup02&quot;;
						pins = &quot;gpio34\0gpio35&quot;;
					};

config {
						pins = &quot;gpio34\0gpio35&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};
			};

sdc2_data_on {
				phandle = &lt;0x3e9&gt;;

config {
					pins = &quot;sdc2_data&quot;;
					drive-strength = &lt;0x0a&gt;;
					bias-pull-up;
				};
			};

onewire_gpio_sleep {
				phandle = &lt;0x588&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio91&quot;;
				};

config {
					pins = &quot;gpio91&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
				};
			};

fpc_reset_int {

int_low {
					phandle = &lt;0x3b4&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio90&quot;;
					};

config {
						pins = &quot;gpio90&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
						input-enable;
					};
				};

reset_high {
					phandle = &lt;0x3b3&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio91&quot;;
					};

config {
						pins = &quot;gpio91&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
						output-high;
					};
				};

reset_low {
					phandle = &lt;0x3b2&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio91&quot;;
					};

config {
						pins = &quot;gpio91&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
						output-low;
					};
				};
			};

ufs_dev_reset_assert {
				phandle = &lt;0x9d&gt;;

config {
					pins = &quot;ufs_reset&quot;;
					drive-strength = &lt;0x08&gt;;
					bias-pull-down;
					output-low;
				};
			};

sdc1_rclk_off {
				phandle = &lt;0x3e4&gt;;

config {
					pins = &quot;sdc1_rclk&quot;;
					bias-pull-down;
				};
			};

qupv3_se11_spi_pins {
				phandle = &lt;0x3c5&gt;;

qupv3_se11_spi_sleep {
					phandle = &lt;0x1a0&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio101\0gpio102\0gpio103\0gpio92&quot;;
					};

config {
						pins = &quot;gpio101\0gpio102\0gpio103\0gpio92&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};

qupv3_se11_spi_active {
					phandle = &lt;0x19f&gt;;

mux {
						function = &quot;qup15&quot;;
						pins = &quot;gpio101\0gpio102\0gpio103\0gpio92&quot;;
					};

config {
						pins = &quot;gpio101\0gpio102\0gpio103\0gpio92&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};
			};

qupv3_se7_i2c_pins {
				phandle = &lt;0x3ba&gt;;

qupv3_se7_i2c_sleep {
					phandle = &lt;0x187&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio6\0gpio7&quot;;
					};

config {
						pins = &quot;gpio6\0gpio7&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

qupv3_se7_i2c_active {
					phandle = &lt;0x186&gt;;

mux {
						function = &quot;qup11&quot;;
						pins = &quot;gpio6\0gpio7&quot;;
					};

config {
						pins = &quot;gpio6\0gpio7&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};
			};

aw8624_gpio_reset {
				phandle = &lt;0x58b&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio4&quot;;
				};

config {
					pins = &quot;gpio4&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
					output-low;
				};
			};

cam_sensor_vddio_disable {
				phandle = &lt;0x5a2&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio5&quot;;
				};

config {
					pins = &quot;gpio5&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
					output-low;
				};
			};

msm_gpio_58 {
				phandle = &lt;0x584&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio58&quot;;
				};

config {
					pins = &quot;gpio58&quot;;
					driver-strength = &lt;0x02&gt;;
					bias-disable;
					output-low;
				};
			};

cd_off {
				phandle = &lt;0x3ec&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio69&quot;;
				};

config {
					pins = &quot;gpio69&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

bot_smartpa_int_active {
				phandle = &lt;0x51e&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio56&quot;;
				};

config {
					pins = &quot;gpio56&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
					input-enable;
				};
			};

cam_sensor_f_vdda_f_vddd_enable {
				phandle = &lt;0x5a3&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio57&quot;;
				};

config {
					pins = &quot;gpio57&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

smartpa_int_active {
				phandle = &lt;0x3f9&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio56&quot;;
				};

config {
					pins = &quot;gpio56&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
					input-enable;
				};
			};

smartpa_enable_active {
				phandle = &lt;0x3fb&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio67&quot;;
				};

config {
					pins = &quot;gpio67&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
					bias-pull-down;
					output-low;
				};
			};

cam_sensor_mipi_switch_sel_high {
				phandle = &lt;0x575&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio88&quot;;
				};

config {
					pins = &quot;gpio88&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
					output-low;
				};
			};

sdc2_clk_off {
				phandle = &lt;0x3e6&gt;;

config {
					pins = &quot;sdc2_clk&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

qupv3_se7_spi_pins {
				phandle = &lt;0x3bb&gt;;

qupv3_se7_spi_sleep {
					phandle = &lt;0x19a&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio6\0gpio7\0gpio8\0gpio9&quot;;
					};

config {
						pins = &quot;gpio6\0gpio7\0gpio8\0gpio9&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};

qupv3_se7_spi_active {
					phandle = &lt;0x199&gt;;

mux {
						function = &quot;qup11&quot;;
						pins = &quot;gpio6\0gpio7\0gpio8\0gpio9&quot;;
					};

config {
						pins = &quot;gpio6\0gpio7\0gpio8\0gpio9&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};
			};

cam_sensor_mclk1_suspend {
				phandle = &lt;0x582&gt;;

mux {
					function = &quot;cam_mclk&quot;;
					pins = &quot;gpio14&quot;;
				};

config {
					pins = &quot;gpio14&quot;;
					drive-strength = &lt;0x04&gt;;
					bias-pull-down;
				};
			};

cam_sensor_front_active {
				phandle = &lt;0x56d&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio23&quot;;
				};

config {
					pins = &quot;gpio23&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

sdc2_cmd_off {
				phandle = &lt;0x3e8&gt;;

config {
					pins = &quot;sdc2_cmd&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
				};
			};

qupv3_se3_i2c_pins {
				phandle = &lt;0x3af&gt;;

qupv3_se3_i2c_active {
					phandle = &lt;0x16d&gt;;

mux {
						function = &quot;qup03&quot;;
						pins = &quot;gpio38\0gpio39&quot;;
					};

config {
						pins = &quot;gpio38\0gpio39&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};

qupv3_se3_i2c_sleep {
					phandle = &lt;0x16e&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio38\0gpio39&quot;;
					};

config {
						pins = &quot;gpio38\0gpio39&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};
			};

nfc {

nfc_int_suspend {
					phandle = &lt;0x3aa&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio37&quot;;
					};

config {
						pins = &quot;gpio37&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

nfc_enable_active {
					phandle = &lt;0x3ab&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio66\0gpio36&quot;;
					};

config {
						pins = &quot;gpio66\0gpio36&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

nfc_int_active {
					phandle = &lt;0x3a9&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio37&quot;;
					};

config {
						pins = &quot;gpio37&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

nfc_enable_suspend {
					phandle = &lt;0x3ac&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio66\0gpio36&quot;;
					};

config {
						pins = &quot;gpio66\0gpio36&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};

nfc_clk_req_active {
					phandle = &lt;0x3ad&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio31&quot;;
					};

config {
						pins = &quot;gpio31&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

nfc_clk_req_suspend {
					phandle = &lt;0x3ae&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio31&quot;;
					};

config {
						pins = &quot;gpio31&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};
			};

pri_i2s_data0 {

pri_i2s_data0_sleep {
					phandle = &lt;0x51a&gt;;

mux {
						function = &quot;pri_mi2s&quot;;
						pins = &quot;gpio52&quot;;
					};

config {
						pins = &quot;gpio52&quot;;
						drive-strength = &lt;0x02&gt;;
					};
				};

pri_i2s_data0_active {
					phandle = &lt;0x516&gt;;

mux {
						function = &quot;pri_mi2s&quot;;
						pins = &quot;gpio52&quot;;
					};

config {
						pins = &quot;gpio52&quot;;
						drive-strength = &lt;0x08&gt;;
						bias-disable;
						input-enable;
					};
				};
			};

cam_sensor_wide_suspend {
				phandle = &lt;0x566&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio26&quot;;
				};

config {
					pins = &quot;gpio26&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
					output-low;
				};
			};

sdc1_clk_on {
				phandle = &lt;0x3dd&gt;;

config {
					pins = &quot;sdc1_clk&quot;;
					drive-strength = &lt;0x10&gt;;
					bias-disable;
				};
			};

wsa_swr_data_pin {

wsa_swr_data_active {
					phandle = &lt;0x3cf&gt;;

mux {
						function = &quot;wsa_data&quot;;
						pins = &quot;gpio50&quot;;
					};

config {
						pins = &quot;gpio50&quot;;
						drive-strength = &lt;0x04&gt;;
						bias-bus-hold;
					};
				};

wsa_swr_data_sleep {
					phandle = &lt;0x3ce&gt;;

mux {
						function = &quot;wsa_data&quot;;
						pins = &quot;gpio50&quot;;
					};

config {
						pins = &quot;gpio50&quot;;
						drive-strength = &lt;0x04&gt;;
						bias-bus-hold;
					};
				};
			};

pmx_ts_reset_suspend {

ts_reset_suspend {
					phandle = &lt;0x591&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio8&quot;;
					};

config {
						pins = &quot;gpio8&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
						bias-pull-down;
					};
				};

tp_reset_suspend {
					phandle = &lt;0x59d&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio8&quot;;
					};

config {
						pins = &quot;gpio8&quot;;
						drive-strength = &lt;0x10&gt;;
						bias-disable;
						output-high;
						slew-rate = &lt;0x01&gt;;
					};
				};
			};

qupv3_se8_i2c_pins {
				phandle = &lt;0x3bc&gt;;

qupv3_se8_i2c_active {
					phandle = &lt;0x188&gt;;

mux {
						function = &quot;qup12&quot;;
						pins = &quot;gpio42\0gpio43&quot;;
					};

config {
						pins = &quot;gpio42\0gpio43&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};

qupv3_se8_i2c_sleep {
					phandle = &lt;0x189&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio42\0gpio43&quot;;
					};

config {
						pins = &quot;gpio42\0gpio43&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};
			};

sdc2_clk_on {
				phandle = &lt;0x3e5&gt;;

config {
					pins = &quot;sdc2_clk&quot;;
					drive-strength = &lt;0x10&gt;;
					bias-disable;
				};
			};

cam_sensor_depth_active {
				phandle = &lt;0x57b&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio21&quot;;
				};

config {
					pins = &quot;gpio21&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

cci1_suspend {
				phandle = &lt;0x1b3&gt;;

mux {
					function = &quot;cci_i2c&quot;;
					pins = &quot;gpio19\0gpio20&quot;;
				};

config {
					pins = &quot;gpio19\0gpio20&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
				};
			};

qupv3_se3_spi_pins {
				phandle = &lt;0x3b1&gt;;

qupv3_se3_spi_sleep {
					phandle = &lt;0x17d&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio38\0gpio39\0gpio40\0gpio41&quot;;
					};

config {
						pins = &quot;gpio38\0gpio39\0gpio40\0gpio41&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};

qupv3_se3_spi_active {
					phandle = &lt;0x17c&gt;;

mux {
						function = &quot;qup03&quot;;
						pins = &quot;gpio38\0gpio39\0gpio40\0gpio41&quot;;
					};

config {
						pins = &quot;gpio38\0gpio39\0gpio40\0gpio41&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};
			};

cam_sensor_mipi_switch_sel_low {
				phandle = &lt;0x578&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio88&quot;;
				};

config {
					pins = &quot;gpio88&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

sde_dp_aux_suspend {
				phandle = &lt;0x3cb&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio42\0gpio33&quot;;
				};

config {
					pins = &quot;gpio42\0gpio33&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
				};
			};

cam_sensor_mclk3_suspend {
				phandle = &lt;0x576&gt;;

mux {
					function = &quot;cam_mclk&quot;;
					pins = &quot;gpio16&quot;;
				};

config {
					pins = &quot;gpio16&quot;;
					drive-strength = &lt;0x04&gt;;
					bias-pull-down;
				};
			};

cam_sensor_front_suspend {
				phandle = &lt;0x56f&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio23&quot;;
				};

config {
					pins = &quot;gpio23&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
					output-low;
				};
			};

wcd9xxx_intr {

wcd_intr_default {
					phandle = &lt;0x3d4&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio58&quot;;
					};

config {
						pins = &quot;gpio58&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
						input-enable;
					};
				};
			};

pmx_ts_release {

ts_release {
					phandle = &lt;0x3f0&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio9\0gpio8&quot;;
					};

config {
						pins = &quot;gpio9\0gpio8&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};
			};

qupv3_se4_4uart_pins {
				phandle = &lt;0x3b6&gt;;

qupv3_se4_ctsrx {
					phandle = &lt;0x175&gt;;

mux {
						function = &quot;qup04&quot;;
						pins = &quot;gpio53\0gpio56&quot;;
					};

config {
						pins = &quot;gpio53\0gpio56&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-no-pull;
					};
				};

qupv3_se4_tx {
					phandle = &lt;0x177&gt;;

mux {
						function = &quot;qup04&quot;;
						pins = &quot;gpio55&quot;;
					};

config {
						pins = &quot;gpio55&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

qupv3_se4_rts {
					phandle = &lt;0x176&gt;;

mux {
						function = &quot;qup04&quot;;
						pins = &quot;gpio54&quot;;
					};

config {
						pins = &quot;gpio54&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
					};
				};
			};

qupv3_se8_spi_pins {
				phandle = &lt;0x3be&gt;;

qupv3_se8_spi_sleep {
					phandle = &lt;0x19c&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio42\0gpio43\0gpio44\0gpio45&quot;;
					};

config {
						pins = &quot;gpio42\0gpio43\0gpio44\0gpio45&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};

qupv3_se8_spi_active {
					phandle = &lt;0x19b&gt;;

mux {
						function = &quot;qup12&quot;;
						pins = &quot;gpio42\0gpio43\0gpio44\0gpio45&quot;;
					};

config {
						pins = &quot;gpio42\0gpio43\0gpio44\0gpio45&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};
			};

cam_sensor_mclk0_active {
				phandle = &lt;0x56c&gt;;

mux {
					function = &quot;cam_mclk&quot;;
					pins = &quot;gpio13&quot;;
				};

config {
					pins = &quot;gpio13&quot;;
					drive-strength = &lt;0x06&gt;;
					bias-disable;
				};
			};

fsa_usbc_ana_en_n@42 {

fsa_usbc_ana_en {
					phandle = &lt;0x18c&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio42&quot;;
					};

config {
						pins = &quot;gpio42&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
						output-low;
					};
				};
			};

bq2597x {

bq2597x_int_suspend {
					phandle = &lt;0x58a&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio55&quot;;
					};

config {
						pins = &quot;gpio55&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
						input-enable;
					};
				};

bq2597x_int_default {
					phandle = &lt;0x589&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio55&quot;;
					};

config {
						pins = &quot;gpio55&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
						input-enable;
					};
				};
			};

qupv3_se4_i2c_pins {
				phandle = &lt;0x3b5&gt;;

qupv3_se4_i2c_active {
					phandle = &lt;0x16f&gt;;

mux {
						function = &quot;qup04&quot;;
						pins = &quot;gpio53\0gpio54&quot;;
					};

config {
						pins = &quot;gpio53\0gpio54&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};

qupv3_se4_i2c_sleep {
					phandle = &lt;0x170&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio53\0gpio54&quot;;
					};

config {
						pins = &quot;gpio53\0gpio54&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};
			};

top_smartpa_int_suspend {
				phandle = &lt;0x51d&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio93&quot;;
				};

config {
					pins = &quot;gpio93&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
					input-enable;
				};
			};

sdc1_data_on {
				phandle = &lt;0x3e1&gt;;

config {
					pins = &quot;sdc1_data&quot;;
					drive-strength = &lt;0x0a&gt;;
					bias-pull-up;
				};
			};

pmx_sde_te {

sde_te_suspend {
					phandle = &lt;0x3c7&gt;;

mux {
						function = &quot;mdp_vsync&quot;;
						pins = &quot;gpio10&quot;;
					};

config {
						pins = &quot;gpio10&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
					};
				};

sde_te1_active {
					phandle = &lt;0x3c8&gt;;

mux {
						function = &quot;mdp_vsync&quot;;
						pins = &quot;gpio11&quot;;
					};

config {
						pins = &quot;gpio11&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
					};
				};

sde_te1_suspend {
					phandle = &lt;0x3c9&gt;;

mux {
						function = &quot;mdp_vsync&quot;;
						pins = &quot;gpio11&quot;;
					};

config {
						pins = &quot;gpio11&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
					};
				};

sde_te_active {
					phandle = &lt;0x3c6&gt;;

mux {
						function = &quot;mdp_vsync&quot;;
						pins = &quot;gpio10&quot;;
					};

config {
						pins = &quot;gpio10&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
					};
				};
			};

cam_sensor_mclk1_active {
				phandle = &lt;0x580&gt;;

mux {
					function = &quot;cam_mclk&quot;;
					pins = &quot;gpio14&quot;;
				};

config {
					pins = &quot;gpio14&quot;;
					drive-strength = &lt;0x04&gt;;
					bias-disable;
				};
			};

sde_dp_aux_active {
				phandle = &lt;0x3ca&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio42\0gpio33&quot;;
				};

config {
					pins = &quot;gpio42\0gpio33&quot;;
					drive-strength = &lt;0x08&gt;;
					bias-disable = &lt;0x00&gt;;
				};
			};

sdc1_rclk_on {
				phandle = &lt;0x3e3&gt;;

config {
					pins = &quot;sdc1_rclk&quot;;
					bias-pull-down;
				};
			};

qupv3_se10_4uart_pins {
				phandle = &lt;0x3c1&gt;;

qupv3_se10_ctsrx {
					phandle = &lt;0x191&gt;;

mux {
						function = &quot;qup14&quot;;
						pins = &quot;gpio110\0gpio113&quot;;
					};

config {
						pins = &quot;gpio110\0gpio113&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-no-pull;
					};
				};

qupv3_se10_tx {
					phandle = &lt;0x193&gt;;

mux {
						function = &quot;qup14&quot;;
						pins = &quot;gpio112&quot;;
					};

config {
						pins = &quot;gpio112&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

qupv3_se10_rts {
					phandle = &lt;0x192&gt;;

mux {
						function = &quot;qup14&quot;;
						pins = &quot;gpio111&quot;;
					};

config {
						pins = &quot;gpio111&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
					};
				};
			};

bot_smartpa_int_suspend {
				phandle = &lt;0x51f&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio56&quot;;
				};

config {
					pins = &quot;gpio56&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
					input-enable;
				};
			};

cam_sensor_mclk2_active {
				phandle = &lt;0x563&gt;;

mux {
					function = &quot;cam_mclk&quot;;
					pins = &quot;gpio15&quot;;
				};

config {
					pins = &quot;gpio15&quot;;
					drive-strength = &lt;0x04&gt;;
					bias-disable;
				};
			};

qupv3_se9_i2c_pins {
				phandle = &lt;0x3bf&gt;;

qupv3_se9_i2c_active {
					phandle = &lt;0x18a&gt;;

mux {
						function = &quot;qup13&quot;;
						pins = &quot;gpio46\0gpio47&quot;;
					};

config {
						pins = &quot;gpio46\0gpio47&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};

qupv3_se9_i2c_sleep {
					phandle = &lt;0x18b&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio46\0gpio47&quot;;
					};

config {
						pins = &quot;gpio6\0gpio7&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};
			};

qupv3_se4_spi_pins {
				phandle = &lt;0x3b7&gt;;

qupv3_se4_spi_active {
					phandle = &lt;0x17e&gt;;

mux {
						function = &quot;qup04&quot;;
						pins = &quot;gpio53\0gpio54\0gpio55\0gpio56&quot;;
					};

config {
						pins = &quot;gpio53\0gpio54\0gpio55\0gpio56&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};

qupv3_se4_spi_sleep {
					phandle = &lt;0x17f&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio53\0gpio54\0gpio55\0gpio56&quot;;
					};

config {
						pins = &quot;gpio53\0gpio54\0gpio55\0gpio56&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};
			};

pmx_ts_active {

tp_active {
					phandle = &lt;0x59b&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio9\0gpio8&quot;;
					};

config {
						pins = &quot;gpio9\0gpio8&quot;;
						drive-strength = &lt;0x10&gt;;
						bias-pull-up;
					};
				};

ts_active {
					phandle = &lt;0x58f&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio8\0gpio9&quot;;
					};

config {
						pins = &quot;gpio8\0gpio9&quot;;
						drive-strength = &lt;0x08&gt;;
						bias-pull-up;
					};
				};
			};

cam_sensor_mclk3_active {
				phandle = &lt;0x573&gt;;

mux {
					function = &quot;cam_mclk&quot;;
					pins = &quot;gpio16&quot;;
				};

config {
					pins = &quot;gpio16&quot;;
					drive-strength = &lt;0x04&gt;;
					bias-disable;
				};
			};

qupv3_se0_i2c_pins {
				phandle = &lt;0x3a4&gt;;

qupv3_se0_i2c_sleep {
					phandle = &lt;0x167&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio49\0gpio50&quot;;
					};

config {
						pins = &quot;gpio49\0gpio50&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

qupv3_se0_i2c_active {
					phandle = &lt;0x166&gt;;

mux {
						function = &quot;qup00&quot;;
						pins = &quot;gpio49\0gpio50&quot;;
					};

config {
						pins = &quot;gpio49\0gpio50&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};
			};

top_smartpa_int_active {
				phandle = &lt;0x51c&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio93&quot;;
				};

config {
					pins = &quot;gpio93&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
					input-enable;
				};
			};

qupv3_se8_2uart_pins {
				phandle = &lt;0x3bd&gt;;

qupv3_se8_2uart_sleep {
					phandle = &lt;0x181&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio44\0gpio45&quot;;
					};

config {
						pins = &quot;gpio44\0gpio45&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};

qupv3_se8_2uart_active {
					phandle = &lt;0x180&gt;;

mux {
						function = &quot;qup12&quot;;
						pins = &quot;gpio44\0gpio45&quot;;
					};

config {
						pins = &quot;gpio44\0gpio45&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};
			};

sde_dp_usbplug_cc_suspend {
				phandle = &lt;0x1ad&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio104&quot;;
				};

config {
					pins = &quot;gpio104&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
				};
			};

cam_sensor_depth_suspend {
				phandle = &lt;0x57c&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio21&quot;;
				};

config {
					pins = &quot;gpio21&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
					output-low;
				};
			};

sdc1_clk_off {
				phandle = &lt;0x3de&gt;;

config {
					pins = &quot;sdc1_clk&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

sdc1_data_off {
				phandle = &lt;0x3e2&gt;;

config {
					pins = &quot;sdc1_data&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
				};
			};

cam_sensor_mclk0_suspend {
				phandle = &lt;0x56e&gt;;

mux {
					function = &quot;cam_mclk&quot;;
					pins = &quot;gpio13&quot;;
				};

config {
					pins = &quot;gpio13&quot;;
					drive-strength = &lt;0x06&gt;;
					bias-pull-down;
				};
			};

ufs_dev_reset_deassert {
				phandle = &lt;0x9e&gt;;

config {
					pins = &quot;ufs_reset&quot;;
					drive-strength = &lt;0x08&gt;;
					output-high;
					bias-pull-down;
				};
			};

smartpa_int_suspend {
				phandle = &lt;0x3fa&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio56&quot;;
				};

config {
					pins = &quot;gpio56&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
					input-enable;
				};
			};

cam_sensor_ultra_suspend {
				phandle = &lt;0x583&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio25&quot;;
				};

config {
					pins = &quot;gpio25&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
					output-low;
				};
			};

pri_i2s_sck_ws {

pri_i2s_sck_sleep {
					phandle = &lt;0x518&gt;;

mux {
						function = &quot;pri_mi2s&quot;;
						pins = &quot;gpio49&quot;;
					};

config {
						pins = &quot;gpio49&quot;;
						drive-strength = &lt;0x02&gt;;
					};
				};

pri_i2s_ws_active {
					phandle = &lt;0x515&gt;;

mux {
						function = &quot;pri_mi2s_ws&quot;;
						pins = &quot;gpio50&quot;;
					};

config {
						pins = &quot;gpio50&quot;;
						drive-strength = &lt;0x08&gt;;
						bias-disable;
						output-high;
					};
				};

pri_i2s_sck_active {
					phandle = &lt;0x514&gt;;

mux {
						function = &quot;pri_mi2s&quot;;
						pins = &quot;gpio49&quot;;
					};

config {
						pins = &quot;gpio49&quot;;
						drive-strength = &lt;0x08&gt;;
						bias-disable;
						output-high;
					};
				};

pri_i2s_ws_sleep {
					phandle = &lt;0x519&gt;;

mux {
						function = &quot;pri_mi2s_ws&quot;;
						pins = &quot;gpio50&quot;;
					};

config {
						pins = &quot;gpio50&quot;;
						drive-strength = &lt;0x02&gt;;
					};
				};
			};

cam_sensor_mipi_switch1_sel_high {
				phandle = &lt;0x5a6&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio90&quot;;
				};

config {
					pins = &quot;gpio90&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
					output-low;
				};
			};

sdc1_cmd_off {
				phandle = &lt;0x3e0&gt;;

config {
					num-grp-pins = &lt;0x01&gt;;
					pins = &quot;sdc1_cmd&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
				};
			};

qupv3_se0_spi_pins {
				phandle = &lt;0x3a5&gt;;

qupv3_se0_spi_sleep {
					phandle = &lt;0x179&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio49\0gpio50\0gpio51\0gpio52&quot;;
					};

config {
						pins = &quot;gpio49\0gpio50\0gpio51\0gpio52&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};

qupv3_se0_spi_active {
					phandle = &lt;0x178&gt;;

mux {
						function = &quot;qup00&quot;;
						pins = &quot;gpio49\0gpio50\0gpio51\0gpio52&quot;;
					};

config {
						pins = &quot;gpio49\0gpio50\0gpio51\0gpio52&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};
			};

msm_gpio_57 {
				phandle = &lt;0x586&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio57&quot;;
				};

config {
					pins = &quot;gpio57&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
				};
			};

pri_i2s_data1 {

pri_i2s_data1_sleep {
					phandle = &lt;0x51b&gt;;

mux {
						function = &quot;pri_mi2s&quot;;
						pins = &quot;gpio51&quot;;
					};

config {
						pins = &quot;gpio51&quot;;
						drive-strength = &lt;0x02&gt;;
					};
				};

pri_i2s_data1_active {
					phandle = &lt;0x517&gt;;

mux {
						function = &quot;pri_mi2s&quot;;
						pins = &quot;gpio51&quot;;
					};

config {
						pins = &quot;gpio51&quot;;
						drive-strength = &lt;0x08&gt;;
						bias-disable;
						output-high;
					};
				};
			};

spkr_2_sd_n {

spkr_2_sd_n_active {
					phandle = &lt;0x3d3&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio52&quot;;
					};

config {
						pins = &quot;gpio52&quot;;
						drive-strength = &lt;0x10&gt;;
						bias-disable;
						output-high;
					};
				};

spkr_2_sd_n_sleep {
					phandle = &lt;0x3d2&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio52&quot;;
					};

config {
						pins = &quot;gpio52&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
						input-enable;
					};
				};
			};

wsa_swr_clk_pin {

wsa_swr_clk_active {
					phandle = &lt;0x3cd&gt;;

mux {
						function = &quot;wsa_clk&quot;;
						pins = &quot;gpio49&quot;;
					};

config {
						pins = &quot;gpio49&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-bus-hold;
					};
				};

wsa_swr_clk_sleep {
					phandle = &lt;0x3cc&gt;;

mux {
						function = &quot;wsa_clk&quot;;
						pins = &quot;gpio49&quot;;
					};

config {
						pins = &quot;gpio49&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-bus-hold;
					};
				};
			};

smartpa_enable_suspend {
				phandle = &lt;0x3fc&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio67&quot;;
				};

config {
					pins = &quot;gpio67&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
					bias-pull-down;
					output-low;
				};
			};

cam_sensor_mipi_switch1_sel_low {
				phandle = &lt;0x5a5&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio90&quot;;
				};

config {
					pins = &quot;gpio90&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

cci0_suspend {
				phandle = &lt;0x1b2&gt;;

mux {
					function = &quot;cci_i2c&quot;;
					pins = &quot;gpio17\0gpio18&quot;;
				};

config {
					pins = &quot;gpio17\0gpio18&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
				};
			};

cam_sensor_mclk2_suspend {
				phandle = &lt;0x565&gt;;

mux {
					function = &quot;cam_mclk&quot;;
					pins = &quot;gpio15&quot;;
				};

config {
					pins = &quot;gpio15&quot;;
					drive-strength = &lt;0x04&gt;;
					bias-pull-down;
				};
			};

cd_on {
				phandle = &lt;0x3eb&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio69&quot;;
				};

config {
					pins = &quot;gpio69&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
				};
			};

qupv3_se10_i2c_pins {
				phandle = &lt;0x3c0&gt;;

qupv3_se10_i2c_sleep {
					phandle = &lt;0x18e&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio110\0gpio111&quot;;
					};

config {
						pins = &quot;gpio110\0gpio111&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};

qupv3_se10_i2c_active {
					phandle = &lt;0x18d&gt;;

mux {
						function = &quot;qup14&quot;;
						pins = &quot;gpio110\0gpio111&quot;;
					};

config {
						pins = &quot;gpio110\0gpio111&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};
			};

cci0_active {
				phandle = &lt;0x1b0&gt;;

mux {
					function = &quot;cci_i2c&quot;;
					pins = &quot;gpio17\0gpio18&quot;;
				};

config {
					pins = &quot;gpio17\0gpio18&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
				};
			};

qupv3_se1_i2c_pins {
				phandle = &lt;0x3a6&gt;;

qupv3_se1_i2c_active {
					phandle = &lt;0x169&gt;;

mux {
						function = &quot;qup01&quot;;
						pins = &quot;gpio0\0gpio1&quot;;
					};

config {
						pins = &quot;gpio0\0gpio1&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};

qupv3_se1_i2c_sleep {
					phandle = &lt;0x16a&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio0\0gpio1&quot;;
					};

config {
						pins = &quot;gpio0\0gpio1&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};
			};

cam_sensor_vddio_enable {
				phandle = &lt;0x5a1&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio5&quot;;
				};

config {
					pins = &quot;gpio5&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

msm_gpio_24_output_high {
				phandle = &lt;0x585&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio58&quot;;
				};

config {
					pins = &quot;gpio58&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
					output-high;
				};
			};

cci1_active {
				phandle = &lt;0x1b1&gt;;

mux {
					function = &quot;cci_i2c&quot;;
					pins = &quot;gpio19\0gpio20&quot;;
				};

config {
					pins = &quot;gpio19\0gpio20&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
				};
			};

sdc2_data_off {
				phandle = &lt;0x3ea&gt;;

config {
					pins = &quot;sdc2_data&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
				};
			};

cam_sensor_macro_suspend {
				phandle = &lt;0x577&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio24&quot;;
				};

config {
					pins = &quot;gpio24&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
					output-low;
				};
			};

spkr_1_sd_n {

spkr_1_sd_n_active {
					phandle = &lt;0x3d1&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio51&quot;;
					};

config {
						pins = &quot;gpio51&quot;;
						drive-strength = &lt;0x10&gt;;
						bias-disable;
						output-high;
					};
				};

spkr_1_sd_n_sleep {
					phandle = &lt;0x3d0&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio51&quot;;
					};

config {
						pins = &quot;gpio51&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-down;
						input-enable;
					};
				};
			};

sde_dp_usbplug_cc_active {
				phandle = &lt;0x1ac&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio104&quot;;
				};

config {
					pins = &quot;gpio104&quot;;
					drive-strength = &lt;0x10&gt;;
					bias-disable;
				};
			};

qupv3_se10_spi_pins {
				phandle = &lt;0x3c2&gt;;

qupv3_se10_spi_active {
					phandle = &lt;0x19d&gt;;

mux {
						function = &quot;qup14&quot;;
						pins = &quot;gpio110\0gpio111\0gpio112\0gpio113&quot;;
					};

config {
						pins = &quot;gpio110\0gpio111\0gpio112\0gpio113&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};

qupv3_se10_spi_sleep {
					phandle = &lt;0x19e&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio110\0gpio111\0gpio112\0gpio113&quot;;
					};

config {
						pins = &quot;gpio110\0gpio111\0gpio112\0gpio113&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};
			};

qupv3_se6_i2c_pins {
				phandle = &lt;0x3b8&gt;;

qupv3_se6_i2c_active {
					phandle = &lt;0x184&gt;;

mux {
						function = &quot;qup10&quot;;
						pins = &quot;gpio59\0gpio60&quot;;
					};

config {
						pins = &quot;gpio59\0gpio60&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-disable;
					};
				};

qupv3_se6_i2c_sleep {
					phandle = &lt;0x185&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio59\0gpio60&quot;;
					};

config {
						pins = &quot;gpio59\0gpio60&quot;;
						drive-strength = &lt;0x02&gt;;
						bias-pull-up;
					};
				};
			};

cam_sensor_f_vdda_f_vddd_disable {
				phandle = &lt;0x5a4&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio57&quot;;
				};

config {
					pins = &quot;gpio57&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
					output-low;
				};
			};

qupv3_se1_spi_pins {
				phandle = &lt;0x3a7&gt;;

qupv3_se1_spi_sleep {
					phandle = &lt;0x17b&gt;;

mux {
						function = &quot;gpio&quot;;
						pins = &quot;gpio0\0gpio1\0gpio2\0gpio3&quot;;
					};

config {
						pins = &quot;gpio0\0gpio1\0gpio2\0gpio3&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};

qupv3_se1_spi_active {
					phandle = &lt;0x17a&gt;;

mux {
						function = &quot;qup01&quot;;
						pins = &quot;gpio0\0gpio1\0gpio2\0gpio3&quot;;
					};

config {
						pins = &quot;gpio0\0gpio1\0gpio2\0gpio3&quot;;
						drive-strength = &lt;0x06&gt;;
						bias-disable;
					};
				};
			};

cci2_suspend {
				phandle = &lt;0x1b5&gt;;

mux {
					function = &quot;cci_i2c&quot;;
					pins = &quot;gpio27\0gpio28&quot;;
				};

config {
					pins = &quot;gpio27\0gpio28&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-down;
				};
			};

cam_sensor_macro_active {
				phandle = &lt;0x574&gt;;

mux {
					function = &quot;gpio&quot;;
					pins = &quot;gpio24&quot;;
				};

config {
					pins = &quot;gpio24&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
				};
			};

cci2_active {
				phandle = &lt;0x1b4&gt;;

mux {
					function = &quot;cci_i2c&quot;;
					pins = &quot;gpio27\0gpio28&quot;;
				};

config {
					pins = &quot;gpio27\0gpio28&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-pull-up;
				};
			};
		};

dcc_v2@10a2000 {
			dcc-ram-offset = &lt;0x6000&gt;;
			reg-names = &quot;dcc-base\0dcc-ram-base&quot;;
			compatible = &quot;qcom,dcc-v2&quot;;
			reg = &lt;0x10a2000 0x1000 0x10ae000 0x2000&gt;;
			phandle = &lt;0x2d2&gt;;
		};

qcom,cam-cpas@ac40000 {
			camnoc-bus-width = &lt;0x20&gt;;
			client-names = &quot;csiphy0\0csiphy1\0csiphy2\0csiphy3\0cci0\0cci1\0csid0\0csid1\0csid2\0iferdi0\0ifenrdi0\0iferdi1\0ifenrdi1\0iferdi2\0ifenrdi2\0ipe0\0ipe1\0cam-cdm-intf0\0cpas-cdm0\0bps0\0icp0\0jpeg-dma0\0jpeg-enc0\0fd0\0lrmecpas0&quot;;
			vdd-corners = &lt;0x01 0x11 0x31 0x41 0x81 0xc1 0x101 0x141 0x151 0x181 0x1a1&gt;;
			clock-names = &quot;gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0slow_ahb_clk_src\0cpas_ahb_clk\0camnoc_axi_clk_src\0camnoc_axi_clk&quot;;
			client-axi-port-names = &quot;cam_hf_0\0cam_hf_0\0cam_hf_0\0cam_hf_0\0cam_sf_0\0cam_sf_0\0cam_hf_0\0cam_hf_0\0cam_hf_0\0cam_hf_1\0cam_hf_0\0cam_hf_1\0cam_hf_0\0cam_hf_1\0cam_hf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_1\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0&quot;;
			reg-names = &quot;cam_cpas_top\0cam_camnoc&quot;;
			qcom,msm-bus,name = &quot;cam_ahb&quot;;
			reg-cam-base = &lt;0x40000 0x42000&gt;;
			cell-index = &lt;0x00&gt;;
			vdd-corner-ahb-mapping = &quot;suspend\0suspend\0minsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo&quot;;
			control-camnoc-axi-clk;
			camss-vdd-supply = &lt;0x1ae&gt;;
			interrupts = &lt;0x00 0x1cb 0x00&gt;;
			clocks = &lt;0x27 0x0e 0x27 0x0f 0x27 0x10 0x29 0x5a 0x29 0x1a 0x29 0x13 0x29 0x12&gt;;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x06&gt;;
			label = &quot;cpas&quot;;
			client-id-based;
			clock-cntl-level = &quot;suspend\0lowsvs\0svs\0svs_l1\0nominal\0turbo&quot;;
			client-bus-camnoc-based;
			compatible = &quot;qcom,cam-cpas&quot;;
			src-clock-name = &quot;camnoc_axi_clk_src&quot;;
			status = &quot;ok&quot;;
			camnoc-axi-clk-bw-margin-perc = &lt;0x14&gt;;
			interrupt-names = &quot;cpas_camnoc&quot;;
			reg = &lt;0xac40000 0x1000 0xac42000 0x6000&gt;;
			regulator-names = &quot;camss-vdd&quot;;
			qcom,msm-bus,vectors-KBps = &lt;0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x1d4c0 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x493e0 0x01 0x24d 0x00 0x493e0&gt;;
			qcom,cam-cx-ipeak = &lt;0x1a3 0x03&gt;;
			clock-rates = &lt;0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x8f0d180 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0xe4e1c00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x1312d000 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x1c9c3800 0x00&gt;;
			arch-compat = &quot;cpas_top&quot;;
			camnoc-axi-min-ib-bw = &lt;0xb2d05e00&gt;;

qcom,axi-port-list {

qcom,axi-port4 {
					qcom,axi-port-name = &quot;cam_sf_1&quot;;

qcom,axi-port-mnoc {
						qcom,msm-bus,name = &quot;cam_sf_1_mnoc&quot;;
						qcom,msm-bus,num-paths = &lt;0x01&gt;;
						qcom,msm-bus,num-cases = &lt;0x02&gt;;
						qcom,msm-bus,vectors-KBps = &lt;0xab 0x200 0x00 0x00 0xab 0x200 0x00 0x00&gt;;
						qcom,msm-bus-vector-dyn-vote;
					};

qcom,axi-port-camnoc {
						qcom,msm-bus,name = &quot;cam_sf_1_camnoc&quot;;
						qcom,msm-bus,num-paths = &lt;0x01&gt;;
						qcom,msm-bus,num-cases = &lt;0x02&gt;;
						qcom,msm-bus,vectors-KBps = &lt;0xb3 0x30a 0x00 0x00 0xb3 0x30a 0x00 0x00&gt;;
						qcom,msm-bus-vector-dyn-vote;
					};
				};

qcom,axi-port2 {
					ib-bw-voting-needed;
					qcom,axi-port-name = &quot;cam_hf_1&quot;;

qcom,axi-port-mnoc {
						qcom,msm-bus,name = &quot;cam_hf_1_mnoc&quot;;
						qcom,msm-bus,num-paths = &lt;0x01&gt;;
						qcom,msm-bus,num-cases = &lt;0x02&gt;;
						qcom,msm-bus,vectors-KBps = &lt;0xac 0x200 0x00 0x00 0xac 0x200 0x00 0x00&gt;;
						qcom,msm-bus-vector-dyn-vote;
					};

qcom,axi-port-camnoc {
						qcom,msm-bus,name = &quot;cam_hf_1_camnoc&quot;;
						qcom,msm-bus,num-paths = &lt;0x01&gt;;
						qcom,msm-bus,num-cases = &lt;0x02&gt;;
						qcom,msm-bus,vectors-KBps = &lt;0xb2 0x30a 0x00 0x00 0xb2 0x30a 0x00 0x00&gt;;
						qcom,msm-bus-vector-dyn-vote;
					};
				};

qcom,axi-port3 {
					qcom,axi-port-name = &quot;cam_sf_0&quot;;

qcom,axi-port-mnoc {
						qcom,msm-bus,name = &quot;cam_sf_0_mnoc&quot;;
						qcom,msm-bus,num-paths = &lt;0x01&gt;;
						qcom,msm-bus,num-cases = &lt;0x02&gt;;
						qcom,msm-bus,vectors-KBps = &lt;0x89 0x200 0x00 0x00 0x89 0x200 0x00 0x00&gt;;
						qcom,msm-bus-vector-dyn-vote;
					};

qcom,axi-port-camnoc {
						qcom,msm-bus,name = &quot;cam_sf_0_camnoc&quot;;
						qcom,msm-bus,num-paths = &lt;0x01&gt;;
						qcom,msm-bus,num-cases = &lt;0x02&gt;;
						qcom,msm-bus,vectors-KBps = &lt;0x94 0x30a 0x00 0x00 0x94 0x30a 0x00 0x00&gt;;
						qcom,msm-bus-vector-dyn-vote;
					};
				};

qcom,axi-port1 {
					ib-bw-voting-needed;
					qcom,axi-port-name = &quot;cam_hf_0&quot;;

qcom,axi-port-mnoc {
						qcom,msm-bus,name = &quot;cam_hf_0_mnoc&quot;;
						qcom,msm-bus,num-paths = &lt;0x01&gt;;
						qcom,msm-bus,num-cases = &lt;0x02&gt;;
						qcom,msm-bus,vectors-KBps = &lt;0x88 0x200 0x00 0x00 0x88 0x200 0x00 0x00&gt;;
						qcom,msm-bus-vector-dyn-vote;
					};

qcom,axi-port-camnoc {
						qcom,msm-bus,name = &quot;cam_hf_0_camnoc&quot;;
						qcom,msm-bus,num-paths = &lt;0x01&gt;;
						qcom,msm-bus,num-cases = &lt;0x02&gt;;
						qcom,msm-bus,vectors-KBps = &lt;0x92 0x30a 0x00 0x00 0x92 0x30a 0x00 0x00&gt;;
						qcom,msm-bus-vector-dyn-vote;
					};
				};
			};
		};

etm@7440000 {
			arm,primecell-periphid = &lt;0xbb95d&gt;;
			clock-names = &quot;apb_pclk&quot;;
			clocks = &lt;0x19 0x00&gt;;
			cpu = &lt;0x15&gt;;
			qcom,tupwr-disable;
			coresight-name = &quot;coresight-etm4&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7440000 0x1000&gt;;
			phandle = &lt;0x440&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x221&gt;;
					phandle = &lt;0x219&gt;;
				};
			};
		};

rpmh-regulator-ldoa4 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa4&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l4 {
				regulator-max-microvolt = &lt;0xe09c0&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0xc92c0&gt;;
				regulator-min-microvolt = &lt;0xc92c0&gt;;
				regulator-name = &quot;pm6150_l4&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x1a9&gt;;
			};
		};

funnel@69C3000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-dl-mm&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x69c3000 0x1000&gt;;
			phandle = &lt;0x44b&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x23e&gt;;
						phandle = &lt;0x22f&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x23f&gt;;
						phandle = &lt;0x240&gt;;
					};
				};
			};
		};

qcom,mdss_mdp@ae00000 {
			iommus = &lt;0x30 0x800 0x440&gt;;
			qcom,sde-safe-lut-macrotile-qseed = &lt;0x00 0xf000&gt;;
			qcom,sde-dither-off = &lt;0x30e0 0x30e0 0x30e0 0x30e0&gt;;
			qcom,sde-qseed-type = &quot;qseedv3lite&quot;;
			qcom,sde-max-per-pipe-bw-kbps = &lt;0x3567e0 0x3567e0 0x3567e0 0x3567e0 0x3567e0&gt;;
			qcom,sde-smart-dma-rev = &quot;smart_dma_v2p5&quot;;
			qcom,sde-mixer-cwb-pref = &quot;none\0none\0cwb\0cwb\0none\0none&quot;;
			qcom,sde-vbif-off = &lt;0x00&gt;;
			qcom,sde-panic-per-pipe;
			qcom,sde-danger-lut = &lt;0x0f 0xffff 0x00 0x00 0xffff&gt;;
			qcom,sde-te2-off = &lt;0x2000 0x2000 0x00 0x00&gt;;
			qcom,sde-sspp-smart-dma-priority = &lt;0x04 0x05 0x01 0x02 0x03&gt;;
			qcom,sde-sspp-qseed-off = &lt;0xa00&gt;;
			qcom,sde-ctl-display-pref = &quot;primary\0none\0none\0none\0none&quot;;
			qcom,sde-dspp-size = &lt;0x1800&gt;;
			qcom,sde-sspp-src-size = &lt;0x1f0&gt;;
			clock-max-rate = &lt;0x00 0x00 0x00 0x00 0x19a14780 0x124f800 0x19a14780 0x19a14780&gt;;
			#address-cells = &lt;0x01&gt;;
			qcom,sde-sspp-excl-rect = &lt;0x01 0x01 0x01 0x01 0x01&gt;;
			qcom,sde-wb-id = &lt;0x02&gt;;
			qcom,sde-safe-lut-macrotile = &lt;0x00 0xf000&gt;;
			qcom,sde-wb-size = &lt;0x2c8&gt;;
			qcom,sde-qos-lut-nrt = &lt;0x00 0x00 0x00&gt;;
			qcom,sde-axi-bus-width = &lt;0x20&gt;;
			connectors = &lt;0x36d 0x55e 0x55f 0x560&gt;;
			qcom,sde-safe-lut-cwb = &lt;0x00 0xffff&gt;;
			qcom,sde-pp-size = &lt;0xd4&gt;;
			qcom,sde-dest-scaler-top-off = &lt;0x61000&gt;;
			clock-names = &quot;gcc_iface\0gcc_bus\0gcc_nrt_bus\0iface_clk\0core_clk\0vsync_clk\0lut_clk\0rot_clk&quot;;
			reg-names = &quot;mdp_phys\0vbif_phys\0regdma_phys&quot;;
			qcom,sde-qos-lut-macrotile-qseed = &lt;0x00 0x112233 0x66777777&gt;;
			qcom,sde-sspp-off = &lt;0x5000 0x7000 0x25000 0x27000 0x29000&gt;;
			qcom,sde-max-dest-scaler-output-linewidth = &lt;0xa00&gt;;
			qcom,sde-qos-cpu-mask = &lt;0x03&gt;;
			qcom,sde-ctl-off = &lt;0x2000 0x2200 0x2400 0x2600 0x2800 0x2a00&gt;;
			qcom,sde-dest-scaler-size = &lt;0xa0&gt;;
			qcom,sde-vbif-qos-nrt-remap = &lt;0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03&gt;;
			qcom,sde-num-mnoc-ports = &lt;0x02&gt;;
			qcom,sde-cdp-setting = &lt;0x01 0x01 0x01 0x00&gt;;
			qcom,sde-dspp-ad-version = &lt;0x40000&gt;;
			qcom,sde-reg-dma-trigger-off = &lt;0x119c&gt;;
			qcom,sde-dram-channels = &lt;0x02&gt;;
			qcom,sde-ctl-size = &lt;0x1e0&gt;;
			qcom,sde-csc-type = &quot;csc-10bit&quot;;
			interrupts = &lt;0x00 0x53 0x00&gt;;
			clocks = &lt;0x27 0x1c 0x27 0x1f 0x27 0x20 0x2a 0x01 0x2a 0x1a 0x2a 0x26 0x2a 0x1c 0x2a 0x22&gt;;
			qcom,sde-merge-3d-size = &lt;0x100&gt;;
			qcom,sde-dsc-off = &lt;0x81000 0x81400&gt;;
			qcom,sde-mixer-pair-mask = &lt;0x02 0x01 0x04 0x03 0x00 0x00&gt;;
			qcom,sde-dither-version = &lt;0x10000&gt;;
			qcom,sde-min-core-ib-kbps = &lt;0x249f00&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,sde-pp-merge-3d-id = &lt;0x00 0x00 0x01 0x01&gt;;
			qcom,sde-off = &lt;0x1000&gt;;
			qcom,sde-vbif-memtype-0 = &lt;0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03&gt;;
			qcom,sde-sspp-clk-ctrl = &lt;0x2ac 0x00 0x2b4 0x00 0x2ac 0x08 0x2b4 0x08 0x2bc 0x08&gt;;
			qcom,sde-dspp-top-off = &lt;0x1300&gt;;
			qcom,dss-cx-ipeak = &lt;0x1a3 0x04&gt;;
			#power-domain-cells = &lt;0x00&gt;;
			qcom,sde-dspp-top-size = &lt;0x80&gt;;
			qcom,sde-qos-cpu-dma-latency = &lt;0x12c&gt;;
			qcom,sde-mixer-blendstages = &lt;0x0b&gt;;
			qcom,sde-safe-lut-linear = &lt;0x00 0xfff8&gt;;
			qcom,sde-qos-lut-linear = &lt;0x00 0x112222 0x22223357&gt;;
			qcom,sde-dsc-size = &lt;0x140&gt;;
			qcom,sde-dither-size = &lt;0x20&gt;;
			qcom,sde-intf-type = &quot;dp\0dsi\0dsi\0dp&quot;;
			qcom,sde-safe-lut-nrt = &lt;0x00 0xffff&gt;;
			qcom,sde-mixer-linewidth = &lt;0xa00&gt;;
			qcom,sde-dest-scaler-top-size = &lt;0x1c&gt;;
			qcom,sde-wb-xin-id = &lt;0x06&gt;;
			qcom,sde-dspp-ad-off = &lt;0x28000 0x27000&gt;;
			qcom,sde-qos-lut-macrotile = &lt;0x00 0x112233 0x44556677&gt;;
			qcom,sde-min-llcc-ib-kbps = &lt;0xc3500&gt;;
			qcom,sde-max-dest-scaler-input-linewidth = &lt;0x800&gt;;
			qcom,sde-has-src-split;
			qcom,sde-sspp-csc-off = &lt;0x1a00&gt;;
			qcom,sde-has-dest-scaler;
			compatible = &quot;qcom,sde-kms&quot;;
			qcom,sde-pp-off = &lt;0x71000 0x71800 0x72000 0x72800&gt;;
			qcom,sde-dest-scaler-off = &lt;0x800 0x1000&gt;;
			qcom,sde-ubwc-version = &lt;0x200&gt;;
			#interrupt-cells = &lt;0x01&gt;;
			clock-rate = &lt;0x00 0x00 0x00 0x00 0x14810600 0x124f800 0xbebc200 0xbebc200&gt;;
			qcom,sde-intf-size = &lt;0x2b8&gt;;
			qcom,sde-intf-off = &lt;0x6b000 0x6b800 0x6c000 0x6c800&gt;;
			qcom,sde-mixer-size = &lt;0x320&gt;;
			qcom,sde-mixer-display-pref = &quot;primary\0primary\0none\0none\0none\0none&quot;;
			qcom,sde-has-idle-pc;
			qcom,sde-wb-clk-ctrl = &lt;0x3b8 0x18&gt;;
			qcom,sde-merge-3d-off = &lt;0x84000 0x84100&gt;;
			qcom,sde-min-dram-ib-kbps = &lt;0xc3500&gt;;
			reg = &lt;0xae00000 0x84208 0xaeb0000 0x2008 0xaeac000 0x214&gt;;
			qcom,sde-mixer-off = &lt;0x45000 0x46000 0x47000 0x48000 0x00 0x00&gt;;
			qcom,sde-max-bw-low-kbps = &lt;0x6c5660&gt;;
			qcom,sde-pipe-order-version = &lt;0x01&gt;;
			qcom,sde-highest-bank-bit = &lt;0x01&gt;;
			qcom,sde-vbif-id = &lt;0x00&gt;;
			phandle = &lt;0x1a6&gt;;
			qcom,sde-cdm-size = &lt;0x224&gt;;
			qcom,sde-vbif-qos-rt-remap = &lt;0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06&gt;;
			qcom,sde-qos-lut-cwb = &lt;0x00 0x75300000 0x00&gt;;
			qcom,sde-mixer-blend-op-off = &lt;0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110&gt;;
			qcom,sde-num-nrt-paths = &lt;0x00&gt;;
			qcom,sde-reg-dma-off = &lt;0x00&gt;;
			qcom,sde-cdm-off = &lt;0x7a200&gt;;
			qcom,sde-reg-dma-version = &lt;0x10001&gt;;
			qcom,sde-vbif-memtype-1 = &lt;0x03 0x03 0x03 0x03 0x03 0x03&gt;;
			qcom,sde-wb-off = &lt;0x66000&gt;;
			qcom,sde-has-cdp;
			qcom,sde-sspp-xin-id = &lt;0x00 0x04 0x01 0x05 0x09&gt;;
			qcom,sde-vbif-size = &lt;0x1040&gt;;
			qcom,sde-sspp-linewidth = &lt;0xb40&gt;;
			qcom,sde-pp-slave = &lt;0x00 0x00 0x00 0x00&gt;;
			qcom,sde-wb-linewidth = &lt;0x1000&gt;;
			qcom,sde-secure-sid-mask = &lt;0x4400801&gt;;
			interrupt-controller;
			qcom,sde-dspp-off = &lt;0x55000 0x57000&gt;;
			qcom,sde-sspp-type = &quot;vig\0vig\0dma\0dma\0dma&quot;;
			#cooling-cells = &lt;0x02&gt;;
			qcom,sde-len = &lt;0x45c&gt;;
			qcom,sde-has-dim-layer;
			qcom,sde-max-bw-high-kbps = &lt;0x6c5660&gt;;

qcom,mdss_dsi_sw43404_amoled_wqhd_cmd {
				qcom,ulps-enabled;
				qcom,mdss-dsi-bl-min-level = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-status-check-mode = &quot;reg_read&quot;;
				qcom,mdss-dsi-panel-status-read-length = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-name = &quot;sw43404 amoled cmd mode dsi boe panel with DSC&quot;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,esd-check-enabled;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
				qcom,mdss-dsi-panel-status-value = &lt;0x9c&gt;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x0a&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-bl-max-level = &lt;0x3ff&gt;;
				qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
				qcom,mdss-dsi-qsync-min-refresh-rate = &lt;0x37&gt;;
				qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
				qcom,mdss-dsi-panel-peak-brightness = &lt;0x401640&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-physical-type = &quot;oled&quot;;
				qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x21&gt;;
				qcom,mdss-dsi-panel-hdr-enabled;
				qcom,mdss-dsi-panel-status-command-state = &quot;dsi_hs_mode&quot;;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-on-check-value = &lt;0x9c&gt;;
				phandle = &lt;0x523&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,panel-supply-entries = &lt;0x521&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-lane-map = &quot;lane_map_0123&quot;;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-panel-status-command = &lt;0x6010001 0x10a&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,platform-te-gpio = &lt;0x174 0x0a 0x00&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 5a 00];
						qcom,partial-update-enabled = &quot;single_roi&quot;;
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x02 0x02 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x0c&gt;;
						qcom,mdss-dsi-nolp-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-jitter = &lt;0x07 0x01&gt;;
						qcom,mdss-dsi-nolp-command = [05 01 00 00 00 00 02 38 00];
						qcom,mdss-dsi-lp1-command = [05 01 00 00 00 00 02 39 00];
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 5a 01];
						qcom,mdss-dsi-panel-height = &lt;0xb40&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = &lt;0x39010000 0x3b0 0xa5003901 0x00 0x35c4200 0x7010000 0x201 0xa0100 0x80 0x11000089 0x30800b40 0x5a005a0 0x2d002d0 0x2000268 0x209adb 0xa000c 0x12000e 0x180010f0 0x30c2000 0x60b0b33 0xe1c2a38 0x46546269 0x7077797b 0x7d7e0102 0x1000940 0x9be19fc 0x19fa19f8 0x1a381a78 0x1ab62af6 0x2b342b74 0x3b746bf4 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x39010000 0x3b0 0xa5003901 0x00 0x9f80008 0x10082d00 0x2d1501 0x00 0x2550805 0x100001e 0x21100 0x39010000 0x3b0 0xa5001501 0x00 0x2e01839 0x1000000 0xcc000 0x536f5150 0x51344f5a 0x33190501 0x7800 0x2350005 0x100003c 0x22900&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x3c&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x1e&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-lp1-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-height = &lt;0xb4&gt;;
						qcom,mdss-dsi-qsync-off-commands-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x5a0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x01&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x130504 0x1f1e0505 0x3020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x08&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,panel-roi-alignment = &lt;0x2d0 0xb4 0xb4 0xb4 0x5a0 0xb4&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsi-qsync-on-commands-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
						qcom,mdss-mdp-transfer-time-us = &lt;0x32c8&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_rm69298_truly_amoled_video {
				qcom,mdss-dsi-panel-name = &quot;rm69298 amoled fhd+ video mode dsi truly panel&quot;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x0d&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-pan-fps-update = &quot;dfps_immediate_porch_mode_vfp&quot;;
				qcom,mdss-dsi-pan-enable-dynamic-fps;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,dsi-supported-dfps-list = &lt;0x3c 0x39 0x35&gt;;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x30&gt;;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				phandle = &lt;0x52d&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-lp11-init;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-map = &quot;lane_map_0123&quot;;
				qcom,mdss-dsi-tx-eot-append;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,display-topology = &lt;0x01 0x00 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x0a&gt;;
						qcom,mdss-dsi-panel-height = &lt;0x870&gt;;
						qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 fe 40 15 01 00 00 00 00 02 0a 15 15 01 00 00 00 00 02 0b cc 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 80 15 01 00 00 00 00 02 0f 87 15 01 00 00 00 00 02 05 08 15 01 00 00 00 00 02 06 08 15 01 00 00 00 00 02 08 08 15 01 00 00 00 00 02 09 08 15 01 00 00 00 00 02 16 15 15 01 00 00 00 00 02 20 8d 15 01 00 00 00 00 02 21 8d 15 01 00 00 00 00 02 24 55 15 01 00 00 00 00 02 26 55 15 01 00 00 00 00 02 28 55 15 01 00 00 00 00 02 2a 55 15 01 00 00 00 00 02 2d 28 15 01 00 00 00 00 02 2f 28 15 01 00 00 00 00 02 30 1e 15 01 00 00 00 00 02 31 1e 15 01 00 00 00 00 02 37 80 15 01 00 00 00 00 02 38 40 15 01 00 00 00 00 02 39 90 15 01 00 00 00 00 02 46 43 15 01 00 00 00 00 02 47 43 15 01 00 00 00 00 02 64 02 15 01 00 00 00 00 02 6f 02 15 01 00 00 00 00 02 74 2f 15 01 00 00 00 00 02 80 16 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 fe a0 15 01 00 00 00 00 02 2b 22 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 2f 35 15 01 00 00 00 00 02 fe 60 15 01 00 00 00 00 02 00 ac 15 01 00 00 00 00 02 01 0f 15 01 00 00 00 00 02 02 ff 15 01 00 00 00 00 02 03 05 15 01 00 00 00 00 02 04 00 15 01 00 00 00 00 02 05 06 15 01 00 00 00 00 02 06 00 15 01 00 00 00 00 02 07 00 15 01 00 00 00 00 02 09 c0 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 02 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0e 00 15 01 00 00 00 00 02 0e 04 15 01 00 00 00 00 02 0f 0e 15 01 00 00 00 00 02 10 a2 15 01 00 00 00 00 02 12 c0 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 14 02 15 01 00 00 00 00 02 15 00 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 17 05 15 01 00 00 00 00 02 18 0e 15 01 00 00 00 00 02 19 a2 15 01 00 00 00 00 02 1b c0 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 04 15 01 00 00 00 00 02 1e 01 15 01 00 00 00 00 02 1f 00 15 01 00 00 00 00 02 20 04 15 01 00 00 00 00 02 21 24 15 01 00 00 00 00 02 22 99 15 01 00 00 00 00 02 24 c0 15 01 00 00 00 00 02 25 00 15 01 00 00 00 00 02 26 04 15 01 00 00 00 00 02 27 01 15 01 00 00 00 00 02 28 00 15 01 00 00 00 00 02 29 06 15 01 00 00 00 00 02 2a 24 15 01 00 00 00 00 02 2b 99 15 01 00 00 00 00 02 83 ca 15 01 00 00 00 00 02 84 0f 15 01 00 00 00 00 02 85 ff 15 01 00 00 00 00 02 86 0a 15 01 00 00 00 00 02 87 00 15 01 00 00 00 00 02 88 08 15 01 00 00 00 00 02 89 00 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 8b 80 15 01 00 00 00 00 02 c7 1f 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 c9 01 15 01 00 00 00 00 02 ca 1f 15 01 00 00 00 00 02 cb 02 15 01 00 00 00 00 02 cc 1f 15 01 00 00 00 00 02 cd 1f 15 01 00 00 00 00 02 ce 1f 15 01 00 00 00 00 02 cf 1f 15 01 00 00 00 00 02 d0 1f 15 01 00 00 00 00 02 d1 1f 15 01 00 00 00 00 02 d2 1f 15 01 00 00 00 00 02 d3 1f 15 01 00 00 00 00 02 d4 1f 15 01 00 00 00 00 02 d5 1f 15 01 00 00 00 00 02 d6 1f 15 01 00 00 00 00 02 d7 1f 15 01 00 00 00 00 02 d8 1f 15 01 00 00 00 00 02 d9 1f 15 01 00 00 00 00 02 da 1f 15 01 00 00 00 00 02 db 1f 15 01 00 00 00 00 02 dc 00 15 01 00 00 00 00 02 dd 0e 15 01 00 00 00 00 02 de 1f 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 04 15 01 00 00 00 00 02 e1 1f 15 01 00 00 00 00 02 e2 01 15 01 00 00 00 00 02 e3 02 15 01 00 00 00 00 02 e4 1f 15 01 00 00 00 00 02 e5 1f 15 01 00 00 00 00 02 e6 1f 15 01 00 00 00 00 02 e7 1f 15 01 00 00 00 00 02 e8 1f 15 01 00 00 00 00 02 e9 1f 15 01 00 00 00 00 02 ea 1f 15 01 00 00 00 00 02 eb 1f 15 01 00 00 00 00 02 ec 1f 15 01 00 00 00 00 02 ed 1f 15 01 00 00 00 00 02 ee 1f 15 01 00 00 00 00 02 ef 03 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 c6 15 15 01 00 00 00 00 02 c9 9e 15 01 00 00 00 00 02 cb 3f 15 01 00 00 00 00 02 d1 0f 15 01 00 00 00 00 02 d3 15 15 01 00 00 00 00 02 d4 15 15 01 00 00 00 00 02 d5 00 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 a9 40 15 01 00 00 00 00 02 cb 05 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 5a ff 15 01 00 00 00 00 02 5c ff 15 01 00 00 00 00 02 5d 0a 15 01 00 00 00 00 02 7d 31 15 01 00 00 00 00 02 7e 4a 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 49 05 15 01 00 00 00 00 02 4a 2e 15 01 00 00 00 00 02 4b 58 15 01 00 00 00 00 02 4c 77 15 01 00 00 00 00 02 4d a1 15 01 00 00 00 00 02 4e de 15 01 00 00 00 00 02 4f 2c 15 01 00 00 00 00 02 50 97 15 01 00 00 00 00 02 51 2a 15 01 00 00 00 00 02 ad ec 15 01 00 00 00 00 02 ae 80 15 01 00 00 00 00 02 af 00 15 01 00 00 00 00 02 b0 50 15 01 00 00 00 00 02 b1 3a 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 56 91 15 01 00 00 00 00 02 58 04 15 01 00 00 00 00 02 59 24 15 01 00 00 00 00 02 5a 05 15 01 00 00 00 00 02 5b c6 15 01 00 00 00 00 02 5c 05 15 01 00 00 00 00 02 5d 66 15 01 00 00 00 00 02 5e 06 15 01 00 00 00 00 02 5f 17 15 01 00 00 00 00 02 60 07 15 01 00 00 00 00 02 61 cf 15 01 00 00 00 00 02 62 07 15 01 00 00 00 00 02 63 98 15 01 00 00 00 00 02 64 08 15 01 00 00 00 00 02 65 65 15 01 00 00 00 00 02 66 09 15 01 00 00 00 00 02 67 37 15 01 00 00 00 00 02 68 0a 15 01 00 00 00 00 02 6b 02 15 01 00 00 00 00 02 6c 0c 15 01 00 00 00 00 02 71 02 15 01 00 00 00 00 02 72 0f 15 01 00 00 00 00 02 73 93 15 01 00 00 00 00 02 74 0f 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 98 cf 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 b4 31 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 aa 03 15 01 00 00 00 00 02 09 13 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 01 41 15 01 00 00 00 00 02 02 00 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 04 ff 15 01 00 00 00 00 02 05 00 15 01 00 00 00 00 02 06 c0 15 01 00 00 00 00 02 07 40 15 01 00 00 00 00 02 08 20 15 01 00 00 00 00 02 19 e0 15 01 00 00 00 00 02 1a 40 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 80 15 01 00 00 00 00 02 60 40 15 01 00 00 00 00 02 61 40 15 01 00 00 00 00 02 62 40 15 01 00 00 00 00 02 63 40 15 01 00 00 00 00 02 64 40 15 01 00 00 00 00 02 65 40 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 02 15 01 00 00 00 00 02 75 10 15 01 00 00 00 00 02 76 14 15 01 00 00 00 00 02 77 1c 15 01 00 00 00 00 02 78 20 15 01 00 00 00 00 02 79 0a 15 01 00 00 00 00 02 7a 00 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c 00 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e 00 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 81 00 15 01 00 00 00 00 02 82 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 84 00 15 01 00 00 00 00 02 85 00 15 01 00 00 00 00 02 86 20 15 01 00 00 00 00 02 87 0a 15 01 00 00 00 00 02 88 02 15 01 00 00 00 00 02 89 2b 15 01 00 00 00 00 02 8a 14 15 01 00 00 00 00 02 8b 01 15 01 00 00 00 00 02 8c 00 15 01 00 00 00 00 02 8d 00 15 01 00 00 00 00 02 8e 00 15 01 00 00 00 00 02 8f 00 15 01 00 00 00 00 02 90 00 15 01 00 00 00 00 02 91 00 15 01 00 00 00 00 02 92 00 15 01 00 00 00 00 02 93 00 15 01 00 00 00 00 02 94 00 15 01 00 00 00 00 02 95 00 15 01 00 00 00 00 02 96 00 15 01 00 00 00 00 02 b2 40 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 b8 d0 15 01 00 00 00 00 02 b9 06 15 01 00 00 00 00 02 ba 00 15 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 05 51 00 00 ff ff 15 01 00 00 00 00 02 c2 09 05 01 00 00 96 00 01 11 05 01 00 00 32 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x1e&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x28&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x04&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x1f0808 0x24220808 0x5020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x10&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00];
						qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_sharp_wqhd_video {
				qcom,adjust-timer-wakeup-ms = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-status-check-mode = &quot;reg_read&quot;;
				qcom,mdss-pan-physical-width-dimension = &lt;0x44&gt;;
				qcom,mdss-dsi-panel-status-read-length = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-name = &quot;Dual Sharp wqhd video mode dsi panel&quot;;
				qcom,mdss-pan-physical-height-dimension = &lt;0x79&gt;;
				qcom,esd-check-enabled;
				qcom,mdss-dsi-panel-status-value = &lt;0x9c&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x0c&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-pan-fps-update = &quot;dfps_immediate_porch_mode_hfp&quot;;
				qcom,mdss-dsi-pan-enable-dynamic-fps;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,dsi-dyn-clk-enable;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x14 0x00 0x14 0x01 0x14&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
				qcom,dsi-dyn-clk-list = &lt;0x1fdf1000 0x1fbd1100 0x1f9b1200 0x1f571400 0x1f791300&gt;;
				qcom,mdss-dsi-lane-0-state;
				qcom,dsi-supported-dfps-list = &lt;0x3c 0x39 0x37&gt;;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x21&gt;;
				qcom,mdss-dsi-panel-status-command-state = &quot;dsi_hs_mode&quot;;
				qcom,mdss-dsi-panel-on-check-value = &lt;0x9c&gt;;
				phandle = &lt;0x52b&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
				qcom,mdss-dsi-tx-eot-append;
				qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-panel-status-command = &lt;0x6010001 0x10a&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,display-topology = &lt;0x02 0x00 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x04&gt;;
						qcom,mdss-dsi-panel-height = &lt;0xa00&gt;;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 10 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 15 01 00 00 00 00 02 90 01 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 58 01 15 01 00 00 00 00 02 c9 00 15 01 00 00 00 00 02 c0 15 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x1e&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x64&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x01&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x2e080a 0x1218080b 0x9030400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x08&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,smmu_sde_sec_cb {
				iommus = &lt;0x30 0x801 0x440&gt;;
				compatible = &quot;qcom,smmu_sde_sec&quot;;
				phandle = &lt;0x36c&gt;;
			};

qcom,mdss_dsi_nt35695b_truly_fhd_cmd {
				qcom,ulps-enabled;
				qcom,mdss-dsi-panel-status-check-mode = &quot;reg_read&quot;;
				qcom,mdss-dsi-panel-status-read-length = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-name = &quot;nt35695b truly fhd command mode dsi panel&quot;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,esd-check-enabled;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-status-value = &lt;0x9c&gt;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x07&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-post-init-delay = &lt;0x01&gt;;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x1c&gt;;
				qcom,mdss-dsi-panel-status-command-state = &quot;dsi_hs_mode&quot;;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-on-check-value = &lt;0x9c&gt;;
				phandle = &lt;0x530&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-tx-eot-append;
				qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-panel-status-command = &lt;0x6010001 0x10a&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x01 0x00 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x0c&gt;;
						qcom,mdss-dsi-panel-height = &lt;0x780&gt;;
						qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00];
						qcom,mdss-dsi-h-front-porch = &lt;0x78&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x130504 0x1f1e0505 0x3020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x02&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsi-v-front-porch = &lt;0x0c&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_sim_dsc_375_cmd {
				qcom,ulps-enabled;
				qcom,adjust-timer-wakeup-ms = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-name = &quot;Simulator cmd mode DSC 3.75:1 dsi panel&quot;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,panel-ack-disabled;
				qcom,mdss-dsi-t-clk-post = &lt;0x0d&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-bl-max-level = &lt;0xfff&gt;;
				qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-te-using-wd;
				qcom,mdss-dsi-t-clk-pre = &lt;0x2d&gt;;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				phandle = &lt;0x529&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,panel-supply-entries = &lt;0x520&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@1 {
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x00&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0x780&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = &lt;0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x00&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-height = &lt;0x10&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x00&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x150505 0x201f0505 0x3020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x00&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x02&gt;;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = &lt;0x5010000 0x10000128 0x5010000 0x40000110&gt;;
						qcom,mdss-dsc-bit-per-component = &lt;0x0a&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};

timing@0 {
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x01 0x01 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x10&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0xa00&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = &lt;0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2723115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00315 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x64&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x20&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-height = &lt;0x10&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x5a0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_hs_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x1a0606 0x22200707 0x4020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x08&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x02&gt;;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsc-bit-per-component = &lt;0x0a&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x0a&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_sim_cmd {
				qcom,ulps-enabled;
				qcom,mdss-dsi-panel-name = &quot;Simulator cmd mode dsi panel&quot;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,panel-ack-disabled;
				qcom,mdss-dsi-t-clk-post = &lt;0x0c&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-bl-max-level = &lt;0xfff&gt;;
				qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
				qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
				qcom,mdss-dsi-panel-peak-brightness = &lt;0x401640&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-te-using-wd;
				qcom,mdss-dsi-t-clk-pre = &lt;0x29&gt;;
				qcom,mdss-dsi-panel-hdr-enabled;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				phandle = &lt;0x527&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,panel-supply-entries = &lt;0x520&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@1 {
						qcom,partial-update-enabled = &quot;single_roi&quot;;
						qcom,mdss-dsi-panel-timings = &lt;0x210909 0x24230808 0x8030400&gt;;
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x01 0x01 0x01 0x02 0x02 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x28&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0x780&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = &lt;0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x78&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x1cc&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-height = &lt;0x28&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x28&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x1a0606 0x22200707 0x4020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x64&gt;;
						qcom,default-topology-index = &lt;0x01&gt;;
						qcom,panel-roi-alignment = &lt;0x21c 0x28 0x21c 0x28 0x21c 0x28&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x2e4&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};

timing@2 {
						qcom,partial-update-enabled = &quot;single_roi&quot;;
						qcom,mdss-dsi-panel-timings = &lt;0x210909 0x24230808 0x8030400&gt;;
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x01 0x01 0x01 0x02 0x02 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x28&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0x500&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = &lt;0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x64&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x168&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x348&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-height = &lt;0x28&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x28&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x1a0606 0x22200707 0x4020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x64&gt;;
						qcom,default-topology-index = &lt;0x01&gt;;
						qcom,panel-roi-alignment = &lt;0x168 0x28 0x168 0x28 0x168 0x28&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x564&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};

timing@0 {
						qcom,partial-update-enabled = &quot;single_roi&quot;;
						qcom,mdss-dsi-panel-timings = &lt;0x210909 0x24230808 0x8030400&gt;;
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x01 0x01 0x01 0x02 0x02 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x28&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0xa00&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = &lt;0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x78&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x64&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-height = &lt;0x28&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x5a0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x28&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x1a0606 0x22200707 0x4020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x64&gt;;
						qcom,default-topology-index = &lt;0x01&gt;;
						qcom,panel-roi-alignment = &lt;0x2d0 0x28 0x2d0 0x28 0x2d0 0x28&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x64&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_sw43404_amoled_wqhd_video {
				qcom,adjust-timer-wakeup-ms = &lt;0x01&gt;;
				qcom,mdss-dsi-bl-min-level = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-name = &quot;sw43404 amoled video mode dsi boe panel with DSC&quot;;
				qcom,mdss-dsi-t-clk-post = &lt;0x0a&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-bl-max-level = &lt;0x3ff&gt;;
				qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
				qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
				qcom,mdss-dsi-panel-peak-brightness = &lt;0x401640&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-pan-fps-update = &quot;dfps_immediate_porch_mode_hfp&quot;;
				qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
				qcom,mdss-dsi-pan-enable-dynamic-fps;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-physical-type = &quot;oled&quot;;
				qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,dsi-supported-dfps-list = &lt;0x3c 0x39 0x37&gt;;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x21&gt;;
				qcom,mdss-dsi-panel-hdr-enabled;
				phandle = &lt;0x522&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,panel-supply-entries = &lt;0x521&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,platform-te-gpio = &lt;0x174 0x0a 0x00&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;
				qcom,mdss-brightness-max-level = &lt;0x7ff&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,display-topology = &lt;0x02 0x02 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x0c&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0xb40&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 03 b0 a5 00 07 01 00 00 00 00 02 01 00 39 01 00 00 00 00 06 b2 00 5d 04 80 49 15 01 00 00 00 00 02 3d 10 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 55 08 39 01 00 00 00 00 09 f8 00 08 10 08 2d 00 00 2d 39 01 00 00 3c 00 03 51 00 00 05 01 00 00 50 00 02 11 00 39 01 00 00 00 00 03 b0 34 04 39 01 00 00 00 00 05 c1 00 00 00 46 39 01 00 00 00 00 03 b0 a5 00 0a 01 00 00 00 00 80 11 00 00 89 30 80 0b 40 05 a0 02 d0 02 d0 02 d0 02 00 02 68 00 20 4e a8 00 0a 00 0c 00 23 00 1c 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05 01 00 00 78 00 02 29 00];
						qcom,mdss-dsi-h-front-porch = &lt;0x0a&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x0a&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-height = &lt;0x2d0&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x5a0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x01&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x130504 0x1f1e0505 0x3020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x0a&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x02&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x0a&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_sharp_qsync_fhd_cmd {
				qcom,adjust-timer-wakeup-ms = &lt;0x01&gt;;
				qcom,mdss-pan-physical-width-dimension = &lt;0x4a&gt;;
				qcom,mdss-dsi-panel-name = &quot;Sharp fhd cmd mode qsync dsi panel&quot;;
				qcom,mdss-pan-physical-height-dimension = &lt;0x86&gt;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x09&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-panel-blackness-level = &lt;0x1361&gt;;
				qcom,mdss-dsi-panel-peak-brightness = &lt;0x626b50&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8&gt;;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x12&gt;;
				qcom,mdss-dsi-panel-hdr-enabled;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				phandle = &lt;0x539&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-tx-eot-append;
				qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@1 {
						qcom,display-topology = &lt;0x02 0x02 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x5a&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x08&gt;;
						qcom,mdss-dsi-panel-jitter = &lt;0x03 0x01&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0x780&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x14&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x0c&gt;;
						qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 02];
						qcom,mdss-dsc-slice-height = &lt;0x08&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0xc0202 0x1d1c0303 0x1020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x0e&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x10&gt;;
						qcom,mdss-mdp-transfer-time-us = &lt;0x2134&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};

timing@2 {
						qcom,display-topology = &lt;0x02 0x02 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x78&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x08&gt;;
						qcom,mdss-dsi-panel-jitter = &lt;0x03 0x01&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0x780&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x14&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x0c&gt;;
						qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 03];
						qcom,mdss-dsc-slice-height = &lt;0x08&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0xf0303 0x1e1d0404 0x2020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x0e&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x10&gt;;
						qcom,mdss-mdp-transfer-time-us = &lt;0x16a8&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};

timing@0 {
						qcom,display-topology = &lt;0x02 0x02 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x08&gt;;
						qcom,mdss-dsi-panel-jitter = &lt;0x03 0x01&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0x780&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x14&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x0c&gt;;
						qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01];
						qcom,mdss-dsc-slice-height = &lt;0x08&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0xa0102 0x1b1b0202 0x20400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x0e&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x10&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_sharp_qsync_wqhd_video {
				qcom,adjust-timer-wakeup-ms = &lt;0x01&gt;;
				qcom,dsi-phy-num = &lt;0x00 0x01&gt;;
				qcom,mdss-pan-physical-width-dimension = &lt;0x4a&gt;;
				qcom,mdss-dsi-panel-name = &quot;Sharp 2k video mode qsync dsi panel&quot;;
				qcom,mdss-pan-physical-height-dimension = &lt;0x86&gt;;
				qcom,dsi-select-clocks = &quot;src_byte_clk0\0src_pixel_clk0&quot;;
				qcom,mdss-dsi-t-clk-post = &lt;0x0a&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,dsi-ctrl-num = &lt;0x00 0x01&gt;;
				qcom,mdss-dsi-panel-blackness-level = &lt;0x1361&gt;;
				qcom,mdss-dsi-panel-peak-brightness = &lt;0x626b50&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8&gt;;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x1e&gt;;
				qcom,mdss-dsi-panel-hdr-enabled;
				phandle = &lt;0x537&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-tx-eot-append;
				qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,display-topology = &lt;0x02 0x02 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x08&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0xa00&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = &lt;0x39010000 0x2ff 0xd0390100 0x02 0x75403901 0x1000 0x2f14039 0x1000000 0x2ff10 0x39010000 0x1000062c 0x1020408 0x10390100 0x02 0xffd03901 0x00 0x2750039 0x1000010 0x2f100 0x39010000 0x2ff 0x10390100 0x02 0xfb013901 0x00 0x2ba0339 0x1000000 0x2bc08 0x39010000 0x2c0 0x83390100 0x11 0xc1892800 0x8020002 0x6800d500 0xa0db709 0x89390100 0x03 0xc210f039 0x1000000 0x2d500 0x39010000 0x2d6 0x390100 0x02 0xde003901 0x00 0x2e10039 0x1000000 0x2e501 0x39010000 0x2bb 0x3390100 0x02 0xf6703901 0x00 0x2f78039 0x1000000 0x5be00 0x10001039 0x1000000 0x23500 0x39010000 0x244 0x390100 0x02 0xff203901 0x00 0x2fb0139 0x1000000 0x28702 0x39010000 0x25d 0x390100 0x02 0x5e143901 0x00 0x25feb39 0x1000000 0x2ff26 0x39010000 0x2fb 0x1390100 0x02 0x60003901 0x00 0x2620139 0x1000000 0x24000 0x39010000 0x2ff 0x28390100 0x02 0xfb013901 0x00 0x2910239 0x1000000 0x2ffe0 0x39010000 0x2fb 0x1390100 0x02 0x48813901 0x00 0x28e0939 0x1000000 0x2fff0 0x39010000 0x2fb 0x1390100 0x02 0x33203901 0x00 0x2343539 0x1000000 0x2ff10 0x5010000 0x78000111 0x5010000 0x78000129&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x14&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x0c&gt;;
						qcom,mdss-dsc-slice-height = &lt;0x08&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x120404 0x1e1e0404 0x2020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x0e&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x7d8&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_sharp_wqhd_cmd {
				qcom,ulps-enabled;
				qcom,adjust-timer-wakeup-ms = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-status-check-mode = &quot;reg_read&quot;;
				qcom,mdss-pan-physical-width-dimension = &lt;0x44&gt;;
				qcom,mdss-dsi-panel-status-read-length = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-name = &quot;Dual Sharp WQHD cmd mode dsi panel&quot;;
				qcom,mdss-pan-physical-height-dimension = &lt;0x79&gt;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,esd-check-enabled;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-status-value = &lt;0x9c&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x0c&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x14 0x00 0x14 0x01 0x14&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x21&gt;;
				qcom,mdss-dsi-panel-status-command-state = &quot;dsi_hs_mode&quot;;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-on-check-value = &lt;0x9c&gt;;
				phandle = &lt;0x52c&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
				qcom,mdss-dsi-tx-eot-append;
				qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,dcs-cmd-by-left;
				qcom,mdss-dsi-panel-status-command = &lt;0x6010001 0x10a&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,partial-update-enabled = &quot;single_roi&quot;;
						qcom,display-topology = &lt;0x02 0x00 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x04&gt;;
						qcom,mdss-dsi-panel-height = &lt;0xa00&gt;;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 15 01 00 00 00 00 02 90 01 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 58 01 15 01 00 00 00 00 02 c9 00 15 01 00 00 00 00 02 c0 15 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x1e&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x64&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x01&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x2e080a 0x1218080b 0x9030400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x08&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,panel-roi-alignment = &lt;0x2d0 0xa0 0xa0 0xa0 0x5a0 0xa0&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_dual_sim_dsc_375_cmd {
				qcom,ulps-enabled;
				qcom,mdss-dsi-panel-name = &quot;Sim dual cmd mode DSC 3.75:1 dsi panel&quot;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,panel-ack-disabled;
				qcom,mdss-dsi-t-clk-post = &lt;0x0d&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-bl-max-level = &lt;0xfff&gt;;
				qcom,mdss-dsi-hor-line-idle = &lt;0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40&gt;;
				qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,cmd-sync-wait-broadcast;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-te-using-wd;
				qcom,mdss-dsi-t-clk-pre = &lt;0x2d&gt;;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				phandle = &lt;0x52a&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,panel-supply-entries = &lt;0x520&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@1 {
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x02 0x02 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x10&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0xa00&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00];
						qcom,mdss-dsi-h-front-porch = &lt;0x64&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x20&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-height = &lt;0x10&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x01&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x180606 0x21200606 0x4020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x07&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsc-bit-per-component = &lt;0x0a&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};

timing@0 {
						qcom,display-topology = &lt;0x02 0x02 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x04&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0xf00&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x1e&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x438&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x64&gt;;
						qcom,mdss-dsc-slice-height = &lt;0x20&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x01&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x1c0707 0x23210707 0x5020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x07&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsc-bit-per-component = &lt;0x0a&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_sw43404_fhd_plus_cmd {
				qcom,ulps-enabled;
				qcom,mdss-dsi-bl-min-level = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-status-check-mode = &quot;reg_read&quot;;
				qcom,mdss-pan-physical-width-dimension = &lt;0x44&gt;;
				qcom,mdss-dsi-panel-status-read-length = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-name = &quot;sw43404 amoled boe fhd+ panel with DSC&quot;;
				qcom,mdss-pan-physical-height-dimension = &lt;0x8a&gt;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,esd-check-enabled;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
				qcom,mdss-dsi-panel-status-value = &lt;0x9c&gt;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x09&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-bl-max-level = &lt;0x3ff&gt;;
				qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
				qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
				qcom,mdss-dsi-panel-peak-brightness = &lt;0x401640&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-physical-type = &quot;oled&quot;;
				qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x1b&gt;;
				qcom,mdss-dsi-panel-hdr-enabled;
				qcom,mdss-dsi-panel-status-command-state = &quot;dsi_hs_mode&quot;;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-on-check-value = &lt;0x9c&gt;;
				phandle = &lt;0x524&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,panel-supply-entries = &lt;0x521&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-lane-map = &quot;lane_map_0123&quot;;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-panel-status-command = &lt;0x6010001 0x10a&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,platform-te-gpio = &lt;0x174 0x0a 0x00&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,partial-update-enabled = &quot;single_roi&quot;;
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x01 0x01 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x10&gt;;
						qcom,mdss-dsi-panel-jitter = &lt;0x03 0x01&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0x870&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 03 b0 a5 00 07 01 00 00 00 00 02 01 00 0a 01 00 00 00 00 80 11 00 00 89 30 80 08 70 04 38 02 1c 02 1c 02 1c 02 00 02 0e 00 20 34 29 00 07 00 0c 00 2e 00 31 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 03 b0 a5 00 15 01 00 00 00 00 02 5e 10 39 01 00 00 00 00 06 b9 bf 11 40 00 30 39 01 00 00 00 00 09 f8 00 08 10 08 2d 00 00 2d 15 01 00 00 00 00 02 55 08 05 01 00 00 1e 00 02 11 00 15 01 00 00 78 00 02 3d 01 39 01 00 00 00 00 03 b0 a5 00 05 01 00 00 78 00 02 35 00 05 01 00 00 3c 00 02 29 00];
						qcom,mdss-dsi-h-front-porch = &lt;0xa0&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x48&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-height = &lt;0x10e&gt;;
						qcom,mdss-dsi-panel-clockrate = &lt;0x15228c00&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x01&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0xf0303 0x1e1d0404 0x2030400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x08&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,panel-roi-alignment = &lt;0x21c 0x10e 0x10e 0x10e 0x438 0x10e&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_sim_video {
				qcom,mdss-dsi-panel-name = &quot;Simulator video mode dsi panel&quot;;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-mode-switch;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,panel-ack-disabled;
				qcom,mdss-dsi-t-clk-post = &lt;0x0d&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
				qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
				qcom,mdss-dsi-panel-peak-brightness = &lt;0x401640&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x00 0x00 0x00 0x01 0x00&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-te-using-wd;
				qcom,mdss-dsi-t-clk-pre = &lt;0x2d&gt;;
				qcom,mdss-dsi-panel-hdr-enabled;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				phandle = &lt;0x525&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,panel-supply-entries = &lt;0x520&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@1 {
						qcom,mdss-dsi-panel-timings = &lt;0x00 0x00 0x00&gt;;
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,video-to-cmd-mode-post-switch-commands-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x08&gt;;
						qcom,mdss-dsi-panel-height = &lt;0x1e0&gt;;
						qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00];
						qcom,mdss-dsi-h-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x280&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-v-back-porch = &lt;0x06&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsi-cmd-mode;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00];
						qcom,video-to-cmd-mode-post-switch-commands = [32 01 00 00 00 00 02 00 00];
						qcom,mdss-dsi-v-front-porch = &lt;0x06&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};

timing@0 {
						qcom,mdss-dsi-panel-timings = &lt;0x00 0x00 0x00&gt;;
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x01 0x00 0x01 0x02 0x00 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,cmd-to-video-mode-post-switch-commands-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x08&gt;;
						qcom,mdss-dsi-video-mode;
						qcom,mdss-dsi-panel-height = &lt;0x1e0&gt;;
						qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00];
						qcom,mdss-dsi-h-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x280&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x1c0707 0x23210707 0x5020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x06&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,cmd-to-video-mode-post-switch-commands = [32 01 00 00 00 00 02 00 00];
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00];
						qcom,mdss-dsi-v-front-porch = &lt;0x06&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};
				};
			};

qcom,sde-reg-bus {
				qcom,msm-bus,name = &quot;mdss_reg&quot;;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x04&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00 0x01 0x24e 0x00 0x249f0 0x01 0x24e 0x00 0x493e0&gt;;
			};

qcom,mdss_dsi_dual_sim_cmd {
				qcom,ulps-enabled;
				qcom,mdss-dsi-panel-name = &quot;Sim dual cmd mode dsi panel&quot;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,panel-ack-disabled;
				qcom,mdss-dsi-t-clk-post = &lt;0x0d&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-bl-max-level = &lt;0xfff&gt;;
				qcom,mdss-dsi-hor-line-idle = &lt;0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40&gt;;
				qcom,mdss-dsi-qsync-min-refresh-rate = &lt;0x2d&gt;;
				qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,cmd-sync-wait-broadcast;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-te-using-wd;
				qcom,mdss-dsi-t-clk-pre = &lt;0x2d&gt;;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				phandle = &lt;0x528&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,panel-supply-entries = &lt;0x520&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@1 {
						qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x02 0x00 0x02 0x01 0x00 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x10&gt;;
						qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];
						qcom,mdss-dsi-panel-height = &lt;0x5a0&gt;;
						qcom,mdss-dsi-on-command = &lt;0x5010000 0x129&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x78&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x2c&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsi-qsync-off-commands-state = &quot;dsi_hs_mode&quot;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x500&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x04&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x1c0707 0x23210707 0x5020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x04&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00];
						qcom,mdss-dsi-qsync-on-commands-state = &quot;dsi_hs_mode&quot;;
						qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};

timing@2 {
						qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];
						qcom,display-topology = &lt;0x02 0x00 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x28&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x04&gt;;
						qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];
						qcom,mdss-dsi-panel-height = &lt;0xf00&gt;;
						qcom,mdss-dsi-on-command = &lt;0x5010000 0x129&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x1e&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x64&gt;;
						qcom,mdss-dsi-qsync-off-commands-state = &quot;dsi_hs_mode&quot;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x01&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x180606 0x21200606 0x4020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x07&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00];
						qcom,mdss-dsi-qsync-on-commands-state = &quot;dsi_hs_mode&quot;;
						qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};

timing@0 {
						qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x02 0x00 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x78&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x04&gt;;
						qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];
						qcom,mdss-dsi-panel-height = &lt;0x780&gt;;
						qcom,mdss-dsi-on-command = &lt;0x5010000 0x129&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x1c&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x04&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsi-qsync-off-commands-state = &quot;dsi_hs_mode&quot;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x240909 0x26240909 0x6020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x0c&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00];
						qcom,mdss-dsi-qsync-on-commands-state = &quot;dsi_hs_mode&quot;;
						qcom,mdss-dsi-v-front-porch = &lt;0x0c&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_sharp_qsync_wqhd_cmd {
				qcom,adjust-timer-wakeup-ms = &lt;0x01&gt;;
				qcom,mdss-pan-physical-width-dimension = &lt;0x4a&gt;;
				qcom,mdss-dsi-panel-name = &quot;Sharp 2k cmd mode qsync dsi panel&quot;;
				qcom,mdss-pan-physical-height-dimension = &lt;0x86&gt;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x0b&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-panel-blackness-level = &lt;0x1361&gt;;
				qcom,mdss-dsi-panel-peak-brightness = &lt;0x626b50&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8&gt;;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x24&gt;;
				qcom,mdss-dsi-panel-hdr-enabled;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				phandle = &lt;0x536&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-tx-eot-append;
				qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@3 {
						qcom,display-topology = &lt;0x02 0x02 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x78&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x08&gt;;
						qcom,mdss-dsi-panel-jitter = &lt;0x03 0x01&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0xa00&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x14&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x0c&gt;;
						qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 03];
						qcom,mdss-dsc-slice-height = &lt;0x08&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x160605 0x201f0606 0x3020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x0e&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x10&gt;;
						qcom,mdss-mdp-transfer-time-us = &lt;0x16a8&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};

timing@1 {
						qcom,display-topology = &lt;0x02 0x02 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x08&gt;;
						qcom,mdss-dsi-panel-jitter = &lt;0x03 0x01&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0x780&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x14&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x0c&gt;;
						qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01];
						qcom,mdss-dsc-slice-height = &lt;0x08&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0xa0102 0x1b1b0202 0x20400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x0e&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x10&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};

timing@2 {
						qcom,display-topology = &lt;0x02 0x02 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x5a&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x08&gt;;
						qcom,mdss-dsi-panel-jitter = &lt;0x03 0x01&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0xa00&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x14&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x0c&gt;;
						qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 02];
						qcom,mdss-dsc-slice-height = &lt;0x08&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x110404 0x1e1e0404 0x2020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x0e&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x10&gt;;
						qcom,mdss-mdp-transfer-time-us = &lt;0x2134&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};

timing@0 {
						qcom,display-topology = &lt;0x02 0x02 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x08&gt;;
						qcom,mdss-dsi-panel-jitter = &lt;0x03 0x01&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0xa00&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x14&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x0c&gt;;
						qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01];
						qcom,mdss-dsc-slice-height = &lt;0x08&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x2d0&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0xb0302 0x1d1c0303 0x1020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x0e&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x10&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_nt35695b_truly_fhd_video {
				qcom,mdss-dsi-panel-status-check-mode = &quot;reg_read&quot;;
				qcom,mdss-dsi-panel-status-read-length = &lt;0x01&gt;;
				qcom,mdss-dsi-panel-name = &quot;nt35695b truly fhd video mode dsi panel&quot;;
				qcom,esd-check-enabled;
				qcom,mdss-dsi-panel-status-value = &lt;0x9c&gt;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x07&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-post-init-delay = &lt;0x01&gt;;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-pan-fps-update = &quot;dfps_immediate_porch_mode_vfp&quot;;
				qcom,mdss-dsi-pan-enable-dynamic-fps;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,dsi-supported-dfps-list = &lt;0x3c 0x37 0x30&gt;;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x1c&gt;;
				qcom,mdss-dsi-panel-status-command-state = &quot;dsi_hs_mode&quot;;
				qcom,mdss-dsi-panel-on-check-value = &lt;0x9c&gt;;
				phandle = &lt;0x52f&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-tx-eot-append;
				qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-panel-status-command = &lt;0x6010001 0x10a&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x01 0x00 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x0c&gt;;
						qcom,mdss-dsi-panel-height = &lt;0x780&gt;;
						qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 03 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00];
						qcom,mdss-dsi-h-front-porch = &lt;0x78&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x130504 0x1f1e0505 0x3020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x02&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsi-v-front-porch = &lt;0x0c&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};
				};
			};

qcom,sde-sspp-vig-blocks {
				qcom,sde-vig-igc = &lt;0x1d00 0x50000&gt;;
				qcom,sde-vig-gamut = &lt;0x1d00 0x50000&gt;;
				qcom,sde-vig-qseed-size = &lt;0xa0&gt;;
				qcom,sde-vig-csc-off = &lt;0x1a00&gt;;
				qcom,sde-vig-inverse-pma;
				qcom,sde-vig-qseed-off = &lt;0xa00&gt;;
			};

qcom,mdss_dsi_rm69299_visionox_amoled_video {
				qcom,mdss-dsi-panel-name = &quot;rm69299 amoled fhd+ video mode dsi visionox panel&quot;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x0e&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x31&gt;;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				phandle = &lt;0x531&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-lp11-init;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-map = &quot;lane_map_0123&quot;;
				qcom,mdss-dsi-tx-eot-append;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,display-topology = &lt;0x01 0x00 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-panel-height = &lt;0x8c8&gt;;
						qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 c2 08 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 51 ff 05 01 00 00 96 00 02 11 00 05 01 00 00 32 00 02 29 00];
						qcom,mdss-dsi-h-front-porch = &lt;0x1a&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x24&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x04&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x200808 0x24230808 0x5020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x04&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00];
						qcom,mdss-dsi-v-front-porch = &lt;0x38&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_dual_sim_video {
				qcom,mdss-dsi-panel-name = &quot;Sim dual video mode dsi panel&quot;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,panel-ack-disabled;
				qcom,mdss-dsi-t-clk-post = &lt;0x0d&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-bl-max-level = &lt;0xfff&gt;;
				qcom,mdss-dsi-qsync-min-refresh-rate = &lt;0x2d&gt;;
				qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-panel-broadcast-mode;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x14 0x00 0xc8 0x01 0x14&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x2d&gt;;
				phandle = &lt;0x526&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,panel-supply-entries = &lt;0x520&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];
						qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
						qcom,display-topology = &lt;0x02 0x00 0x02 0x01 0x00 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x10&gt;;
						qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];
						qcom,mdss-dsi-panel-height = &lt;0x5a0&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x78&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x2c&gt;;
						qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
						qcom,mdss-dsi-qsync-off-commands-state = &quot;dsi_hs_mode&quot;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x500&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x04&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x1c0707 0x23210707 0x5020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x04&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
						qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
						qcom,mdss-dsi-qsync-on-commands-state = &quot;dsi_hs_mode&quot;;
						qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};

qcom,sde-dspp-blocks {
				qcom,sde-dspp-memcolor = &lt;0x880 0x10007&gt;;
				qcom,sde-dspp-gc = &lt;0x17c0 0x10008&gt;;
				qcom,sde-dspp-pcc = &lt;0x1700 0x40000&gt;;
				qcom,sde-dspp-igc = &lt;0x00 0x30001&gt;;
				qcom,sde-dspp-hist = &lt;0x800 0x10007&gt;;
				qcom,sde-dspp-vlut = &lt;0xa00 0x10008&gt;;
				qcom,sde-dspp-dither = &lt;0x82c 0x10007&gt;;
				qcom,sde-dspp-gamut = &lt;0x1000 0x40001&gt;;
				qcom,sde-dspp-sixzone = &lt;0x900 0x10007&gt;;
				qcom,sde-dspp-hsic = &lt;0x800 0x10007&gt;;
			};

qcom,sde-data-bus {
				qcom,msm-bus,name = &quot;mdss_sde&quot;;
				qcom,msm-bus,num-paths = &lt;0x02&gt;;
				qcom,msm-bus,num-cases = &lt;0x03&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0x16 0x200 0x00 0x00 0x17 0x200 0x00 0x00 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800&gt;;
			};

qcom,sde-sspp-dma-blocks {

dgm@1 {
					qcom,sde-dma-igc = &lt;0x1400 0x50000&gt;;
					qcom,sde-dma-gc = &lt;0x600 0x50000&gt;;
					qcom,sde-dma-csc-off = &lt;0x1200&gt;;
					qcom,sde-dma-inverse-pma;
				};

dgm@0 {
					qcom,sde-dma-igc = &lt;0x400 0x50000&gt;;
					qcom,sde-dma-gc = &lt;0x600 0x50000&gt;;
					qcom,sde-dma-csc-off = &lt;0x200&gt;;
					qcom,sde-dma-inverse-pma;
				};
			};

qcom,mdss_dsi_sharp_qsync_fhd_video {
				qcom,adjust-timer-wakeup-ms = &lt;0x01&gt;;
				qcom,mdss-pan-physical-width-dimension = &lt;0x4a&gt;;
				qcom,mdss-dsi-panel-name = &quot;Sharp fhd video mode qsync dsi panel&quot;;
				qcom,mdss-dsi-min-refresh-rate = &lt;0x3c&gt;;
				qcom,mdss-pan-physical-height-dimension = &lt;0x86&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x0a&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-max-refresh-rate = &lt;0x78&gt;;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-panel-blackness-level = &lt;0x1361&gt;;
				qcom,mdss-dsi-panel-peak-brightness = &lt;0x626b50&gt;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-pan-fps-update = &quot;dfps_immediate_porch_mode_vfp&quot;;
				qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8&gt;;
				qcom,mdss-dsi-pan-enable-dynamic-fps;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,dsi-supported-dfps-list = &lt;0x78 0x5a 0x3c&gt;;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x20&gt;;
				qcom,mdss-dsi-panel-hdr-enabled;
				phandle = &lt;0x538&gt;;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-tx-eot-append;
				qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,display-topology = &lt;0x02 0x02 0x02&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x14&gt;;
						qcom,compression-mode = &quot;dsc&quot;;
						qcom,mdss-dsi-panel-height = &lt;0x780&gt;;
						qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
						qcom,mdss-dsc-block-prediction-enable;
						qcom,mdss-dsi-on-command = &lt;0x39010000 0x2ff 0xd0390100 0x02 0x75403901 0x1000 0x2f14039 0x1000000 0x2ff10 0x39010000 0x1000062c 0x1020408 0x10390100 0x02 0xffd03901 0x00 0x2750039 0x1000010 0x2f100 0x39010000 0x2ff 0x10390100 0x02 0xfb013901 0x00 0x2ba0339 0x1000000 0x2bc08 0x39010000 0x2c0 0x85390100 0x11 0xc1892800 0x8020002 0xe00bb00 0x70db70c 0xb7390100 0x03 0xc210f039 0x1000000 0x2d500 0x39010000 0x2d6 0x390100 0x02 0xde003901 0x00 0x2e10039 0x1000000 0x2e501 0x39010000 0x2bb 0x3390100 0x02 0xf6703901 0x00 0x2f78039 0x1000000 0x5be00 0x10001039 0x1000000 0x23500 0x39010000 0x244 0x390100 0x02 0xff203901 0x00 0x2fb0139 0x1000000 0x28702 0x39010000 0x25d 0x390100 0x02 0x5e143901 0x00 0x25feb39 0x1000000 0x2ff26 0x39010000 0x2fb 0x1390100 0x02 0x60003901 0x00 0x2620139 0x1000000 0x24000 0x39010000 0x2ff 0x28390100 0x02 0xfb013901 0x00 0x2910239 0x1000000 0x2ffe0 0x39010000 0x2fb 0x1390100 0x02 0x48813901 0x00 0x28e0939 0x1000000 0x2fff0 0x39010000 0x2fb 0x1390100 0x02 0x33203901 0x00 0x2343539 0x1000000 0x2ff10 0x5010000 0x78000111 0x5010000 0x78000129&gt;;
						qcom,mdss-dsi-h-front-porch = &lt;0x7c&gt;;
						qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x14&gt;;
						qcom,mdss-dsc-slice-height = &lt;0x08&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x21c&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x130404 0x1f1f0405 0x3020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x0e&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsc-slice-per-pkt = &lt;0x01&gt;;
						qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
						qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
						qcom,mdss-dsi-v-front-porch = &lt;0x7b0&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
					};
				};
			};

qcom,mdss_dsi_rm69298_truly_amoled_cmd {
				qcom,mdss-dsi-panel-name = &quot;rm69298 amoled fhd+ cmd mode dsi truly panel&quot;;
				qcom,mdss-dsi-te-using-te-pin;
				qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
				qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
				qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
				qcom,mdss-dsi-t-clk-post = &lt;0x0d&gt;;
				qcom,mdss-dsi-lane-2-state;
				qcom,mdss-dsi-te-check-enable;
				qcom,mdss-dsi-bllp-eof-power-mode;
				qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
				qcom,mdss-dsi-lane-3-state;
				qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
				qcom,mdss-dsi-reset-sequence = &lt;0x01 0x0a 0x00 0x0a 0x01 0x0a&gt;;
				qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
				qcom,mdss-dsi-lane-0-state;
				qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
				qcom,mdss-dsi-t-clk-pre = &lt;0x30&gt;;
				qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
				phandle = &lt;0x52e&gt;;
				qcom,mdss-dsi-bllp-power-mode;
				qcom,mdss-dsi-stream = &lt;0x00&gt;;
				qcom,mdss-dsi-lp11-init;
				qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
				qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
				qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-map = &quot;lane_map_0123&quot;;
				qcom,mdss-dsi-tx-eot-append;
				qcom,mdss-dsi-traffic-mode = &quot;non_burst_sync_event&quot;;
				qcom,mdss-dsi-border-color = &lt;0x00&gt;;
				qcom,mdss-dsi-lane-1-state;
				qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
				qcom,mdss-dsi-bpp = &lt;0x18&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
						qcom,display-topology = &lt;0x01 0x00 0x01&gt;;
						qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
						qcom,mdss-dsi-h-pulse-width = &lt;0x0a&gt;;
						qcom,mdss-dsi-panel-height = &lt;0x870&gt;;
						qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 fe 40 15 01 00 00 00 00 02 0a 15 15 01 00 00 00 00 02 0b cc 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 80 15 01 00 00 00 00 02 0f 87 15 01 00 00 00 00 02 05 08 15 01 00 00 00 00 02 06 08 15 01 00 00 00 00 02 08 08 15 01 00 00 00 00 02 09 08 15 01 00 00 00 00 02 16 15 15 01 00 00 00 00 02 20 8d 15 01 00 00 00 00 02 21 8d 15 01 00 00 00 00 02 24 55 15 01 00 00 00 00 02 26 55 15 01 00 00 00 00 02 28 55 15 01 00 00 00 00 02 2a 55 15 01 00 00 00 00 02 2d 28 15 01 00 00 00 00 02 2f 28 15 01 00 00 00 00 02 30 1e 15 01 00 00 00 00 02 31 1e 15 01 00 00 00 00 02 37 80 15 01 00 00 00 00 02 38 40 15 01 00 00 00 00 02 39 90 15 01 00 00 00 00 02 46 43 15 01 00 00 00 00 02 47 43 15 01 00 00 00 00 02 64 02 15 01 00 00 00 00 02 6f 02 15 01 00 00 00 00 02 74 2f 15 01 00 00 00 00 02 80 16 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 fe a0 15 01 00 00 00 00 02 2b 22 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 2f 35 15 01 00 00 00 00 02 fe 60 15 01 00 00 00 00 02 00 ac 15 01 00 00 00 00 02 01 0f 15 01 00 00 00 00 02 02 ff 15 01 00 00 00 00 02 03 05 15 01 00 00 00 00 02 04 00 15 01 00 00 00 00 02 05 06 15 01 00 00 00 00 02 06 00 15 01 00 00 00 00 02 07 00 15 01 00 00 00 00 02 09 c0 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 02 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0e 00 15 01 00 00 00 00 02 0e 04 15 01 00 00 00 00 02 0f 0e 15 01 00 00 00 00 02 10 a2 15 01 00 00 00 00 02 12 c0 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 14 02 15 01 00 00 00 00 02 15 00 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 17 05 15 01 00 00 00 00 02 18 0e 15 01 00 00 00 00 02 19 a2 15 01 00 00 00 00 02 1b c0 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 04 15 01 00 00 00 00 02 1e 01 15 01 00 00 00 00 02 1f 00 15 01 00 00 00 00 02 20 04 15 01 00 00 00 00 02 21 24 15 01 00 00 00 00 02 22 99 15 01 00 00 00 00 02 24 c0 15 01 00 00 00 00 02 25 00 15 01 00 00 00 00 02 26 04 15 01 00 00 00 00 02 27 01 15 01 00 00 00 00 02 28 00 15 01 00 00 00 00 02 29 06 15 01 00 00 00 00 02 2a 24 15 01 00 00 00 00 02 2b 99 15 01 00 00 00 00 02 83 ca 15 01 00 00 00 00 02 84 0f 15 01 00 00 00 00 02 85 ff 15 01 00 00 00 00 02 86 0a 15 01 00 00 00 00 02 87 00 15 01 00 00 00 00 02 88 08 15 01 00 00 00 00 02 89 00 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 8b 80 15 01 00 00 00 00 02 c7 1f 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 c9 01 15 01 00 00 00 00 02 ca 1f 15 01 00 00 00 00 02 cb 02 15 01 00 00 00 00 02 cc 1f 15 01 00 00 00 00 02 cd 1f 15 01 00 00 00 00 02 ce 1f 15 01 00 00 00 00 02 cf 1f 15 01 00 00 00 00 02 d0 1f 15 01 00 00 00 00 02 d1 1f 15 01 00 00 00 00 02 d2 1f 15 01 00 00 00 00 02 d3 1f 15 01 00 00 00 00 02 d4 1f 15 01 00 00 00 00 02 d5 1f 15 01 00 00 00 00 02 d6 1f 15 01 00 00 00 00 02 d7 1f 15 01 00 00 00 00 02 d8 1f 15 01 00 00 00 00 02 d9 1f 15 01 00 00 00 00 02 da 1f 15 01 00 00 00 00 02 db 1f 15 01 00 00 00 00 02 dc 00 15 01 00 00 00 00 02 dd 0e 15 01 00 00 00 00 02 de 1f 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 04 15 01 00 00 00 00 02 e1 1f 15 01 00 00 00 00 02 e2 01 15 01 00 00 00 00 02 e3 02 15 01 00 00 00 00 02 e4 1f 15 01 00 00 00 00 02 e5 1f 15 01 00 00 00 00 02 e6 1f 15 01 00 00 00 00 02 e7 1f 15 01 00 00 00 00 02 e8 1f 15 01 00 00 00 00 02 e9 1f 15 01 00 00 00 00 02 ea 1f 15 01 00 00 00 00 02 eb 1f 15 01 00 00 00 00 02 ec 1f 15 01 00 00 00 00 02 ed 1f 15 01 00 00 00 00 02 ee 1f 15 01 00 00 00 00 02 ef 03 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 c6 15 15 01 00 00 00 00 02 c9 9e 15 01 00 00 00 00 02 cb 3f 15 01 00 00 00 00 02 d1 0f 15 01 00 00 00 00 02 d3 15 15 01 00 00 00 00 02 d4 15 15 01 00 00 00 00 02 d5 00 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 a9 40 15 01 00 00 00 00 02 cb 05 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 5a ff 15 01 00 00 00 00 02 5c ff 15 01 00 00 00 00 02 5d 0a 15 01 00 00 00 00 02 7d 31 15 01 00 00 00 00 02 7e 4a 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 49 05 15 01 00 00 00 00 02 4a 2e 15 01 00 00 00 00 02 4b 58 15 01 00 00 00 00 02 4c 77 15 01 00 00 00 00 02 4d a1 15 01 00 00 00 00 02 4e de 15 01 00 00 00 00 02 4f 2c 15 01 00 00 00 00 02 50 97 15 01 00 00 00 00 02 51 2a 15 01 00 00 00 00 02 ad ec 15 01 00 00 00 00 02 ae 80 15 01 00 00 00 00 02 af 00 15 01 00 00 00 00 02 b0 50 15 01 00 00 00 00 02 b1 3a 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 56 91 15 01 00 00 00 00 02 58 04 15 01 00 00 00 00 02 59 24 15 01 00 00 00 00 02 5a 05 15 01 00 00 00 00 02 5b c6 15 01 00 00 00 00 02 5c 05 15 01 00 00 00 00 02 5d 66 15 01 00 00 00 00 02 5e 06 15 01 00 00 00 00 02 5f 17 15 01 00 00 00 00 02 60 07 15 01 00 00 00 00 02 61 cf 15 01 00 00 00 00 02 62 07 15 01 00 00 00 00 02 63 98 15 01 00 00 00 00 02 64 08 15 01 00 00 00 00 02 65 65 15 01 00 00 00 00 02 66 09 15 01 00 00 00 00 02 67 37 15 01 00 00 00 00 02 68 0a 15 01 00 00 00 00 02 6b 02 15 01 00 00 00 00 02 6c 0c 15 01 00 00 00 00 02 71 02 15 01 00 00 00 00 02 72 0f 15 01 00 00 00 00 02 73 93 15 01 00 00 00 00 02 74 0f 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 98 cf 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 b4 31 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 aa 03 15 01 00 00 00 00 02 09 13 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 01 41 15 01 00 00 00 00 02 02 00 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 04 ff 15 01 00 00 00 00 02 05 00 15 01 00 00 00 00 02 06 c0 15 01 00 00 00 00 02 07 40 15 01 00 00 00 00 02 08 20 15 01 00 00 00 00 02 19 e0 15 01 00 00 00 00 02 1a 40 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 80 15 01 00 00 00 00 02 60 40 15 01 00 00 00 00 02 61 40 15 01 00 00 00 00 02 62 40 15 01 00 00 00 00 02 63 40 15 01 00 00 00 00 02 64 40 15 01 00 00 00 00 02 65 40 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 02 15 01 00 00 00 00 02 75 10 15 01 00 00 00 00 02 76 14 15 01 00 00 00 00 02 77 1c 15 01 00 00 00 00 02 78 20 15 01 00 00 00 00 02 79 0a 15 01 00 00 00 00 02 7a 00 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c 00 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e 00 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 81 00 15 01 00 00 00 00 02 82 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 84 00 15 01 00 00 00 00 02 85 00 15 01 00 00 00 00 02 86 20 15 01 00 00 00 00 02 87 0a 15 01 00 00 00 00 02 88 02 15 01 00 00 00 00 02 89 2b 15 01 00 00 00 00 02 8a 14 15 01 00 00 00 00 02 8b 01 15 01 00 00 00 00 02 8c 00 15 01 00 00 00 00 02 8d 00 15 01 00 00 00 00 02 8e 00 15 01 00 00 00 00 02 8f 00 15 01 00 00 00 00 02 90 00 15 01 00 00 00 00 02 91 00 15 01 00 00 00 00 02 92 00 15 01 00 00 00 00 02 93 00 15 01 00 00 00 00 02 94 00 15 01 00 00 00 00 02 95 00 15 01 00 00 00 00 02 96 00 15 01 00 00 00 00 02 b2 40 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 b8 d0 15 01 00 00 00 00 02 b9 06 15 01 00 00 00 00 02 ba 00 15 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 05 51 00 00 ff ff 15 01 00 00 00 00 02 c2 08 15 01 00 00 00 00 02 35 00 05 01 00 00 96 00 01 11 05 01 00 00 32 00 01 29];
						qcom,mdss-dsi-h-front-porch = &lt;0x1e&gt;;
						qcom,mdss-dsi-h-back-porch = &lt;0x28&gt;;
						qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
						qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
						qcom,mdss-dsi-v-pulse-width = &lt;0x04&gt;;
						qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
						qcom,mdss-dsi-panel-phy-timings = &lt;0x1f0808 0x24220808 0x5020400&gt;;
						qcom,mdss-dsi-v-back-porch = &lt;0x10&gt;;
						qcom,default-topology-index = &lt;0x00&gt;;
						qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00];
						qcom,mdss-dsi-v-front-porch = &lt;0x08&gt;;
						qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					};
				};
			};
		};

jtagmm@7540000 {
			clock-names = &quot;core_clk&quot;;
			reg-names = &quot;etm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			compatible = &quot;qcom,jtagv8-mm&quot;;
			qcom,coresight-jtagmm-cpu = &lt;0x16&gt;;
			reg = &lt;0x7540000 0x1000&gt;;
			phandle = &lt;0x2ad&gt;;
		};

qcom,msm-cdsp-loader {
			compatible = &quot;qcom,cdsp-loader&quot;;
			qcom,proc-img-to-load = &quot;cdsp&quot;;
		};

rpmh-regulator-smpc8 {
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;smpc8&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm6150l-s8 {
				regulator-max-microvolt = &lt;0x157c00&gt;;
				qcom,init-voltage = &lt;0x111700&gt;;
				regulator-min-microvolt = &lt;0x111700&gt;;
				regulator-name = &quot;pm6150l_s8&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x3ff&gt;;
			};
		};

i2c@0x880000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x166&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			interrupts = &lt;0x00 0x259 0x00&gt;;
			clocks = &lt;0x27 0x44 0x27 0x67 0x27 0x68&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x168&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,i2c-geni&quot;;
			pinctrl-1 = &lt;0x167&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0x880000 0x4000&gt;;
			phandle = &lt;0x34d&gt;;
			dmas = &lt;0x165 0x00 0x00 0x03 0x40 0x00 0x165 0x01 0x00 0x03 0x40 0x00&gt;;
		};

qcom,dsi-display@23 {
			qcom,dsi-phy-num = &lt;0x00 0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x537&gt;;
			qcom,dsi-ctrl-num = &lt;0x00 0x01&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_sharp_qsync_wqhd_video_display&quot;;
			phandle = &lt;0x558&gt;;
		};

cti@601d000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti13&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x601d000 0x1000&gt;;
			phandle = &lt;0x482&gt;;
		};

lpass_core_hw_vote {
			qcom,codec-ext-clk-src = &lt;0x09&gt;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,audio-ref-clk&quot;;
			phandle = &lt;0x4cd&gt;;
		};

qcom,msm-dai-tdm-sen-rx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9050&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9150&gt;;
			phandle = &lt;0x4c4&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-sen-rx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9050&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x4c5&gt;;
			};
		};

qcom,gdsc@17d048 {
			qcom,no-status-check-on-disable;
			qcom,gds-timeout = &lt;0x1f4&gt;;
			regulator-name = &quot;hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x17d048 0x04&gt;;
			phandle = &lt;0x1c9&gt;;
		};

qcom,msm-compr-dsp {
			compatible = &quot;qcom,msm-compr-dsp&quot;;
			phandle = &lt;0x269&gt;;
		};

dsi_panel_pwr_supply_no_labibb {
			#address-cells = &lt;0x01&gt;;
			#size-cells = &lt;0x00&gt;;
			phandle = &lt;0x59e&gt;;

qcom,panel-supply-entry@0 {
				qcom,supply-disable-load = &lt;0x50&gt;;
				qcom,supply-enable-load = &lt;0x7d00&gt;;
				qcom,supply-name = &quot;vddio&quot;;
				qcom,supply-max-voltage = &lt;0x1d0d80&gt;;
				reg = &lt;0x00&gt;;
				qcom,supply-min-voltage = &lt;0x1b7740&gt;;
			};
		};

clocks {

sleep-clk {
				clock-output-names = &quot;chip_sleep_clk&quot;;
				#clock-cells = &lt;0x01&gt;;
				clock-frequency = &lt;0x7d00&gt;;
				compatible = &quot;fixed-clock&quot;;
				phandle = &lt;0x2b1&gt;;
			};
		};

stm@6002000 {
			arm,primecell-periphid = &lt;0x3b962&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;stm-base\0stm-stimulus-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-stm&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6002000 0x1000 0x16280000 0x180000&gt;;
			phandle = &lt;0x444&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x225&gt;;
					phandle = &lt;0x1e2&gt;;
				};
			};
		};

i2c@0xa94000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x18f&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			interrupts = &lt;0x00 0x166 0x00&gt;;
			clocks = &lt;0x27 0x61 0x27 0x69 0x27 0x6a&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,i2c-geni&quot;;
			pinctrl-1 = &lt;0x190&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0xa94000 0x4000&gt;;
			phandle = &lt;0x360&gt;;
			dmas = &lt;0x183 0x00 0x05 0x03 0x40 0x00 0x183 0x01 0x05 0x03 0x40 0x00&gt;;
		};

qcom,msm-dai-cdc-dma {
			compatible = &quot;qcom,msm-dai-cdc-dma&quot;;
			phandle = &lt;0x495&gt;;

qcom,msm-dai-va-cdc-dma-0-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb021&gt;;
				phandle = &lt;0x496&gt;;
			};

qcom,msm-dai-rx-cdc-dma-6-rx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb03c&gt;;
				phandle = &lt;0x2a1&gt;;
			};

qcom,msm-dai-rx-cdc-dma-3-rx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb036&gt;;
				phandle = &lt;0x29b&gt;;
			};

qcom,msm-dai-rx-cdc-dma-0-rx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb030&gt;;
				phandle = &lt;0x295&gt;;
			};

qcom,msm-dai-wsa-cdc-dma-0-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb001&gt;;
				phandle = &lt;0x291&gt;;
			};

qcom,msm-dai-wsa-cdc-dma-0-rx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb000&gt;;
				phandle = &lt;0x290&gt;;
			};

qcom,msm-dai-tx-cdc-dma-5-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb03b&gt;;
				phandle = &lt;0x2a0&gt;;
			};

qcom,msm-dai-tx-cdc-dma-2-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb035&gt;;
				phandle = &lt;0x29a&gt;;
			};

qcom,msm-dai-va-cdc-dma-2-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb025&gt;;
				phandle = &lt;0x498&gt;;
			};

qcom,msm-dai-rx-cdc-dma-5-rx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb03a&gt;;
				phandle = &lt;0x29f&gt;;
			};

qcom,msm-dai-rx-cdc-dma-2-rx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb034&gt;;
				phandle = &lt;0x299&gt;;
			};

qcom,msm-dai-wsa-cdc-dma-2-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb005&gt;;
				phandle = &lt;0x294&gt;;
			};

qcom,msm-dai-tx-cdc-dma-4-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb039&gt;;
				phandle = &lt;0x29e&gt;;
			};

qcom,msm-dai-tx-cdc-dma-1-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb033&gt;;
				phandle = &lt;0x298&gt;;
			};

qcom,msm-dai-va-cdc-dma-1-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb023&gt;;
				phandle = &lt;0x497&gt;;
			};

qcom,msm-dai-rx-cdc-dma-7-rx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb03e&gt;;
				phandle = &lt;0x2a2&gt;;
			};

qcom,msm-dai-rx-cdc-dma-4-rx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb038&gt;;
				phandle = &lt;0x29d&gt;;
			};

qcom,msm-dai-rx-cdc-dma-1-rx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb032&gt;;
				phandle = &lt;0x297&gt;;
			};

qcom,msm-dai-wsa-cdc-dma-1-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb003&gt;;
				phandle = &lt;0x293&gt;;
			};

qcom,msm-dai-wsa-cdc-dma-1-rx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb002&gt;;
				phandle = &lt;0x292&gt;;
			};

qcom,msm-dai-tx-cdc-dma-3-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb037&gt;;
				phandle = &lt;0x29c&gt;;
			};

qcom,msm-dai-tx-cdc-dma-0-tx {
				compatible = &quot;qcom,msm-dai-cdc-dma-dev&quot;;
				qcom,msm-dai-cdc-dma-dev-id = &lt;0xb031&gt;;
				phandle = &lt;0x296&gt;;
			};
		};

qcom,msm-pcm-routing {
			compatible = &quot;qcom,msm-pcm-routing&quot;;
			phandle = &lt;0x268&gt;;
		};

tx_core_clk {
			qcom,codec-ext-clk-src = &lt;0x07&gt;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,audio-ref-clk&quot;;
			phandle = &lt;0x4e0&gt;;
			qcom,codec-lpass-clk-id = &lt;0x30c&gt;;
			qcom,codec-lpass-ext-clk-freq = &lt;0x124f800&gt;;
		};

cti@78e0000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-apss_cti0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x78e0000 0x1000&gt;;
			phandle = &lt;0x45e&gt;;
		};

qcom,sps {
			qcom,pipe-attr-ee;
			compatible = &quot;qcom,msm-sps-4k&quot;;
		};

tpdm@6006000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-qdss&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6006000 0x1000&gt;;
			phandle = &lt;0x44a&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x23d&gt;;
					phandle = &lt;0x23c&gt;;
				};
			};
		};

cti@601a000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti10&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x601a000 0x1000&gt;;
			phandle = &lt;0x47f&gt;;
		};

cti@6a11000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-ddr_dl_1_cti1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6a11000 0x1000&gt;;
			phandle = &lt;0x464&gt;;
		};

qcom,dsi-display@1 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x523&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_sw43404_amoled_cmd_display&quot;;
			phandle = &lt;0x540&gt;;
		};

smcinvoke@86d00000 {
			reg-names = &quot;secapp-region&quot;;
			compatible = &quot;qcom,smcinvoke&quot;;
			reg = &lt;0x86d00000 0x3e00000&gt;;
			phandle = &lt;0x2db&gt;;
		};

qcom,npu@0x9800000 {
			memory-region = &lt;0xb6&gt;;
			qcom,pas-id = &lt;0x17&gt;;
			compatible = &quot;qcom,pil-tz-generic&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x9800000 0x800000&gt;;
			qcom,firmware-name = &quot;npu&quot;;
		};

cti@6c13000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-titan&quot;;
			compatible = &quot;arm,primecell&quot;;
			status = &quot;disabled&quot;;
			reg = &lt;0x6c13000 0x1000&gt;;
			phandle = &lt;0x474&gt;;
		};

qcom,dsi-display@13 {
			qcom,dsi-phy-num = &lt;0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk1\0mux_pixel_clk1&quot;;
			qcom,dsi-panel = &lt;0x52f&gt;;
			qcom,dsi-ctrl-num = &lt;0x01&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_nt35695b_truly_fhd_video_display&quot;;
			phandle = &lt;0x54c&gt;;
		};

qcom,msm-dai-tdm-quat-rx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9030&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9130&gt;;
			phandle = &lt;0x4c0&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-quat-rx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9030&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x28c&gt;;
			};
		};

rpmh-regulator-ldoc2 {
			qcom,mode-threshold-currents = &lt;0x00 0x2710&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoc2&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150l-l2 {
				regulator-max-microvolt = &lt;0x14a140&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x124f80&gt;;
				regulator-min-microvolt = &lt;0x124f80&gt;;
				regulator-name = &quot;pm6150l_l2&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x32&gt;;
			};
		};

qcom,cam-lrme {
			compatible = &quot;qcom,cam-lrme&quot;;
			status = &quot;ok&quot;;
			arch-compat = &quot;lrme&quot;;
		};

qcom,gdsc@17d038 {
			qcom,no-status-check-on-disable;
			qcom,gds-timeout = &lt;0x1f4&gt;;
			regulator-name = &quot;hlos1_vote_aggre_noc_mmu_tbu2_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x17d038 0x04&gt;;
			phandle = &lt;0x1c7&gt;;
		};

qcom,msm-eud@88e0000 {
			clock-names = &quot;eud_ahb2phy_clk&quot;;
			reg-names = &quot;eud_base\0eud_mode_mgr2&quot;;
			interrupts = &lt;0x00 0x1ec 0x04&gt;;
			clocks = &lt;0x27 0x97&gt;;
			qcom,secure-eud-en;
			compatible = &quot;qcom,msm-eud&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;eud_irq&quot;;
			reg = &lt;0x88e0000 0x2000 0x88e4000 0x1000&gt;;
			phandle = &lt;0x25c&gt;;
			qcom,eud-clock-vote-req;
		};

qcom,mdss_dsi_g7b_37_02_0b_dsc_video {
			qcom,mdss-pan-physical-width-dimension = &lt;0x46&gt;;
			qcom,mdss-dsi-panel-name = &quot;xiaomi 37 02 0b video mode dsc dsi panel&quot;;
			qcom,mdss-pan-physical-height-dimension = &lt;0x9a&gt;;
			qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
			qcom,mdss-dsi-underflow-color = &lt;0x00&gt;;
			qcom,mdss-dsi-t-clk-post = &lt;0x0e&gt;;
			qcom,mdss-dsi-lane-2-state;
			qcom,mdss-dsi-bllp-eof-power-mode;
			qcom,mdss-dsi-panel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-pan-enable-smart-fps;
			qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
			qcom,mdss-dsi-panel-max-luminance = &lt;0x0f 0x20&gt;;
			qcom,bl-update-flag = &quot;delay_until_first_frame&quot;;
			qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
			qcom,mdss-dsi-panel-xy-coordinate = &lt;0x0f 0x18&gt;;
			qcom,mdss-dsi-qsync-min-refresh-rate = &lt;0x3c&gt;;
			qcom,mdss-dsi-panel-max-luminance-valid = &lt;0x01 0x01&gt;;
			qcom,dispparam-enabled;
			qcom,mdss-dsi-panel-peak-brightness = &lt;0x401640&gt;;
			qcom,mdss-dsi-lane-3-state;
			qcom,mdss-dsi-pan-fps-update = &quot;dfps_immediate_porch_mode_vfp&quot;;
			qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
			qcom,mdss-dsi-pan-enable-dynamic-fps;
			qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-reset-sequence = &lt;0x01 0x05 0x00 0x01 0x01 0x0a&gt;;
			qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
			qcom,is-tddi-flag;
			qcom,mdss-dsi-lane-0-state;
			qcom,dsi-supported-dfps-list = &lt;0x78 0x5a 0x3c 0x32 0x1e&gt;;
			qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
			qcom,mdss-panel-on-dimming-delay = &lt;0xc8&gt;;
			qcom,mdss-dsi-t-clk-pre = &lt;0x34&gt;;
			qcom,mdss-dsi-panel-hdr-enabled;
			qcom,cont-splash-enabled;
			qcom,mdss-dsi-panel-model = &quot;xiaomi 37 02 0a VIDEO PANEL&quot;;
			phandle = &lt;0x53d&gt;;
			qcom,mdss-dsi-bllp-power-mode;
			qcom,mdss-dsi-stream = &lt;0x00&gt;;
			qcom,mdss-dsi-lp11-init;
			qcom,mdss-dsi-tx-eot-append;
			qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
			qcom,mdss-dsi-border-color = &lt;0x00&gt;;
			qcom,mdss-dsi-lane-1-state;
			qcom,esd-err-irq-gpio = &lt;0x174 0x20 0x2002&gt;;
			qcom,mdss-dsi-bpp = &lt;0x18&gt;;
			qcom,disp-panel-offon-mode-enabled;
			qcom,mdss-brightness-max-level = &lt;0xfff&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
					qcom,mdss-dsi-dispparam-cabcstillon-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
					qcom,display-topology = &lt;0x01 0x01 0x01&gt;;
					qcom,mdss-dsi-panel-framerate = &lt;0x78&gt;;
					qcom,mdss-dsi-h-pulse-width = &lt;0x0c&gt;;
					qcom,mdss-dsi-dispparam-xy-coordinate-command = [15 01 00 00 00 00 02 ff 10 06 01 00 01 05 00 02 a1 00];
					qcom,mdss-dsi-read-lockdown-info-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command = [39 01 00 00 00 00 03 51 0d b5];
					qcom,mdss-dsi-dispparam-xy-coordinate-command-state = &quot;dsi_hs_mode&quot;;
					qcom,compression-mode = &quot;dsc&quot;;
					qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-cabcmovieon-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-displayoff-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingoff-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingon-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-lcd-hbm-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-cabcmovieon-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 03];
					qcom,mdss-dsi-panel-height = &lt;0x960&gt;;
					qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
					qcom,mdss-dsi-panel-xy-coordinate = &lt;0x0f 0x18&gt;;
					qcom,mdss-dsc-block-prediction-enable;
					qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 23 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 00 80 15 00 00 00 00 00 02 01 84 15 00 00 00 00 00 02 05 2d 15 00 00 00 00 00 02 06 00 15 00 00 00 00 00 02 07 00 15 00 00 00 00 00 02 08 01 15 00 00 00 00 00 02 09 45 15 00 00 00 00 00 02 11 01 15 00 00 00 00 00 02 12 95 15 00 00 00 00 00 02 15 68 15 00 00 00 00 00 02 16 0b 15 00 00 00 00 00 02 29 0a 15 00 00 00 00 00 02 30 ff 15 00 00 00 00 00 02 31 fe 15 00 00 00 00 00 02 32 fd 15 00 00 00 00 00 02 33 fb 15 00 00 00 00 00 02 34 f8 15 00 00 00 00 00 02 35 f5 15 00 00 00 00 00 02 36 f3 15 00 00 00 00 00 02 37 f2 15 00 00 00 00 00 02 38 f2 15 00 00 00 00 00 02 39 f2 15 00 00 00 00 00 02 3a ef 15 00 00 00 00 00 02 3b ec 15 00 00 00 00 00 02 3d e9 15 00 00 00 00 00 02 3f e5 15 00 00 00 00 00 02 40 e5 15 00 00 00 00 00 02 41 e5 15 00 00 00 00 00 02 2a 13 15 00 00 00 00 00 02 45 ff 15 00 00 00 00 00 02 46 f4 15 00 00 00 00 00 02 47 e7 15 00 00 00 00 00 02 48 da 15 00 00 00 00 00 02 49 cd 15 00 00 00 00 00 02 4a c0 15 00 00 00 00 00 02 4b b3 15 00 00 00 00 00 02 4c b2 15 00 00 00 00 00 02 4d b2 15 00 00 00 00 00 02 4e b2 15 00 00 00 00 00 02 4f 99 15 00 00 00 00 00 02 50 80 15 00 00 00 00 00 02 51 68 15 00 00 00 00 00 02 52 66 15 00 00 00 00 00 02 53 66 15 00 00 00 00 00 02 54 66 15 00 00 00 00 00 02 2b 0e 15 00 00 00 00 00 02 58 ff 15 00 00 00 00 00 02 59 fb 15 00 00 00 00 00 02 5a f7 15 00 00 00 00 00 02 5b f3 15 00 00 00 00 00 02 5c ef 15 00 00 00 00 00 02 5d e3 15 00 00 00 00 00 02 5e da 15 00 00 00 00 00 02 5f d8 15 00 00 00 00 00 02 60 d8 15 00 00 00 00 00 02 61 d8 15 00 00 00 00 00 02 62 cb 15 00 00 00 00 00 02 63 bf 15 00 00 00 00 00 02 64 b3 15 00 00 00 00 00 02 65 b2 15 00 00 00 00 00 02 66 b2 15 01 00 00 00 00 02 67 b2 15 01 00 00 00 00 02 ff 26 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 81 0e 15 01 00 00 00 00 02 88 0c 15 01 00 00 00 00 02 ff e0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 35 82 15 00 00 00 00 00 02 4e 02 15 01 00 00 00 00 02 ff f0 15 00 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 ff d0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 09 af 15 01 00 00 00 00 02 ff c0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 9c 11 15 00 00 00 00 00 02 9d 11 15 01 00 00 00 00 02 ff f0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 9c 00 15 01 00 00 00 00 02 ff 10 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 b0 00 39 00 00 00 00 00 03 51 0b 6c 15 01 00 00 00 00 02 53 24 15 01 00 00 46 00 02 11 00 15 01 00 00 00 00 02 29 00 15 01 00 00 00 00 02 ff 27 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 3f 01 15 00 00 00 00 00 02 43 08 15 00 00 00 00 00 02 40 25 15 01 00 00 00 00 02 ff 10];
					qcom,mdss-dsi-h-front-porch = &lt;0x28&gt;;
					qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
					qcom,mdss-dsi-h-back-porch = &lt;0x28&gt;;
					qcom,mdss-dsi-dispparam-cabcstillon-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 02];
					qcom,mdss-dsi-dispparam-cabcuion-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 01];
					qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command = [39 01 00 00 00 00 03 51 0e 8c];
					qcom,mdss-dsi-dispparam-lcd-hbm-off-command = [39 01 00 00 00 00 03 51 0b 6c];
					qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
					qcom,mdss-dsc-slice-height = &lt;0x14&gt;;
					qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
					qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
					qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
					qcom,mdss-dsi-dispparam-cabcoff-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00];
					qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 24];
					qcom,mdss-dsi-panel-phy-timings = &lt;0x1c0707 0x23210707 0x5020400&gt;;
					qcom,mdss-dsi-v-back-porch = &lt;0x1e&gt;;
					qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,default-topology-index = &lt;0x00&gt;;
					qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
					qcom,mdss-dsc-slice-per-pkt = &lt;0x02&gt;;
					qcom,mdss-dsi-h-sync-pulse = &lt;0x01&gt;;
					qcom,mdss-dsc-scr-version = &lt;0x00&gt;;
					qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 27 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 3f 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 28 00 15 01 00 00 46 00 02 10 00];
					qcom,mdss-dsi-displayon-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-dispparam-cabcuion-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
					qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c];
					qcom,mdss-dsi-v-front-porch = &lt;0x20&gt;;
					qcom,mdss-dsi-displayoff-command = [15 01 00 00 20 00 02 28 00];
					qcom,mdss-dsi-displayon-command = [15 01 00 00 14 00 02 29 00];
					qcom,mdss-dsi-read-lockdown-info-command = [15 01 00 00 00 00 02 ff 21 06 01 00 00 00 00 01 f1];
					qcom,mdss-dsi-dispparam-cabcoff-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsc-version = &lt;0x11&gt;;
				};
			};
		};

qcom,camera-flash@2 {
			cell-index = &lt;0x02&gt;;
			torch-source = &lt;0x2f6&gt;;
			switch-source = &lt;0x2fb&gt;;
			compatible = &quot;qcom,camera-flash&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x02 0x00&gt;;
			phandle = &lt;0x567&gt;;
			flash-source = &lt;0x2f3&gt;;
		};

qcom,cam-isp {
			compatible = &quot;qcom,cam-isp&quot;;
			status = &quot;ok&quot;;
			arch-compat = &quot;ife&quot;;
		};

rpmh-regulator-ldoa18 {
			compatible = &quot;qcom,rpmh-xob-regulator&quot;;
			qcom,resource-name = &quot;ldoa18&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm6150-l18 {
				regulator-max-microvolt = &lt;0x2dc6c0&gt;;
				regulator-min-microvolt = &lt;0x2dc6c0&gt;;
				regulator-name = &quot;pm6150_l18&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x40c&gt;;
			};
		};

qcom,mdss_dsi_phy0@ae94400 {
			qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00];
			reg-names = &quot;dsi_phy\0dyn_refresh_base&quot;;
			cell-index = &lt;0x00&gt;;
			label = &quot;dsi-phy-0&quot;;
			qcom,platform-lane-config = &lt;0x00 0x00 0x00 0x00 0x80&gt;;
			compatible = &quot;qcom,dsi-phy-v3.0&quot;;
			vdda-0p9-supply = &lt;0x1a9&gt;;
			qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
			reg = &lt;0xae94400 0x7c0 0xae94200 0x100&gt;;
			phandle = &lt;0x374&gt;;

qcom,phy-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

qcom,cam-icp {
			icp_pc_en;
			num-bps = &lt;0x01&gt;;
			num-ipe = &lt;0x02&gt;;
			num-a5 = &lt;0x01&gt;;
			compat-hw-name = &quot;qcom,a5\0qcom,ipe0\0qcom,ipe1\0qcom,bps&quot;;
			compatible = &quot;qcom,cam-icp&quot;;
			status = &quot;ok&quot;;
		};

qcom,csiphy@ace2000 {
			clock-names = &quot;cphy_rx_clk_src\0csiphy0_clk\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk&quot;;
			reg-names = &quot;csiphy&quot;;
			reg-cam-base = &lt;0xe2000&gt;;
			csi-vdd-voltage = &lt;0x124f80&gt;;
			cell-index = &lt;0x01&gt;;
			interrupts = &lt;0x00 0x1de 0x00&gt;;
			clocks = &lt;0x29 0x1b 0x29 0x24 0x29 0x25 0x29 0x1f 0x29 0x1e&gt;;
			gdscr-supply = &lt;0x1ae&gt;;
			clock-cntl-level = &quot;svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,csiphy-v1.2\0qcom,csiphy&quot;;
			src-clock-name = &quot;csi1phytimer_clk_src&quot;;
			mipi-csi-vdd-supply = &lt;0x1a8&gt;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;csiphy&quot;;
			reg = &lt;0xace2000 0x2000&gt;;
			regulator-names = &quot;gdscr\0refgen&quot;;
			phandle = &lt;0x379&gt;;
			refgen-supply = &lt;0x1af&gt;;
			clock-rates = &lt;0x16e36000 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00&gt;;
		};

tpdm@78b0000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-llm-gold&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x78b0000 0x1000&gt;;
			phandle = &lt;0x43a&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x213&gt;;
					phandle = &lt;0x212&gt;;
				};
			};
		};

tpdm@69e1000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk\0npu_core_apb_clk\0npu_core_atb_clk\0npu_core_clk\0npu_core_clk_src\0npu_core_cti_clk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00 0x2c 0x0c 0x2c 0x0d 0x2c 0x0e 0x2c 0x0f 0x2c 0x10&gt;;
			coresight-name = &quot;coresight-tpdm-npu&quot;;
			vdd-supply = &lt;0x23&gt;;
			compatible = &quot;arm,primecell&quot;;
			qcom,tpdm-regs = &quot;vdd\0vdd_cx&quot;;
			reg = &lt;0x69e1000 0x1000&gt;;
			phandle = &lt;0x486&gt;;
			vdd_cx-supply = &lt;0x1d&gt;;
			qcom,tpdm-clks = &quot;npu_core_apb_clk\0npu_core_atb_clk\0npu_core_clk\0npu_core_clk_src\0npu_core_cti_clk&quot;;

port {

endpoint {
					remote-endpoint = &lt;0x258&gt;;
					phandle = &lt;0x23a&gt;;
				};
			};
		};

qcom,cpu0-llcc-ddr-latmon {
			qcom,cachemiss-ev = &lt;0x1000&gt;;
			qcom,core-dev-table = &lt;0xbb800 0x478 0xf8700 0x6b8 0x130b00 0x826 0x16d7a8 0xb71 0x1b8a00 0xf27&gt;;
			qcom,cpulist = &lt;0x11 0x12 0x13 0x14 0x15 0x16&gt;;
			compatible = &quot;qcom,arm-memlat-mon&quot;;
			phandle = &lt;0x317&gt;;
			qcom,target-dev = &lt;0xc3&gt;;
		};

tpdm@6b48000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-north&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b48000 0x1000&gt;;
			phandle = &lt;0x459&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x254&gt;;
					phandle = &lt;0x237&gt;;
				};
			};
		};

system_pm {
			compatible = &quot;qcom,system-pm&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
		};

cpuss_dump {
			compatible = &quot;qcom,cpuss-dump&quot;;

qcom,l2_tlb_dump400 {
				qcom,dump-node = &lt;0x4d&gt;;
				qcom,dump-id = &lt;0x124&gt;;
			};

qcom,l2_tlb_dump0 {
				qcom,dump-node = &lt;0x49&gt;;
				qcom,dump-id = &lt;0x120&gt;;
			};

qcom,l1_d_cache100 {
				qcom,dump-node = &lt;0x3e&gt;;
				qcom,dump-id = &lt;0x81&gt;;
			};

qcom,l2_tlb_dump700 {
				qcom,dump-node = &lt;0x50&gt;;
				qcom,dump-id = &lt;0x127&gt;;
			};

qcom,llcc2_d_cache {
				qcom,dump-node = &lt;0x52&gt;;
				qcom,dump-id = &lt;0x141&gt;;
			};

qcom,l1_d_cache400 {
				qcom,dump-node = &lt;0x41&gt;;
				qcom,dump-id = &lt;0x84&gt;;
			};

qcom,l1_i_cache100 {
				qcom,dump-node = &lt;0x36&gt;;
				qcom,dump-id = &lt;0x61&gt;;
			};

qcom,l1_d_tlb_dump600 {
				qcom,dump-node = &lt;0x47&gt;;
				qcom,dump-id = &lt;0x46&gt;;
			};

qcom,l1_d_cache700 {
				qcom,dump-node = &lt;0x44&gt;;
				qcom,dump-id = &lt;0x87&gt;;
			};

qcom,l1_i_cache400 {
				qcom,dump-node = &lt;0x39&gt;;
				qcom,dump-id = &lt;0x64&gt;;
			};

qcom,l2_tlb_dump300 {
				qcom,dump-node = &lt;0x4c&gt;;
				qcom,dump-id = &lt;0x123&gt;;
			};

qcom,l1_i_tlb_dump700 {
				qcom,dump-node = &lt;0x46&gt;;
				qcom,dump-id = &lt;0x27&gt;;
			};

qcom,l1_i_cache700 {
				qcom,dump-node = &lt;0x3c&gt;;
				qcom,dump-id = &lt;0x67&gt;;
			};

qcom,l2_tlb_dump600 {
				qcom,dump-node = &lt;0x4f&gt;;
				qcom,dump-id = &lt;0x126&gt;;
			};

qcom,l1_d_cache0 {
				qcom,dump-node = &lt;0x3d&gt;;
				qcom,dump-id = &lt;0x80&gt;;
			};

qcom,l2_cache_dump700 {
				qcom,dump-node = &lt;0x10&gt;;
				qcom,dump-id = &lt;0xc7&gt;;
			};

qcom,l1_d_cache300 {
				qcom,dump-node = &lt;0x40&gt;;
				qcom,dump-id = &lt;0x83&gt;;
			};

qcom,llcc1_d_cache {
				qcom,dump-node = &lt;0x51&gt;;
				qcom,dump-id = &lt;0x140&gt;;
			};

qcom,l1_d_cache600 {
				qcom,dump-node = &lt;0x43&gt;;
				qcom,dump-id = &lt;0x86&gt;;
			};

qcom,l1_i_cache300 {
				qcom,dump-node = &lt;0x38&gt;;
				qcom,dump-id = &lt;0x63&gt;;
			};

qcom,l2_tlb_dump200 {
				qcom,dump-node = &lt;0x4b&gt;;
				qcom,dump-id = &lt;0x122&gt;;
			};

qcom,l1_i_tlb_dump600 {
				qcom,dump-node = &lt;0x45&gt;;
				qcom,dump-id = &lt;0x26&gt;;
			};

qcom,l1_i_cache600 {
				qcom,dump-node = &lt;0x3b&gt;;
				qcom,dump-id = &lt;0x66&gt;;
			};

qcom,l2_tlb_dump500 {
				qcom,dump-node = &lt;0x4e&gt;;
				qcom,dump-id = &lt;0x125&gt;;
			};

qcom,l1_i_cache0 {
				qcom,dump-node = &lt;0x35&gt;;
				qcom,dump-id = &lt;0x60&gt;;
			};

qcom,l2_cache_dump600 {
				qcom,dump-node = &lt;0x0e&gt;;
				qcom,dump-id = &lt;0xc6&gt;;
			};

qcom,l1_d_cache200 {
				qcom,dump-node = &lt;0x3f&gt;;
				qcom,dump-id = &lt;0x82&gt;;
			};

qcom,l1_d_cache500 {
				qcom,dump-node = &lt;0x42&gt;;
				qcom,dump-id = &lt;0x85&gt;;
			};

qcom,l1_i_cache200 {
				qcom,dump-node = &lt;0x37&gt;;
				qcom,dump-id = &lt;0x62&gt;;
			};

qcom,l2_tlb_dump100 {
				qcom,dump-node = &lt;0x4a&gt;;
				qcom,dump-id = &lt;0x121&gt;;
			};

qcom,l1_d_tlb_dump700 {
				qcom,dump-node = &lt;0x48&gt;;
				qcom,dump-id = &lt;0x47&gt;;
			};

qcom,l1_i_cache500 {
				qcom,dump-node = &lt;0x3a&gt;;
				qcom,dump-id = &lt;0x65&gt;;
			};
		};

cti@69C2000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-dlmm_cti1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x69c2000 0x1000&gt;;
			phandle = &lt;0x467&gt;;
		};

cti@6a03000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-ddr_dl_0_cti1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6a03000 0x1000&gt;;
			phandle = &lt;0x462&gt;;
		};

tpdm@6b02000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-swao-0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b02000 0x1000&gt;;
			phandle = &lt;0x42f&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x1fe&gt;;
					phandle = &lt;0x1fc&gt;;
				};
			};
		};

llcc-bw-opp-table {
			compatible = &quot;operating-points-v2&quot;;
			phandle = &lt;0xbc&gt;;

opp-300 {
				opp-hz = &lt;0x00 0x11e1&gt;;
			};

opp-600 {
				opp-hz = &lt;0x00 0x23c3&gt;;
			};

opp-806 {
				opp-hz = &lt;0x00 0x300a&gt;;
			};

opp-466 {
				opp-hz = &lt;0x00 0x1bc6&gt;;
			};

opp-933 {
				opp-hz = &lt;0x00 0x379c&gt;;
			};
		};

qcom,msm-pcm-dtmf {
			compatible = &quot;qcom,msm-pcm-dtmf&quot;;
			phandle = &lt;0x490&gt;;
		};

qcom,gpi-dma@0x800000 {
			iommus = &lt;0x30 0x216 0x00&gt;;
			qcom,gpii-mask = &lt;0x0f&gt;;
			qcom,smmu-cfg = &lt;0x01&gt;;
			reg-names = &quot;gpi-top&quot;;
			interrupts = &lt;0x00 0xf4 0x00 0x00 0xf5 0x00 0x00 0xf6 0x00 0x00 0xf7 0x00 0x00 0xf8 0x00 0x00 0xf9 0x00 0x00 0xfa 0x00 0x00 0xfb 0x00&gt;;
			qcom,ev-factor = &lt;0x02&gt;;
			qcom,iova-range = &lt;0x00 0x100000 0x00 0x100000&gt;;
			compatible = &quot;qcom,gpi-dma&quot;;
			status = &quot;ok&quot;;
			qcom,max-num-gpii = &lt;0x08&gt;;
			reg = &lt;0x800000 0x60000&gt;;
			phandle = &lt;0x165&gt;;
			#dma-cells = &lt;0x05&gt;;
		};

rpmh-regulator-ldoa2 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa2&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l2 {
				regulator-max-microvolt = &lt;0x101d00&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0xe6780&gt;;
				regulator-min-microvolt = &lt;0xe6780&gt;;
				regulator-name = &quot;pm6150_l2&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x403&gt;;
			};
		};

msm_cdc_pinctrl@29 {
			pinctrl-names = &quot;aud_active\0aud_sleep&quot;;
			pinctrl-0 = &lt;0x509&gt;;
			compatible = &quot;qcom,msm-cdc-pinctrl&quot;;
			qcom,lpi-gpios;
			pinctrl-1 = &lt;0x50a&gt;;
			status = &quot;disabled&quot;;
			phandle = &lt;0x510&gt;;
		};

mem_dump {
			memory-region = &lt;0x53&gt;;
			compatible = &quot;qcom,mem-dump&quot;;

tmc_etf {
				qcom,dump-size = &lt;0x10000&gt;;
				qcom,dump-id = &lt;0xf0&gt;;
			};

fcm {
				qcom,dump-size = &lt;0x8400&gt;;
				qcom,dump-id = &lt;0xee&gt;;
			};

etf_reg {
				qcom,dump-size = &lt;0x1000&gt;;
				qcom,dump-id = &lt;0x101&gt;;
			};

rpm_sw {
				qcom,dump-size = &lt;0x28000&gt;;
				qcom,dump-id = &lt;0xea&gt;;
			};

etfswao_reg {
				qcom,dump-size = &lt;0x1000&gt;;
				qcom,dump-id = &lt;0x102&gt;;
			};

etr_reg {
				qcom,dump-size = &lt;0x1000&gt;;
				qcom,dump-id = &lt;0x100&gt;;
			};

pmic {
				qcom,dump-size = &lt;0x10000&gt;;
				qcom,dump-id = &lt;0xe4&gt;;
			};

etf_swao {
				qcom,dump-size = &lt;0x8400&gt;;
				qcom,dump-id = &lt;0xf1&gt;;
			};

misc_data {
				qcom,dump-size = &lt;0x1000&gt;;
				qcom,dump-id = &lt;0xe8&gt;;
			};

rpmh {
				qcom,dump-size = &lt;0x2000000&gt;;
				qcom,dump-id = &lt;0xec&gt;;
			};
		};

qcom,msm-pcm {
			qcom,msm-pcm-dsp-id = &lt;0x00&gt;;
			compatible = &quot;qcom,msm-pcm-dsp&quot;;
			phandle = &lt;0x25e&gt;;
		};

qcom,dsi-display {
			vdda-3p3-supply = &lt;0x40c&gt;;
			pinctrl-names = &quot;panel_active\0panel_suspend&quot;;
			qcom,panel-te-source = &lt;0x00&gt;;
			pinctrl-0 = &lt;0x3c6 0x2ed&gt;;
			clock-names = &quot;mux_byte_clk0\0mux_pixel_clk0\0mux_byte_clk1\0mux_pixel_clk1\0src_byte_clk0\0src_pixel_clk0\0shadow_byte_clk0\0shadow_pixel_clk0&quot;;
			clocks = &lt;0x36a 0x06 0x36a 0x09 0x36b 0x20 0x36b 0x23 0x36a 0x03 0x36a 0x08 0x36a 0x11 0x36a 0x15&gt;;
			qcom,dsi-display-list = &lt;0x53f 0x540 0x541 0x542 0x543 0x544 0x545 0x546 0x547 0x548 0x549 0x54a 0x54b 0x54c 0x54d 0x54e 0x54f 0x550 0x551 0x552 0x553 0x554 0x555 0x556 0x557 0x557 0x558 0x559 0x55a 0x55b&gt;;
			qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
			ibb-supply = &lt;0x2f0&gt;;
			qcom,dsi-phy = &lt;0x374 0x375&gt;;
			compatible = &quot;qcom,dsi-display&quot;;
			vddio-supply = &lt;0x408&gt;;
			pinctrl-1 = &lt;0x3c7&gt;;
			lab-supply = &lt;0x2ef&gt;;
			phandle = &lt;0x55f&gt;;
			qcom,dsi-ctrl = &lt;0x372 0x373&gt;;
			qcom,platform-te-gpio = &lt;0x174 0x0a 0x00&gt;;
		};

qcom,msm-sec-auxpcm {
			qcom,msm-cpudai-auxpcm-quant = &lt;0x02 0x02&gt;;
			qcom,msm-cpudai-auxpcm-frame = &lt;0x05 0x04&gt;;
			qcom,msm-cpudai-auxpcm-sync = &lt;0x01 0x01&gt;;
			qcom,msm-auxpcm-interface = &quot;secondary&quot;;
			qcom,msm-cpudai-auxpcm-slot-mapping = &lt;0x01 0x01&gt;;
			qcom,msm-cpudai-auxpcm-data = &lt;0x00 0x00&gt;;
			qcom,msm-cpudai-afe-clk-ver = &lt;0x02&gt;;
			qcom,msm-cpudai-auxpcm-num-slots = &lt;0x01 0x01&gt;;
			compatible = &quot;qcom,msm-auxpcm-dev&quot;;
			qcom,msm-cpudai-auxpcm-mode = &lt;0x00 0x00&gt;;
			phandle = &lt;0x272&gt;;
			qcom,msm-cpudai-auxpcm-pcm-clk-rate = &lt;0x1f4000 0x1f4000&gt;;
		};

qcom,dsi-display@21 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x535&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_g7b_42_02_0b_video_display&quot;;
			phandle = &lt;0x554&gt;;
		};

funnel@6943000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			qcom,proxy-regs = &quot;vddcx\0vdd&quot;;
			vddcx-supply = &lt;0x1c5&gt;;
			clock-names = &quot;apb_pclk\0gpu_apb_clk&quot;;
			reg-names = &quot;funnel-base&quot;;
			qcom,proxy-clks = &quot;gpu_apb_clk&quot;;
			clocks = &lt;0x19 0x00 0x2b 0x08&gt;;
			coresight-name = &quot;coresight-funnel-gfx&quot;;
			vdd-supply = &lt;0x24e&gt;;
			compatible = &quot;arm,primecell&quot;;
			status = &quot;disabled&quot;;
			reg = &lt;0x6943000 0x1000&gt;;
			regulator-names = &quot;vddcx\0vdd&quot;;
			phandle = &lt;0x455&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x24f&gt;;
						phandle = &lt;0x234&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x250&gt;;
						phandle = &lt;0x251&gt;;
					};
				};
			};
		};

tpdm@6850000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-pimem&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6850000 0x1000&gt;;
			phandle = &lt;0x45b&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x256&gt;;
					phandle = &lt;0x239&gt;;
				};
			};
		};

qcom,gdsc@ad0b004 {
			qcom,poll-cfg-gdscr;
			clock-names = &quot;ahb_clk&quot;;
			clocks = &lt;0x27 0x0e&gt;;
			regulator-name = &quot;ife_1_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xad0b004 0x04&gt;;
			phandle = &lt;0x1b8&gt;;
		};

msm_cdc_pinctrl_pri {
			pinctrl-names = &quot;aud_active\0aud_sleep&quot;;
			pinctrl-0 = &lt;0x514 0x515 0x516 0x517&gt;;
			compatible = &quot;qcom,msm-cdc-pinctrl&quot;;
			pinctrl-1 = &lt;0x518 0x519 0x51a 0x51b&gt;;
			phandle = &lt;0x513&gt;;
		};

cti@7900000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-apss_cti2&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7900000 0x1000&gt;;
			phandle = &lt;0x460&gt;;
		};

spi@0x890000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x17e&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			interrupts = &lt;0x00 0x25d 0x00&gt;;
			clocks = &lt;0x27 0x4c 0x27 0x67 0x27 0x68&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x168&gt;;
			spi-max-frequency = &lt;0x2faf080&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,spi-geni&quot;;
			pinctrl-1 = &lt;0x17f&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0x890000 0x4000&gt;;
			phandle = &lt;0x357&gt;;
			dmas = &lt;0x165 0x00 0x04 0x01 0x40 0x00 0x165 0x01 0x04 0x01 0x40 0x00&gt;;
		};

i2c@0xa80000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x184&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			interrupts = &lt;0x00 0x161 0x00&gt;;
			clocks = &lt;0x27 0x57 0x27 0x69 0x27 0x6a&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,i2c-geni&quot;;
			pinctrl-1 = &lt;0x185&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0xa80000 0x4000&gt;;
			phandle = &lt;0x35a&gt;;
			dmas = &lt;0x183 0x00 0x00 0x03 0x40 0x00 0x183 0x01 0x00 0x03 0x40 0x00&gt;;
		};

qcom,mdss_rotator@ae00000 {
			power-domains = &lt;0x1a6&gt;;
			qcom,mdss-rot-mode = &lt;0x01&gt;;
			rot-vdd-supply = &lt;0xcb&gt;;
			qcom,mdss-rot-safe-lut = &lt;0xffff 0xffff&gt;;
			clock-names = &quot;gcc_iface\0gcc_bus\0iface_clk\0rot_clk&quot;;
			reg-names = &quot;mdp_phys\0rot_vbif_phys&quot;;
			qcom,msm-bus,name = &quot;mdss_rotator&quot;;
			interrupts = &lt;0x02 0x00&gt;;
			clocks = &lt;0x27 0x1c 0x27 0x20 0x2a 0x01 0x2a 0x22&gt;;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x03&gt;;
			interrupt-parent = &lt;0x1a6&gt;;
			qcom,mdss-rot-vbif-memtype = &lt;0x03 0x03&gt;;
			qcom,mdss-sbuf-headroom = &lt;0x14&gt;;
			qcom,mdss-rot-qos-cpu-dma-latency = &lt;0x4b&gt;;
			qcom,mdss-highest-bank-bit = &lt;0x01&gt;;
			qcom,mdss-rot-vbif-qos-setting = &lt;0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03&gt;;
			compatible = &quot;qcom,sde_rotator&quot;;
			qcom,mdss-rot-cdp-setting = &lt;0x01 0x01&gt;;
			qcom,mdss-rot-danger-lut = &lt;0x00 0x00&gt;;
			qcom,mdss-default-ot-rd-limit = &lt;0x20&gt;;
			qcom,supply-names = &quot;rot-vdd&quot;;
			qcom,mdss-rot-qos-lut = &lt;0x00 0x00 0x00 0x00&gt;;
			qcom,mdss-default-ot-wr-limit = &lt;0x20&gt;;
			reg = &lt;0xae00000 0xac000 0xaeb8000 0x3000&gt;;
			#list-cells = &lt;0x01&gt;;
			phandle = &lt;0x36e&gt;;
			qcom,mdss-rot-qos-cpu-mask = &lt;0x0f&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x19 0x200 0x00 0x00 0x19 0x200 0x00 0x61a800 0x19 0x200 0x00 0x61a800&gt;;
			cache-slices = &lt;0x1a7 0x04&gt;;
			cache-slice-names = &quot;rotator&quot;;

qcom,smmu_rot_unsec_cb {
				iommus = &lt;0x30 0x1020 0x00&gt;;
				compatible = &quot;qcom,smmu_sde_rot_unsec&quot;;
				phandle = &lt;0x370&gt;;
			};

qcom,rot-reg-bus {
				qcom,msm-bus,name = &quot;mdss_rot_reg&quot;;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x02&gt;;
				phandle = &lt;0x36f&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00&gt;;
			};

qcom,smmu_rot_sec_cb {
				iommus = &lt;0x30 0x1021 0x00&gt;;
				compatible = &quot;qcom,smmu_sde_rot_sec&quot;;
				phandle = &lt;0x371&gt;;
			};
		};

qcom,msm-dai-q6-meta-mi2s-prim {
			qcom,msm-dai-q6-meta-mi2s-dev-id = &lt;0x1300&gt;;
			qcom,msm-mi2s-rx-lines = &lt;0xff 0x0f 0x03 0x03&gt;;
			qcom,msm-mi2s-member-id = &lt;0x00 0x01 0x02 0x03&gt;;
			qcom,msm-mi2s-num-members = &lt;0x04&gt;;
			compatible = &quot;qcom,msm-dai-q6-meta-mi2s&quot;;
			phandle = &lt;0x493&gt;;
		};

maxim_ds28e16 {
			label = &quot;max_ds28e16&quot;;
			compatible = &quot;maxim,ds28e16&quot;;
			maxim,version = &lt;0x01&gt;;
			status = &quot;ok&quot;;
			phandle = &lt;0x5b2&gt;;
		};

cti@6017000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti7&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6017000 0x1000&gt;;
			phandle = &lt;0x47c&gt;;
		};

qcom,cpu6-llcc-ddr-lat {
			qcom,src-dst-ports = &lt;0x81 0x200&gt;;
			governor = &quot;performance&quot;;
			compatible = &quot;qcom,devbw&quot;;
			phandle = &lt;0xc4&gt;;
			qcom,active-only;
			operating-points-v2 = &lt;0xbe&gt;;
		};

cti@6b21000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-aop-m3&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b21000 0x1000&gt;;
			phandle = &lt;0x473&gt;;
		};

qcom,dsi-display@11 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x52d&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_rm69298_truly_amoled_vid_display&quot;;
			phandle = &lt;0x54a&gt;;
		};

qcom,msm-dai-mi2s {
			compatible = &quot;qcom,msm-dai-mi2s&quot;;
			phandle = &lt;0x491&gt;;

qcom,msm-dai-q6-mi2s-prim {
				qcom,msm-dai-q6-mi2s-dev-id = &lt;0x00&gt;;
				qcom,msm-mi2s-rx-lines = &lt;0x01&gt;;
				qcom,msm-mi2s-tx-lines = &lt;0x02&gt;;
				compatible = &quot;qcom,msm-dai-q6-mi2s&quot;;
				phandle = &lt;0x26c&gt;;
			};

qcom,msm-dai-q6-mi2s-quin {
				qcom,msm-dai-q6-mi2s-dev-id = &lt;0x04&gt;;
				qcom,msm-mi2s-rx-lines = &lt;0x01&gt;;
				qcom,msm-mi2s-tx-lines = &lt;0x02&gt;;
				compatible = &quot;qcom,msm-dai-q6-mi2s&quot;;
				phandle = &lt;0x270&gt;;
			};

qcom,msm-dai-q6-mi2s-senary {
				qcom,msm-dai-q6-mi2s-dev-id = &lt;0x06&gt;;
				qcom,msm-mi2s-rx-lines = &lt;0x00&gt;;
				qcom,msm-mi2s-tx-lines = &lt;0x03&gt;;
				compatible = &quot;qcom,msm-dai-q6-mi2s&quot;;
				phandle = &lt;0x492&gt;;
			};

qcom,msm-dai-q6-mi2s-quat {
				qcom,msm-dai-q6-mi2s-dev-id = &lt;0x03&gt;;
				qcom,msm-mi2s-rx-lines = &lt;0x01&gt;;
				qcom,msm-mi2s-tx-lines = &lt;0x02&gt;;
				compatible = &quot;qcom,msm-dai-q6-mi2s&quot;;
				phandle = &lt;0x26f&gt;;
			};

qcom,msm-dai-q6-mi2s-tert {
				qcom,msm-dai-q6-mi2s-dev-id = &lt;0x02&gt;;
				qcom,msm-mi2s-rx-lines = &lt;0x00&gt;;
				qcom,msm-mi2s-tx-lines = &lt;0x03&gt;;
				compatible = &quot;qcom,msm-dai-q6-mi2s&quot;;
				phandle = &lt;0x26e&gt;;
			};

qcom,msm-dai-q6-mi2s-sec {
				qcom,msm-dai-q6-mi2s-dev-id = &lt;0x01&gt;;
				qcom,msm-mi2s-rx-lines = &lt;0x01&gt;;
				qcom,msm-mi2s-tx-lines = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-mi2s&quot;;
				phandle = &lt;0x26d&gt;;
			};
		};

gpio_keys {
			pinctrl-names = &quot;default&quot;;
			pinctrl-0 = &lt;0x561&gt;;
			label = &quot;gpio-keys&quot;;
			compatible = &quot;gpio-keys&quot;;

vol_up {
				linux,can-disable;
				label = &quot;volume_up&quot;;
				linux,input-type = &lt;0x01&gt;;
				gpio-key,wakeup;
				linux,code = &lt;0x73&gt;;
				debounce-interval = &lt;0x0f&gt;;
				gpios = &lt;0x2ec 0x02 0x01&gt;;
			};
		};

modem_etm0 {
			qcom,inst-id = &lt;0x02&gt;;
			coresight-name = &quot;coresight-modem-etm0&quot;;
			compatible = &quot;qcom,coresight-remote-etm&quot;;

port {

endpoint {
					remote-endpoint = &lt;0x1f1&gt;;
					phandle = &lt;0x1e5&gt;;
				};
			};
		};

qcom,lpm-levels {
			#address-cells = &lt;0x01&gt;;
			#size-cells = &lt;0x00&gt;;
			compatible = &quot;qcom,lpm-levels&quot;;

qcom,pm-cluster@0 {
				qcom,psci-mode-mask = &lt;0xfff&gt;;
				#address-cells = &lt;0x01&gt;;
				qcom,clstr-tmr-add = &lt;0x3e8&gt;;
				#size-cells = &lt;0x00&gt;;
				label = &quot;L3&quot;;
				qcom,psci-mode-shift = &lt;0x04&gt;;
				reg = &lt;0x00&gt;;

qcom,pm-cluster-level@3 {
					qcom,exit-latency-us = &lt;0x19a2&gt;;
					qcom,psci-mode = &lt;0xc24&gt;;
					qcom,is-reset;
					label = &quot;llcc-off&quot;;
					qcom,notify-rpm;
					qcom,min-child-idx = &lt;0x02&gt;;
					qcom,min-residency-us = &lt;0x2662&gt;;
					reg = &lt;0x03&gt;;
					qcom,entry-latency-us = &lt;0xcbf&gt;;
				};

qcom,pm-cpu@1 {
					qcom,psci-mode-mask = &lt;0x0f&gt;;
					qcom,tmr-add = &lt;0x64&gt;;
					#address-cells = &lt;0x01&gt;;
					qcom,cpu = &lt;0x17 0x18&gt;;
					#size-cells = &lt;0x00&gt;;
					qcom,psci-mode-shift = &lt;0x00&gt;;
					qcom,ref-premature-cnt = &lt;0x03&gt;;
					qcom,ref-stddev = &lt;0x64&gt;;
					qcom,disable-ipi-prediction;

qcom,pm-cpu-level@2 {
						qcom,exit-latency-us = &lt;0x73e&gt;;
						qcom,is-reset;
						qcom,psci-cpu-mode = &lt;0x04&gt;;
						label = &quot;rail-pc&quot;;
						qcom,use-broadcast-timer;
						qcom,min-residency-us = &lt;0x15b3&gt;;
						reg = &lt;0x02&gt;;
						qcom,entry-latency-us = &lt;0x20e&gt;;
					};

qcom,pm-cpu-level@0 {
						qcom,exit-latency-us = &lt;0x42&gt;;
						qcom,psci-cpu-mode = &lt;0x01&gt;;
						label = &quot;wfi&quot;;
						qcom,min-residency-us = &lt;0x79&gt;;
						reg = &lt;0x00&gt;;
						qcom,entry-latency-us = &lt;0x37&gt;;
					};

qcom,pm-cpu-level@1 {
						qcom,exit-latency-us = &lt;0x4dc&gt;;
						qcom,is-reset;
						qcom,psci-cpu-mode = &lt;0x03&gt;;
						label = &quot;pc&quot;;
						qcom,use-broadcast-timer;
						qcom,min-residency-us = &lt;0x89f&gt;;
						reg = &lt;0x01&gt;;
						qcom,entry-latency-us = &lt;0x20b&gt;;
					};
				};

qcom,pm-cluster-level@1 {
					qcom,exit-latency-us = &lt;0xbe8&gt;;
					qcom,psci-mode = &lt;0x04&gt;;
					qcom,is-reset;
					label = &quot;l3-pc&quot;;
					qcom,min-child-idx = &lt;0x02&gt;;
					qcom,min-residency-us = &lt;0x17e6&gt;;
					reg = &lt;0x01&gt;;
					qcom,entry-latency-us = &lt;0xac0&gt;;
				};

qcom,pm-cluster-level@2 {
					qcom,exit-latency-us = &lt;0x11d2&gt;;
					qcom,psci-mode = &lt;0x224&gt;;
					qcom,is-reset;
					label = &quot;cx-off&quot;;
					qcom,notify-rpm;
					qcom,min-child-idx = &lt;0x02&gt;;
					qcom,min-residency-us = &lt;0x2113&gt;;
					reg = &lt;0x02&gt;;
					qcom,entry-latency-us = &lt;0xe36&gt;;
				};

qcom,pm-cpu@0 {
					qcom,psci-mode-mask = &lt;0x0f&gt;;
					qcom,tmr-add = &lt;0x3e8&gt;;
					#address-cells = &lt;0x01&gt;;
					qcom,cpu = &lt;0x11 0x12 0x13 0x14 0x15 0x16&gt;;
					#size-cells = &lt;0x00&gt;;
					qcom,psci-mode-shift = &lt;0x00&gt;;
					qcom,ref-premature-cnt = &lt;0x01&gt;;
					qcom,ref-stddev = &lt;0x1f4&gt;;
					qcom,disable-ipi-prediction;

qcom,pm-cpu-level@2 {
						qcom,exit-latency-us = &lt;0x393&gt;;
						qcom,is-reset;
						qcom,psci-cpu-mode = &lt;0x04&gt;;
						label = &quot;rail-pc&quot;;
						qcom,use-broadcast-timer;
						qcom,min-residency-us = &lt;0xfa1&gt;;
						reg = &lt;0x02&gt;;
						qcom,entry-latency-us = &lt;0x2be&gt;;
					};

qcom,pm-cpu-level@0 {
						qcom,exit-latency-us = &lt;0x3c&gt;;
						qcom,psci-cpu-mode = &lt;0x01&gt;;
						label = &quot;wfi&quot;;
						qcom,min-residency-us = &lt;0x79&gt;;
						reg = &lt;0x00&gt;;
						qcom,entry-latency-us = &lt;0x3d&gt;;
					};

qcom,pm-cpu-level@1 {
						qcom,exit-latency-us = &lt;0x385&gt;;
						qcom,is-reset;
						qcom,psci-cpu-mode = &lt;0x03&gt;;
						label = &quot;pc&quot;;
						qcom,use-broadcast-timer;
						qcom,min-residency-us = &lt;0x6ee&gt;;
						reg = &lt;0x01&gt;;
						qcom,entry-latency-us = &lt;0x225&gt;;
					};
				};

qcom,pm-cluster-level@0 {
					qcom,exit-latency-us = &lt;0x258&gt;;
					qcom,psci-mode = &lt;0x01&gt;;
					label = &quot;l3-wfi&quot;;
					qcom,min-residency-us = &lt;0x4ec&gt;;
					reg = &lt;0x00&gt;;
					qcom,entry-latency-us = &lt;0x294&gt;;
				};
			};
		};

fingerprint_fortsense {
			fs,gpio-irq = &lt;0x174 0x39 0x00&gt;;
			fs,gpio-reset = &lt;0x174 0x3a 0x00&gt;;
			compatible = &quot;fs,fingerprint&quot;;
			status = &quot;ok&quot;;
			fs_vdd-supply = &lt;0x411&gt;;
		};

qcom,msm_fastrpc {
			qcom,fastrpc-adsp-audio-pdr;
			qcom,rpc-latency-us = &lt;0x263&gt;;
			compatible = &quot;qcom,msm-fastrpc-compute&quot;;
			qcom,fastrpc-adsp-sensors-pdr;
			qcom,adsp-remoteheap-vmid = &lt;0x16 0x25&gt;;

qcom,msm_fastrpc_compute_cb3 {
				iommus = &lt;0x30 0x1423 0x00 0x30 0x1443 0x00&gt;;
				dma-coherent;
				label = &quot;cdsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb1 {
				iommus = &lt;0x30 0x1421 0x00 0x30 0x1441 0x00&gt;;
				dma-coherent;
				label = &quot;cdsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb15 {
				iommus = &lt;0x30 0x1b28 0x00&gt;;
				dma-coherent;
				shared-cb = &lt;0x03&gt;;
				label = &quot;adsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb13 {
				iommus = &lt;0x30 0x1b26 0x00&gt;;
				dma-coherent;
				label = &quot;adsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb6 {
				iommus = &lt;0x30 0x1406 0x60&gt;;
				dma-coherent;
				label = &quot;cdsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb11 {
				iommus = &lt;0x30 0x1b24 0x00&gt;;
				dma-coherent;
				label = &quot;adsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb4 {
				iommus = &lt;0x30 0x1424 0x00 0x30 0x1444 0x00&gt;;
				dma-coherent;
				label = &quot;cdsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb2 {
				iommus = &lt;0x30 0x1422 0x00 0x30 0x1442 0x00&gt;;
				dma-coherent;
				label = &quot;cdsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb9 {
				iommus = &lt;0x30 0x1409 0x60&gt;;
				dma-coherent;
				qcom,secure-context-bank;
				label = &quot;cdsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb14 {
				iommus = &lt;0x30 0x1b27 0x00&gt;;
				dma-coherent;
				label = &quot;adsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb12 {
				iommus = &lt;0x30 0x1b25 0x00&gt;;
				dma-coherent;
				label = &quot;adsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb5 {
				iommus = &lt;0x30 0x1425 0x00 0x30 0x1445 0x00&gt;;
				dma-coherent;
				label = &quot;cdsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};

qcom,msm_fastrpc_compute_cb10 {
				iommus = &lt;0x30 0x1b23 0x00&gt;;
				dma-coherent;
				label = &quot;adsprpc-smd&quot;;
				compatible = &quot;qcom,msm-fastrpc-compute-cb&quot;;
			};
		};

qcom,camera-flash@0 {
			cell-index = &lt;0x00&gt;;
			torch-source = &lt;0x2f6&gt;;
			switch-source = &lt;0x2fb&gt;;
			compatible = &quot;qcom,camera-flash&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x00 0x00&gt;;
			phandle = &lt;0x57e&gt;;
			flash-source = &lt;0x2f3&gt;;
		};

ddr-bw-opp-table {
			compatible = &quot;operating-points-v2&quot;;
			phandle = &lt;0xbe&gt;;

opp-1017 {
				opp-hz = &lt;0x00 0xf27&gt;;
			};

opp-300 {
				opp-hz = &lt;0x00 0x478&gt;;
			};

opp-451 {
				opp-hz = &lt;0x00 0x6b8&gt;;
			};

opp-1353 {
				opp-hz = &lt;0x00 0x1429&gt;;
			};

opp-1804 {
				opp-hz = &lt;0x00 0x1ae1&gt;;
			};

opp-768 {
				opp-hz = &lt;0x00 0xb71&gt;;
			};

opp-200 {
				opp-hz = &lt;0x00 0x2fa&gt;;
			};

opp-681 {
				opp-hz = &lt;0x00 0xa25&gt;;
			};

opp-1555 {
				opp-hz = &lt;0x00 0x172b&gt;;
			};

opp-547 {
				opp-hz = &lt;0x00 0x826&gt;;
			};
		};

qcom,gpubw {
			qcom,src-dst-ports = &lt;0x1a 0x200&gt;;
			governor = &quot;bw_vbif&quot;;
			compatible = &quot;qcom,devbw&quot;;
			phandle = &lt;0x2a4&gt;;
			operating-points-v2 = &lt;0x2a3&gt;;
		};

replicator@604a000 {
			arm,primecell-periphid = &lt;0x3b909&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;replicator-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-replicator-qdss1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x604a000 0x1000&gt;;
			phandle = &lt;0x41e&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x01&gt;;

endpoint {
						remote-endpoint = &lt;0x1d3&gt;;
						phandle = &lt;0x1f9&gt;;
					};
				};

port@1 {
					reg = &lt;0x01&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1d4&gt;;
						phandle = &lt;0x1d1&gt;;
					};
				};
			};
		};

cti@6014000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti4&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6014000 0x1000&gt;;
			phandle = &lt;0x479&gt;;
		};

rx_npl_clk {
			qcom,codec-ext-clk-src = &lt;0x06&gt;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,audio-ref-clk&quot;;
			phandle = &lt;0x4e4&gt;;
			qcom,codec-lpass-clk-id = &lt;0x30f&gt;;
			qcom,codec-lpass-ext-clk-freq = &lt;0x1588800&gt;;
		};

tpdm@69d0000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-qm&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x69d0000 0x1000&gt;;
			phandle = &lt;0x45a&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x255&gt;;
					phandle = &lt;0x238&gt;;
				};
			};
		};

rpmh-regulator-ldoa16 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa16&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l16 {
				regulator-max-microvolt = &lt;0x2d6900&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x1b7740&gt;;
				regulator-min-microvolt = &lt;0x1b7740&gt;;
				regulator-name = &quot;pm6150_l16&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x40b&gt;;
			};
		};

ipa_smmu_ap {
			iommus = &lt;0x30 0x520 0x00&gt;;
			qcom,smmu-s1-bypass;
			qcom,additional-mapping = &lt;0x146a8000 0x146a8000 0x2000&gt;;
			qcom,iova-mapping = &lt;0x20000000 0x40000000&gt;;
			compatible = &quot;qcom,ipa-smmu-ap-cb&quot;;
			phandle = &lt;0x31c&gt;;
		};

etm@7340000 {
			arm,primecell-periphid = &lt;0xbb95d&gt;;
			clock-names = &quot;apb_pclk&quot;;
			clocks = &lt;0x19 0x00&gt;;
			cpu = &lt;0x14&gt;;
			qcom,tupwr-disable;
			coresight-name = &quot;coresight-etm3&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7340000 0x1000&gt;;
			phandle = &lt;0x43f&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x220&gt;;
					phandle = &lt;0x218&gt;;
				};
			};
		};

qcom,battery-data {
			qcom,batt-id-range-pct = &lt;0x0f&gt;;
			phandle = &lt;0x58e&gt;;

qcom,04890898_xiaomi_K6_SWBN53_5020mah_FG {
				qcom,max-voltage-uv = &lt;0x43e6d0&gt;;
				mi,six-pin-battery;
				qcom,battery-type = &quot;K6_sunwoda_5020mah&quot;;
				qcom,jeita-fcc-ranges = &lt;0x00 0x32 0xef420 0x33 0x64 0x258960 0x65 0x96 0x347d80 0x97 0x1e0 0x5b8d80 0x1e1 0x258 0x258960&gt;;
				qcom,nom-batt-capacity-mah = &lt;0x139c&gt;;
				mi,step-chg-hysteresis = &lt;0x1388&gt;;
				mi,use-bq-pump;
				qcom,qg-batt-profile-ver = &lt;0x64&gt;;
				qcom,fastchg-current-ma = &lt;0x1770&gt;;
				qcom,jeita-fv-ranges = &lt;0x00 0x32 0x43e6d0 0x33 0x64 0x43e6d0 0x65 0x96 0x43e6d0 0x97 0x1e0 0x4434f0 0x1e1 0x258 0x3e8fa0&gt;;
				qcom,ffc-max-voltage-uv = &lt;0x4434f0&gt;;
				qcom,step-chg-ranges = &lt;0x2dcaa8 0x40d990 0x5b8d80 0x40d991 0x426030 0x4ac4a0 0x426031 0x43e6d0 0x4ac4a0 0x43e6d1 0x440de0 0x3b8260 0x440de1 0x4434f0 0x3b8260&gt;;
				qcom,battery-therm-kohm = &lt;0x64&gt;;
				qcom,batt-id-kohm = &lt;0x64&gt;;
				qcom,battery-beta = &lt;0x109a&gt;;
				qcom,fg-cc-cv-threshold-uv = &lt;0x43bfc0&gt;;

qcom,pc-temp-z2-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x2b8b 0x283a 0x2a3d 0x28a3 0x281a 0x2a9d 0x2a1c 0x2a52 0x290d 0x28dc 0x29ea 0x2a32 0x2a59 0x2955 0x28b8 0x2991 0x2a18 0x2a4e 0x2970 0x289b 0x295b 0x29f9 0x2a1f 0x2957 0x2892 0x2932 0x29cc 0x29eb 0x292d 0x2883 0x2910 0x299d 0x29b6 0x290c 0x2879 0x28f3 0x297c 0x2984 0x28ed 0x2868 0x28e4 0x2960 0x295f 0x28d5 0x2859 0x28de 0x2954 0x2940 0x28c4 0x2855 0x28da 0x2955 0x2935 0x28b6 0x2852 0x28dc 0x2957 0x294b 0x28aa 0x2838 0x28ed 0x2960 0x296c 0x28a0 0x27d9 0x2905 0x298d 0x297e 0x2895 0x27a0 0x2924 0x29bc 0x298a 0x287c 0x27a4 0x294e 0x29d3 0x2998 0x2866 0x27ac 0x2976 0x29e6 0x29ad 0x2858 0x27b8 0x299f 0x29f9 0x29c5 0x2836 0x27d1 0x29c2 0x2a13 0x29da 0x2830 0x27ed 0x29db 0x2a24 0x29ed 0x2848 0x280a 0x29ef 0x2a24 0x2a06 0x2871 0x2828 0x29f8 0x2a20 0x2a3a 0x28dd 0x284b 0x29e9 0x2a18 0x2a6d 0x299a 0x2871 0x29cc 0x29f9 0x2a62 0x29d2 0x2895 0x29c0 0x29d9 0x2a1b 0x295b 0x28b0 0x29bd 0x29e1 0x29f4 0x28e9 0x28cc 0x29bb 0x2a10 0x2a44 0x2942 0x28fb 0x29c0 0x2a38 0x2aaf 0x2a21 0x293b 0x29d2 0x2a4f 0x2ab9 0x2a60 0x294c 0x29e3 0x2a5f 0x2a9a 0x29d2 0x28b4 0x29f0 0x2a5d 0x2a74 0x2936 0x2802 0x29fb 0x2a47 0x2a3a 0x28f6 0x27cc 0x2a05 0x2a35 0x2a03 0x28ca 0x27a7 0x2a0d 0x2a32 0x29fd 0x28b4 0x27a3 0x2a16 0x2a30 0x2a09 0x28c1 0x27d2 0x2a22 0x2a32 0x2a1b 0x28df 0x2818 0x2a31 0x2a41 0x2a44 0x292b 0x285e 0x2a44 0x2a59 0x2a7f 0x29af 0x28ae 0x2a65 0x2a7b 0x2aba 0x2a02 0x28eb 0x2a8d 0x2aa9 0x2aff 0x2a40 0x2914 0x2ab4 0x2acb 0x2b25 0x2a6e 0x2943 0x2ada 0x2adc 0x2b2a 0x2a8a 0x29b1 0x2b24 0x2af6 0x2b2e 0x2a9b 0x2a24 0x2b9c 0x2b36 0x2b3a 0x2a91 0x2a38 0x2afb 0x2c81 0x2b74 0x2a1b 0x29be 0x2a46 0x2ce2 0x2b8c 0x297a 0x28e7 0x2a12 0x2d0e 0x2b57 0x2974 0x28d4 0x2a0c 0x2cff 0x2b49 0x2975 0x28f4 0x2a17 0x2d65 0x2b7d 0x2a06 0x298c 0x29d5 0x2df3 0x2bbb 0x29c7 0x2938 0x29ba 0x2e30 0x2b50 0x28ac 0x2810 0x290f 0x2da6 0x2ab5 0x285b 0x27cf 0x289e 0x2cf8 0x2a64 0x2812 0x27a2 0x27c5 0x2bd5 0x2a13 0x27f2 0x274e 0x27c5 0x2bd5 0x2a13 0x27f2 0x274e 0x27c5 0x2bd5 0x2a13 0x27f2 0x274e&gt;;
				};

qcom,pc-temp-z6-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x3c94 0x3a90 0x394b 0x38dc 0x38b6 0x3c90 0x3ad3 0x396b 0x38f4 0x38ce 0x3c84 0x3ad0 0x397c 0x3902 0x38dc 0x3c6f 0x3ab3 0x397a 0x3906 0x38e3 0x3c3e 0x3a95 0x396e 0x3902 0x38e1 0x3c06 0x3a79 0x3960 0x38fc 0x38dc 0x3bdc 0x3a5e 0x3955 0x38f6 0x38d8 0x3bb6 0x3a44 0x394b 0x38f1 0x38d4 0x3b94 0x3a2c 0x3940 0x38eb 0x38d0 0x3b75 0x3a17 0x3935 0x38e2 0x38ca 0x3b59 0x3a04 0x392b 0x38da 0x38c3 0x3b40 0x39f3 0x3921 0x38d3 0x38bd 0x3b2a 0x39e3 0x3917 0x38ce 0x38b9 0x3b15 0x39d3 0x3910 0x38c9 0x38b5 0x3aff 0x39c6 0x3909 0x38c4 0x38b1 0x3aea 0x39be 0x3903 0x38c0 0x38ad 0x3adb 0x39b7 0x38fd 0x38bb 0x38a9 0x3acf 0x39b3 0x38f8 0x38b6 0x38a5 0x3ac7 0x39b1 0x38f5 0x38b2 0x38a1 0x3ac4 0x39af 0x38f2 0x38af 0x389e 0x3ac2 0x39bc 0x38f1 0x38ad 0x389b 0x3ac1 0x39e0 0x390b 0x38b9 0x38a2 0x3ad5 0x39f1 0x392d 0x38d8 0x38bf 0x3af7 0x39f2 0x3931 0x38e3 0x38cc 0x3b01 0x39f3 0x3930 0x38e2 0x38cb 0x3afd 0x39f1 0x392d 0x38e0 0x38c8 0x3af8 0x39ea 0x3929 0x38de 0x38c6 0x3af1 0x39e2 0x3925 0x38dc 0x38c5 0x3ae6 0x39dd 0x3921 0x38d9 0x38c3 0x3adc 0x39d8 0x391d 0x38d5 0x38be 0x3ad4 0x39d4 0x3919 0x38d0 0x38b7 0x3acd 0x39d0 0x3914 0x38ca 0x38b2 0x3ac7 0x39cd 0x3910 0x38c4 0x38ad 0x3ac3 0x39ca 0x390c 0x38bf 0x38a8 0x3abf 0x39c7 0x3909 0x38bc 0x38a4 0x3abc 0x39c6 0x3906 0x38ba 0x38a1 0x3ab9 0x39c4 0x3903 0x38b7 0x389f 0x3ab8 0x39c4 0x3901 0x38b4 0x389d 0x3aba 0x39c5 0x3901 0x38b4 0x389d 0x3abc 0x39c7 0x3906 0x38b8 0x38a0 0x3abc 0x39c7 0x3908 0x38bc 0x38a4 0x3aba 0x39c3 0x3906 0x38bd 0x38a7 0x3ab7 0x39be 0x3903 0x38be 0x38aa 0x3aaf 0x39b9 0x3900 0x38bd 0x38ab 0x3a77 0x399d 0x38f0 0x38b4 0x38a3 0x3a6c 0x398b 0x38df 0x38a2 0x3890 0x3a68 0x3984 0x38da 0x389c 0x388b 0x3a66 0x3981 0x38d1 0x3894 0x3880 0x3a69 0x397f 0x38cb 0x3889 0x3877 0x3a6e 0x3987 0x38d1 0x3896 0x3887 0x3a7a 0x3991 0x38e0 0x38a6 0x3898 0x3a83 0x3996 0x38e3 0x38aa 0x389c 0x3a8d 0x399e 0x38e7 0x38ae 0x38a0 0x3aa0 0x39a8 0x38ec 0x38b0 0x38a3 0x3aa0 0x39a8 0x38ec 0x38b0 0x38a3 0x3aa0 0x39a8 0x38ec 0x38b0 0x38a3&gt;;
				};

qcom,pc-temp-y2-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x2965 0x2a0e 0x2c86 0x2d4c 0x2bc0 0x2b78 0x2986 0x2a33 0x2c7b 0x2d10 0x2b86 0x2b44 0x29d5 0x2a77 0x2c6c 0x2cd0 0x2b4a 0x2b06 0x2a33 0x2ac3 0x2c5a 0x2c93 0x2b10 0x2ac7 0x2a83 0x2b02 0x2c46 0x2c5e 0x2add 0x2a91 0x2aa7 0x2b1d 0x2c2f 0x2c39 0x2ab5 0x2a6c 0x2aa7 0x2b1b 0x2c10 0x2c20 0x2a93 0x2a56 0x2aa7 0x2b16 0x2bf2 0x2c0d 0x2a78 0x2a44 0x2aa7 0x2b17 0x2be9 0x2bfa 0x2a6b 0x2a32 0x2aa9 0x2b24 0x2be5 0x2be5 0x2a64 0x2a19 0x2aad 0x2b31 0x2be4 0x2bda 0x2a5f 0x2a08 0x2acd 0x2b30 0x2bf2 0x2be1 0x2a5b 0x2a04 0x2b0e 0x2b28 0x2c12 0x2bf1 0x2a56 0x2a03 0x2b44 0x2b36 0x2c33 0x2c02 0x2a64 0x2a04 0x2b84 0x2b92 0x2c57 0x2c1b 0x2ab1 0x2a06 0x2bb3 0x2bec 0x2c82 0x2c3d 0x2aed 0x2a08 0x2bc0 0x2c1b 0x2cc7 0x2c72 0x2af9 0x2a0a 0x2bc9 0x2c51 0x2d11 0x2cbc 0x2b02 0x2a0d 0x2bd5 0x2c62 0x2d2d 0x2d19 0x2b37 0x2a34 0x2bee 0x2c6b 0x2d38 0x2da2 0x2bfe 0x2aee 0x2c0a 0x2c76 0x2d3d 0x2ded 0x2c7d 0x2b68 0x2c1f 0x2c82 0x2d42 0x2db6 0x2c4e 0x2b5e 0x2c31 0x2c93 0x2d4e 0x2d5f 0x2bfe 0x2b4e 0x2c35 0x2ca3 0x2d5a 0x2d53 0x2be5 0x2b4b 0x2c17 0x2cbb 0x2d72 0x2d77 0x2be3 0x2b4e 0x2be6 0x2cce 0x2d89 0x2d9f 0x2bf0 0x2b52 0x2b43 0x2cb8 0x2d98 0x2dbd 0x2c2e 0x2b69 0x29df 0x2c76 0x2da7 0x2ddb 0x2c85 0x2b97 0x291f 0x2c51 0x2dbe 0x2dfb 0x2ca2 0x2bd5 0x27cd 0x2c58 0x2de8 0x2e20 0x2c9e 0x2c42 0x266a 0x2c5d 0x2e03 0x2e40 0x2ca7 0x2c9f 0x2627 0x2c31 0x2ded 0x2e58 0x2d02 0x2cd8 0x260d 0x2bc0 0x2dc0 0x2e6a 0x2d79 0x2d04 0x25f9 0x2b30 0x2dac 0x2e72 0x2d97 0x2d1a 0x25e7 0x29e6 0x2da6 0x2e76 0x2d9b 0x2d38 0x25da 0x2886 0x2d9e 0x2e73 0x2d99 0x2d3c 0x25d3 0x27c1 0x2d79 0x2e44 0x2d31 0x2cef 0x25cf 0x2692 0x2d2d 0x2df6 0x2c93 0x2c77 0x25cb 0x25f4 0x2cde 0x2dd0 0x2c79 0x2c2f 0x25c8 0x25dd 0x2c89 0x2dbd 0x2c95 0x2bfe 0x25c6 0x25d0 0x2c27 0x2daa 0x2ca7 0x2bdb 0x25c4 0x25c9 0x2bac 0x2d90 0x2c8b 0x2bc8 0x25c3 0x25c5 0x2b21 0x2d6b 0x2c4e 0x2bb1 0x25c2 0x25c2 0x2a95 0x2d03 0x2ba6 0x2b3c 0x25c0 0x25c0 0x2a0f 0x2c8c 0x2afd 0x2a95 0x25bf 0x25bf 0x2a1a 0x2c48 0x2ae7 0x2a50 0x25be 0x25bf 0x2a13 0x2c37 0x2b28 0x2a58 0x25be 0x25be 0x29f2 0x2c32 0x2b4e 0x2a87 0x25bd 0x25bd 0x29e3 0x2c38 0x2b88 0x2a79 0x25bb 0x25bc 0x29d4 0x2c55 0x2afb 0x2a52 0x25ba 0x25bb 0x298e 0x2c23 0x2a7c 0x2a0b 0x25b8 0x25ba 0x28fb 0x2bb6 0x2a49 0x29d6 0x25b5 0x25b9 0x26dc 0x2b46 0x2a1d 0x297e 0x25b2 0x25b7 0x25fa 0x2ae6 0x299b 0x28ce 0x25b2 0x25b7 0x25fa 0x2ae6 0x299b 0x28ce 0x25b2 0x25b7 0x25fa 0x2ae6 0x299b 0x28ce&gt;;
				};

qcom,pc-temp-y6-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x15e9 0x1508 0x1416 0x1399 0x137a 0x1373 0x15f5 0x151c 0x1421 0x139a 0x137b 0x1374 0x1604 0x1530 0x142b 0x139b 0x137c 0x1376 0x1613 0x1542 0x1433 0x139d 0x137d 0x1377 0x161e 0x154e 0x1438 0x139e 0x137e 0x1378 0x1623 0x1553 0x143a 0x139f 0x1380 0x1379 0x1622 0x1550 0x1438 0x13a0 0x1381 0x137a 0x161f 0x154a 0x1434 0x13a1 0x1382 0x137a 0x161c 0x1543 0x1431 0x13a2 0x1383 0x137b 0x1617 0x153c 0x142f 0x13a4 0x1384 0x137c 0x1614 0x1538 0x142e 0x13a5 0x1385 0x137d 0x1616 0x1539 0x142f 0x13a7 0x1387 0x137e 0x1619 0x153c 0x142f 0x13a9 0x1388 0x137f 0x161d 0x153f 0x1430 0x13ac 0x138a 0x1381 0x1623 0x1542 0x1433 0x13af 0x138c 0x1382 0x1627 0x1544 0x1436 0x13b3 0x138f 0x1384 0x1615 0x1543 0x143e 0x13b7 0x1392 0x1386 0x15ea 0x153f 0x1447 0x13bc 0x1394 0x1389 0x15d5 0x1537 0x1447 0x13c1 0x1399 0x138d 0x15cd 0x1518 0x1437 0x13c8 0x13a1 0x1394 0x15c6 0x14f7 0x1424 0x13cc 0x13a6 0x1398 0x15be 0x14e4 0x1414 0x13bd 0x139a 0x138e 0x15b5 0x14d5 0x1405 0x13a5 0x1387 0x137f 0x15ad 0x14ca 0x13fe 0x139c 0x1380 0x1379 0x15a4 0x14c3 0x13fa 0x1399 0x137e 0x1377 0x159e 0x14bc 0x13f8 0x1398 0x137d 0x1376 0x159d 0x14b2 0x13f8 0x1399 0x137d 0x1377 0x15a0 0x14a8 0x13f8 0x139b 0x137f 0x1378 0x15a4 0x14a4 0x13f9 0x139d 0x1381 0x1379 0x15b4 0x14a9 0x13fa 0x139f 0x1383 0x137b 0x15cd 0x14b2 0x13fa 0x13a1 0x1386 0x137e 0x15e5 0x14c0 0x13f9 0x13a3 0x1389 0x1381 0x1600 0x14db 0x13f8 0x13a5 0x138c 0x1384 0x161f 0x14fa 0x13f7 0x13a7 0x138d 0x1384 0x1641 0x151e 0x13f7 0x13a9 0x138c 0x1384 0x1667 0x1547 0x13f7 0x13aa 0x138b 0x1383 0x168e 0x1574 0x13fc 0x13a5 0x1387 0x1380 0x16b9 0x15a5 0x1407 0x139e 0x1381 0x137c 0x16e2 0x15d7 0x1411 0x139b 0x1381 0x137b 0x1707 0x1609 0x141c 0x139b 0x1381 0x137d 0x172c 0x163c 0x1428 0x139b 0x1381 0x137e 0x1755 0x166f 0x1437 0x139c 0x1382 0x137e 0x1780 0x16a4 0x144a 0x139e 0x1382 0x137c 0x17b6 0x16e3 0x1461 0x139d 0x137d 0x1375 0x17fc 0x1731 0x147f 0x13a0 0x137e 0x1376 0x184c 0x1784 0x147e 0x13a6 0x138b 0x1388 0x1842 0x175f 0x1485 0x13ae 0x1396 0x1394 0x1880 0x1799 0x149f 0x13b8 0x13a0 0x139d 0x18cf 0x17d6 0x14bb 0x13c3 0x13a6 0x139d 0x1931 0x1812 0x14cd 0x13be 0x138c 0x1382 0x19b6 0x1850 0x14d6 0x13aa 0x1386 0x1380 0x1a95 0x1896 0x14fb 0x13af 0x138a 0x1383 0x1cfb 0x1923 0x155a 0x13b7 0x1390 0x1388 0x2413 0x1a28 0x1602 0x13c9 0x139f 0x139e 0x2413 0x1a28 0x1602 0x13c9 0x139f 0x139e 0x2413 0x1a28 0x1602 0x13c9 0x139f 0x139e&gt;;
				};

qcom,pc-temp-z3-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x4c4f 0x4bcc 0x4b8c 0x4b7d 0x4b7d 0x4c97 0x4c14 0x4bbb 0x4b91 0x4b87 0x4cd1 0x4c3b 0x4bde 0x4bae 0x4b9e 0x4cf6 0x4c56 0x4bef 0x4bc2 0x4bb4 0x4d11 0x4c6a 0x4bfa 0x4bcc 0x4bbd 0x4d25 0x4c7b 0x4c01 0x4bd4 0x4bc3 0x4d34 0x4c86 0x4c08 0x4bdc 0x4bca 0x4d41 0x4c87 0x4c0d 0x4be4 0x4bd1 0x4d48 0x4c86 0x4c0d 0x4be7 0x4bd4 0x4d4d 0x4c84 0x4c0c 0x4be4 0x4bd3 0x4d51 0x4c81 0x4c0a 0x4bde 0x4bcf 0x4d50 0x4c7b 0x4c03 0x4bd8 0x4bcb 0x4d4b 0x4c74 0x4bfa 0x4bd0 0x4bc4 0x4d44 0x4c69 0x4bf1 0x4bc9 0x4bbe 0x4d3b 0x4c5f 0x4be8 0x4bc4 0x4bba 0x4d2f 0x4c5a 0x4be1 0x4bc0 0x4bb6 0x4d25 0x4c56 0x4bdd 0x4bbc 0x4bb3 0x4d1d 0x4c51 0x4bda 0x4bb8 0x4bb0 0x4d15 0x4c48 0x4bd7 0x4bb4 0x4bad 0x4d10 0x4c42 0x4bd3 0x4baf 0x4ba8 0x4d0c 0x4c50 0x4bd1 0x4bac 0x4ba4 0x4d0a 0x4c79 0x4be0 0x4bae 0x4ba3 0x4d19 0x4c89 0x4bf4 0x4bb3 0x4ba4 0x4d32 0x4c76 0x4bf0 0x4bb4 0x4ba4 0x4d38 0x4c5a 0x4bd3 0x4ba3 0x4b9f 0x4d2d 0x4c4a 0x4bc3 0x4b93 0x4b99 0x4d1e 0x4c3d 0x4bc3 0x4ba6 0x4ba6 0x4d12 0x4c37 0x4bc3 0x4bd4 0x4bd0 0x4d05 0x4c3e 0x4bca 0x4be4 0x4be2 0x4cfe 0x4c4a 0x4be4 0x4be2 0x4bd8 0x4cfb 0x4c54 0x4bf4 0x4bde 0x4bca 0x4cf9 0x4c5e 0x4bf5 0x4bd7 0x4bc1 0x4cf7 0x4c64 0x4bf5 0x4bcb 0x4bba 0x4cf5 0x4c61 0x4bf2 0x4bc0 0x4bb2 0x4cf2 0x4c5c 0x4beb 0x4bb8 0x4ba9 0x4cee 0x4c58 0x4be4 0x4bb1 0x4ba1 0x4ce9 0x4c54 0x4bdc 0x4bad 0x4b9e 0x4ce3 0x4c50 0x4bd5 0x4ba9 0x4b9b 0x4cdb 0x4c4b 0x4bd3 0x4ba7 0x4b9a 0x4cd1 0x4c44 0x4bd1 0x4ba6 0x4b99 0x4cc7 0x4c3d 0x4bd1 0x4ba5 0x4b99 0x4cbc 0x4c38 0x4bd2 0x4bae 0x4ba3 0x4cab 0x4c31 0x4bd2 0x4bb9 0x4bb3 0x4c8c 0x4c26 0x4bcd 0x4bb7 0x4bb4 0x4b90 0x4bf6 0x4bb8 0x4bab 0x4ba9 0x4b69 0x4be0 0x4bae 0x4b90 0x4b90 0x4b62 0x4bd2 0x4bad 0x4b8e 0x4b8c 0x4b5f 0x4bd2 0x4ba2 0x4b8c 0x4b82 0x4b5e 0x4ba7 0x4b9b 0x4b7d 0x4b7a 0x4b5d 0x4bb7 0x4b95 0x4b8d 0x4b86 0x4b61 0x4b6a 0x4b9c 0x4ba4 0x4ba0 0x4b61 0x4b65 0x4b92 0x4ba7 0x4ba0 0x4b63 0x4b61 0x4b8f 0x4ba9 0x4ba2 0x4b68 0x4b5a 0x4b90 0x4b9d 0x4ba0 0x4b68 0x4b5a 0x4b90 0x4b9d 0x4ba0 0x4b68 0x4b5a 0x4b90 0x4b9d 0x4ba0&gt;;
				};

qcom,pc-temp-v1-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0xac5b 0xacdf 0xad2f 0xad4b 0xad54 0xab9b 0xac29 0xac88 0xacac 0xacb6 0xaad0 0xab6b 0xabd6 0xabfe 0xac0a 0xa9fb 0xaaa6 0xab1a 0xab46 0xab53 0xa919 0xa9d6 0xaa54 0xaa83 0xaa93 0xa82f 0xa8f2 0xa981 0xa9b4 0xa9c7 0xa743 0xa804 0xa89c 0xa8d6 0xa8ed 0xa652 0xa715 0xa7ad 0xa7e8 0xa804 0xa563 0xa621 0xa6bc 0xa6f7 0xa713 0xa476 0xa52f 0xa5c6 0xa602 0xa620 0xa38e 0xa441 0xa4d2 0xa50d 0xa52a 0xa2ab 0xa355 0xa3df 0xa41b 0xa438 0xa1cd 0xa26f 0xa2f1 0xa32c 0xa348 0xa0f6 0xa18d 0xa208 0xa241 0xa25c 0xa029 0xa0b1 0xa125 0xa159 0xa174 0x9f63 0x9fe1 0xa049 0xa077 0xa091 0x9e98 0x9f17 0x9f73 0x9f9c 0x9fb5 0x9dc2 0x9e50 0x9ea3 0x9ec9 0x9edf 0x9cf1 0x9d94 0x9dde 0x9dfe 0x9e11 0x9c36 0x9cca 0x9d26 0x9d42 0x9d52 0x9b90 0x9bc7 0x9c55 0x9c7e 0x9c92 0x9ada 0x9a96 0x9b33 0x9b84 0x9ba4 0x99e5 0x99a9 0x9a0b 0x9a63 0x9a88 0x98e1 0x9904 0x994c 0x9987 0x99a2 0x9836 0x987e 0x98c2 0x98ee 0x9904 0x97c9 0x980f 0x9846 0x986a 0x987e 0x9773 0x97b2 0x97d1 0x97e7 0x97f6 0x9728 0x975b 0x9764 0x976b 0x9773 0x96e9 0x9705 0x96fc 0x96fa 0x96fe 0x96ad 0x96b2 0x9697 0x9693 0x9699 0x9671 0x9664 0x963b 0x9635 0x963c 0x9638 0x961a 0x95e9 0x95e1 0x95e4 0x9604 0x95d7 0x959e 0x9595 0x9591 0x95d3 0x959f 0x955a 0x954c 0x9541 0x95a6 0x956e 0x951c 0x9505 0x94f4 0x957c 0x953d 0x94e3 0x94bf 0x94a8 0x9555 0x9511 0x94af 0x947e 0x945b 0x9521 0x94df 0x947b 0x943d 0x940d 0x94d0 0x9492 0x9431 0x93eb 0x93b2 0x9469 0x942a 0x93c9 0x937f 0x9343 0x93f5 0x93b5 0x9353 0x9305 0x92c5 0x9369 0x932d 0x92d2 0x927d 0x9235 0x92cb 0x9295 0x9245 0x91ea 0x919a 0x921c 0x91e1 0x91a0 0x914b 0x90fa 0x91be 0x915f 0x9121 0x90d5 0x9092 0x9167 0x9116 0x90d6 0x9097 0x9056 0x9146 0x9103 0x90c1 0x9082 0x9041 0x9128 0x90e9 0x90b2 0x9071 0x9032 0x9103 0x90cb 0x9094 0x904e 0x9001 0x9098 0x9041 0x9015 0x8f96 0x8f2b 0x8f45 0x8ecb 0x8ead 0x8e1e 0x8dab 0x8d62 0x8cdb 0x8cce 0x8c32 0x8bbd 0x8afe 0x8a5c 0x8a64 0x89b7 0x893d 0x87c0 0x86ec 0x8717 0x8651 0x85cc 0x829f 0x8159 0x81e8 0x80d9 0x8038 0x7530 0x7530 0x7530 0x7530 0x7530&gt;;
				};

qcom,pc-temp-y3-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x347f 0x3468 0x340e 0x33e7 0x33e0 0x33df 0x3486 0x346b 0x3412 0x33e9 0x33e1 0x33df 0x3492 0x346e 0x3416 0x33eb 0x33e1 0x33e0 0x34a1 0x3471 0x3419 0x33ec 0x33e2 0x33e0 0x34ad 0x3473 0x341c 0x33ee 0x33e2 0x33e1 0x34b3 0x3475 0x341f 0x33ef 0x33e3 0x33e2 0x34b4 0x3476 0x3420 0x33ef 0x33e4 0x33e3 0x34b5 0x3477 0x3421 0x33f0 0x33e5 0x33e4 0x34b4 0x3478 0x3423 0x33f1 0x33e7 0x33e5 0x34af 0x3478 0x3425 0x33f2 0x33e8 0x33e5 0x34ab 0x3478 0x3426 0x33f2 0x33e8 0x33e5 0x34b7 0x347f 0x3426 0x33f2 0x33e9 0x33e6 0x34cd 0x348b 0x3425 0x33f2 0x33e9 0x33e7 0x34cf 0x348a 0x3424 0x33f3 0x33ea 0x33e8 0x34a2 0x3462 0x3422 0x33f7 0x33ee 0x33e9 0x347d 0x3441 0x341f 0x33f9 0x33f1 0x33ea 0x3480 0x3449 0x341b 0x33f8 0x33f0 0x33eb 0x3488 0x345d 0x3417 0x33f7 0x33ee 0x33ec 0x348a 0x3463 0x3415 0x33f8 0x33ee 0x33ed 0x347f 0x3456 0x3414 0x33fa 0x33f2 0x33ef 0x3471 0x3447 0x3413 0x33fc 0x33f4 0x33f0 0x3467 0x343f 0x3410 0x33f8 0x33ef 0x33eb 0x345f 0x3439 0x340b 0x33f0 0x33e6 0x33e4 0x3457 0x3432 0x3409 0x33ec 0x33e2 0x33e2 0x3450 0x342c 0x3407 0x33e9 0x33e1 0x33e1 0x3449 0x3426 0x3406 0x33e8 0x33e0 0x33e1 0x3439 0x3422 0x3405 0x33e9 0x33e1 0x33e0 0x3420 0x341f 0x3405 0x33ea 0x33e1 0x33e0 0x3417 0x341b 0x3404 0x33ea 0x33e1 0x33e1 0x341f 0x3410 0x3402 0x33e9 0x33e0 0x33e2 0x342b 0x3408 0x3401 0x33e9 0x33df 0x33e2 0x3439 0x3409 0x3401 0x33e9 0x33e0 0x33e2 0x344a 0x3413 0x3400 0x33e9 0x33e1 0x33e1 0x345e 0x341c 0x3400 0x33e9 0x33e1 0x33e2 0x3474 0x3424 0x3400 0x33ea 0x33e2 0x33e2 0x348e 0x342d 0x3400 0x33ea 0x33e2 0x33e3 0x34ad 0x343c 0x3401 0x33ea 0x33e1 0x33e2 0x34d2 0x3453 0x3405 0x33e9 0x33e0 0x33e0 0x34f8 0x346e 0x3408 0x33e9 0x33e0 0x33e0 0x351f 0x348e 0x340a 0x33e9 0x33e2 0x33e1 0x3546 0x34b5 0x340c 0x33e9 0x33e4 0x33e2 0x3570 0x34e1 0x340e 0x33e9 0x33e4 0x33e2 0x359c 0x3514 0x3410 0x33e9 0x33e4 0x33e2 0x35d3 0x3551 0x3415 0x33e9 0x33e2 0x33df 0x3618 0x359c 0x341c 0x33ec 0x33e3 0x33e0 0x3663 0x35e2 0x3421 0x33f1 0x33eb 0x33e8 0x364a 0x35b3 0x3425 0x33f6 0x33ee 0x33ea 0x368c 0x35e7 0x342f 0x33fa 0x33f0 0x33eb 0x36e2 0x3618 0x343b 0x33fd 0x33f0 0x33ea 0x374b 0x3654 0x3442 0x33fc 0x33e9 0x33e5 0x37e1 0x368d 0x3444 0x33f5 0x33e8 0x33e5 0x38e3 0x36d9 0x344c 0x33f9 0x33ea 0x33e8 0x3b92 0x3780 0x3465 0x33fc 0x33f1 0x33ee 0x4378 0x38bc 0x34d2 0x3407 0x33f9 0x33f7 0x4378 0x38bc 0x34d2 0x3407 0x33f9 0x33f7 0x4378 0x38bc 0x34d2 0x3407 0x33f9 0x33f7&gt;;
				};

qcom,pc-temp-z4-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x3cb2 0x3b84 0x3a97 0x3a22 0x39ea 0x3c9d 0x3bcc 0x3a96 0x3a2a 0x39ff 0x3c7c 0x3bb9 0x3a94 0x3a21 0x39fb 0x3c4c 0x3b66 0x3a86 0x3a15 0x39f4 0x3bed 0x3b17 0x3a5b 0x3a00 0x39e6 0x3b87 0x3ad9 0x3a32 0x39e6 0x39cf 0x3b3c 0x3aa1 0x3a13 0x39cf 0x39bb 0x3afa 0x3a74 0x39f8 0x39b8 0x39a9 0x3ac2 0x3a4f 0x39e1 0x39a6 0x3999 0x3a91 0x3a2f 0x39cc 0x3995 0x398a 0x3a67 0x3a13 0x39bb 0x3989 0x397f 0x3a46 0x39fb 0x39ad 0x3985 0x397b 0x3a2b 0x39e6 0x39a2 0x3983 0x397a 0x3a14 0x39d3 0x399c 0x3980 0x3979 0x39fd 0x39c5 0x3999 0x397c 0x3975 0x39e9 0x39ba 0x3995 0x3977 0x3971 0x39df 0x39b3 0x398e 0x3973 0x396c 0x39dc 0x39b1 0x3986 0x396e 0x3967 0x39d9 0x39b4 0x3983 0x396a 0x3963 0x39d8 0x39bb 0x3981 0x3968 0x3962 0x39d6 0x39c9 0x3981 0x3967 0x3961 0x39d6 0x39e7 0x39a4 0x397d 0x3972 0x39f0 0x3a04 0x39da 0x39bb 0x39b3 0x3a1f 0x3a26 0x39fa 0x39e0 0x39d3 0x3a31 0x3a3f 0x3a12 0x39f1 0x39d3 0x3a35 0x3a41 0x3a1b 0x39fa 0x39d2 0x3a36 0x3a3d 0x3a14 0x39e1 0x39be 0x3a33 0x3a36 0x3a05 0x39a1 0x3984 0x3a25 0x3a21 0x39ee 0x3981 0x396a 0x3a15 0x3a03 0x39c6 0x3977 0x3969 0x3a05 0x39ea 0x39a8 0x3971 0x3968 0x39f4 0x39d3 0x3998 0x396e 0x3966 0x39e5 0x39c3 0x398d 0x396c 0x3961 0x39d9 0x39bc 0x3989 0x396b 0x395f 0x39cf 0x39b7 0x3988 0x396d 0x3961 0x39c6 0x39b4 0x3987 0x396e 0x3962 0x39be 0x39b1 0x3988 0x396e 0x3963 0x39b8 0x39b0 0x3989 0x396e 0x3963 0x39b5 0x39b1 0x398c 0x3970 0x3965 0x39b2 0x39b4 0x3995 0x397b 0x396f 0x39ab 0x39b4 0x399a 0x3984 0x3977 0x399e 0x39a8 0x3992 0x397a 0x396f 0x3992 0x3999 0x3987 0x396d 0x3962 0x3988 0x398e 0x3984 0x396d 0x3963 0x3a10 0x3970 0x3973 0x3966 0x395e 0x3a26 0x395d 0x3957 0x395c 0x394f 0x3a25 0x395d 0x394b 0x3950 0x3946 0x3a1f 0x3952 0x3942 0x3940 0x393b 0x3a1d 0x397a 0x393d 0x393b 0x3930 0x3a1c 0x396c 0x394d 0x3943 0x3947 0x3a25 0x39d7 0x3963 0x3946 0x3946 0x3a2b 0x39df 0x3970 0x3947 0x394a 0x3a2e 0x39e8 0x3976 0x3948 0x394a 0x3a36 0x39f2 0x3977 0x3954 0x394c 0x3a36 0x39f2 0x3977 0x3954 0x394c 0x3a36 0x39f2 0x3977 0x3954 0x394c&gt;;
				};

qcom,pc-temp-v2-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0xad4d 0xad39 0xad2f 0xad2a 0xad02 0xacee 0xac29 0xac30 0xac52 0xac5c 0xac31 0xac1e 0xab1e 0xab36 0xab7a 0xab8f 0xab61 0xab4f 0xaa31 0xaa50 0xaaa7 0xaac3 0xaa94 0xaa82 0xa963 0xa97e 0xa9dd 0xa9fa 0xa9c9 0xa9b8 0xa891 0xa8a8 0xa90a 0xa928 0xa8f7 0xa8e6 0xa7a8 0xa7b9 0xa821 0xa844 0xa814 0xa804 0xa6b4 0xa6bf 0xa72c 0xa754 0xa727 0xa719 0xa5bc 0xa5c2 0xa637 0xa663 0xa638 0xa62b 0xa4bc 0xa4bf 0xa53f 0xa56d 0xa543 0xa536 0xa3c2 0xa3c5 0xa449 0xa477 0xa450 0xa443 0xa2d9 0xa2e0 0xa356 0xa385 0xa35f 0xa352 0xa1fa 0xa206 0xa267 0xa294 0xa270 0xa265 0xa120 0xa12a 0xa17d 0xa1a9 0xa187 0xa17c 0xa051 0xa04b 0xa097 0xa0c4 0xa0a3 0xa098 0x9f6f 0x9f6f 0x9fba 0x9fe4 0x9fc5 0x9fba 0x9e3d 0x9e9c 0x9eee 0x9f0b 0x9eed 0x9ee4 0x9cd7 0x9dcb 0x9e25 0x9e37 0x9e1a 0x9e13 0x9bb7 0x9cde 0x9d41 0x9d69 0x9d50 0x9d4b 0x9adb 0x9bbe 0x9c39 0x9ca4 0x9c92 0x9c8e 0x9a10 0x9a9f 0x9b33 0x9bce 0x9bc4 0x9bc2 0x993f 0x99a8 0x9a3f 0x9ac1 0x9abb 0x9abd 0x9871 0x98c7 0x9958 0x99a6 0x99a2 0x99a7 0x97b1 0x9800 0x9896 0x98d1 0x98cf 0x98d6 0x96f9 0x9751 0x97f0 0x9828 0x982a 0x9832 0x9654 0x96b1 0x975c 0x9796 0x9799 0x97a1 0x95c7 0x960e 0x96d5 0x9714 0x9718 0x971d 0x9549 0x9570 0x965a 0x96a1 0x96a4 0x96a6 0x94ed 0x94f8 0x95e9 0x9632 0x9638 0x9639 0x94ae 0x949d 0x9581 0x95c9 0x95d3 0x95d5 0x9479 0x9457 0x9520 0x9568 0x9577 0x9578 0x9443 0x9428 0x94c2 0x950f 0x9524 0x9523 0x940f 0x9405 0x946b 0x94be 0x94d6 0x94d3 0x93d7 0x93e2 0x941d 0x9473 0x9481 0x9479 0x939d 0x93bd 0x93d6 0x942e 0x9429 0x9417 0x935f 0x9394 0x9398 0x93e5 0x93c9 0x93af 0x931d 0x935f 0x9365 0x938a 0x935e 0x9339 0x92d7 0x931b 0x9338 0x9328 0x92ed 0x92bc 0x9288 0x92cc 0x92f9 0x92ca 0x9286 0x9250 0x9226 0x926d 0x92a0 0x9270 0x9228 0x91f2 0x91bd 0x9200 0x9236 0x920e 0x91c4 0x918e 0x915b 0x9188 0x91b6 0x919c 0x9150 0x9117 0x90fb 0x9102 0x9128 0x9120 0x90d5 0x9099 0x90a4 0x9092 0x90a2 0x9096 0x904e 0x900e 0x9053 0x902f 0x903c 0x903e 0x9001 0x8fc6 0x8ffb 0x8fca 0x8ffd 0x9017 0x8fe6 0x8fad 0x8fc7 0x8f8c 0x8fde 0x9009 0x8fda 0x8fa0 0x8f86 0x8f3e 0x8fb7 0x8ff3 0x8fc2 0x8f86 0x8f26 0x8ed5 0x8f6b 0x8fc2 0x8f81 0x8f2f 0x8e81 0x8e37 0x8eb3 0x8f17 0x8e6e 0x8df4 0x8d72 0x8d4a 0x8d40 0x8d79 0x8cae 0x8c2a 0x8bcc 0x8bbd 0x8b15 0x8b5c 0x8a70 0x89e0 0x8968 0x8972 0x881e 0x8892 0x877e 0x86d5 0x85e5 0x8632 0x840c 0x84b2 0x8344 0x828c 0x8024 0x80e2 0x7ce0 0x7e6b 0x7cce 0x7b70 0x6ea4 0x7318 0x6820 0x7079 0x69aa 0x6832&gt;;
				};

qcom,fcc1-temp-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-data = &lt;0x1295 0x131b 0x1385 0x13bf 0x13d6&gt;;
				};

qcom,pc-temp-y4-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x4160 0x4123 0x40b5 0x406a 0x4050 0x404d 0x418a 0x415d 0x40d4 0x406b 0x4051 0x404f 0x41d7 0x41b9 0x40f8 0x406c 0x4054 0x4051 0x422e 0x421b 0x4119 0x406e 0x4056 0x4052 0x4277 0x426b 0x4131 0x4070 0x4058 0x4053 0x429b 0x428e 0x413b 0x4072 0x4059 0x4054 0x42a0 0x428a 0x4137 0x4075 0x405a 0x4053 0x42a2 0x4280 0x412e 0x4078 0x405b 0x4053 0x42a5 0x4275 0x4128 0x407b 0x405c 0x4053 0x42a9 0x4267 0x4124 0x407f 0x405e 0x4056 0x42ac 0x425d 0x4122 0x4084 0x4061 0x4058 0x429c 0x4257 0x4126 0x408b 0x4065 0x405a 0x427f 0x4253 0x412f 0x4093 0x406a 0x405c 0x4283 0x425f 0x413a 0x4099 0x406d 0x405f 0x42f3 0x42c9 0x414c 0x409e 0x406e 0x4063 0x4350 0x4321 0x4163 0x40a4 0x406f 0x4067 0x42f9 0x430c 0x418b 0x40b4 0x4078 0x406c 0x4232 0x42cb 0x41b6 0x40ca 0x4087 0x4072 0x41e0 0x4286 0x41b7 0x40dc 0x4097 0x407e 0x41d0 0x4232 0x4180 0x40f0 0x40ad 0x4092 0x41c2 0x41e2 0x4142 0x40f9 0x40b8 0x409e 0x41ab 0x41ac 0x4111 0x40d0 0x409e 0x408a 0x418a 0x4181 0x40e7 0x408d 0x4073 0x4068 0x4168 0x415f 0x40d2 0x4079 0x4063 0x405b 0x413b 0x4146 0x40c6 0x4072 0x405e 0x4056 0x411c 0x412d 0x40c0 0x4070 0x405c 0x4053 0x4126 0x4103 0x40be 0x4072 0x405e 0x4055 0x4148 0x40cd 0x40bd 0x4078 0x4062 0x4058 0x4160 0x40ba 0x40bd 0x407d 0x4068 0x405c 0x416e 0x40c5 0x40bf 0x4084 0x4072 0x4062 0x417b 0x40d6 0x40c0 0x408b 0x407d 0x4068 0x4186 0x40e3 0x40bb 0x4092 0x4086 0x4072 0x4190 0x40ef 0x40b0 0x4099 0x408e 0x407d 0x419b 0x4101 0x40a9 0x409d 0x408e 0x407f 0x41a8 0x4125 0x40a2 0x40a1 0x408b 0x407c 0x41b3 0x414d 0x409e 0x40a3 0x4086 0x4078 0x41b8 0x4167 0x40a5 0x4093 0x407a 0x406f 0x41bb 0x4183 0x40b5 0x4078 0x406a 0x4064 0x41bc 0x418f 0x40c3 0x406f 0x4063 0x4062 0x41b8 0x4190 0x40cd 0x406c 0x405f 0x4064 0x41b3 0x418f 0x40d7 0x406b 0x405d 0x4065 0x41b3 0x418a 0x40e2 0x406f 0x405c 0x4063 0x41b7 0x417b 0x40ec 0x4073 0x405c 0x405f 0x41c0 0x417c 0x40f1 0x406b 0x404e 0x404a 0x41d9 0x418b 0x40fc 0x406b 0x404e 0x4049 0x41f6 0x41b6 0x40f2 0x4072 0x4066 0x4074 0x41d3 0x41a7 0x40fc 0x407f 0x4084 0x4097 0x41e4 0x41cf 0x411d 0x4098 0x40a5 0x40b5 0x41f5 0x4205 0x4143 0x40b8 0x40b6 0x40b9 0x4200 0x4224 0x415a 0x40a9 0x406f 0x4063 0x4200 0x4240 0x414b 0x4072 0x405b 0x405b 0x41f7 0x423f 0x4148 0x4076 0x405f 0x405b 0x4234 0x4238 0x4185 0x4081 0x405f 0x405b 0x44ae 0x4236 0x41de 0x409e 0x407b 0x4089 0x44ae 0x4236 0x41de 0x409e 0x407b 0x4089 0x44ae 0x4236 0x41de 0x409e 0x407b 0x4089&gt;;
				};

qcom,pc-temp-z1-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x3024 0x2dea 0x2bc0 0x2ab7 0x2a5d 0x302e 0x2e0c 0x2be0 0x2ade 0x2a85 0x3034 0x2e16 0x2bf3 0x2aeb 0x2a92 0x3037 0x2e15 0x2bf6 0x2aee 0x2a98 0x3038 0x2e10 0x2bf2 0x2aed 0x2a98 0x3037 0x2e04 0x2bed 0x2aea 0x2a96 0x3035 0x2df4 0x2be6 0x2ae6 0x2a94 0x3033 0x2de7 0x2bdc 0x2ae2 0x2a91 0x302e 0x2dda 0x2bd4 0x2adf 0x2a8f 0x300e 0x2dce 0x2bcb 0x2add 0x2a8f 0x2fe4 0x2dc1 0x2bc6 0x2adb 0x2a8f 0x2fd3 0x2db4 0x2bc3 0x2ada 0x2a8e 0x2fcc 0x2db0 0x2bc1 0x2ad9 0x2a8e 0x2fc5 0x2dae 0x2bc0 0x2ad8 0x2a8d 0x2fb7 0x2dad 0x2bbf 0x2ad8 0x2a8d 0x2fa6 0x2dab 0x2bbf 0x2ad8 0x2a8e 0x2f99 0x2da9 0x2bbe 0x2ad9 0x2a8e 0x2f8b 0x2da7 0x2bbe 0x2ad9 0x2a90 0x2f80 0x2da0 0x2bbe 0x2ad9 0x2a91 0x2f7e 0x2d99 0x2bbf 0x2ada 0x2a92 0x2f7e 0x2d99 0x2bbf 0x2ada 0x2a93 0x2f7f 0x2d9b 0x2bbf 0x2adb 0x2a94 0x2f80 0x2d9d 0x2bc0 0x2adb 0x2a94 0x2f84 0x2da3 0x2bc1 0x2adc 0x2a95 0x2f86 0x2da9 0x2bc3 0x2add 0x2a97 0x2f84 0x2da9 0x2bc5 0x2adf 0x2a9a 0x2f84 0x2da7 0x2bc8 0x2ae2 0x2a9c 0x2f8b 0x2da5 0x2bcb 0x2ae5 0x2a9f 0x2f94 0x2da8 0x2bcf 0x2ae8 0x2aa2 0x2f9a 0x2dac 0x2bd3 0x2aeb 0x2aa4 0x2f9a 0x2dae 0x2bd7 0x2aef 0x2aa7 0x2f9a 0x2db0 0x2bdb 0x2af2 0x2aaa 0x2f9c 0x2db3 0x2bdf 0x2af5 0x2aae 0x2fa7 0x2db7 0x2be4 0x2af9 0x2ab2 0x2fb2 0x2dbc 0x2bea 0x2afe 0x2ab5 0x2fb7 0x2dc1 0x2bef 0x2b02 0x2ab9 0x2fb9 0x2dc5 0x2bf3 0x2b06 0x2abd 0x2fba 0x2dcb 0x2bf6 0x2b0a 0x2ac0 0x2fcb 0x2dd5 0x2bfb 0x2b0d 0x2ac4 0x2fe0 0x2de6 0x2c03 0x2b11 0x2ac7 0x2fe5 0x2df2 0x2c09 0x2b15 0x2ac9 0x2fea 0x2df9 0x2c0e 0x2b18 0x2acc 0x2ff3 0x2e04 0x2c12 0x2b1a 0x2ace 0x3009 0x2e1e 0x2c18 0x2b1d 0x2ad0 0x301e 0x2e1e 0x2c23 0x2b22 0x2ad3 0x300c 0x2e16 0x2c28 0x2b25 0x2ad5 0x3015 0x2e1c 0x2c28 0x2b25 0x2ad5 0x300e 0x2e18 0x2c26 0x2b26 0x2ad7 0x3004 0x2e12 0x2c28 0x2b28 0x2ad9 0x301b 0x2e17 0x2c34 0x2b2e 0x2add 0x302a 0x2e2b 0x2c39 0x2b32 0x2ae1 0x303f 0x2e3b 0x2c40 0x2b39 0x2ae7 0x311f 0x2e59 0x2c46 0x2b3f 0x2aed 0x3044 0x2e53 0x2c54 0x2b4b 0x2af8 0x3044 0x2e53 0x2c54 0x2b4b 0x2af8 0x3044 0x2e53 0x2c54 0x2b4b 0x2af8&gt;;
				};

qcom,pc-temp-z5-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x3352 0x32b9 0x34bc 0x3633 0x380e 0x376c 0x398a 0x3bb1 0x3a34 0x3a7e 0x3ad8 0x3d06 0x4090 0x40b8 0x413f 0x3d58 0x3f3c 0x428a 0x4579 0x47b9 0x3f17 0x414f 0x439c 0x479d 0x4ab6 0x40d7 0x4380 0x44bc 0x4970 0x4cfe 0x432d 0x4593 0x462a 0x4c9c 0x504a 0x4602 0x4773 0x47a7 0x513a 0x5542 0x4935 0x491e 0x4911 0x54b4 0x59e6 0x4d46 0x4af9 0x4a75 0x573a 0x5de3 0x51c6 0x4d43 0x4bf6 0x58db 0x6116 0x55f2 0x4fe4 0x4e1f 0x5842 0x6119 0x5a28 0x52d8 0x4fe4 0x55de 0x5e52 0x5e75 0x5652 0x4fca 0x5473 0x5c8d 0x6282 0x59c7 0x4eb6 0x556e 0x5d04 0x66a0 0x5d63 0x4e30 0x56e0 0x5e18 0x6c3a 0x60bf 0x5065 0x57e5 0x5ff5 0x76e2 0x6172 0x53cd 0x5a64 0x641c 0x802c 0x5f28 0x559f 0x5c65 0x6751 0x8152 0x5cfd 0x56a8 0x5e9e 0x6916 0x8070 0x7580 0x58ba 0x6093 0x6a3b 0x801a 0xb7b7 0x6cb5 0x6141 0x68a5 0x98ab 0xd2e7 0x8539 0x613f 0x60fc 0xc286 0xabdf 0x8086 0x5f37 0x57f2 0xccae 0x7914 0x5f36 0x4e44 0x4aed 0xb56f 0x6571 0x49e9 0x3e8e 0x400c 0x9a13 0x59ef 0x45f9 0x44a4 0x48d9 0x8c6e 0x55b9 0x43d9 0x5659 0x671e 0x8232 0x57fa 0x45a6 0x61a0 0x73c1 0x7e47 0x5d05 0x4f91 0x688b 0x6dd1 0x80f5 0x64ab 0x5a27 0x6c4d 0x6768 0x865c 0x736d 0x632f 0x6afd 0x675e 0x8c3c 0x80a1 0x6b8e 0x67b5 0x6925 0x93f8 0x8823 0x7197 0x665c 0x6977 0x9b89 0x8dd2 0x76c5 0x6808 0x67a8 0xa11e 0x910a 0x78f3 0x69a8 0x6617 0xa5df 0x9342 0x7721 0x69d7 0x6701 0xaa1b 0x9465 0x73bf 0x69ad 0x6945 0xae67 0x9218 0x70a8 0x677c 0x6918 0xb1e2 0x8c28 0x6caa 0x608a 0x5ff4 0xb357 0x88a3 0x6a9f 0x5ba2 0x5832 0xb37a 0x86c9 0x6ad4 0x64c8 0x67c7 0xb17b 0x8618 0x6b05 0x7092 0x7eda 0xa7c5 0x85b2 0x6621 0x6d0f 0x7f20 0x42b2 0x82a3 0x61ec 0x62bf 0x6ff9 0x349c 0x79d8 0x6524 0x4de4 0x51d8 0x3394 0x65d9 0x6b27 0x50dc 0x528a 0x3351 0x6cc9 0x65e9 0x5ad2 0x53ef 0x3334 0x566d 0x6585 0x54da 0x5b5a 0x336c 0x52f5 0x5425 0x6285 0x5eaa 0x33bc 0x3534 0x47d7 0x5bda 0x5f40 0x330a 0x33da 0x3fac 0x58ae 0x56d7 0x3298 0x3299 0x3c9d 0x5317 0x50a9 0x31f6 0x3125 0x3b54 0x42d6 0x459b 0x31f6 0x3125 0x3b54 0x42d6 0x459b 0x31f6 0x3125 0x3b54 0x42d6 0x459b&gt;;
				};

qcom,fcc2-temp-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-data = &lt;0x1368 0x1367 0x138c 0x139a 0x139a 0x1397&gt;;
				};

qcom,pc-temp-y1-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x1768 0x15c5 0x14a8 0x1395 0x1300 0x12cd 0x175c 0x15c5 0x14b1 0x1395 0x12ff 0x12cd 0x174f 0x15c5 0x14b8 0x1394 0x12fe 0x12cc 0x1743 0x15c6 0x14bc 0x1392 0x12fd 0x12cc 0x1739 0x15c7 0x14be 0x1391 0x12fc 0x12cb 0x1735 0x15c8 0x14bf 0x138f 0x12fb 0x12ca 0x1737 0x15cb 0x14bc 0x138c 0x12fb 0x12ca 0x173a 0x15cf 0x14b7 0x138a 0x12fa 0x12c9 0x173d 0x15d0 0x14b3 0x1388 0x12f9 0x12c9 0x1742 0x15ca 0x14ae 0x1386 0x12f8 0x12c8 0x1746 0x15c5 0x14aa 0x1385 0x12f7 0x12c8 0x1745 0x15c5 0x14a7 0x1384 0x12f6 0x12c7 0x1742 0x15c6 0x14a4 0x1384 0x12f5 0x12c7 0x1742 0x15c5 0x14a4 0x1383 0x12f4 0x12c6 0x1748 0x15bf 0x14a4 0x1381 0x12f4 0x12c6 0x1751 0x15ba 0x14a5 0x1380 0x12f4 0x12c6 0x175b 0x15c4 0x14a4 0x1380 0x12f4 0x12c5 0x1766 0x15d7 0x14a3 0x1380 0x12f4 0x12c5 0x1769 0x15dd 0x14a3 0x1381 0x12f4 0x12c5 0x1764 0x15d2 0x14a5 0x1382 0x12f4 0x12c6 0x175f 0x15c9 0x14a7 0x1383 0x12f4 0x12c7 0x175b 0x15c9 0x14a5 0x1384 0x12f6 0x12c8 0x1750 0x15cb 0x14a2 0x1384 0x12f8 0x12c8 0x174c 0x15cb 0x14a2 0x1385 0x12f9 0x12c9 0x174c 0x15cd 0x14a6 0x1387 0x12f9 0x12cb 0x174a 0x15cf 0x14a9 0x138a 0x12fa 0x12cc 0x1746 0x15ce 0x14a8 0x138b 0x12fa 0x12cd 0x173e 0x15c9 0x14a5 0x138d 0x12fc 0x12cf 0x1739 0x15c4 0x14a6 0x138f 0x12fd 0x12d0 0x1735 0x15c5 0x14ac 0x1391 0x12ff 0x12d2 0x1731 0x15c7 0x14b0 0x1394 0x1301 0x12d4 0x172f 0x15c5 0x14b1 0x1395 0x1303 0x12d5 0x172e 0x15c0 0x14b0 0x1396 0x1304 0x12d6 0x172d 0x15be 0x14b1 0x1398 0x1306 0x12d7 0x1729 0x15c1 0x14b7 0x139a 0x1308 0x12d8 0x1724 0x15c4 0x14bb 0x139c 0x1309 0x12da 0x1721 0x15c1 0x14b9 0x139d 0x130a 0x12db 0x171c 0x15b8 0x14b4 0x139d 0x130b 0x12dc 0x1718 0x15b1 0x14b3 0x139e 0x130c 0x12dd 0x1711 0x15ac 0x14b5 0x13a1 0x130d 0x12df 0x170b 0x15a7 0x14b8 0x13a3 0x130e 0x12e0 0x170b 0x15a6 0x14bd 0x13a5 0x130f 0x12e1 0x170b 0x15a8 0x14c3 0x13a8 0x1312 0x12e3 0x1708 0x15aa 0x14cb 0x13ab 0x1314 0x12e5 0x1710 0x15ad 0x14cc 0x13b0 0x1318 0x12e7 0x175b 0x15bc 0x14d5 0x13b5 0x1318 0x12e8 0x173f 0x15c3 0x14dd 0x13b4 0x1318 0x12e8 0x1740 0x15cd 0x14d4 0x13b8 0x1318 0x12e8 0x1739 0x15d3 0x1569 0x13b2 0x1318 0x12e9 0x174d 0x15d4 0x14f9 0x13b2 0x1319 0x12e9 0x1751 0x15d6 0x14d8 0x13b8 0x131a 0x12eb 0x1745 0x15cf 0x14e6 0x13bc 0x131e 0x12ef 0x1739 0x15d1 0x14e2 0x13c3 0x1323 0x12f3 0x1777 0x15d9 0x14e4 0x13cd 0x132b 0x12fb 0x1777 0x15d9 0x14e4 0x13cd 0x132b 0x12fb 0x1777 0x15d9 0x14e4 0x13cd 0x132b 0x12fb&gt;;
				};

qcom,pc-temp-y5-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x30d6 0x3d28 0x48ec 0x4a0a 0x48c8 0x4c34 0x353f 0x3ef9 0x4846 0x481e 0x474e 0x4a58 0x3a8f 0x40c2 0x477f 0x4638 0x4506 0x4899 0x3fe4 0x426d 0x46b0 0x4457 0x4288 0x4718 0x4460 0x43e1 0x45f4 0x427c 0x4069 0x45f7 0x471f 0x4506 0x4564 0x40a7 0x3f42 0x4558 0x4873 0x45ff 0x44fd 0x3ebf 0x3ede 0x455e 0x494d 0x46bf 0x4497 0x3ced 0x3e88 0x4593 0x4940 0x46cd 0x440f 0x3b89 0x3e13 0x44df 0x47d6 0x4627 0x433f 0x3a6b 0x3d5d 0x41f0 0x46bf 0x45a7 0x4259 0x3951 0x3c7b 0x3f71 0x4b53 0x47ed 0x40ca 0x37d0 0x3b0e 0x3e71 0x5424 0x4c50 0x3ea2 0x3676 0x399d 0x3dbc 0x55ba 0x4c88 0x3cf8 0x366c 0x39d9 0x3d4e 0x4e47 0x43d4 0x3b63 0x3772 0x3c75 0x3d8f 0x4808 0x3c83 0x3a97 0x381d 0x3e29 0x3ddb 0x4d00 0x4491 0x3bad 0x3754 0x3bd5 0x3d2c 0x5812 0x5652 0x3e70 0x3618 0x382f 0x3c3b 0x5b8d 0x5bc3 0x429f 0x377c 0x385c 0x3cc9 0x58bc 0x5917 0x4aec 0x409c 0x3d75 0x3edf 0x55e9 0x56a4 0x5111 0x4839 0x423f 0x4171 0x5555 0x56ff 0x52a1 0x4afa 0x4504 0x4504 0x547c 0x5835 0x5395 0x4cb6 0x470f 0x488e 0x536e 0x58f5 0x5417 0x4c2a 0x46c2 0x4903 0x51a8 0x5966 0x5476 0x47d2 0x433d 0x47c8 0x4ef3 0x59ba 0x54c8 0x44f0 0x4041 0x461c 0x46c9 0x591d 0x5512 0x4645 0x3f8c 0x4327 0x3730 0x5681 0x5556 0x485e 0x3f7c 0x3fde 0x3102 0x52a9 0x55a0 0x486f 0x3f03 0x3f58 0x30f9 0x451b 0x5601 0x4688 0x3c8e 0x3fe0 0x311b 0x3803 0x5681 0x4546 0x3af5 0x404d 0x317c 0x37b3 0x58d9 0x45d4 0x3c65 0x4041 0x324d 0x3a48 0x5c9c 0x4736 0x3f65 0x4055 0x3310 0x3c1b 0x5cdd 0x498b 0x4244 0x4220 0x339c 0x3c25 0x5773 0x4e97 0x4567 0x487f 0x342f 0x3ba5 0x5240 0x5292 0x4842 0x4cb6 0x3530 0x3afe 0x5094 0x544e 0x4a62 0x4c8d 0x36b5 0x38f9 0x4f5e 0x556d 0x4c52 0x4c18 0x375e 0x37e1 0x4d54 0x5491 0x4ecc 0x4cec 0x3676 0x37d3 0x4961 0x4e97 0x5200 0x51c9 0x3505 0x37c7 0x454e 0x4927 0x54a7 0x5777 0x33fd 0x3782 0x41e2 0x46b3 0x56bf 0x5d77 0x3323 0x36ec 0x3f84 0x4524 0x57e4 0x615d 0x3309 0x36bb 0x3f62 0x4459 0x4d04 0x4ac0 0x3316 0x3689 0x3ecb 0x4367 0x4250 0x4207 0x3326 0x3514 0x4112 0x432d 0x45ac 0x4188 0x33f0 0x35e4 0x4197 0x4679 0x4584 0x3f8f 0x3482 0x36c1 0x4361 0x485d 0x4389 0x3e65 0x3590 0x3801 0x47f8 0x4947 0x441c 0x3d8e 0x362d 0x3c42 0x4c6e 0x4bab 0x428d 0x4194 0x36b1 0x3fa8 0x4b05 0x4bf6 0x423e 0x3fe5 0x35ec 0x3ce5 0x45c4 0x4d9a 0x407f 0x4001 0x3258 0x3722 0x387d 0x4cc1 0x4df6 0x47da 0x2a28 0x339f 0x3511 0x57ae 0x5fcc 0x66db 0x2a28 0x339f 0x3511 0x57ae 0x5fcc 0x66db 0x2a28 0x339f 0x3511 0x57ae 0x5fcc 0x66db&gt;;
				};
			};

qcom,4890802_xiaomi_K6_NVT_5020mAH_PM7150 {
				qcom,max-voltage-uv = &lt;0x43e6d0&gt;;
				mi,six-pin-battery;
				qcom,battery-type = &quot;K6_nvt_5020mah&quot;;
				qcom,jeita-fcc-ranges = &lt;0x00 0x32 0xef420 0x33 0x64 0x258960 0x65 0x96 0x347d80 0x97 0x1e0 0x5b8d80 0x1e1 0x258 0x258960&gt;;
				qcom,nom-batt-capacity-mah = &lt;0x139c&gt;;
				mi,step-chg-hysteresis = &lt;0x1388&gt;;
				mi,use-bq-pump;
				qcom,qg-batt-profile-ver = &lt;0x64&gt;;
				qcom,fastchg-current-ma = &lt;0x1770&gt;;
				qcom,jeita-fv-ranges = &lt;0x00 0x32 0x43e6d0 0x33 0x64 0x43e6d0 0x65 0x96 0x43e6d0 0x97 0x1e0 0x4434f0 0x1e1 0x258 0x3e8fa0&gt;;
				qcom,ffc-max-voltage-uv = &lt;0x4434f0&gt;;
				qcom,step-chg-ranges = &lt;0x2dcaa8 0x40d990 0x5b8d80 0x40d991 0x426030 0x4ac4a0 0x426031 0x43e6d0 0x4ac4a0 0x43e6d1 0x440de0 0x3b8260 0x440de1 0x4434f0 0x3b8260&gt;;
				qcom,battery-therm-kohm = &lt;0x64&gt;;
				qcom,batt-id-kohm = &lt;0x64&gt;;
				qcom,battery-beta = &lt;0x109a&gt;;
				qcom,fg-cc-cv-threshold-uv = &lt;0x43bfc0&gt;;

qcom,pc-temp-z2-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x282c 0x2a5f 0x2a22 0x2817 0x27b1 0x27f9 0x298b 0x28d6 0x2861 0x27a9 0x2830 0x2905 0x2912 0x285d 0x27aa 0x2858 0x28dd 0x2939 0x285b 0x27b3 0x284e 0x28ba 0x291e 0x284f 0x27b1 0x2838 0x2897 0x28e2 0x282c 0x279e 0x282f 0x2870 0x28b1 0x2810 0x2790 0x282e 0x2856 0x2885 0x27de 0x2779 0x282d 0x2849 0x286d 0x27b1 0x275e 0x2828 0x283e 0x286e 0x27ae 0x275c 0x281b 0x283d 0x2870 0x27a4 0x2760 0x280f 0x284b 0x2872 0x279c 0x2766 0x2806 0x2860 0x2874 0x279a 0x2771 0x27ff 0x2873 0x2878 0x2798 0x277c 0x27ff 0x2889 0x2886 0x279d 0x2786 0x2807 0x289e 0x289b 0x27ac 0x2799 0x2812 0x28b3 0x28a9 0x27b8 0x27a2 0x281e 0x28c7 0x28b4 0x27c3 0x27a7 0x282d 0x28da 0x28bf 0x27d0 0x27ac 0x283d 0x28ec 0x28c9 0x27dd 0x27b3 0x284e 0x28fc 0x28d5 0x27ef 0x27c2 0x285f 0x2911 0x290c 0x2829 0x27d6 0x2872 0x2923 0x2999 0x28fa 0x27ff 0x2885 0x2932 0x29d9 0x2983 0x281f 0x2897 0x2947 0x296a 0x290d 0x2828 0x28a4 0x294d 0x28ea 0x2853 0x282d 0x28b0 0x293c 0x28e0 0x2846 0x282b 0x28ba 0x292a 0x28e7 0x28a7 0x2813 0x28c5 0x2929 0x28f3 0x28de 0x27f1 0x28cd 0x292a 0x2927 0x28a0 0x27ad 0x28d0 0x292d 0x2957 0x283d 0x2766 0x28d3 0x2935 0x2948 0x2801 0x275e 0x28d6 0x2941 0x2918 0x27d0 0x276a 0x28dd 0x2949 0x2907 0x27c0 0x277a 0x28e6 0x2951 0x2915 0x27d6 0x2791 0x28eb 0x2958 0x292b 0x27fb 0x27b1 0x28ee 0x2960 0x293e 0x281e 0x27e2 0x28f3 0x2969 0x2955 0x2846 0x282a 0x28fe 0x2978 0x2975 0x286b 0x285e 0x290f 0x298d 0x29af 0x2893 0x2880 0x2920 0x299c 0x29d9 0x28b0 0x2894 0x2933 0x29a2 0x29ce 0x28ba 0x2895 0x294b 0x29a8 0x29b9 0x28c1 0x2891 0x296f 0x29b4 0x29b3 0x28d1 0x289b 0x2a82 0x2a2c 0x29cd 0x28d7 0x28a0 0x2ac3 0x2a65 0x29e8 0x28e8 0x2871 0x2a88 0x2a70 0x29d2 0x28d0 0x2865 0x29f6 0x2abb 0x29b4 0x28d2 0x2881 0x29c1 0x2b34 0x29ad 0x28e1 0x2894 0x2973 0x2ba5 0x29eb 0x2926 0x28f1 0x2801 0x2b9d 0x29e4 0x28f8 0x2889 0x2854 0x2b68 0x29ad 0x2879 0x27e6 0x288d 0x2aa8 0x299a 0x282d 0x27a5 0x27b9 0x295f 0x2959 0x27fb 0x2772 0x27b9 0x295f 0x2959 0x27fb 0x2772 0x27b9 0x295f 0x2959 0x27fb 0x2772&gt;;
				};

qcom,pc-temp-z6-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x3d0d 0x3ae6 0x3958 0x38fa 0x38af 0x3d90 0x3aef 0x39b2 0x390c 0x38e0 0x3d47 0x3aed 0x3999 0x3902 0x38db 0x3cea 0x3ac9 0x397a 0x38f2 0x38cf 0x3c96 0x3a85 0x3962 0x38e6 0x38c7 0x3c3f 0x3a54 0x394c 0x38dc 0x38c2 0x3bf6 0x3a2d 0x3939 0x38d3 0x38bc 0x3bb8 0x3a0d 0x392a 0x38cb 0x38b4 0x3b83 0x39f2 0x391d 0x38c4 0x38ad 0x3b56 0x39dc 0x3911 0x38be 0x38a9 0x3b2f 0x39c7 0x3907 0x38b9 0x38a7 0x3b0e 0x39b4 0x38ff 0x38b4 0x38a4 0x3af2 0x39a6 0x38fa 0x38b1 0x38a1 0x3ad9 0x399d 0x38f6 0x38ae 0x389f 0x3ac3 0x3997 0x38f1 0x38aa 0x389c 0x3aad 0x3992 0x38ed 0x38a7 0x3898 0x3a9d 0x398e 0x38ea 0x38a4 0x3895 0x3a95 0x398a 0x38e7 0x38a1 0x3892 0x3a90 0x3984 0x38e4 0x389e 0x388f 0x3a8a 0x397e 0x38e0 0x3899 0x388b 0x3a83 0x397c 0x38dd 0x3894 0x3885 0x3a7d 0x397f 0x38e7 0x3897 0x3887 0x3a7d 0x3985 0x390b 0x38b9 0x38a4 0x3a81 0x3998 0x391c 0x38d0 0x38ba 0x3a88 0x39bb 0x391c 0x38ce 0x38b8 0x3a9d 0x39c7 0x391a 0x38c9 0x38b3 0x3ab7 0x39c0 0x3917 0x38c6 0x38b0 0x3abd 0x39b6 0x3910 0x38c4 0x38ae 0x3abd 0x39b0 0x390b 0x38c1 0x38ab 0x3abd 0x39ab 0x390a 0x38bd 0x38a7 0x3ab9 0x39a7 0x3908 0x38b9 0x38a2 0x3ab1 0x39a5 0x3905 0x38b5 0x389e 0x3aab 0x39a3 0x3901 0x38af 0x3899 0x3aa8 0x39a2 0x38fe 0x38ab 0x3894 0x3aa4 0x39a0 0x38fc 0x38a7 0x388f 0x3aa1 0x399f 0x38fa 0x38a4 0x3889 0x3a9d 0x399d 0x38f8 0x38a2 0x3886 0x3a9b 0x399c 0x38f6 0x389f 0x3884 0x3a9c 0x399d 0x38f6 0x389f 0x3884 0x3a9d 0x399d 0x38f8 0x38a3 0x3889 0x3a9f 0x399e 0x38fa 0x38a7 0x388e 0x3aa4 0x399d 0x38f8 0x38a6 0x388e 0x3aa6 0x399b 0x38f3 0x38a3 0x388e 0x3aa8 0x399a 0x38f1 0x38a4 0x3892 0x3a94 0x398d 0x38ea 0x38a1 0x3890 0x3a8e 0x3983 0x38e0 0x3894 0x3880 0x3a8c 0x3980 0x38dc 0x3891 0x387d 0x3a88 0x397c 0x38d8 0x388b 0x3876 0x3a87 0x3978 0x38d1 0x3882 0x386d 0x3a89 0x3979 0x38cf 0x387d 0x3866 0x3a8c 0x397f 0x38d8 0x388c 0x3879 0x3a95 0x398b 0x38e2 0x3899 0x3888 0x3aaa 0x3995 0x38e6 0x389e 0x388d 0x3ac7 0x39ab 0x38ee 0x38a2 0x3891 0x3ac7 0x39ab 0x38ee 0x38a2 0x3891 0x3ac7 0x39ab 0x38ee 0x38a2 0x3891&gt;;
				};

qcom,pc-temp-y2-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x294b 0x29a1 0x2b8e 0x2cad 0x2b51 0x2b32 0x2969 0x29c2 0x2b97 0x2c62 0x2b23 0x2b02 0x299a 0x29f7 0x2b94 0x2c17 0x2af0 0x2acb 0x29d0 0x2a31 0x2b89 0x2bd0 0x2abf 0x2a94 0x29fe 0x2a60 0x2b78 0x2b93 0x2a96 0x2a67 0x2a17 0x2a73 0x2b63 0x2b67 0x2a7b 0x2a4b 0x2a1b 0x2a6f 0x2b44 0x2b48 0x2a6e 0x2a3e 0x2a1d 0x2a6a 0x2b21 0x2b2f 0x2a64 0x2a34 0x2a24 0x2a6c 0x2b08 0x2b18 0x2a58 0x2a24 0x2a3f 0x2a82 0x2af2 0x2b01 0x2a49 0x2a04 0x2a60 0x2a9b 0x2aea 0x2aee 0x2a37 0x29f2 0x2a76 0x2aac 0x2af3 0x2add 0x2a1c 0x29fa 0x2a8a 0x2abf 0x2b08 0x2ad1 0x2a04 0x2a05 0x2aab 0x2ae7 0x2b2b 0x2ad4 0x2a04 0x29fc 0x2aff 0x2b51 0x2b68 0x2ae7 0x2a11 0x29e2 0x2b45 0x2b9e 0x2ba6 0x2b02 0x2a18 0x29d4 0x2b48 0x2bc4 0x2be0 0x2b35 0x2a11 0x29d2 0x2b43 0x2be9 0x2c16 0x2b7d 0x2a0b 0x29d3 0x2b42 0x2bec 0x2c48 0x2be0 0x2a2f 0x29e4 0x2b4b 0x2bd2 0x2c77 0x2c5c 0x2aa7 0x2a1c 0x2b56 0x2bbf 0x2c86 0x2c85 0x2b04 0x2a58 0x2b5c 0x2bce 0x2c7b 0x2c74 0x2b3f 0x2a9d 0x2b60 0x2be7 0x2c70 0x2c5b 0x2b64 0x2ad7 0x2b62 0x2bea 0x2c75 0x2c40 0x2b5d 0x2af0 0x2b54 0x2bda 0x2c85 0x2c1d 0x2b3e 0x2b04 0x2b3a 0x2bc0 0x2c8f 0x2c15 0x2b36 0x2b0b 0x2b21 0x2b97 0x2c98 0x2c41 0x2b57 0x2b0e 0x2b06 0x2b59 0x2c9e 0x2c72 0x2b7b 0x2b15 0x2ad5 0x2adc 0x2c97 0x2c92 0x2b94 0x2b29 0x291e 0x2988 0x2c84 0x2cb8 0x2bba 0x2b52 0x26aa 0x28b9 0x2c7c 0x2cd5 0x2bcd 0x2b7f 0x260e 0x2839 0x2c7c 0x2cfc 0x2bf3 0x2bb7 0x25fa 0x2746 0x2c7b 0x2d14 0x2c23 0x2be3 0x25ee 0x26c5 0x2c6d 0x2d09 0x2c4c 0x2bf3 0x25e5 0x2649 0x2c4d 0x2cf0 0x2c71 0x2bff 0x25dd 0x25f7 0x2c24 0x2cdd 0x2c77 0x2bfd 0x25d7 0x25e1 0x2be3 0x2ccc 0x2c50 0x2bd6 0x25d2 0x25d4 0x2b93 0x2cbc 0x2c1c 0x2bb2 0x25ce 0x25cc 0x2b3b 0x2ca8 0x2be3 0x2ba9 0x25ca 0x25c8 0x2ad2 0x2c90 0x2ba8 0x2b9e 0x25c8 0x25c4 0x2a5f 0x2c83 0x2ba2 0x2b89 0x25c6 0x25c1 0x29dc 0x2c72 0x2bc4 0x2b49 0x25c4 0x25bf 0x28bd 0x2c50 0x2bc7 0x2b35 0x25c3 0x25be 0x26d5 0x2c03 0x2b9e 0x2b3c 0x25c1 0x25bc 0x262e 0x2bc5 0x2b6a 0x2b06 0x25bf 0x25bb 0x25fe 0x2b95 0x2b3e 0x2a85 0x25be 0x25ba 0x25df 0x2bab 0x2aea 0x2a63 0x25bd 0x25ba 0x25ce 0x2ba3 0x2af1 0x2a6c 0x25bb 0x25b9 0x25c5 0x2b94 0x2b02 0x2a53 0x25b8 0x25b8 0x25bf 0x2b93 0x2b37 0x2a62 0x25b4 0x25b6 0x25ba 0x2b44 0x2afa 0x2a55 0x25b1 0x25b2 0x25b7 0x2adb 0x2aa4 0x2a1b 0x25b0 0x25b0 0x25b4 0x2a4b 0x2a36 0x29b5 0x25af 0x25b0 0x25b3 0x2991 0x29af 0x2931 0x25af 0x25b0 0x25b3 0x2991 0x29af 0x2931 0x25af 0x25b0 0x25b3 0x2991 0x29af 0x2931&gt;;
				};

qcom,pc-temp-y6-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x15dd 0x150f 0x142e 0x13a3 0x1375 0x136c 0x15e6 0x1523 0x143c 0x13a2 0x1376 0x136d 0x15ec 0x1533 0x1446 0x13a2 0x1377 0x136f 0x15f0 0x153f 0x144c 0x13a2 0x1377 0x1370 0x15f3 0x1547 0x144f 0x13a1 0x1378 0x1371 0x15f4 0x154a 0x144f 0x13a1 0x1378 0x1371 0x15f3 0x1546 0x144d 0x13a1 0x1379 0x1372 0x15f0 0x1540 0x1447 0x13a1 0x1379 0x1372 0x15ec 0x153a 0x1443 0x13a1 0x137a 0x1372 0x15e7 0x1534 0x143f 0x13a1 0x137a 0x1372 0x15e3 0x1531 0x143e 0x13a2 0x137b 0x1373 0x15e1 0x1534 0x143e 0x13a3 0x137c 0x1373 0x15df 0x1538 0x143e 0x13a4 0x137d 0x1374 0x15de 0x153c 0x143e 0x13a7 0x137e 0x1375 0x15da 0x1540 0x1441 0x13aa 0x1380 0x1376 0x15d4 0x1542 0x1445 0x13ae 0x1381 0x1377 0x15c9 0x153c 0x144e 0x13b2 0x1384 0x1379 0x15b6 0x152e 0x1457 0x13b8 0x1388 0x137b 0x15a9 0x151c 0x1453 0x13c0 0x138d 0x137f 0x15a2 0x1500 0x1442 0x13cb 0x1396 0x1386 0x159c 0x14ea 0x1431 0x13cd 0x1398 0x1389 0x1598 0x14e1 0x141f 0x13be 0x1394 0x1387 0x1595 0x14db 0x1410 0x13ac 0x138d 0x1384 0x1593 0x14d5 0x1409 0x13a0 0x1384 0x137d 0x1592 0x14d0 0x1405 0x1398 0x1379 0x1372 0x1591 0x14ca 0x1402 0x1395 0x1375 0x136e 0x158f 0x14c1 0x1400 0x1395 0x1375 0x136e 0x158c 0x14b9 0x13ff 0x1396 0x1375 0x136e 0x158b 0x14b8 0x13fe 0x1397 0x1376 0x136e 0x1594 0x14c3 0x13fe 0x1399 0x1377 0x136f 0x15a6 0x14d2 0x13fd 0x139b 0x1379 0x1370 0x15b9 0x14e6 0x13fa 0x139d 0x137b 0x1373 0x15ce 0x1501 0x13f8 0x139e 0x137e 0x1375 0x15e5 0x151f 0x13fb 0x139f 0x1381 0x1379 0x15fe 0x1542 0x1405 0x13a0 0x1383 0x137c 0x161a 0x1569 0x1411 0x13a0 0x1383 0x137c 0x1639 0x1595 0x141f 0x139d 0x1380 0x1378 0x1659 0x15c7 0x1431 0x139b 0x137c 0x1374 0x167b 0x15fb 0x1446 0x139b 0x137b 0x1374 0x169d 0x1634 0x145e 0x139c 0x137a 0x1375 0x16be 0x1671 0x147a 0x139d 0x137b 0x1377 0x16e4 0x16b1 0x1498 0x13a4 0x137e 0x137b 0x170d 0x16f7 0x14ba 0x13a7 0x137e 0x137a 0x1740 0x1743 0x14e1 0x13a8 0x1377 0x1370 0x1784 0x17a0 0x1511 0x13a9 0x1372 0x136a 0x17f0 0x17d2 0x1537 0x13ac 0x137a 0x1374 0x181c 0x1813 0x1573 0x13b5 0x1383 0x137f 0x185b 0x1868 0x15c1 0x13bf 0x138f 0x138b 0x18f3 0x18c8 0x1632 0x13cd 0x139a 0x1397 0x1a15 0x195e 0x16d0 0x13d8 0x13a0 0x139b 0x1dcc 0x1ac5 0x17c8 0x13d7 0x1389 0x1380 0x2989 0x217d 0x192c 0x13d2 0x1382 0x137b 0x46c0 0x3c73 0x1cd2 0x13f1 0x1387 0x137e 0xb1f2 0xded8 0x37c8 0x1424 0x1390 0x1385 0xb1f2 0xded8 0x37c8 0x1424 0x1390 0x1385 0xb1f2 0xded8 0x37c8 0x1424 0x1390 0x1385&gt;;
				};

qcom,pc-temp-z3-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x4c2c 0x4c64 0x4bd1 0x4b90 0x4b82 0x4ca3 0x4c55 0x4bca 0x4bb1 0x4ba5 0x4cf0 0x4c50 0x4be4 0x4bba 0x4baf 0x4d1c 0x4c5e 0x4bf2 0x4bbf 0x4bb3 0x4d2b 0x4c6e 0x4bf4 0x4bc3 0x4bb8 0x4d35 0x4c71 0x4bf6 0x4bc6 0x4bbf 0x4d36 0x4c71 0x4bf7 0x4bc7 0x4bc1 0x4d2f 0x4c70 0x4bf8 0x4bc9 0x4bc0 0x4d25 0x4c6d 0x4bf9 0x4bcb 0x4bbe 0x4d1e 0x4c67 0x4bf5 0x4bca 0x4bbd 0x4d18 0x4c60 0x4bee 0x4bc4 0x4bbc 0x4d12 0x4c57 0x4be8 0x4bc0 0x4bbb 0x4d0b 0x4c4d 0x4be3 0x4bbe 0x4bba 0x4d05 0x4c46 0x4bdf 0x4bbd 0x4bb7 0x4cff 0x4c3f 0x4bdb 0x4bbb 0x4bb5 0x4cf7 0x4c3a 0x4bd8 0x4bb9 0x4bb1 0x4ced 0x4c37 0x4bd6 0x4bb7 0x4bae 0x4cdf 0x4c33 0x4bd3 0x4bb5 0x4bab 0x4cce 0x4c2d 0x4bd1 0x4bb2 0x4ba8 0x4cc3 0x4c26 0x4bcc 0x4bac 0x4ba4 0x4cbd 0x4c24 0x4bc8 0x4ba5 0x4b9e 0x4cb9 0x4c27 0x4bcd 0x4ba5 0x4b9e 0x4cb9 0x4c2c 0x4be0 0x4bb2 0x4ba3 0x4cbb 0x4c31 0x4be9 0x4bbb 0x4ba8 0x4cbe 0x4c38 0x4bd8 0x4bb1 0x4ba8 0x4cc5 0x4c3a 0x4bc4 0x4ba0 0x4ba7 0x4cce 0x4c30 0x4bc3 0x4ba4 0x4baa 0x4cd0 0x4c27 0x4bc6 0x4bc4 0x4bbf 0x4ccc 0x4c26 0x4bcb 0x4bd7 0x4bcc 0x4cc6 0x4c27 0x4bdc 0x4bd3 0x4bc7 0x4cc1 0x4c29 0x4bec 0x4bcd 0x4bbf 0x4cba 0x4c2d 0x4beb 0x4bc5 0x4bb8 0x4cb5 0x4c32 0x4be4 0x4bbd 0x4bb3 0x4cb1 0x4c32 0x4bdf 0x4bb5 0x4bac 0x4cad 0x4c31 0x4bda 0x4baf 0x4ba3 0x4ca9 0x4c30 0x4bd6 0x4baa 0x4b9a 0x4ca5 0x4c2c 0x4bd1 0x4ba5 0x4b95 0x4ca1 0x4c27 0x4bcc 0x4b9f 0x4b91 0x4c9c 0x4c22 0x4bc9 0x4b9e 0x4b90 0x4c97 0x4c1e 0x4bc8 0x4b9f 0x4b90 0x4c91 0x4c19 0x4bc7 0x4ba0 0x4b90 0x4c88 0x4c16 0x4bc4 0x4b9f 0x4b93 0x4c7f 0x4c11 0x4bc0 0x4b9e 0x4b98 0x4c75 0x4c0a 0x4bbc 0x4b9f 0x4b9c 0x4c2a 0x4bf0 0x4bb4 0x4b9f 0x4b9c 0x4c15 0x4bde 0x4bac 0x4b93 0x4b90 0x4be8 0x4bdb 0x4ba8 0x4b8f 0x4b8f 0x4b6c 0x4bbf 0x4ba4 0x4b8c 0x4b83 0x4b67 0x4b85 0x4b99 0x4b85 0x4b7f 0x4b5f 0x4b85 0x4b93 0x4b82 0x4b7a 0x4b49 0x4b83 0x4b98 0x4b8e 0x4b85 0x4b58 0x4b7e 0x4b9c 0x4b9d 0x4b93 0x4b69 0x4b79 0x4b97 0x4b9e 0x4b95 0x4b7e 0x4b92 0x4b96 0x4b99 0x4b96 0x4b7e 0x4b92 0x4b96 0x4b99 0x4b96 0x4b7e 0x4b92 0x4b96 0x4b99 0x4b96&gt;;
				};

qcom,pc-temp-v1-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0xac3c 0xaccb 0xad2e 0xad4e 0xad57 0xab5b 0xabe8 0xac43 0xac4e 0xac51 0xaa76 0xab05 0xab6a 0xab76 0xab77 0xa98e 0xaa25 0xaa92 0xaaa8 0xaaad 0xa8a2 0xa945 0xa9b3 0xa9d0 0xa9d6 0xa7b2 0xa85b 0xa8d0 0xa8f3 0xa8f9 0xa6c2 0xa769 0xa7e3 0xa80d 0xa814 0xa5d1 0xa674 0xa6ed 0xa71b 0xa727 0xa4e1 0xa580 0xa5f5 0xa623 0xa635 0xa3f7 0xa48b 0xa4fe 0xa52e 0xa541 0xa311 0xa39d 0xa409 0xa43a 0xa44a 0xa231 0xa2b3 0xa319 0xa349 0xa358 0xa155 0xa1cf 0xa22f 0xa25b 0xa269 0xa080 0xa0f3 0xa14a 0xa170 0xa17f 0x9faf 0xa01c 0xa06b 0xa08f 0xa09d 0x9ee2 0x9f4a 0x9f93 0x9fb3 0x9fc1 0x9e1c 0x9e7c 0x9ec3 0x9ee1 0x9eee 0x9d5b 0x9db8 0x9dfb 0x9e16 0x9e22 0x9ca0 0x9d05 0x9d3e 0x9d55 0x9d5f 0x9bf5 0x9c5d 0x9c97 0x9ca9 0x9caf 0x9b5f 0x9bb0 0x9bed 0x9c02 0x9c07 0x9acd 0x9aff 0x9b08 0x9b2e 0x9b38 0x9a33 0x9a41 0x99e2 0x9a0b 0x9a1e 0x9994 0x994e 0x98fd 0x9914 0x9927 0x98eb 0x9838 0x9867 0x987e 0x988f 0x981f 0x9788 0x97ef 0x9808 0x9816 0x9753 0x972f 0x9784 0x9791 0x979d 0x96d0 0x96eb 0x9726 0x971d 0x9726 0x9676 0x969f 0x96cb 0x96b4 0x96b9 0x9631 0x9656 0x966c 0x9655 0x9658 0x95ff 0x9613 0x9616 0x9601 0x9601 0x95d7 0x95d3 0x95d0 0x95b6 0x95b1 0x95b1 0x9599 0x9594 0x9573 0x9567 0x958e 0x9566 0x955b 0x9533 0x9522 0x956e 0x9539 0x9527 0x94f7 0x94e2 0x954f 0x9511 0x94f5 0x94bd 0x94a3 0x9534 0x94f0 0x94c7 0x9483 0x9461 0x9512 0x94ce 0x949b 0x944a 0x941d 0x94de 0x9497 0x945e 0x9403 0x93cc 0x9498 0x9442 0x9404 0x93a3 0x9365 0x9440 0x93de 0x9399 0x9336 0x92f0 0x93c6 0x9365 0x9326 0x92c6 0x9279 0x933a 0x92d8 0x92a2 0x9247 0x91f7 0x9299 0x922e 0x91fd 0x91a5 0x914f 0x91fd 0x9193 0x9161 0x9112 0x90c3 0x9176 0x9123 0x90f3 0x90b8 0x907a 0x914d 0x90ff 0x90d4 0x9098 0x905a 0x9135 0x90e9 0x90bc 0x9082 0x9045 0x910f 0x90d3 0x90ab 0x906f 0x9030 0x90ee 0x90ae 0x9085 0x9042 0x8ffb 0x90bb 0x9007 0x8fbc 0x8f5d 0x8f07 0x8fe7 0x8e55 0x8e0d 0x8dab 0x8d57 0x8e0f 0x8c0a 0x8bc9 0x8b6b 0x8b19 0x8b8d 0x88d2 0x88ab 0x885b 0x880c 0x8759 0x833d 0x83c8 0x8399 0x8356 0x7530 0x7530 0x7530 0x7530 0x7530&gt;;
				};

qcom,pc-temp-y3-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x3473 0x3457 0x3410 0x33ee 0x33e1 0x33dd 0x3477 0x345a 0x3413 0x33ee 0x33e1 0x33de 0x347d 0x345f 0x3416 0x33ee 0x33e1 0x33df 0x3485 0x3464 0x3419 0x33ee 0x33e2 0x33e0 0x348c 0x3468 0x341c 0x33ef 0x33e3 0x33e1 0x348f 0x346a 0x341e 0x33ef 0x33e3 0x33e2 0x3490 0x346c 0x3420 0x33ef 0x33e4 0x33e2 0x3490 0x346c 0x3422 0x33f0 0x33e5 0x33e3 0x3490 0x346c 0x3423 0x33f1 0x33e6 0x33e3 0x348e 0x3469 0x3425 0x33f1 0x33e6 0x33e4 0x348c 0x3467 0x3426 0x33f2 0x33e6 0x33e4 0x3492 0x346e 0x3427 0x33f2 0x33e6 0x33e5 0x34a1 0x3479 0x3427 0x33f2 0x33e7 0x33e5 0x34a4 0x3475 0x3426 0x33f3 0x33e7 0x33e6 0x3483 0x3456 0x3421 0x33f6 0x33e7 0x33e6 0x3462 0x3441 0x341d 0x33f8 0x33e8 0x33e6 0x3463 0x3448 0x341a 0x33f8 0x33ea 0x33e6 0x346b 0x3453 0x3418 0x33f9 0x33ec 0x33e6 0x346e 0x3453 0x3416 0x33f8 0x33ed 0x33e8 0x3465 0x3444 0x3415 0x33f7 0x33ee 0x33eb 0x3459 0x3436 0x3412 0x33f6 0x33ee 0x33ec 0x3453 0x3431 0x340d 0x33f4 0x33ec 0x33ea 0x3450 0x342d 0x3408 0x33f1 0x33e8 0x33e6 0x344d 0x3428 0x3405 0x33ed 0x33e5 0x33e3 0x344a 0x3422 0x3404 0x33ea 0x33e1 0x33e0 0x3447 0x341d 0x3402 0x33e8 0x33e0 0x33df 0x343f 0x341a 0x3400 0x33e8 0x33e0 0x33df 0x342a 0x3416 0x33ff 0x33e8 0x33e0 0x33df 0x341e 0x340f 0x33fd 0x33e8 0x33df 0x33df 0x3423 0x33fa 0x33fc 0x33e9 0x33df 0x33de 0x342e 0x33ed 0x33fb 0x33e9 0x33de 0x33de 0x3437 0x33f7 0x33fa 0x33e8 0x33df 0x33de 0x3441 0x340b 0x33f9 0x33e8 0x33df 0x33de 0x344d 0x341b 0x33fa 0x33e7 0x33df 0x33de 0x345c 0x342a 0x33fc 0x33e7 0x33e0 0x33e0 0x346d 0x343c 0x33fe 0x33e7 0x33e0 0x33e0 0x3482 0x344f 0x3400 0x33e7 0x33e0 0x33df 0x349a 0x3465 0x3403 0x33e7 0x33df 0x33de 0x34b6 0x3484 0x3406 0x33e7 0x33df 0x33de 0x34d4 0x34b2 0x3409 0x33e7 0x33e0 0x33de 0x34f7 0x34ea 0x340d 0x33e8 0x33e0 0x33df 0x351d 0x352c 0x3411 0x33ea 0x33e2 0x33e0 0x3544 0x3579 0x3418 0x33eb 0x33e1 0x33e0 0x3577 0x35ce 0x3421 0x33ea 0x33df 0x33dd 0x35bb 0x3639 0x3436 0x33ea 0x33de 0x33dc 0x362f 0x366d 0x344a 0x33ec 0x33e3 0x33e1 0x3658 0x36b9 0x3467 0x33f0 0x33e6 0x33e4 0x3694 0x3719 0x348b 0x33f4 0x33e9 0x33e6 0x3736 0x377d 0x34e4 0x33f8 0x33ea 0x33e8 0x3870 0x381f 0x356e 0x33fb 0x33ea 0x33e6 0x3c9b 0x39b3 0x3666 0x33fa 0x33e6 0x33e4 0x4b24 0x41ea 0x37f6 0x33fb 0x33e5 0x33e3 0x7284 0x6594 0x3c35 0x3406 0x33e9 0x33e6 0xffff 0xffff 0x5ca9 0x341a 0x33f0 0x33ef 0xffff 0xffff 0x5ca9 0x341a 0x33f0 0x33ef 0xffff 0xffff 0x5ca9 0x341a 0x33f0 0x33ef&gt;;
				};

qcom,pc-temp-z4-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x3deb 0x3b60 0x3a1b 0x3a2c 0x39bc 0x3ef6 0x3bc6 0x3b0a 0x3a3d 0x3a0c 0x3e3a 0x3bdd 0x3abe 0x3a22 0x39fd 0x3d5d 0x3b88 0x3a68 0x39f4 0x39db 0x3cb5 0x3b02 0x3a33 0x39d6 0x39c3 0x3c19 0x3aa5 0x3a06 0x39be 0x39af 0x3ba0 0x3a64 0x39e2 0x39aa 0x399e 0x3b42 0x3a31 0x39c3 0x3994 0x398c 0x3af4 0x3a09 0x39ab 0x3983 0x397e 0x3ab2 0x39e9 0x399a 0x397b 0x3977 0x3a7a 0x39cf 0x398c 0x3976 0x3973 0x3a4b 0x39b7 0x3984 0x3972 0x3970 0x3a23 0x39a6 0x3980 0x396d 0x396d 0x3a02 0x399e 0x397c 0x3969 0x3969 0x39e5 0x3999 0x3977 0x3964 0x3966 0x39c8 0x3995 0x3972 0x395f 0x3963 0x39b9 0x3992 0x396e 0x395b 0x3960 0x39ba 0x3990 0x396b 0x3957 0x395d 0x39c0 0x398a 0x3967 0x3954 0x395a 0x39c1 0x3982 0x3963 0x3950 0x3954 0x39b2 0x397f 0x3960 0x394d 0x394e 0x39a1 0x3981 0x396d 0x3954 0x3954 0x399f 0x3986 0x39a4 0x398e 0x3991 0x39a0 0x39a6 0x39cc 0x39bc 0x39c0 0x39a1 0x39ee 0x39e1 0x39c3 0x39bb 0x39c2 0x3a0a 0x39ed 0x39c7 0x39ae 0x39f3 0x39ff 0x39e8 0x39be 0x399b 0x39ff 0x39ee 0x39d1 0x398d 0x397a 0x39ff 0x39df 0x39b9 0x396c 0x3964 0x39fe 0x39cf 0x399e 0x3967 0x3960 0x39f9 0x39c0 0x3988 0x3963 0x395d 0x39eb 0x39b1 0x3980 0x3961 0x3959 0x39de 0x39a5 0x397c 0x395e 0x3955 0x39d3 0x399e 0x397a 0x395c 0x3952 0x39c8 0x3999 0x3979 0x395a 0x394f 0x39bc 0x3995 0x3978 0x3959 0x394e 0x39b0 0x3990 0x3977 0x3959 0x394e 0x39a5 0x398c 0x3975 0x395a 0x394e 0x3999 0x3989 0x3975 0x395c 0x394f 0x398e 0x3987 0x3977 0x3963 0x395b 0x3988 0x3985 0x397a 0x396a 0x3966 0x3984 0x397c 0x3975 0x3967 0x3962 0x397d 0x3971 0x396b 0x3961 0x3959 0x396c 0x396a 0x3966 0x395f 0x395e 0x3967 0x3957 0x3957 0x3957 0x3959 0x3968 0x394c 0x3944 0x3945 0x3941 0x3997 0x3948 0x3940 0x3942 0x393b 0x3a1e 0x395b 0x3939 0x3939 0x3937 0x3a20 0x3995 0x3936 0x392d 0x3929 0x3a24 0x398d 0x3933 0x3924 0x3920 0x3a35 0x3991 0x393b 0x3937 0x393e 0x3a23 0x39a6 0x3945 0x393b 0x3945 0x3a28 0x39b2 0x394c 0x393e 0x394b 0x3a2b 0x39a5 0x3950 0x3945 0x394b 0x3a2b 0x39a5 0x3950 0x3945 0x394b 0x3a2b 0x39a5 0x3950 0x3945 0x394b&gt;;
				};

qcom,pc-temp-v2-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0xad43 0xad39 0xad2a 0xad1b 0xacf3 0xacee 0xac0a 0xabff 0xac0e 0xac09 0xabe5 0xabdd 0xaaed 0xaae2 0xab05 0xab05 0xaae5 0xaadd 0xa9f2 0xa9e6 0xaa13 0xaa15 0xa9f9 0xa9f1 0xa91a 0xa90b 0xa938 0xa938 0xa91f 0xa919 0xa843 0xa82f 0xa858 0xa856 0xa840 0xa83d 0xa75c 0xa73e 0xa766 0xa767 0xa753 0xa752 0xa66d 0xa646 0xa66e 0xa673 0xa661 0xa660 0xa57c 0xa54d 0xa575 0xa57d 0xa56d 0xa56d 0xa485 0xa44f 0xa47b 0xa485 0xa476 0xa477 0xa38f 0xa35d 0xa384 0xa391 0xa382 0xa384 0xa2a1 0xa280 0xa293 0xa29f 0xa293 0xa295 0xa1b7 0xa1ac 0xa1a7 0xa1b2 0xa1a7 0xa1aa 0xa0c7 0xa0d9 0xa0bf 0xa0cc 0xa0c1 0xa0c4 0x9fd2 0xa006 0x9fde 0x9fec 0x9fe0 0x9fe3 0x9ed8 0x9f2c 0x9f09 0x9f13 0x9f08 0x9f0a 0x9dcf 0x9e46 0x9e4b 0x9e41 0x9e38 0x9e38 0x9cbc 0x9d53 0x9d8b 0x9d75 0x9d70 0x9d6f 0x9bc3 0x9c54 0x9cab 0x9cb9 0x9cb6 0x9cb5 0x9aed 0x9b41 0x9baf 0x9c07 0x9c04 0x9c07 0x9a27 0x9a42 0x9aba 0x9b3c 0x9b41 0x9b49 0x9968 0x996a 0x99c6 0x9a3c 0x9a58 0x9a69 0x98b4 0x98a9 0x98e5 0x993e 0x996d 0x9984 0x9809 0x97f3 0x982a 0x9871 0x989c 0x98b4 0x9769 0x974c 0x9788 0x97bc 0x97da 0x97ed 0x96d0 0x96aa 0x96f4 0x9724 0x973d 0x974c 0x9637 0x9600 0x966c 0x96a5 0x96bf 0x96cc 0x959a 0x9560 0x95f0 0x9635 0x9652 0x965d 0x9521 0x94f3 0x9582 0x95cf 0x95eb 0x95f4 0x94d1 0x94a5 0x951d 0x9571 0x958c 0x9593 0x9493 0x9467 0x94bd 0x951a 0x9537 0x953c 0x9456 0x9435 0x945d 0x94c9 0x94ec 0x94ef 0x941d 0x940b 0x940e 0x947d 0x94a4 0x94a6 0x93e4 0x93de 0x93dc 0x9437 0x945f 0x945f 0x93ac 0x93b2 0x93b6 0x93f5 0x941c 0x9419 0x9374 0x9383 0x938d 0x93b0 0x93cd 0x93c3 0x9338 0x9351 0x9364 0x9369 0x936e 0x9352 0x92f9 0x931b 0x9335 0x931f 0x930c 0x92e0 0x92b3 0x92da 0x92f9 0x92d2 0x92b1 0x9280 0x9266 0x928d 0x92b0 0x9282 0x9256 0x9227 0x9210 0x9235 0x9256 0x922d 0x91fb 0x91cc 0x91b8 0x91cd 0x91df 0x91d0 0x91a1 0x9172 0x915e 0x9153 0x9152 0x9157 0x912b 0x90fd 0x9106 0x90c4 0x90ab 0x90c4 0x9098 0x9063 0x90b3 0x9035 0x900c 0x903f 0x9022 0x8fef 0x9064 0x8fbb 0x8fa7 0x9005 0x8ff4 0x8fc2 0x9039 0x8f91 0x8f85 0x8ff8 0x8feb 0x8fb8 0x900a 0x8f71 0x8f63 0x8fe4 0x8fde 0x8faa 0x8fd9 0x8f4e 0x8f32 0x8fc6 0x8fc6 0x8f92 0x8fa7 0x8f2a 0x8ed1 0x8f7a 0x8f85 0x8f4c 0x8f6e 0x8eeb 0x8df6 0x8e81 0x8e74 0x8e29 0x8f14 0x8e17 0x8c27 0x8c82 0x8c8a 0x8c45 0x8e5c 0x8bf5 0x898d 0x89eb 0x8a08 0x89c6 0x8cda 0x88ab 0x8586 0x8644 0x868e 0x8652 0x89ed 0x835b 0x7ef2 0x80a5 0x814a 0x8120 0x8636 0x7db4 0x6bec 0x6bcc 0x6e89 0x71d2&gt;;
				};

qcom,fcc1-temp-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-data = &lt;0x12cd 0x1366 0x13d6 0x13f6 0x13ff&gt;;
				};

qcom,pc-temp-y4-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x412c 0x4135 0x40c2 0x406f 0x4049 0x4048 0x4159 0x4164 0x40e7 0x4070 0x404b 0x404a 0x4197 0x41ab 0x410d 0x4072 0x404c 0x404c 0x41d9 0x41f6 0x412f 0x4072 0x404d 0x404d 0x4211 0x4232 0x4146 0x4073 0x404e 0x404e 0x4230 0x424b 0x414f 0x4073 0x404e 0x404e 0x423b 0x4245 0x4149 0x4073 0x404d 0x404d 0x4241 0x423b 0x413e 0x4072 0x404c 0x404c 0x4242 0x4238 0x4135 0x4072 0x404c 0x404c 0x4241 0x4237 0x412e 0x4074 0x404e 0x404c 0x423f 0x4237 0x412b 0x4076 0x4050 0x404c 0x422f 0x4238 0x412d 0x407b 0x4053 0x404c 0x420f 0x423c 0x4133 0x4082 0x4056 0x404e 0x4208 0x4251 0x413f 0x4087 0x4059 0x404f 0x423f 0x42a7 0x4159 0x408c 0x405e 0x4052 0x4275 0x42df 0x4177 0x4093 0x4063 0x4056 0x4250 0x42b6 0x41a0 0x40a3 0x4068 0x405b 0x41dd 0x4260 0x41c2 0x40b8 0x4070 0x4061 0x419d 0x4219 0x41b5 0x40d7 0x4080 0x406c 0x418e 0x41d5 0x4180 0x4100 0x409b 0x407d 0x4183 0x41a0 0x414b 0x410a 0x40a5 0x4084 0x4173 0x417f 0x4117 0x40db 0x409c 0x4084 0x4160 0x4166 0x40eb 0x40a1 0x408e 0x4083 0x414b 0x414c 0x40d5 0x4082 0x4077 0x4077 0x412e 0x4133 0x40c5 0x406b 0x4058 0x4058 0x4114 0x4115 0x40ba 0x4065 0x404e 0x404b 0x410a 0x40e0 0x40b1 0x4064 0x404e 0x404a 0x4104 0x40a8 0x40aa 0x4064 0x404e 0x4049 0x4102 0x40a5 0x40a4 0x4067 0x4050 0x404a 0x4111 0x40cd 0x409e 0x406c 0x4056 0x404e 0x412c 0x40ea 0x4095 0x4071 0x405c 0x4054 0x413c 0x40e9 0x407f 0x4075 0x4065 0x405b 0x4146 0x40e7 0x4070 0x4078 0x406c 0x4064 0x414d 0x40f1 0x4074 0x407a 0x4073 0x406d 0x4154 0x4104 0x4080 0x407a 0x4079 0x4076 0x4159 0x4118 0x408f 0x4079 0x4079 0x4077 0x415e 0x412c 0x40a3 0x406d 0x406d 0x4068 0x4162 0x413d 0x40b9 0x4063 0x4062 0x405c 0x4164 0x4141 0x40cd 0x4061 0x405c 0x405c 0x4160 0x4141 0x40e0 0x4060 0x4058 0x405f 0x4157 0x4140 0x40eb 0x4063 0x4059 0x4063 0x4152 0x413c 0x40f0 0x406e 0x4060 0x406d 0x4151 0x4132 0x40f2 0x4071 0x405e 0x406b 0x4154 0x4125 0x40f3 0x4071 0x404c 0x404f 0x4167 0x4117 0x40f0 0x406a 0x403d 0x403a 0x4177 0x4106 0x40ea 0x406b 0x4047 0x404d 0x4175 0x4109 0x40fc 0x407a 0x4060 0x406d 0x416e 0x4114 0x4128 0x408e 0x4082 0x4092 0x417b 0x4125 0x413e 0x40b3 0x40a7 0x40b5 0x418a 0x413c 0x416f 0x40d1 0x40ba 0x40c5 0x41d6 0x4158 0x41a1 0x40c8 0x4074 0x406d 0x4399 0x4210 0x41b0 0x40a7 0x405a 0x405c 0x490a 0x477c 0x4233 0x40c8 0x405d 0x405b 0x5dd2 0x7d98 0x538d 0x40fa 0x4066 0x405a 0x5dd2 0x7d98 0x538d 0x40fa 0x4066 0x405a 0x5dd2 0x7d98 0x538d 0x40fa 0x4066 0x405a&gt;;
				};

qcom,pc-temp-z1-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x2fac 0x2dba 0x2bfe 0x2af9 0x2a90 0x2fa4 0x2da6 0x2c0d 0x2ae6 0x2a7d 0x2f98 0x2d94 0x2bf4 0x2ada 0x2a76 0x2f8c 0x2d85 0x2bdf 0x2ad0 0x2a72 0x2f7f 0x2d78 0x2bd6 0x2ac9 0x2a6d 0x2f74 0x2d6d 0x2bcf 0x2ac2 0x2a68 0x2f6c 0x2d63 0x2bc5 0x2abd 0x2a64 0x2f5e 0x2d59 0x2bb4 0x2ab7 0x2a61 0x2f4d 0x2d4d 0x2ba8 0x2ab3 0x2a5f 0x2f3c 0x2d41 0x2ba4 0x2ab1 0x2a5d 0x2f26 0x2d35 0x2ba2 0x2ab0 0x2a5c 0x2f16 0x2d27 0x2ba1 0x2aaf 0x2a5b 0x2f0d 0x2d1e 0x2ba1 0x2aad 0x2a5b 0x2f07 0x2d23 0x2ba0 0x2aac 0x2a5a 0x2f01 0x2d2c 0x2b9f 0x2aac 0x2a5b 0x2ef4 0x2d2f 0x2b9d 0x2aac 0x2a5b 0x2ee9 0x2d2d 0x2b9d 0x2aad 0x2a5b 0x2eea 0x2d2c 0x2b9d 0x2aad 0x2a5d 0x2eed 0x2d2b 0x2b9d 0x2aae 0x2a5e 0x2ef1 0x2d2a 0x2b9f 0x2ab0 0x2a5f 0x2f0d 0x2d2a 0x2ba2 0x2ab2 0x2a60 0x2f2c 0x2d2f 0x2ba4 0x2ab2 0x2a61 0x2f29 0x2d34 0x2ba6 0x2ab2 0x2a63 0x2f0f 0x2d36 0x2ba8 0x2ab2 0x2a66 0x2efc 0x2d38 0x2ba9 0x2ab4 0x2a67 0x2f00 0x2d3b 0x2baa 0x2ab9 0x2a69 0x2f09 0x2d3e 0x2bae 0x2abd 0x2a6b 0x2f0e 0x2d43 0x2bb4 0x2ac1 0x2a6e 0x2f2e 0x2d47 0x2bb8 0x2ac4 0x2a71 0x2f4b 0x2d4d 0x2bb9 0x2ac7 0x2a73 0x2f40 0x2d52 0x2bbb 0x2aca 0x2a76 0x2f1f 0x2d56 0x2bbe 0x2acd 0x2a79 0x2f17 0x2d59 0x2bc4 0x2ad0 0x2a7c 0x2f8a 0x2d5d 0x2bc9 0x2ad3 0x2a7f 0x3014 0x2d61 0x2bcc 0x2ad7 0x2a83 0x300d 0x2d65 0x2bcf 0x2adb 0x2a86 0x2f8f 0x2d6d 0x2bd4 0x2ae0 0x2a8a 0x2f41 0x2d76 0x2bd9 0x2ae3 0x2a8d 0x2f4b 0x2d7f 0x2bdf 0x2ae7 0x2a90 0x2f5b 0x2d89 0x2be6 0x2aec 0x2a93 0x2f68 0x2d91 0x2bed 0x2af0 0x2a96 0x2f74 0x2d98 0x2bf2 0x2af3 0x2a9a 0x2f80 0x2d9e 0x2bf7 0x2af7 0x2a9d 0x2f8b 0x2da7 0x2bff 0x2afa 0x2a9f 0x2fa2 0x2da7 0x2c06 0x2afe 0x2aa2 0x3005 0x2daf 0x2c08 0x2b02 0x2aa3 0x3084 0x2da7 0x2c0c 0x2b02 0x2aa3 0x2f98 0x2dae 0x2c0f 0x2b01 0x2aa3 0x2fa0 0x2dab 0x2c07 0x2b03 0x2aa5 0x2fb9 0x2db8 0x2c0e 0x2b09 0x2aa8 0x2fcc 0x2dca 0x2c1e 0x2b0e 0x2aad 0x2fc7 0x2dcf 0x2c1e 0x2b16 0x2ab4 0x2fcc 0x2dd3 0x2c2f 0x2b1f 0x2abc 0x2fd6 0x2e0b 0x2c3b 0x2b2d 0x2ac9 0x2fd6 0x2e0b 0x2c3b 0x2b2d 0x2ac9 0x2fd6 0x2e0b 0x2c3b 0x2b2d 0x2ac9&gt;;
				};

qcom,pc-temp-z5-lut {
					qcom,lut-col-legend = &lt;0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x318d 0x3ac2 0x3d1b 0x383a 0x3947 0x342e 0x3bdd 0x3c8e 0x435b 0x44b4 0x36eb 0x3d43 0x421d 0x470b 0x4ad2 0x3965 0x3f3e 0x45f5 0x4a9f 0x4e64 0x3b56 0x41ed 0x47ca 0x4d19 0x52ee 0x3d07 0x446a 0x4912 0x4ecb 0x580c 0x3eba 0x4698 0x4b31 0x50d3 0x5c94 0x407e 0x48ea 0x4ebd 0x5616 0x6034 0x427a 0x4ba1 0x523b 0x5bc7 0x6379 0x44eb 0x4ea8 0x554a 0x5cdc 0x66c6 0x47d8 0x5206 0x57e2 0x5c4f 0x6a10 0x4b22 0x561c 0x58b0 0x5cf6 0x6d53 0x4ef4 0x598f 0x5898 0x601b 0x7119 0x539a 0x5b9a 0x58c3 0x63e1 0x7498 0x59de 0x5d49 0x5a4a 0x6735 0x7730 0x63dd 0x5f70 0x5cd9 0x6b37 0x7985 0x6a44 0x637a 0x5f99 0x6f5a 0x7acd 0x6820 0x668b 0x62e4 0x74f1 0x7fdb 0x62dc 0x66a2 0x65f6 0x7862 0x846d 0x60eb 0x6609 0x67f2 0x75cb 0x85b9 0x648f 0x674a 0x6a51 0x70e2 0x880a 0x6b8d 0x79c7 0x79cf 0x72e6 0x88a9 0x76b6 0x8ed5 0xa69a 0x87ae 0x8847 0x8b40 0x9709 0xbaad 0x9604 0x877c 0xa16f 0x9d17 0x8e5e 0x79b4 0x739a 0xbbcc 0x9d8b 0x5971 0x4cb5 0x51b8 0xd3c2 0x8655 0x5152 0x4960 0x4f41 0xd6ae 0x6dc1 0x4f31 0x615a 0x695d 0xc767 0x6b24 0x4f81 0x72c9 0x7b87 0xb522 0x6abd 0x62ca 0x784e 0x7dc0 0xa7a7 0x6aec 0x791b 0x7b8e 0x7eab 0x9b62 0x73ae 0x7ecd 0x7ad0 0x7f2f 0x94d8 0x810a 0x8173 0x76d8 0x80aa 0x919c 0x8bae 0x84ef 0x7507 0x8068 0x8fb1 0x960a 0x8b12 0x7782 0x7923 0x8f40 0x9a78 0x8f6e 0x7a32 0x714f 0x8f3c 0x9aa5 0x8e98 0x7959 0x7090 0x8f88 0x9a32 0x8c20 0x7679 0x7099 0x944f 0x990d 0x8ad0 0x7573 0x7076 0x9b91 0x9617 0x8a51 0x763f 0x6e2c 0x9cbe 0x92d5 0x895a 0x76fe 0x6bea 0x985a 0x8f95 0x8330 0x7268 0x6da7 0x979b 0x8c6b 0x7a38 0x6a8c 0x73ab 0x9edf 0x88b7 0x764b 0x7067 0x823d 0x7c4a 0x8194 0x7896 0x769c 0x8930 0x6b34 0x75c9 0x7b1c 0x6714 0x6f17 0x59da 0x70ac 0x7113 0x5f00 0x66e3 0x3069 0x4e21 0x6f67 0x5f22 0x560a 0x2fe4 0x374a 0x5ddb 0x6180 0x6114 0x2f2c 0x3822 0x5ab4 0x6b05 0x70c7 0x2dd3 0x3789 0x5cd0 0x6e4c 0x688e 0x2f0a 0x3507 0x526f 0x67a9 0x5b09 0x2f80 0x336f 0x48eb 0x5d36 0x4fd8 0x3183 0x3708 0x4571 0x4b6b 0x45c3 0x3183 0x3708 0x4571 0x4b6b 0x45c3 0x3183 0x3708 0x4571 0x4b6b 0x45c3&gt;;
				};

qcom,fcc2-temp-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-data = &lt;0x1344 0x1395 0x13d2 0x13dc 0x13d3 0x13cc&gt;;
				};

qcom,pc-temp-y1-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x1697 0x1559 0x148e 0x1385 0x12db 0x12a2 0x16a9 0x1561 0x1483 0x1380 0x12dc 0x12a1 0x16b6 0x1566 0x1478 0x137c 0x12dc 0x12a1 0x16bf 0x156a 0x146e 0x1377 0x12db 0x12a1 0x16c4 0x156c 0x1466 0x1374 0x12db 0x12a0 0x16c6 0x156e 0x1463 0x1371 0x12da 0x12a0 0x16c1 0x1578 0x1464 0x136f 0x12d9 0x129f 0x16b7 0x1587 0x1466 0x136e 0x12d7 0x129f 0x16b3 0x1587 0x1465 0x136d 0x12d5 0x129e 0x16b1 0x1572 0x145f 0x136d 0x12d4 0x129d 0x16af 0x1563 0x145b 0x136c 0x12d3 0x129d 0x16ae 0x1561 0x145d 0x1369 0x12d2 0x129c 0x16ac 0x1560 0x145e 0x1365 0x12d2 0x129c 0x16ac 0x155f 0x145e 0x1364 0x12d1 0x129c 0x16ae 0x155f 0x145e 0x1363 0x12d1 0x129c 0x16b0 0x155f 0x145e 0x1363 0x12d1 0x129d 0x16b4 0x1563 0x145f 0x1362 0x12d0 0x129c 0x16b9 0x1568 0x1460 0x1361 0x12d0 0x129c 0x16bc 0x1569 0x1461 0x1362 0x12d0 0x129c 0x16bb 0x1569 0x1463 0x1364 0x12d0 0x129d 0x16b9 0x1569 0x1464 0x1365 0x12d1 0x129e 0x16b9 0x156a 0x1466 0x1367 0x12d2 0x129f 0x16b8 0x156e 0x1468 0x1369 0x12d4 0x12a0 0x16b7 0x1572 0x1469 0x136c 0x12d5 0x12a2 0x16b3 0x157c 0x1469 0x136f 0x12d8 0x12a5 0x16af 0x1582 0x1469 0x1371 0x12da 0x12a6 0x16b2 0x157b 0x1468 0x1372 0x12dc 0x12a7 0x16c0 0x1571 0x1468 0x1373 0x12dd 0x12a7 0x16c7 0x156d 0x146a 0x1375 0x12df 0x12a8 0x16bd 0x156b 0x146e 0x1379 0x12e0 0x12ab 0x16ae 0x156b 0x1470 0x137c 0x12e2 0x12ad 0x16ab 0x1573 0x146f 0x1381 0x12e5 0x12ae 0x16b0 0x1582 0x146e 0x1384 0x12e8 0x12b0 0x16b4 0x1585 0x1471 0x1384 0x12ea 0x12b2 0x16b1 0x157a 0x1474 0x1383 0x12ed 0x12b5 0x16aa 0x1571 0x1476 0x1384 0x12ef 0x12b7 0x16a9 0x1572 0x1478 0x138a 0x12f1 0x12b8 0x16ac 0x1574 0x1479 0x138d 0x12f2 0x12b9 0x16ae 0x1575 0x1478 0x138c 0x12f3 0x12ba 0x16ab 0x1575 0x1477 0x138b 0x12f3 0x12bb 0x16a4 0x1577 0x1478 0x138c 0x12f4 0x12bc 0x16a4 0x1577 0x147d 0x1390 0x12f5 0x12bd 0x16bc 0x1576 0x147e 0x1394 0x12f6 0x12be 0x16c5 0x1578 0x147f 0x1399 0x12f7 0x12c1 0x16aa 0x157c 0x1485 0x13a0 0x12fd 0x12c4 0x16c5 0x158f 0x1491 0x13a7 0x1300 0x12c6 0x16d4 0x1597 0x1491 0x13a7 0x1300 0x12c7 0x16e6 0x15a2 0x1499 0x13a7 0x1301 0x12c7 0x16f1 0x15a6 0x149b 0x13a6 0x1304 0x12c7 0x171a 0x15a5 0x1492 0x13ab 0x1301 0x12c8 0x1708 0x15aa 0x14a9 0x13ab 0x1302 0x12ca 0x175a 0x15cd 0x14bc 0x13b5 0x1309 0x12cd 0x177f 0x160e 0x14f4 0x13c5 0x130f 0x12d4 0x17cb 0x162a 0x151f 0x13d9 0x1318 0x12dc 0x17cb 0x162a 0x151f 0x13d9 0x1318 0x12dc 0x17cb 0x162a 0x151f 0x13d9 0x1318 0x12dc&gt;;
				};

qcom,pc-temp-y5-lut {
					qcom,lut-col-legend = &lt;0xfffffff6 0x00 0x0a 0x19 0x28 0x32&gt;;
					qcom,lut-row-legend = &lt;0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00&gt;;
					qcom,lut-data = &lt;0x3956 0x39ed 0x4452 0x5a3e 0x51bf 0x49a6 0x3b55 0x3bb4 0x44cb 0x55c8 0x4fa5 0x4c20 0x3d43 0x3d82 0x4540 0x50e4 0x4db3 0x4e85 0x3f0f 0x3f35 0x45b0 0x4c2f 0x4c0f 0x508f 0x40a7 0x40ac 0x461b 0x4845 0x4adf 0x51f6 0x41fa 0x41c4 0x4682 0x45c4 0x4a45 0x5275 0x4302 0x42a4 0x46f9 0x4480 0x4a7a 0x5219 0x43e1 0x4348 0x4759 0x438a 0x4acd 0x5154 0x44b1 0x4322 0x4735 0x422e 0x49c6 0x503f 0x454e 0x41cf 0x463f 0x4060 0x467a 0x4e68 0x4632 0x40f1 0x4507 0x3ec2 0x43b3 0x4cb5 0x4af0 0x43b8 0x43a4 0x3c86 0x4203 0x4b38 0x5398 0x4828 0x41e2 0x3a96 0x406c 0x499a 0x55e0 0x4838 0x3f35 0x3ab4 0x3ea7 0x4790 0x4cdd 0x438e 0x3b62 0x3bb7 0x3cb5 0x446a 0x43fe 0x406c 0x39f0 0x3c1c 0x3bfc 0x41a5 0x48b5 0x4a9b 0x3e4e 0x3aaf 0x3c86 0x3f01 0x573a 0x5af4 0x456c 0x3928 0x3d33 0x3d16 0x5d38 0x5d3d 0x4c4f 0x3a18 0x3d05 0x3d25 0x5861 0x5718 0x53db 0x3e1a 0x3c0e 0x3e23 0x52e7 0x52e5 0x5737 0x43e8 0x3c8f 0x3ff1 0x52ca 0x54b4 0x5800 0x50d0 0x4914 0x4925 0x54b2 0x5806 0x585e 0x5b38 0x55b9 0x5282 0x56a6 0x59ac 0x5918 0x58b7 0x54a8 0x5372 0x5899 0x5a99 0x5aea 0x519b 0x4f69 0x5326 0x5a27 0x5b38 0x5ba3 0x4f2f 0x4c69 0x5273 0x561b 0x59b4 0x5acd 0x4f2d 0x4afe 0x50b7 0x435d 0x5558 0x5a1f 0x4f4d 0x49b2 0x4e3f 0x367d 0x4e9b 0x5c17 0x506a 0x475a 0x4ac9 0x3455 0x3dd3 0x6028 0x5292 0x4391 0x4657 0x3322 0x33c5 0x611e 0x53a2 0x426e 0x446a 0x32fa 0x34ee 0x5d4e 0x545b 0x4334 0x43d2 0x3326 0x36fc 0x58d5 0x5564 0x4494 0x438c 0x3371 0x3784 0x5678 0x580b 0x47d6 0x4693 0x3431 0x37b0 0x5492 0x5bc4 0x4d72 0x4ddd 0x356a 0x37f1 0x523e 0x5d7f 0x5221 0x51a5 0x3668 0x387a 0x4ef5 0x5e5f 0x565f 0x5307 0x3765 0x3940 0x4cb0 0x5e3b 0x5966 0x542b 0x37f7 0x3a27 0x4bc0 0x5a23 0x5b01 0x5604 0x37e9 0x3b78 0x4ad4 0x5479 0x5c13 0x5826 0x37b2 0x3c3b 0x4a38 0x5360 0x5c1e 0x590f 0x3737 0x3bd6 0x49d5 0x53cd 0x5b2a 0x5965 0x353f 0x3ae6 0x47cc 0x51d8 0x5a35 0x5a21 0x33c1 0x394d 0x41b7 0x4d02 0x5804 0x5cb0 0x3228 0x3890 0x3cd3 0x49df 0x4b8d 0x4dbd 0x32aa 0x36a6 0x39f4 0x4b6e 0x4d2e 0x496e 0x32b7 0x36cd 0x396d 0x4d24 0x495b 0x4246 0x32f5 0x373e 0x36f4 0x4a75 0x44d3 0x3d59 0x336b 0x36b3 0x38fe 0x48ca 0x4102 0x3b81 0x3428 0x370c 0x387f 0x4795 0x3fbe 0x39db 0x32c0 0x37ad 0x380c 0x472c 0x404e 0x3fd8 0x2b6e 0x3032 0x360f 0x4a23 0x43c7 0x3e37 0x2655 0x2694 0x324e 0x4889 0x46ef 0x3ed2 0x2442 0x23ae 0x2540 0x4791 0x51a6 0x4e27 0x2442 0x23ae 0x2540 0x4791 0x51a6 0x4e27 0x2442 0x23ae 0x2540 0x4791 0x51a6 0x4e27&gt;;
				};
			};
		};

jtagmm@7440000 {
			clock-names = &quot;core_clk&quot;;
			reg-names = &quot;etm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			compatible = &quot;qcom,jtagv8-mm&quot;;
			qcom,coresight-jtagmm-cpu = &lt;0x15&gt;;
			reg = &lt;0x7440000 0x1000&gt;;
			phandle = &lt;0x2ac&gt;;
		};

interrupt-controller@b220000 {
			interrupt-parent = &lt;0x1a&gt;;
			compatible = &quot;qcom,pdc-sdmmagpie&quot;;
			#interrupt-cells = &lt;0x03&gt;;
			reg = &lt;0xb220000 0x400&gt;;
			phandle = &lt;0x01&gt;;
			interrupt-controller;
		};

kryo-erp {
			interrupts = &lt;0x01 0x06 0x04 0x00 0x23 0x04&gt;;
			compatible = &quot;arm,arm64-kryo-cpu-erp&quot;;
			interrupt-names = &quot;l1-l2-faultirq\0l3-scu-faultirq&quot;;
		};

qusb@88e2000 {
			qcom,vdd-voltage-level = &lt;0x00 0xd6d80 0xd6d80&gt;;
			clock-names = &quot;ref_clk_src\0cfg_ahb_clk&quot;;
			reg-names = &quot;qusb_phy_base\0efuse_addr\0refgen_north_bg_reg_addr&quot;;
			qcom,qusb-phy-reg-offset = &lt;0x240 0x1a0 0x210 0x230 0xa8 0x254 0x198 0x27c 0x280 0x284 0x288 0x2a0&gt;;
			qcom,qusb-phy-init-seq = &lt;0x23 0x210 0x03 0x04 0x7c 0x18c 0x80 0x2c 0x0a 0x184 0x19 0xb4 0x40 0x194 0x16 0x198 0x21 0x214 0x08 0x220 0x58 0x224 0x07 0x240 0x29 0x244 0xca 0x248 0x07 0x24c 0x03 0x250 0x30 0x23c 0x22 0x210&gt;;
			phy_type = &quot;utmi&quot;;
			resets = &lt;0x27 0x09&gt;;
			clocks = &lt;0x2f 0x00 0x27 0x97&gt;;
			vdd-supply = &lt;0x1a9&gt;;
			compatible = &quot;qcom,qusb2phy-v2&quot;;
			qcom,efuse-bit-pos = &lt;0x19&gt;;
			reg = &lt;0x88e2000 0x400 0x780200 0x04 0x88e7014 0x04&gt;;
			phandle = &lt;0x25a&gt;;
			qcom,efuse-num-bits = &lt;0x03&gt;;
			qcom,qusb-phy-host-init-seq = &lt;0x23 0x210 0x03 0x04 0x7c 0x18c 0x80 0x2c 0x0a 0x184 0x19 0xb4 0x40 0x194 0x20 0x198 0x21 0x214 0x00 0x220 0x18 0x224 0x37 0x240 0x29 0x244 0xca 0x248 0x04 0x24c 0x03 0x250 0x00 0x23c 0x22 0x210&gt;;
			reset-names = &quot;phy_reset&quot;;
			vdda33-supply = &lt;0xa5&gt;;
			vdda18-supply = &lt;0x1cf&gt;;
		};

qcom,wdt@17c10000 {
			qcom,bark-time = &lt;0x4e20&gt;;
			reg-names = &quot;wdt-base&quot;;
			qcom,scandump-sizes = &lt;0x10100 0x10100 0x10100 0x10100 0x10100 0x10100 0x25900 0x25900&gt;;
			interrupts = &lt;0x00 0x00 0x00 0x00 0x01 0x00&gt;;
			qcom,wakeup-enable;
			compatible = &quot;qcom,msm-watchdog&quot;;
			qcom,ipi-ping;
			qcom,pet-time = &lt;0x3a98&gt;;
			reg = &lt;0x17c10000 0x1000&gt;;
			phandle = &lt;0x2bb&gt;;
		};

cti@6867000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-turing&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6867000 0x1000&gt;;
			phandle = &lt;0x46e&gt;;
		};

cti@6011000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6011000 0x1000&gt;;
			phandle = &lt;0x476&gt;;
		};

qcom,cpu-llcc-ddr-bw {
			qcom,src-dst-ports = &lt;0x81 0x200&gt;;
			governor = &quot;performance&quot;;
			compatible = &quot;qcom,devbw&quot;;
			phandle = &lt;0xbf&gt;;
			qcom,active-only;
			operating-points-v2 = &lt;0xbe&gt;;
		};

demux {
			compatible = &quot;qcom,demux&quot;;
		};

qcom,jpegenc@ac4e000 {
			clock-names = &quot;jpegenc_clk_src\0jpegenc_clk&quot;;
			reg-names = &quot;jpege_hw&quot;;
			reg-cam-base = &lt;0x4e000&gt;;
			cell-index = &lt;0x00&gt;;
			camss-vdd-supply = &lt;0x1ae&gt;;
			interrupts = &lt;0x00 0x1da 0x00&gt;;
			clocks = &lt;0x29 0x4d 0x29 0x4c&gt;;
			clock-cntl-level = &quot;nominal&quot;;
			compatible = &quot;qcom,cam_jpeg_enc&quot;;
			src-clock-name = &quot;jpegenc_clk_src&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;jpeg&quot;;
			reg = &lt;0xac4e000 0x4000&gt;;
			regulator-names = &quot;camss-vdd&quot;;
			phandle = &lt;0x397&gt;;
			clock-rates = &lt;0x23c34600 0x00&gt;;
		};

simtray {
			compatible = &quot;xiaomi,simtray-status&quot;;
			status-gpio = &lt;0x174 0x52 0x00&gt;;
		};

qcom,msm-lsm-client {
			compatible = &quot;qcom,msm-lsm-client&quot;;
			phandle = &lt;0x267&gt;;
		};

tpda@7862000 {
			arm,primecell-periphid = &lt;0x3b969&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpda-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpda-apss&quot;;
			qcom,dsb-elem-size = &lt;0x00 0x20&gt;;
			compatible = &quot;arm,primecell&quot;;
			qcom,tpda-atid = &lt;0x42&gt;;
			reg = &lt;0x7862000 0x1000&gt;;
			phandle = &lt;0x435&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x20b&gt;;
						phandle = &lt;0x207&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x20c&gt;;
						phandle = &lt;0x20d&gt;;
					};
				};
			};
		};

ssphy@88e8000 {
			qcom,vbus-valid-override;
			qcom,vdd-voltage-level = &lt;0x00 0xd6d80 0xd6d80&gt;;
			clock-names = &quot;aux_clk\0pipe_clk\0ref_clk_src\0ref_clk\0com_aux_clk\0cfg_ahb_clk&quot;;
			reg-names = &quot;qmp_phy_base&quot;;
			resets = &lt;0x27 0x05 0x27 0x07&gt;;
			clocks = &lt;0x27 0x93 0x27 0x96 0x2f 0x00 0x27 0x92 0x27 0x95 0x27 0x97&gt;;
			extcon = &lt;0x25b&gt;;
			vdd-supply = &lt;0x1a9&gt;;
			qcom,qmp-phy-reg-offset = &lt;0x1d74 0x1cd8 0x1cdc 0x1c04 0x1c00 0x1c08 0xffff 0x2a18 0x08 0x04 0x1c 0x00 0x10 0x0c 0x1a0c&gt;;
			compatible = &quot;qcom,usb-ssphy-qmp-dp-combo&quot;;
			status = &quot;disabled&quot;;
			reg = &lt;0x88e8000 0x3000&gt;;
			phandle = &lt;0x25d&gt;;
			reset-names = &quot;global_phy_reset\0phy_reset&quot;;
			qcom,qmp-phy-init-seq = &lt;0x1048 0x07 0x00 0x1080 0x14 0x00 0x1034 0x08 0x00 0x1138 0x30 0x00 0x103c 0x02 0x00 0x108c 0x08 0x00 0x115c 0x16 0x00 0x1164 0x01 0x00 0x113c 0x80 0x00 0x10b0 0x82 0x00 0x10b8 0xab 0x00 0x10bc 0xea 0x00 0x10c0 0x02 0x00 0x1060 0x06 0x00 0x1068 0x16 0x00 0x1070 0x36 0x00 0x10dc 0x00 0x00 0x10d8 0x3f 0x00 0x10f8 0x01 0x00 0x10f4 0xc9 0x00 0x1148 0x0a 0x00 0x10a0 0x00 0x00 0x109c 0x34 0x00 0x1098 0x15 0x00 0x1090 0x04 0x00 0x1154 0x00 0x00 0x1094 0x00 0x00 0x10f0 0x00 0x00 0x1040 0x0a 0x00 0x1010 0x01 0x00 0x101c 0x31 0x00 0x1020 0x01 0x00 0x1014 0x00 0x00 0x1018 0x00 0x00 0x1024 0x85 0x00 0x1028 0x07 0x00 0x1430 0x0b 0x00 0x14d4 0x0f 0x00 0x14d8 0x4e 0x00 0x14dc 0x18 0x00 0x14f8 0x77 0x00 0x14fc 0x80 0x00 0x1504 0x03 0x00 0x150c 0x16 0x00 0x1564 0x05 0x00 0x14c0 0x03 0x00 0x1830 0x0b 0x00 0x18d4 0x0f 0x00 0x18d8 0x4e 0x00 0x18dc 0x18 0x00 0x18f8 0x77 0x00 0x18fc 0x80 0x00 0x1904 0x03 0x00 0x190c 0x16 0x00 0x1964 0x05 0x00 0x18c0 0x03 0x00 0x1260 0x10 0x00 0x12a4 0x12 0x00 0x128c 0x16 0x00 0x1248 0x09 0x00 0x1244 0x06 0x00 0x1660 0x10 0x00 0x16a4 0x12 0x00 0x168c 0x16 0x00 0x1648 0x09 0x00 0x1644 0x06 0x00 0x1cc8 0x83 0x00 0x1ccc 0x09 0x00 0x1cd0 0xa2 0x00 0x1cd4 0x40 0x00 0x1cc4 0x02 0x00 0x1c80 0xd1 0x00 0x1c84 0x1f 0x00 0x1c88 0x47 0x00 0x1c64 0x1b 0x00 0x1434 0x75 0x00 0x1834 0x75 0x00 0x1dd8 0xba 0x00 0x1c0c 0x9f 0x00 0x1c10 0x9f 0x00 0x1c14 0xb7 0x00 0x1c18 0x4e 0x00 0x1c1c 0x65 0x00 0x1c20 0x6b 0x00 0x1c24 0x15 0x00 0x1c28 0x0d 0x00 0x1c2c 0x15 0x00 0x1c30 0x0d 0x00 0x1c34 0x15 0x00 0x1c38 0x0d 0x00 0x1c3c 0x15 0x00 0x1c40 0x1d 0x00 0x1c44 0x15 0x00 0x1c48 0x0d 0x00 0x1c4c 0x15 0x00 0x1c50 0x0d 0x00 0x1e0c 0x21 0x00 0x1e10 0x60 0x00 0x1c5c 0x02 0x00 0x1ca0 0x04 0x00 0x1c8c 0x44 0x00 0x1c70 0xe7 0x00 0x1c74 0x03 0x00 0x1c78 0x40 0x00 0x1c7c 0x00 0x00 0x1cb8 0x75 0x00 0x1cb0 0x86 0x00 0x1cbc 0x13 0x00 0x1cac 0x04 0x00 0xffffffff 0xffffffff 0x00&gt;;
			core-supply = &lt;0x1a8&gt;;
		};

qcom,msm_npu@9800000 {
			iommus = &lt;0x30 0x1461 0x00&gt;;
			clock-names = &quot;qdss_clk\0armwic_core_clk\0cal_dp_clk\0cal_dp_cdc_clk\0conf_noc_ahb_clk\0comp_noc_axi_clk\0npu_core_clk\0npu_core_cti_clk\0npu_core_apb_clk\0npu_core_atb_clk\0npu_cpc_clk\0npu_cpc_timer_clk\0qtimer_core_clk\0sleep_clk\0bwmon_clk\0perf_cnt_clk\0bto_core_clk\0xo_clk&quot;;
			reg-names = &quot;tcm\0core\0bwmon\0qfprom_physical&quot;;
			interrupts = &lt;0x00 0x247 0x01 0x00 0x249 0x01 0x00 0x24b 0x01&gt;;
			clocks = &lt;0x19 0x00 0x2c 0x04 0x2c 0x08 0x2c 0x07 0x2c 0x0b 0x2c 0x0a 0x2c 0x0e 0x2c 0x10 0x2c 0x0c 0x2c 0x0d 0x2c 0x11 0x2c 0x12 0x2c 0x14 0x2c 0x15 0x2c 0x06 0x2c 0x13 0x2c 0x05 0x2c 0x16&gt;;
			vdd-supply = &lt;0x23&gt;;
			compatible = &quot;qcom,msm-npu&quot;;
			qcom,vdd_cx-uV-uA = &lt;0x181 0x186a0&gt;;
			interrupt-names = &quot;error_irq\0wdg_bite_irq\0ipc_irq&quot;;
			reg = &lt;0x9800000 0x40000 0x9900000 0x10000 0x9960200 0x600 0x780000 0x7000&gt;;
			phandle = &lt;0x79&gt;;
			mboxes = &lt;0x2a5 0x00 0x2a6 0x00&gt;;
			cache-slices = &lt;0x1a7 0x17&gt;;
			vdd_cx-supply = &lt;0x1d&gt;;
			qcom,proxy-reg-names = &quot;vdd\0vdd_cx&quot;;
			qcom,npubw-dev = &lt;0xc8&gt;;
			qcom,npu-cxlimit-enable;
			mbox-names = &quot;npu_low\0npu_high&quot;;
			#cooling-cells = &lt;0x02&gt;;
			cache-slice-names = &quot;npu&quot;;

qcom,npu-pwrlevels {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;
				initial-pwrlevel = &lt;0x04&gt;;
				compatible = &quot;qcom,npu-pwrlevels&quot;;

qcom,npu-pwrlevel@3 {
					clk-freq = &lt;0x00 0x11e1a300 0x23c34600 0x23c34600 0x47868c0 0x18054ac0 0x11e1a300 0x8f0d180 0x124f800 0xe4e1c00 0x11e1a300 0x124f800 0x124f800 0x00 0x124f800 0x23c34600 0x124f800 0x124f800&gt;;
					vreg = &lt;0x04&gt;;
					reg = &lt;0x03&gt;;
				};

qcom,npu-pwrlevel@1 {
					clk-freq = &lt;0x00 0x8f0d180 0x17d78400 0x17d78400 0x23c3460 0xbebc200 0x8f0d180 0x47868c0 0x124f800 0x7270e00 0x8f0d180 0x124f800 0x124f800 0x00 0x124f800 0x17d78400 0x124f800 0x124f800&gt;;
					vreg = &lt;0x02&gt;;
					reg = &lt;0x01&gt;;
				};

qcom,npu-pwrlevel@4 {
					clk-freq = &lt;0x00 0x17d78400 0x29b92700 0x29b92700 0x47868c0 0x1fc4ef40 0x17d78400 0x8f0d180 0x124f800 0x11e1a300 0x17d78400 0x124f800 0x124f800 0x00 0x124f800 0x29b92700 0x124f800 0x124f800&gt;;
					vreg = &lt;0x06&gt;;
					reg = &lt;0x04&gt;;
				};

qcom,npu-pwrlevel@2 {
					clk-freq = &lt;0x00 0xbebc200 0x1bce39a0 0x1bce39a0 0x23c3460 0x11e1a300 0xbebc200 0x47868c0 0x124f800 0x7270e00 0xbebc200 0x124f800 0x124f800 0x00 0x124f800 0x1bce39a0 0x124f800 0x124f800&gt;;
					vreg = &lt;0x03&gt;;
					reg = &lt;0x02&gt;;
				};

qcom,npu-pwrlevel@0 {
					clk-freq = &lt;0x00 0x5f5e100 0x11e1a300 0x11e1a300 0x1c9c380 0x8f0d180 0x5f5e100 0x23c3460 0x124f800 0x3938700 0x5f5e100 0x124f800 0x124f800 0x00 0x124f800 0x11e1a300 0x124f800 0x124f800&gt;;
					vreg = &lt;0x01&gt;;
					reg = &lt;0x00&gt;;
				};
			};
		};

qcom,msm-tert-auxpcm {
			qcom,msm-cpudai-auxpcm-quant = &lt;0x02 0x02&gt;;
			qcom,msm-cpudai-auxpcm-frame = &lt;0x05 0x04&gt;;
			qcom,msm-cpudai-auxpcm-sync = &lt;0x01 0x01&gt;;
			qcom,msm-auxpcm-interface = &quot;tertiary&quot;;
			qcom,msm-cpudai-auxpcm-slot-mapping = &lt;0x01 0x01&gt;;
			qcom,msm-cpudai-auxpcm-data = &lt;0x00 0x00&gt;;
			qcom,msm-cpudai-afe-clk-ver = &lt;0x02&gt;;
			qcom,msm-cpudai-auxpcm-num-slots = &lt;0x01 0x01&gt;;
			compatible = &quot;qcom,msm-auxpcm-dev&quot;;
			qcom,msm-cpudai-auxpcm-mode = &lt;0x00 0x00&gt;;
			phandle = &lt;0x273&gt;;
			qcom,msm-cpudai-auxpcm-pcm-clk-rate = &lt;0x1f4000 0x1f4000&gt;;
		};

qcom,msm-transcode-loopback {
			compatible = &quot;qcom,msm-transcode-loopback&quot;;
			phandle = &lt;0x48b&gt;;
		};

qcom,dsi-display@8 {
			qcom,dsi-phy-num = &lt;0x00 0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x52a&gt;;
			qcom,dsi-ctrl-num = &lt;0x00 0x01&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_dual_sim_dsc_375_cmd_display&quot;;
			phandle = &lt;0x547&gt;;
		};

cti@69a4000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-wcss_cti0&quot;;
			compatible = &quot;arm,primecell&quot;;
			status = &quot;disabled&quot;;
			reg = &lt;0x69a4000 0x1000&gt;;
			phandle = &lt;0x46a&gt;;
		};

qcom,ion {
			#address-cells = &lt;0x01&gt;;
			#size-cells = &lt;0x00&gt;;
			compatible = &quot;qcom,msm-ion&quot;;

qcom,ion-heap@13 {
				memory-region = &lt;0x1c2&gt;;
				qcom,ion-heap-type = &quot;DMA&quot;;
				reg = &lt;0x0d&gt;;
			};

qcom,ion-heap@14 {
				qcom,ion-heap-type = &quot;SECURE_CARVEOUT&quot;;
				reg = &lt;0x0e&gt;;

cdsp {
					memory-region = &lt;0x1c4&gt;;
					token = &lt;0x20000000&gt;;
				};
			};

qcom,ion-heap@10 {
				memory-region = &lt;0x1c3&gt;;
				qcom,ion-heap-type = &quot;HYP_CMA&quot;;
				reg = &lt;0x0a&gt;;
			};

qcom,ion-heap@9 {
				qcom,ion-heap-type = &quot;SYSTEM_SECURE&quot;;
				reg = &lt;0x09&gt;;
			};

qcom,ion-heap@19 {
				memory-region = &lt;0x1c1&gt;;
				qcom,ion-heap-type = &quot;DMA&quot;;
				reg = &lt;0x13&gt;;
			};

qcom,ion-heap@27 {
				memory-region = &lt;0x9a&gt;;
				qcom,ion-heap-type = &quot;DMA&quot;;
				reg = &lt;0x1b&gt;;
			};

qcom,ion-heap@25 {
				qcom,ion-heap-type = &quot;SYSTEM&quot;;
				reg = &lt;0x19&gt;;
				phandle = &lt;0x39b&gt;;
			};
		};

dbu1 {
			enable-active-high;
			regulator-name = &quot;dbu1&quot;;
			startup-delay-us = &lt;0x00&gt;;
			compatible = &quot;regulator-fixed&quot;;
			phandle = &lt;0x512&gt;;
		};

rpmh-regulator-ldoc9 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoc9&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150l-l9 {
				regulator-max-microvolt = &lt;0x328980&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x2d0370&gt;;
				regulator-min-microvolt = &lt;0x2d0370&gt;;
				regulator-name = &quot;pm6150l_l9&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x413&gt;;
			};
		};

qcom,msm-adsp-loader {
			qcom,adsp-state = &lt;0x00&gt;;
			compatible = &quot;qcom,adsp-loader&quot;;
			status = &quot;ok&quot;;
		};

syscon@0x5091508 {
			compatible = &quot;syscon&quot;;
			reg = &lt;0x5091508 0x04&gt;;
			phandle = &lt;0xcd&gt;;
		};

qcom,gdsc@17d044 {
			qcom,no-status-check-on-disable;
			qcom,gds-timeout = &lt;0x1f4&gt;;
			regulator-name = &quot;hlos1_vote_mmnoc_mmu_tbu_sf_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x17d044 0x04&gt;;
			phandle = &lt;0x1ca&gt;;
		};

qcom,gpi-dma@0xa00000 {
			iommus = &lt;0x30 0x4d6 0x00&gt;;
			qcom,gpii-mask = &lt;0x0f&gt;;
			qcom,smmu-cfg = &lt;0x01&gt;;
			reg-names = &quot;gpi-top&quot;;
			interrupts = &lt;0x00 0x117 0x00 0x00 0x118 0x00 0x00 0x119 0x00 0x00 0x11a 0x00 0x00 0x11b 0x00 0x00 0x11c 0x00 0x00 0x125 0x00 0x00 0x126 0x00&gt;;
			qcom,ev-factor = &lt;0x02&gt;;
			qcom,iova-range = &lt;0x00 0x100000 0x00 0x100000&gt;;
			compatible = &quot;qcom,gpi-dma&quot;;
			status = &quot;ok&quot;;
			qcom,max-num-gpii = &lt;0x08&gt;;
			reg = &lt;0xa00000 0x60000&gt;;
			phandle = &lt;0x183&gt;;
			#dma-cells = &lt;0x05&gt;;
		};

qcom,msm-dai-q6-meta-mi2s-sec {
			qcom,msm-dai-q6-meta-mi2s-dev-id = &lt;0x1302&gt;;
			qcom,msm-mi2s-rx-lines = &lt;0xff 0x0f 0x03 0x03&gt;;
			qcom,msm-mi2s-member-id = &lt;0x00 0x01 0x02 0x03&gt;;
			qcom,msm-mi2s-num-members = &lt;0x04&gt;;
			compatible = &quot;qcom,msm-dai-q6-meta-mi2s&quot;;
			phandle = &lt;0x494&gt;;
		};

rpmh-regulator-bobc1 {
			qcom,mode-threshold-currents = &lt;0x00 0xf4240 0x1e8480&gt;;
			qcom,regulator-type = &quot;pmic5-bob&quot;;
			qcom,send-defaults;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;bobc1&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x00 0x02 0x04&gt;;

regulator-pm6150l-bob-ao {
				regulator-max-microvolt = &lt;0x3c6cc0&gt;;
				qcom,init-mode = &lt;0x03&gt;;
				qcom,init-voltage = &lt;0x324b00&gt;;
				regulator-min-microvolt = &lt;0x324b00&gt;;
				regulator-name = &quot;pm6150l_bob_ao&quot;;
				qcom,set = &lt;0x01&gt;;
				phandle = &lt;0x416&gt;;
			};

regulator-pm6150l-bob {
				regulator-max-microvolt = &lt;0x3c6cc0&gt;;
				qcom,init-mode = &lt;0x00&gt;;
				qcom,init-voltage = &lt;0x324b00&gt;;
				regulator-min-microvolt = &lt;0x324b00&gt;;
				regulator-name = &quot;pm6150l_bob&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x415&gt;;
			};
		};

qcom,msm-dai-q6-hdmi_ms {
			compatible = &quot;qcom,msm-dai-q6-hdmi&quot;;
			qcom,msm-dai-q6-dev-id = &lt;0x6002&gt;;
			phandle = &lt;0x48e&gt;;
		};

rpmh-regulator-smpf2 {
			compatible = &quot;qcom,rpmh-xob-regulator&quot;;
			qcom,resource-name = &quot;smpf2&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm8009-s2 {
				regulator-max-microvolt = &lt;0x2c4020&gt;;
				regulator-min-microvolt = &lt;0x2c4020&gt;;
				regulator-name = &quot;pm8009_s2&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x401&gt;;
			};
		};

qcom,gdsc@ad08004 {
			qcom,poll-cfg-gdscr;
			clock-names = &quot;ahb_clk&quot;;
			qcom,support-hw-trigger;
			clocks = &lt;0x27 0x0e&gt;;
			regulator-name = &quot;ipe_0_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xad08004 0x04&gt;;
			phandle = &lt;0x1b9&gt;;
		};

rpmh-regulator-ldof7 {
			compatible = &quot;qcom,rpmh-xob-regulator&quot;;
			qcom,resource-name = &quot;ldof7&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm8009-l7 {
				regulator-max-microvolt = &lt;0x1b7740&gt;;
				regulator-min-microvolt = &lt;0x1b7740&gt;;
				regulator-name = &quot;pm8009_l7&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x41c&gt;;
			};
		};

qcom,rpmh {
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,rpmh-clk-sdmmagpie&quot;;
			phandle = &lt;0x2f&gt;;
			mboxes = &lt;0x1b 0x00&gt;;
			mbox-names = &quot;apps&quot;;
		};

qcom,mdss_dsi_g7b_42_02_0b_dsc_video {
			qcom,mdss-pan-physical-width-dimension = &lt;0x44&gt;;
			qcom,mdss-dsi-panel-name = &quot;xiaomi 42 02 0b video mode dsc dsi panel&quot;;
			qcom,mdss-pan-physical-height-dimension = &lt;0x88&gt;;
			qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
			qcom,mdss-dsi-underflow-color = &lt;0x00&gt;;
			qcom,mdss-dsi-t-clk-post = &lt;0x0e&gt;;
			qcom,mdss-dsi-lane-2-state;
			qcom,mdss-dsi-bllp-eof-power-mode;
			qcom,mdss-dsi-panel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-pan-enable-smart-fps;
			qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
			qcom,mdss-dsi-panel-max-luminance = &lt;0x0f 0x20&gt;;
			qcom,bl-update-flag = &quot;delay_until_first_frame&quot;;
			qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
			qcom,mdss-dsi-panel-xy-coordinate = &lt;0x0f 0x18&gt;;
			qcom,mdss-dsi-panel-max-luminance-valid = &lt;0x01 0x01&gt;;
			qcom,dispparam-enabled;
			qcom,mdss-dsi-panel-peak-brightness = &lt;0x401640&gt;;
			qcom,mdss-dsi-lane-3-state;
			qcom,mdss-dsi-pan-fps-update = &quot;dfps_immediate_porch_mode_vfp&quot;;
			qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
			qcom,mdss-dsi-pan-enable-dynamic-fps;
			qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-reset-sequence = &lt;0x00 0x0a 0x01 0x0a&gt;;
			qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
			qcom,mdss-dsi-lane-0-state;
			qcom,dsi-supported-dfps-list = &lt;0x1e 0x3c 0x5a 0x78&gt;;
			qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
			qcom,mdss-panel-on-dimming-delay = &lt;0x78&gt;;
			qcom,mdss-dsi-t-clk-pre = &lt;0x34&gt;;
			qcom,mdss-dsi-panel-hdr-enabled;
			qcom,cont-splash-enabled;
			qcom,mdss-dsi-panel-model = &quot;xiaomi 42 02 0b VIDEO PANEL&quot;;
			phandle = &lt;0x535&gt;;
			qcom,mdss-dsi-bllp-power-mode;
			qcom,mdss-dsi-stream = &lt;0x00&gt;;
			qcom,mdss-dsi-lp11-init;
			qcom,mdss-dsi-tx-eot-append;
			qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
			qcom,mdss-dsi-border-color = &lt;0x00&gt;;
			qcom,mdss-dsi-lane-1-state;
			qcom,mdss-dsi-bpp = &lt;0x18&gt;;
			qcom,disp-panel-offon-mode-enabled;
			qcom,mdss-brightness-max-level = &lt;0xfff&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
					qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
					qcom,display-topology = &lt;0x01 0x01 0x01&gt;;
					qcom,mdss-dsi-panel-framerate = &lt;0x78&gt;;
					qcom,mdss-dsi-h-pulse-width = &lt;0x0c&gt;;
					qcom,compression-mode = &quot;dsc&quot;;
					qcom,mdss-dsi-displayoff-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-panel-height = &lt;0x924&gt;;
					qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
					qcom,mdss-dsc-block-prediction-enable;
					qcom,mdss-dsi-on-command = &lt;0x15010000 0x2ff 0x10150100 0x02 0xfb011501 0x00 0x2fb0139 0x1000000 0x3c21b 0xa0150100 0x02 0xff201501 0x00 0x2fb0115 0x1000000 0x2fb01 0x15010000 0x206 0x50150100 0x02 0x7281501 0x00 0x269ea15 0x1000000 0x295d1 0x15010000 0x296 0xd1150100 0x02 0x890c1501 0x00 0x28a0c15 0x1000000 0x2ff24 0x15010000 0x2fb 0x1150100 0x02 0xfb011501 0x00 0x2012115 0x1000000 0x20221 0x15010000 0x203 0x10150100 0x02 0x4241501 0x00 0x2070115 0x1000000 0x2080b 0x15010000 0x20a 0xc150100 0x02 0xb0f1501 0x00 0x20c2215 0x1000000 0x20d2c 0x15010000 0x20e 0x2e150100 0x02 0xf301501 0x00 0x2103215 0x1000000 0x21217 0x15010000 0x213 0x17150100 0x02 0x14151501 0x00 0x2151515 0x1000000 0x21613 0x15010000 0x217 0x13150100 0x02 0x19211501 0x00 0x21b1015 0x1000000 0x21c24 0x15010000 0x21d 0x21150100 0x02 0x1f011501 0x00 0x2200b15 0x1000000 0x2220c 0x15010000 0x223 0xf150100 0x02 0x24221501 0x00 0x2252d15 0x1000000 0x2262f 0x15010000 0x227 0x31150100 0x02 0x28331501 0x00 0x22a1715 0x1000000 0x22b17 0x15010000 0x22d 0x15150100 0x02 0x2f151501 0x00 0x2301315 0x1000000 0x23113 0x15010000 0x232 0x5150100 0x02 0x33031501 0x00 0x2340315 0x1000000 0x23501 0x15010000 0x236 0x3c150100 0x02 0x4e3b1501 0x00 0x24f3b15 0x1000000 0x2533b 0x15010000 0x279 0x22150100 0x02 0x7b901501 0x00 0x27d0315 0x1000000 0x28003 0x15010000 0x281 0x3150100 0x02 0x82131501 0x00 0x2843115 0x1000000 0x28504 0x15010000 0x286 0x4150100 0x02 0x87041501 0x00 0x2901315 0x1000000 0x29231 0x15010000 0x293 0x4150100 0x02 0x94041501 0x00 0x2950415 0x1000000 0x29cf4 0x15010000 0x29d 0x1150100 0x02 0xa0101501 0x00 0x2a21015 0x1000000 0x2a403 0x15010000 0x2a5 0x3150100 0x02 0xc90c1501 0x00 0x2d13415 0x1000000 0x2d980 0x15010000 0x2ff 0x25150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x2665d 0x15010000 0x267 0x10150100 0x02 0x68581501 0x00 0x2691015 0x1000000 0x26b00 0x15010000 0x271 0x6d150100 0x02 0x77721501 0x00 0x27e2d15 0x1000000 0x28100 0x15010000 0x284 0x78150100 0x02 0x85751501 0x00 0x28d0015 0x1000000 0x2c1a9 0x15010000 0x2c2 0x5a150100 0x02 0xc3071501 0x00 0x2ef0815 0x1000000 0x2f114 0x15010000 0x2ff 0x26150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x20010 0x15010000 0x201 0x7c150100 0x02 0x3001501 0x00 0x2047c15 0x1000000 0x20508 0x15010000 0x206 0x21150100 0x02 0x8211501 0x00 0x2140215 0x1000000 0x21501 0x15010000 0x274 0xaf150100 0x02 0x81101501 0x00 0x2830415 0x1000000 0x28402 0x15010000 0x285 0x1150100 0x02 0x86021501 0x00 0x2870115 0x1000000 0x28806 0x15010000 0x28a 0x1a150100 0x02 0x8b111501 0x00 0x28c2415 0x1000000 0x28e42 0x15010000 0x28f 0x11150100 0x02 0x90111501 0x00 0x2911115 0x1000000 0x29a80 0x15010000 0x29b 0x42150100 0x02 0x9c001501 0x00 0x29d0015 0x1000000 0x29e00 0x15010000 0x2ff 0x27150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x22081 0x15010000 0x221 0x82150100 0x02 0x25811501 0x00 0x226ab15 0x1000000 0x26e12 0x15010000 0x26f 0x150100 0x02 0x70001501 0x00 0x2710015 0x1000000 0x27200 0x15010000 0x273 0x76150100 0x02 0x74101501 0x00 0x2753215 0x1000000 0x27654 0x15010000 0x277 0x150100 0x02 0x7d091501 0x00 0x27e2715 0x1000000 0x28027 0x15010000 0x282 0x9150100 0x02 0x83271501 0x00 0x2880315 0x1000000 0x28903 0x15010000 0x2ff 0x2a150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x20607 0x15010000 0x20a 0x60150100 0x02 0x15071501 0x00 0x216c315 0x1000000 0x21a40 0x15010000 0x21b 0xa150100 0x02 0x1d0a1501 0x00 0x21e4215 0x1000000 0x21f42 0x15010000 0x220 0x42150100 0x02 0x37701501 0x00 0x2444c15 0x1000000 0x24af0 0x15010000 0x24e 0x4150100 0x02 0x4f041501 0x00 0x2574315 0x1000000 0x25843 0x15010000 0x259 0x43150100 0x02 0x621c1501 0x00 0x2634c15 0x1000000 0x2794c 0x15010000 0x27a 0x9150100 0x02 0x7c011501 0x00 0x27ff015 0x1000000 0x28304 0x15010000 0x284 0x4150100 0x02 0x8c431501 0x00 0x28d4315 0x1000000 0x28e43 0x15010000 0x297 0x1c150100 0x02 0x984c1501 0x00 0x2a9a015 0x1000000 0x2dea0 0x15010000 0x2ff 0x2c150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x2030f 0x15010000 0x204 0xf150100 0x02 0x50f1501 0x00 0x20d0115 0x1000000 0x20e3c 0x15010000 0x217 0x3b150100 0x02 0x183b1501 0x00 0x2193b15 0x1000000 0x22f10 0x15010000 0x230 0x40150100 0x02 0x32001501 0x00 0x2334015 0x1000000 0x23521 0x15010000 0x237 0x21150100 0x02 0x3a011501 0x00 0x23b0115 0x1000000 0x24d0f 0x15010000 0x24e 0x4150100 0x02 0x4f0a1501 0x00 0x2560f15 0x1000000 0x2580f 0x15010000 0x259 0xf150100 0x02 0x61011501 0x00 0x2623c15 0x1000000 0x26b3b 0x15010000 0x26c 0x3b150100 0x02 0x6d3b1501 0x00 0x2811015 0x1000000 0x28240 0x15010000 0x284 0x150100 0x02 0x85401501 0x00 0x2872115 0x1000000 0x28921 0x15010000 0x28c 0x1150100 0x02 0x8d011501 0x00 0x29d0f15 0x1000000 0x29e04 0x15010000 0x29f 0xa150100 0x02 0xffe01501 0x00 0x2fb0115 0x1000000 0x2fb01 0x15010000 0x2ff 0xf0150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x2ffd0 0x15010000 0x2fb 0x1150100 0x02 0xfb011501 0x00 0x2ff2015 0x1000000 0x2fb01 0x15010000 0x2fb 0x1390100 0x11 0xb0000000 0x17003a00 0x55006d00 0x81009400 0xa5390100 0x11 0xb100b500 0xea011101 0x50017e01 0xca020302 0x5390100 0x11 0xb2023e02 0x7f02ac02 0xe3030903 0x37034703 0x56390100 0x0d 0xb3036903 0x7f039b03 0xbb03d403 0xd8390100 0x11 0xb4000000 0x17003a00 0x55006d00 0x81009400 0xa5390100 0x11 0xb500b500 0xea011101 0x50017e01 0xca020302 0x5390100 0x11 0xb6023e02 0x7f02ac02 0xe3030903 0x37034703 0x56390100 0x0d 0xb7036903 0x7f039b03 0xbb03d403 0xd8390100 0x11 0xb8000000 0x17003a00 0x55006d00 0x81009400 0xa5390100 0x11 0xb900b500 0xea011101 0x50017e01 0xca020302 0x5390100 0x11 0xba023e02 0x7f02ac02 0xe3030903 0x37034703 0x56390100 0x0d 0xbb036903 0x7f039b03 0xbb03d403 0xd8150100 0x02 0xff211501 0x00 0x2fb0115 0x1000000 0x2fb01 0x39010000 0x11b0 0x17 0x3a0055 0x6d0081 0x9400a5 0x39010000 0x11b1 0xb500ea 0x1110150 0x17e01ca 0x2030205 0x39010000 0x11b2 0x23e027f 0x2ac02e3 0x3090337 0x3470356 0x39010000 0xdb3 0x369037f 0x39b03bb 0x3d403d8 0x39010000 0x11b4 0x17 0x3a0055 0x6d0081 0x9400a5 0x39010000 0x11b5 0xb500ea 0x1110150 0x17e01ca 0x2030205 0x39010000 0x11b6 0x23e027f 0x2ac02e3 0x3090337 0x3470356 0x39010000 0xdb7 0x369037f 0x39b03bb 0x3d403d8 0x39010000 0x11b8 0x17 0x3a0055 0x6d0081 0x9400a5 0x39010000 0x11b9 0xb500ea 0x1110150 0x17e01ca 0x2030205 0x39010000 0x11ba 0x23e027f 0x2ac02e3 0x3090337 0x3470356 0x39010000 0xdbb 0x369037f 0x39b03bb 0x3d403d8 0x15010000 0x2ff 0x10150100 0x02 0xfb011501 0x00 0x2fb0115 0x1000000 0x251ff 0x15010000 0x253 0x2c150100 0x02 0x55010501 0x7800 0x2110005 0x1000000 0x22900&gt;;
					qcom,mdss-dsi-h-front-porch = &lt;0x64&gt;;
					qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
					qcom,mdss-dsi-h-back-porch = &lt;0x78&gt;;
					qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
					qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
					qcom,mdss-dsc-slice-height = &lt;0x14&gt;;
					qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
					qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
					qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
					qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-panel-phy-timings = &lt;0x220809 0x25230909 0x6020400&gt;;
					qcom,mdss-dsi-v-back-porch = &lt;0x08&gt;;
					qcom,default-topology-index = &lt;0x00&gt;;
					qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
					qcom,mdss-dsc-slice-per-pkt = &lt;0x02&gt;;
					qcom,mdss-dsi-h-sync-pulse = &lt;0x01&gt;;
					qcom,mdss-dsc-scr-version = &lt;0x00&gt;;
					qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 46 00 02 10 00];
					qcom,mdss-dsi-displayon-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
					qcom,mdss-dsi-v-front-porch = &lt;0x0a&gt;;
					qcom,mdss-dsi-displayoff-command = [05 01 00 00 20 00 02 28 00];
					qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00];
					qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsc-version = &lt;0x11&gt;;
				};
			};
		};

qcom,msm-quat-auxpcm {
			qcom,msm-cpudai-auxpcm-quant = &lt;0x02 0x02&gt;;
			qcom,msm-cpudai-auxpcm-frame = &lt;0x05 0x04&gt;;
			qcom,msm-cpudai-auxpcm-sync = &lt;0x01 0x01&gt;;
			qcom,msm-auxpcm-interface = &quot;quaternary&quot;;
			qcom,msm-cpudai-auxpcm-slot-mapping = &lt;0x01 0x01&gt;;
			qcom,msm-cpudai-auxpcm-data = &lt;0x00 0x00&gt;;
			qcom,msm-cpudai-afe-clk-ver = &lt;0x02&gt;;
			qcom,msm-cpudai-auxpcm-num-slots = &lt;0x01 0x01&gt;;
			compatible = &quot;qcom,msm-auxpcm-dev&quot;;
			qcom,msm-cpudai-auxpcm-mode = &lt;0x00 0x00&gt;;
			phandle = &lt;0x274&gt;;
			qcom,msm-cpudai-auxpcm-pcm-clk-rate = &lt;0x1f4000 0x1f4000&gt;;
		};

rx_core_clk {
			qcom,codec-ext-clk-src = &lt;0x05&gt;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,audio-ref-clk&quot;;
			phandle = &lt;0x4e3&gt;;
			qcom,codec-lpass-clk-id = &lt;0x30e&gt;;
			qcom,codec-lpass-ext-clk-freq = &lt;0x1588800&gt;;
		};

refgen-regulator@ff1000 {
			regulator-enable-ramp-delay = &lt;0x05&gt;;
			regulator-name = &quot;refgen&quot;;
			compatible = &quot;qcom,refgen-regulator&quot;;
			qcom,proxy-consumer-enable;
			reg = &lt;0xff1000 0x60&gt;;
			phandle = &lt;0x1af&gt;;
			proxy-supply = &lt;0x1af&gt;;
		};

qcom,msm-audio-apr {
			qcom,subsys-name = &quot;apr_adsp&quot;;
			compatible = &quot;qcom,msm-audio-apr&quot;;
			phandle = &lt;0x4ac&gt;;

qcom,msm-audio-ion {
				iommus = &lt;0x30 0x1b21 0x00&gt;;
				qcom,smmu-enabled;
				qcom,smmu-sid-mask = &lt;0x00 0x0f&gt;;
				compatible = &quot;qcom,msm-audio-ion&quot;;
				phandle = &lt;0x4ad&gt;;
				qcom,smmu-version = &lt;0x02&gt;;
			};

qcom,q6core-audio {
				compatible = &quot;qcom,q6core-audio&quot;;
				phandle = &lt;0x4ae&gt;;

bolero-cdc {
					qcom,num-macros = &lt;0x03&gt;;
					slew_rate_val2 = &lt;0x0f 0x00&gt;;
					qcom,va-without-decimation;
					slew_rate_reg2 = &lt;0x62b6f004 0x00&gt;;
					compatible = &quot;qcom,bolero-codec&quot;;
					slew_rate_val1 = &lt;0x3333 0x00&gt;;
					phandle = &lt;0x4af&gt;;
					slew_rate_reg1 = &lt;0x62b6f000 0x00&gt;;

wcd937x-codec {
						qcom,rx-slave = &lt;0x4ed&gt;;
						qcom,cdc-vddpx-1-voltage = &lt;0x1b7740 0x1b7740&gt;;
						qcom,cdc-vdd-mic-bias-voltage = &lt;0x324b00 0x324b00&gt;;
						qcom,cdc-vddpx-1-current = &lt;0x2710&gt;;
						qcom,cdc-vdd-mic-bias-current = &lt;0x61a8&gt;;
						qcom,wcd-rst-gpio-node = &lt;0x4ec&gt;;
						qcom,tx-slave = &lt;0x4ee&gt;;
						qcom,tx_swr_ch_map = &lt;0x00 0x12 0x01 0x00 0x12 0x01 0x13 0x01 0x00 0x14 0x01 0x14 0x02 0x00 0x15 0x02 0x16 0x01 0x00 0x16 0x02 0x17 0x02 0x00 0x17 0x02 0x11 0x04 0x00 0x18 0x03 0x18 0x01 0x00 0x1a 0x03 0x19 0x02 0x00 0x1b 0x03 0x1a 0x04 0x00 0x1c 0x03 0x1b 0x08 0x00 0x1d&gt;;
						qcom,cdc-micbias2-mv = &lt;0xabe&gt;;
						cdc-vdd-ldo-rxtx-supply = &lt;0x31&gt;;
						qcom,rx_swr_ch_map = &lt;0x00 0x09 0x01 0x00 0x09 0x00 0x0a 0x02 0x00 0x0a 0x01 0x0d 0x01 0x00 0x0d 0x02 0x0b 0x01 0x00 0x0b 0x02 0x0c 0x02 0x00 0x0c 0x03 0x0e 0x01 0x00 0x0e 0x04 0x0f 0x01 0x00 0x0f 0x04 0x10 0x02 0x00 0x10&gt;;
						cdc-vdd-buck-supply = &lt;0x40a&gt;;
						qcom,cdc-vdd-ldo-rxtx-voltage = &lt;0x1b7740 0x1b7740&gt;;
						qcom,cdc-static-supplies = &quot;cdc-vdd-ldo-rxtx\0cdc-vddpx-1\0cdc-vdd-mic-bias&quot;;
						qcom,cdc-vdd-ldo-rxtx-current = &lt;0x61a8&gt;;
						qcom,cdc-vdd-buck-voltage = &lt;0x1b7740 0x1b7740&gt;;
						compatible = &quot;qcom,wcd937x-codec&quot;;
						qcom,cdc-vdd-buck-current = &lt;0x9eb10&gt;;
						cdc-vdd-mic-bias-supply = &lt;0x415&gt;;
						qcom,cdc-micbias1-mv = &lt;0xabe&gt;;
						cdc-vddpx-1-supply = &lt;0x31&gt;;
						phandle = &lt;0x4f5&gt;;
						qcom,cdc-on-demand-supplies = &quot;cdc-vdd-buck&quot;;
						qcom,cdc-micbias3-mv = &lt;0xabe&gt;;
					};

rx-macro@62ee0000 {
						clock-names = &quot;rx_core_clk\0rx_npl_clk&quot;;
						clocks = &lt;0x4e3 0x00 0x4e4 0x00&gt;;
						qcom,rx_mclk_mode_muxsel = &lt;0x62c25020&gt;;
						compatible = &quot;qcom,rx-macro&quot;;
						reg = &lt;0x62ee0000 0x00&gt;;
						qcom,rx-bcl-pmic-params = [00 00 1e];
						phandle = &lt;0x594&gt;;
						qcom,rx-swr-gpios = &lt;0x4e5&gt;;

rx_swr_master {
							qcom,swr-clock-stop-mode0 = &lt;0x01&gt;;
							#address-cells = &lt;0x02&gt;;
							qcom,swr-num-dev = &lt;0x01&gt;;
							interrupts = &lt;0x00 0x129 0x00&gt;;
							swrm-io-base = &lt;0x62ef0000 0x00&gt;;
							#size-cells = &lt;0x00&gt;;
							qcom,swr_master_id = &lt;0x02&gt;;
							compatible = &quot;qcom,swr-mstr&quot;;
							interrupt-names = &quot;swr_master_irq&quot;;
							qcom,swr-port-mapping = &lt;0x01 0x09 0x01 0x01 0x0a 0x02 0x02 0x0d 0x01 0x03 0x0b 0x01 0x03 0x0c 0x02 0x04 0x0e 0x01 0x05 0x0f 0x01 0x05 0x10 0x02&gt;;
							phandle = &lt;0x595&gt;;
							qcom,swr-num-ports = &lt;0x05&gt;;

wcd937x-rx-slave {
								compatible = &quot;qcom,wcd937x-slave&quot;;
								reg = &lt;0x00 0x1170224&gt;;
								phandle = &lt;0x4ed&gt;;
							};
						};
					};

wsa-macro@62f00000 {
						qcom,wsa-swr-gpios = &lt;0x4e8&gt;;
						clock-names = &quot;wsa_core_clk\0wsa_npl_clk&quot;;
						clocks = &lt;0x4e6 0x00 0x4e7 0x00&gt;;
						qcom,wsa-bcl-pmic-params = [00 00 1e];
						compatible = &quot;qcom,wsa-macro&quot;;
						status = &quot;disabled&quot;;
						reg = &lt;0x62f00000 0x00&gt;;
						phandle = &lt;0x596&gt;;

wsa_swr_master {
							#address-cells = &lt;0x02&gt;;
							qcom,swr-num-dev = &lt;0x02&gt;;
							interrupts = &lt;0x00 0x127 0x00&gt;;
							swrm-io-base = &lt;0x62f10000 0x00&gt;;
							#size-cells = &lt;0x00&gt;;
							qcom,swr_master_id = &lt;0x01&gt;;
							compatible = &quot;qcom,swr-mstr&quot;;
							interrupt-names = &quot;swr_master_irq&quot;;
							qcom,swr-port-mapping = &lt;0x01 0x01 0x01 0x02 0x03 0x0f 0x03 0x02 0x03 0x04 0x05 0x01 0x05 0x07 0x0f 0x06 0x06 0x03 0x07 0x04 0x03 0x08 0x08 0x03&gt;;
							phandle = &lt;0x597&gt;;
							qcom,swr-num-ports = &lt;0x08&gt;;

wsa881x@21170213 {
								qcom,bolero-handle = &lt;0x4af&gt;;
								compatible = &quot;qcom,wsa881x&quot;;
								reg = &lt;0x00 0x21170213&gt;;
								qcom,spkr-sd-n-node = &lt;0x4e9&gt;;
								phandle = &lt;0x4f3&gt;;
							};

wsa881x@20170212 {
								qcom,bolero-handle = &lt;0x4af&gt;;
								compatible = &quot;qcom,wsa881x&quot;;
								reg = &lt;0x00 0x20170212&gt;;
								qcom,spkr-sd-n-node = &lt;0x4ea&gt;;
								phandle = &lt;0x4f2&gt;;
							};

wsa881x@21170214 {
								qcom,bolero-handle = &lt;0x4af&gt;;
								compatible = &quot;qcom,wsa881x&quot;;
								reg = &lt;0x00 0x21170214&gt;;
								qcom,spkr-sd-n-node = &lt;0x4ea&gt;;
								phandle = &lt;0x4f4&gt;;
							};

wsa881x@20170211 {
								qcom,bolero-handle = &lt;0x4af&gt;;
								compatible = &quot;qcom,wsa881x&quot;;
								reg = &lt;0x00 0x20170211&gt;;
								qcom,spkr-sd-n-node = &lt;0x4e9&gt;;
								phandle = &lt;0x4f1&gt;;
							};
						};
					};

va-macro@62f20000 {
						clock-names = &quot;va_core_clk&quot;;
						clocks = &lt;0x4eb 0x00&gt;;
						compatible = &quot;qcom,va-macro&quot;;
						reg = &lt;0x62f20000 0x00&gt;;
						phandle = &lt;0x598&gt;;
					};

tx-macro@62ec0000 {
						clock-names = &quot;tx_core_clk\0tx_npl_clk&quot;;
						clocks = &lt;0x4e0 0x00 0x4e1 0x00&gt;;
						qcom,tx-dmic-sample-rate = &lt;0x249f00&gt;;
						compatible = &quot;qcom,tx-macro&quot;;
						reg = &lt;0x62ec0000 0x00&gt;;
						phandle = &lt;0x592&gt;;
						qcom,tx-swr-gpios = &lt;0x4e2&gt;;

tx_swr_master {
							qcom,swr-clock-stop-mode0 = &lt;0x01&gt;;
							#address-cells = &lt;0x02&gt;;
							qcom,swr-num-dev = &lt;0x01&gt;;
							interrupts = &lt;0x00 0x128 0x00 0x00 0x1f4 0x00&gt;;
							swrm-io-base = &lt;0x62ed0000 0x00&gt;;
							#size-cells = &lt;0x00&gt;;
							qcom,swr_master_id = &lt;0x03&gt;;
							compatible = &quot;qcom,swr-mstr&quot;;
							interrupt-names = &quot;swr_master_irq\0swr_wake_irq&quot;;
							qcom,swr-port-mapping = &lt;0x01 0x21 0x0f 0x02 0x12 0x01 0x02 0x13 0x02 0x03 0x14 0x01 0x03 0x15 0x02 0x04 0x16 0x01 0x04 0x17 0x02 0x04 0x18 0x04 0x04 0x19 0x08 0x05 0x1a 0x01 0x05 0x1b 0x02 0x05 0x1c 0x04 0x05 0x1d 0x08&gt;;
							phandle = &lt;0x593&gt;;
							qcom,swr-wakeup-required = &lt;0x00&gt;;
							qcom,swr-mstr-tx-wakeup-capable;
							qcom,swr-mstr-irq-wakeup-capable = &lt;0x01&gt;;
							qcom,swr-num-ports = &lt;0x05&gt;;

wcd937x-tx-slave {
								compatible = &quot;qcom,wcd937x-slave&quot;;
								reg = &lt;0x00 0x1170223&gt;;
								phandle = &lt;0x4ee&gt;;
							};
						};
					};
				};

sound {
					qcom,audio-routing = &quot;AMIC2\0MIC BIAS2\0MIC BIAS2\0Analog Mic2\0AMIC1\0MIC BIAS1\0MIC BIAS1\0Analog Mic1\0AMIC3\0MIC BIAS3\0MIC BIAS3\0Analog Mic3\0AMIC4\0MIC BIAS3\0TX_AIF1 CAP\0VA_MCLK\0TX_AIF2 CAP\0VA_MCLK\0RX AIF1 PB\0VA_MCLK\0RX AIF2 PB\0VA_MCLK\0RX AIF3 PB\0VA_MCLK\0RX AIF4 PB\0VA_MCLK\0HPHL_OUT\0VA_MCLK\0HPHR_OUT\0VA_MCLK\0AUX_OUT\0VA_MCLK\0IN1_HPHL\0HPHL_OUT\0IN2_HPHR\0HPHR_OUT\0IN3_AUX\0AUX_OUT\0TX SWR_ADC0\0ADC1_OUTPUT\0TX SWR_ADC2\0ADC2_OUTPUT\0TX SWR_ADC3\0ADC3_OUTPUT\0RX_TX DEC0_INP\0TX DEC0 MUX\0RX_TX DEC1_INP\0TX DEC1 MUX\0RX_TX DEC2_INP\0TX DEC2 MUX\0RX_TX DEC3_INP\0TX DEC3 MUX\0SpkrLeft IN\0WSA_SPK1 OUT\0SpkrRight IN\0WSA_SPK2 OUT\0WSA_SPK1 OUT\0VA_MCLK\0WSA_SPK2 OUT\0VA_MCLK&quot;;
					qcom,ext-disp-audio-rx = &lt;0x01&gt;;
					qcom,msm-mbhc-gnd-swh = &lt;0x01&gt;;
					asoc-codec = &lt;0x48c 0x4af 0x376&gt;;
					asoc-cpu-names = &quot;msm-dai-q6-dp.24608\0msm-dai-q6-mi2s.0\0msm-dai-q6-mi2s.1\0msm-dai-q6-mi2s.2\0msm-dai-q6-mi2s.3\0msm-dai-q6-mi2s.4\0msm-dai-q6-auxpcm.1\0msm-dai-q6-auxpcm.2\0msm-dai-q6-auxpcm.3\0msm-dai-q6-auxpcm.4\0msm-dai-q6-auxpcm.5\0msm-dai-q6-dev.224\0msm-dai-q6-dev.225\0msm-dai-q6-dev.241\0msm-dai-q6-dev.240\0msm-dai-q6-dev.32771\0msm-dai-q6-dev.32772\0msm-dai-q6-dev.32773\0msm-dai-q6-dev.32770\0msm-dai-q6-dev.16398\0msm-dai-q6-dev.16399\0msm-dai-q6-dev.16401\0msm-dai-q6-dev.16400\0msm-dai-q6-dev.8194\0msm-dai-q6-dev.8195\0msm-dai-q6-dev.28672\0msm-dai-q6-dev.28673\0msm-dai-q6-tdm.36864\0msm-dai-q6-tdm.36865\0msm-dai-q6-tdm.36880\0msm-dai-q6-tdm.36881\0msm-dai-q6-tdm.36896\0msm-dai-q6-tdm.36897\0msm-dai-q6-tdm.36912\0msm-dai-q6-tdm.36913\0msm-dai-q6-tdm.36928\0msm-dai-q6-tdm.36929\0msm-dai-cdc-dma-dev.45056\0msm-dai-cdc-dma-dev.45057\0msm-dai-cdc-dma-dev.45058\0msm-dai-cdc-dma-dev.45059\0msm-dai-cdc-dma-dev.45061\0msm-dai-cdc-dma-dev.45104\0msm-dai-cdc-dma-dev.45105\0msm-dai-cdc-dma-dev.45106\0msm-dai-cdc-dma-dev.45107\0msm-dai-cdc-dma-dev.45108\0msm-dai-cdc-dma-dev.45109\0msm-dai-cdc-dma-dev.45110\0msm-dai-cdc-dma-dev.45111\0msm-dai-cdc-dma-dev.45112\0msm-dai-cdc-dma-dev.45113\0msm-dai-cdc-dma-dev.45114\0msm-dai-cdc-dma-dev.45115\0msm-dai-cdc-dma-dev.45116\0msm-dai-cdc-dma-dev.45118&quot;;
					qcom,cdc-dmic01-gpios = &lt;0x4ef&gt;;
					asoc-codec-names = &quot;msm-stub-codec.1\0bolero_codec\0msm-ext-disp-audio-codec-rx&quot;;
					qcom,msm_audio_ssr_devs = &lt;0x4ac 0x4ae 0x4f6 0x4af&gt;;
					qcom,codec-aux-devs = &lt;0x4f5&gt;;
					asoc-cpu = &lt;0x26b 0x26c 0x26d 0x26e 0x26f 0x270 0x271 0x272 0x273 0x274 0x275 0x276 0x277 0x278 0x279 0x27a 0x27b 0x27c 0x27d 0x27e 0x27f 0x280 0x281 0x282 0x283 0x284 0x285 0x286 0x287 0x288 0x289 0x28a 0x28b 0x28c 0x28d 0x28e 0x28f 0x290 0x291 0x292 0x293 0x294 0x295 0x296 0x297 0x298 0x299 0x29a 0x29b 0x29c 0x29d 0x29e 0x29f 0x2a0 0x2a1 0x2a2&gt;;
					qcom,msm-mi2s-master = &lt;0x01 0x01 0x01 0x01 0x01&gt;;
					qcom,wsa-devs = &lt;0x4f1 0x4f2 0x4f3 0x4f4&gt;;
					qcom,model = &quot;sm6150-idp-snd-card&quot;;
					compatible = &quot;qcom,sm6150-asoc-snd&quot;;
					qcom,msm-mbhc-hphl-swh = &lt;0x01&gt;;
					qcom,pri-mi2s-gpios = &lt;0x513&gt;;
					qcom,auxpcm-audio-intf = &lt;0x01&gt;;
					phandle = &lt;0x4b7&gt;;
					qcom,codec-max-aux-devs = &lt;0x01&gt;;
					asoc-platform-names = &quot;msm-pcm-dsp.0\0msm-pcm-dsp.1\0msm-pcm-dsp.2\0msm-voip-dsp\0msm-pcm-voice\0msm-pcm-loopback\0msm-compress-dsp\0msm-pcm-hostless\0msm-pcm-afe\0msm-lsm-client\0msm-pcm-routing\0msm-compr-dsp\0msm-pcm-dsp-noirq&quot;;
					qcom,mi2s-audio-intf = &lt;0x01&gt;;
					qcom,wsa-aux-dev-prefix = &quot;SpkrLeft\0SpkrRight\0SpkrLeft\0SpkrRight&quot;;
					qcom,wsa-max-devs = &lt;0x00&gt;;
					asoc-platform = &lt;0x25e 0x25f 0x260 0x261 0x262 0x263 0x264 0x265 0x266 0x267 0x268 0x269 0x26a&gt;;
					qcom,wcn-btfm = &lt;0x01&gt;;
					qcom,cdc-dmic23-gpios = &lt;0x4f0&gt;;
				};
			};
		};

qcom,msm-dai-fe {
			compatible = &quot;qcom,msm-dai-fe&quot;;
		};

timer@0x17c20000 {
			#address-cells = &lt;0x01&gt;;
			#size-cells = &lt;0x01&gt;;
			clock-frequency = &lt;0x124f800&gt;;
			compatible = &quot;arm,armv7-timer-mem&quot;;
			ranges;
			reg = &lt;0x17c20000 0x1000&gt;;

frame@17c2b000 {
				interrupts = &lt;0x00 0x0d 0x04&gt;;
				frame-number = &lt;0x05&gt;;
				status = &quot;disabled&quot;;
				reg = &lt;0x17c2b000 0x1000&gt;;
			};

frame@17c25000 {
				interrupts = &lt;0x00 0x0a 0x04&gt;;
				frame-number = &lt;0x02&gt;;
				status = &quot;disabled&quot;;
				reg = &lt;0x17c25000 0x1000&gt;;
			};

frame@0x17c21000 {
				interrupts = &lt;0x00 0x08 0x04 0x00 0x06 0x04&gt;;
				frame-number = &lt;0x00&gt;;
				reg = &lt;0x17c21000 0x1000 0x17c22000 0x1000&gt;;
			};

frame@17c2d000 {
				interrupts = &lt;0x00 0x0e 0x04&gt;;
				frame-number = &lt;0x06&gt;;
				status = &quot;disabled&quot;;
				reg = &lt;0x17c2d000 0x1000&gt;;
			};

frame@17c27000 {
				interrupts = &lt;0x00 0x0b 0x04&gt;;
				frame-number = &lt;0x03&gt;;
				status = &quot;disabled&quot;;
				reg = &lt;0x17c27000 0x1000&gt;;
			};

frame@17c29000 {
				interrupts = &lt;0x00 0x0c 0x04&gt;;
				frame-number = &lt;0x04&gt;;
				status = &quot;disabled&quot;;
				reg = &lt;0x17c29000 0x1000&gt;;
			};

frame@17c23000 {
				interrupts = &lt;0x00 0x09 0x04&gt;;
				frame-number = &lt;0x01&gt;;
				status = &quot;disabled&quot;;
				reg = &lt;0x17c23000 0x1000&gt;;
			};
		};

tpdm@6834000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-modem-1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6834000 0x1000&gt;;
			phandle = &lt;0x428&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x1f0&gt;;
					phandle = &lt;0x1ee&gt;;
				};
			};
		};

spi@0xa90000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x19d&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			interrupts = &lt;0x00 0x165 0x00&gt;;
			clocks = &lt;0x27 0x5f 0x27 0x69 0x27 0x6a&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			spi-max-frequency = &lt;0x2faf080&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,spi-geni&quot;;
			pinctrl-1 = &lt;0x19e&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0xa90000 0x4000&gt;;
			phandle = &lt;0x366&gt;;
			dmas = &lt;0x183 0x00 0x04 0x01 0x40 0x00 0x183 0x01 0x04 0x01 0x40 0x00&gt;;
		};

rpmh-regulator-modemlvl {
			compatible = &quot;qcom,rpmh-arc-regulator&quot;;
			qcom,resource-name = &quot;mss.lvl&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm6150l-s7 {
				regulator-max-microvolt = &lt;0x10000&gt;;
				regulator-min-microvolt = &lt;0x11&gt;;
				regulator-name = &quot;pm6150l_s7_level&quot;;
				qcom,init-voltage-level = &lt;0x11&gt;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0xb0&gt;;
			};
		};

qcom,gdsc@17d034 {
			qcom,no-status-check-on-disable;
			qcom,gds-timeout = &lt;0x1f4&gt;;
			regulator-name = &quot;hlos1_vote_aggre_noc_mmu_tbu1_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x17d034 0x04&gt;;
			phandle = &lt;0x1c6&gt;;
		};

qcom,mdss_dsi_xiaomi_f4_42_06_0c_fhd_cmd {
			qcom,ulps-enabled;
			qcom,disp-doze-backlight-threshold = &lt;0x08&gt;;
			qcom,mdss-pan-physical-width-dimension = &lt;0x45&gt;;
			qcom,mdss-dsi-panel-name = &quot;xiaomi f4 42 06 0c fhd cmd dsi panel&quot;;
			qcom,mdss-pan-physical-height-dimension = &lt;0x95&gt;;
			qcom,mdss-dsi-te-using-te-pin;
			qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
			qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
			qcom,mdss-dsi-t-clk-post = &lt;0x0e&gt;;
			qcom,mdss-dsi-lane-2-state;
			qcom,mdss-dsi-te-check-enable;
			qcom,mdss-dsi-bllp-eof-power-mode;
			qcom,mdss-dsi-panel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
			qcom,bl-update-flag = &quot;delay_until_first_frame&quot;;
			qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
			qcom,disp-fod-off-dimming-delay = &lt;0x55&gt;;
			qcom,dispparam-enabled;
			qcom,mdss-dsi-panel-peak-brightness = &lt;0x419ce0&gt;;
			qcom,mdss-dsi-lane-3-state;
			qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
			qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-bl-dcs-type-ss-ea;
			qcom,mdss-dsi-reset-sequence = &lt;0x00 0x01 0x01 0x0a&gt;;
			qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
			qcom,mdss-dsi-lane-0-state;
			qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
			qcom,mdss-panel-on-dimming-delay = &lt;0xc8&gt;;
			qcom,mdss-dsi-t-clk-pre = &lt;0x33&gt;;
			qcom,mdss-dsi-panel-hdr-enabled;
			qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
			phandle = &lt;0x53c&gt;;
			qcom,mdss-dsi-bllp-power-mode;
			qcom,mdss-dsi-panel-sleepwrmod = &lt;0x00&gt;;
			qcom,mdss-dsi-stream = &lt;0x00&gt;;
			qcom,mdss-dsi-lp11-init;
			qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
			qcom,mdss-dsi-tx-eot-append;
			qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
			qcom,mdss-dsi-border-color = &lt;0x00&gt;;
			qcom,mdss-dsi-lane-1-state;
			qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
			qcom,mdss-dsi-bpp = &lt;0x18&gt;;
			qcom,mdss-brightness-max-level = &lt;0x7ff&gt;;

qcom,mdss-dsi-display-timings {

rpmh-regulator-gfxlvl {
			compatible = &quot;qcom,rpmh-arc-regulator&quot;;
			qcom,resource-name = &quot;gfx.lvl&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm6150-s2-level {
				regulator-max-microvolt = &lt;0x10000&gt;;
				regulator-min-microvolt = &lt;0x11&gt;;
				regulator-name = &quot;pm6150_s2_level&quot;;
				qcom,init-voltage-level = &lt;0x11&gt;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x20&gt;;
			};
		};

audio_etm0 {
			qcom,inst-id = &lt;0x05&gt;;
			coresight-name = &quot;coresight-audio-etm0&quot;;
			compatible = &quot;qcom,coresight-remote-etm&quot;;

port {

endpoint {
					remote-endpoint = &lt;0x1e3&gt;;
					phandle = &lt;0x1e0&gt;;
				};
			};
		};

ufsice@1d90000 {
			clock-names = &quot;ufs_core_clk\0bus_clk\0iface_clk\0ice_core_clk&quot;;
			qcom,bus-vector-names = &quot;MIN\0MAX&quot;;
			qcom,msm-bus,name = &quot;ufs_ice_noc&quot;;
			qcom,instance-type = &quot;ufs&quot;;
			clocks = &lt;0x27 0x7e 0x27 0x7c 0x27 0x7d 0x27 0x81&gt;;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x02&gt;;
			qcom,op-freq-hz = &lt;0x00 0x00 0x00 0x11e1a300&gt;;
			compatible = &quot;qcom,ice&quot;;
			vdd-hba-supply = &lt;0x9b&gt;;
			reg = &lt;0x1d90000 0x8000&gt;;
			phandle = &lt;0x2dd&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x01 0x28a 0x00 0x00 0x01 0x28a 0x3e8 0x00&gt;;
			qcom,enable-ice-clk;
		};

rpmh-regulator-ldoa14 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa14&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l14 {
				regulator-max-microvolt = &lt;0x1c5200&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x1a3ec0&gt;;
				regulator-min-microvolt = &lt;0x1a3ec0&gt;;
				regulator-name = &quot;pm6150_l14&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x409&gt;;
			};
		};

qcom,csid-lite0@acc8000 {
			camss-supply = &lt;0x1ae&gt;;
			clock-control-debugfs = &quot;true&quot;;
			clock-names = &quot;ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_clk&quot;;
			reg-names = &quot;csid-lite&quot;;
			reg-cam-base = &lt;0xc8000&gt;;
			cell-index = &lt;0x02&gt;;
			interrupts = &lt;0x00 0x1b6 0x00&gt;;
			clocks = &lt;0x29 0x42 0x29 0x41 0x29 0x1b 0x29 0x40 0x29 0x3f 0x29 0x3e&gt;;
			clock-cntl-level = &quot;lowsvs\0svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,csid-lite175&quot;;
			src-clock-name = &quot;ife_csid_clk_src&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;csid-lite&quot;;
			reg = &lt;0xacc8000 0x1000&gt;;
			regulator-names = &quot;camss&quot;;
			phandle = &lt;0x391&gt;;
			clock-rates = &lt;0x11e1a300 0x00 0x00 0x00 0x1312d000 0x00 0x16e36000 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x17d78400 0x00 0x00 0x00 0x23c34600 0x00&gt;;
		};

qcom,cpu6-llcc-ddr-latmon {
			qcom,cachemiss-ev = &lt;0x1000&gt;;
			qcom,core-dev-table = &lt;0xc4c70 0x6b8 0x10b170 0x826 0x1433e0 0xf27 0x1a1300 0x172b 0x253500 0x1ae1&gt;;
			qcom,cpulist = &lt;0x17 0x18&gt;;
			compatible = &quot;qcom,arm-memlat-mon&quot;;
			phandle = &lt;0x318&gt;;
			qcom,target-dev = &lt;0xc4&gt;;
		};

qcom,ipe0 {
			ipe0-vdd-supply = &lt;0x1b9&gt;;
			clock-control-debugfs = &quot;true&quot;;
			clock-names = &quot;ipe_0_ahb_clk\0ipe_0_areg_clk\0ipe_0_axi_clk\0ipe_0_clk_src\0ipe_0_clk&quot;;
			reg-names = &quot;ipe0_top&quot;;
			reg-cam-base = &lt;0x87000&gt;;
			cell-index = &lt;0x00&gt;;
			clocks = &lt;0x29 0x43 0x29 0x44 0x29 0x45 0x29 0x47 0x29 0x46&gt;;
			clock-cntl-level = &quot;lowsvs\0svs\0svs_l1\0nominal\0turbo&quot;;
			compatible = &quot;qcom,cam-ipe&quot;;
			src-clock-name = &quot;ipe_0_clk_src&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xac87000 0x3000&gt;;
			regulator-names = &quot;ipe0-vdd&quot;;
			phandle = &lt;0x394&gt;;
			qcom,cam-cx-ipeak = &lt;0x1a3 0x03&gt;;
			clock-rates = &lt;0x00 0x00 0x00 0x1443fd00 0x00 0x00 0x00 0x00 0x19a14780 0x00 0x00 0x00 0x00 0x1efe9200 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600 0x00&gt;;
		};

qcom,mdss_dp_pll@ae90000 {
			clock-names = &quot;iface_clk\0ref_clk_src\0ref_clk\0cfg_ahb_clk\0pipe_clk&quot;;
			reg-names = &quot;pll_base\0phy_base\0ln_tx0_base\0ln_tx1_base\0gdsc_base&quot;;
			cell-index = &lt;0x00&gt;;
			clocks = &lt;0x2a 0x01 0x2f 0x00 0x27 0x92 0x27 0x97 0x27 0x96&gt;;
			#clock-cells = &lt;0x01&gt;;
			label = &quot;MDSS DP PLL&quot;;
			compatible = &quot;qcom,mdss_dp_pll_10nm&quot;;
			gdsc-supply = &lt;0xcb&gt;;
			clock-rate = &lt;0x00&gt;;
			reg = &lt;0x88ea000 0x200 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0xaf03000 0x08&gt;;
			phandle = &lt;0x1aa&gt;;

qcom,platform-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

qcom,platform-supply-entry@0 {
					qcom,supply-disable-load = &lt;0x00&gt;;
					qcom,supply-enable-load = &lt;0x00&gt;;
					qcom,supply-name = &quot;gdsc&quot;;
					qcom,supply-max-voltage = &lt;0x00&gt;;
					reg = &lt;0x00&gt;;
					qcom,supply-min-voltage = &lt;0x00&gt;;
				};
			};
		};

spi@0xa88000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x19b&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			interrupts = &lt;0x00 0x163 0x00&gt;;
			clocks = &lt;0x27 0x5b 0x27 0x69 0x27 0x6a&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			spi-max-frequency = &lt;0x2faf080&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,spi-geni&quot;;
			pinctrl-1 = &lt;0x19c&gt;;
			status = &quot;ok&quot;;
			reg = &lt;0xa88000 0x4000&gt;;
			phandle = &lt;0x365&gt;;
			dmas = &lt;0x183 0x00 0x02 0x01 0x40 0x00 0x183 0x01 0x02 0x01 0x40 0x00&gt;;

irled@0 {
				spi-max-frequency = &lt;0x124f800&gt;;
				compatible = &quot;ir-spi&quot;;
				status = &quot;ok&quot;;
				reg = &lt;0x00&gt;;
			};
		};

dsu_pmu@0 {
			interrupts = &lt;0x00 0x32 0x04&gt;;
			compatible = &quot;arm,dsu-pmu&quot;;
			cpus = &lt;0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18&gt;;
		};

cti@6c29000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-dlct_cti0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6c29000 0x1000&gt;;
			phandle = &lt;0x468&gt;;
		};

cti@6b05000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-swao_cti1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b05000 0x1000&gt;;
			phandle = &lt;0x470&gt;;
		};

arm,smmu-kgsl@5040000 {
			#global-interrupts = &lt;0x02&gt;;
			clock-names = &quot;gcc_gpu_memnoc_gfx_clk&quot;;
			attach-impl-defs = &lt;0x6000 0x2378 0x6060 0x1055 0x678c 0x08 0x6794 0x28 0x6800 0x06 0x6900 0x3ff 0x6924 0x204 0x6928 0x11000 0x6930 0x800 0x6960 0xffffffff 0x6b64 0x1a5551 0x6b68 0x9a82a382&gt;;
			interrupts = &lt;0x00 0xe5 0x04 0x00 0xe7 0x04 0x00 0x16c 0x04 0x00 0x16d 0x04 0x00 0x16e 0x04 0x00 0x16f 0x04 0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04 0x00 0x173 0x04&gt;;
			clocks = &lt;0x27 0x2b&gt;;
			qcom,disable-atos;
			qcom,regulator-names = &quot;vdd&quot;;
			vdd-supply = &lt;0x1c5&gt;;
			qcom,use-3-lvl-tables;
			#iommu-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,smmu-v2&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x5040000 0x10000&gt;;
			phandle = &lt;0x1cd&gt;;
			qcom,dynamic;
		};

qcom,cpu0-llcc-ddr-lat {
			qcom,src-dst-ports = &lt;0x81 0x200&gt;;
			governor = &quot;performance&quot;;
			compatible = &quot;qcom,devbw&quot;;
			phandle = &lt;0xc3&gt;;
			qcom,active-only;
			operating-points-v2 = &lt;0xbe&gt;;
		};

timer {
			interrupts = &lt;0x01 0x01 0xf08 0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x00 0xf08&gt;;
			clock-frequency = &lt;0x124f800&gt;;
			compatible = &quot;arm,armv8-timer&quot;;
		};

qcom,smp2p-cdsp {
			qcom,local-pid = &lt;0x00&gt;;
			interrupts = &lt;0x00 0x240 0x01&gt;;
			qcom,remote-pid = &lt;0x05&gt;;
			compatible = &quot;qcom,smp2p&quot;;
			qcom,smem = &lt;0x5e 0x1b0&gt;;
			qcom,ipc = &lt;0x99 0x00 0x06&gt;;

qcom,smp2p-rdbg5-out {
				qcom,entry-name = &quot;rdbg&quot;;
				#qcom,smem-state-cells = &lt;0x01&gt;;
				phandle = &lt;0x1be&gt;;
			};

qcom,smp2p-qvrexternal5-out {
				qcom,entry-name = &quot;qvrexternal&quot;;
				#qcom,smem-state-cells = &lt;0x01&gt;;
				phandle = &lt;0x1c0&gt;;
			};

slave-kernel {
				qcom,entry-name = &quot;slave-kernel&quot;;
				#interrupt-cells = &lt;0x02&gt;;
				phandle = &lt;0xae&gt;;
				interrupt-controller;
			};

master-kernel {
				qcom,entry-name = &quot;master-kernel&quot;;
				#qcom,smem-state-cells = &lt;0x01&gt;;
				phandle = &lt;0xaf&gt;;
			};

qcom,smp2p-rdbg5-in {
				qcom,entry-name = &quot;rdbg&quot;;
				#interrupt-cells = &lt;0x02&gt;;
				phandle = &lt;0x1bf&gt;;
				interrupt-controller;
			};
		};

tx_swr_clk_data_pinctrl {
			pinctrl-names = &quot;aud_active\0aud_sleep&quot;;
			pinctrl-0 = &lt;0x503 0x504 0x505&gt;;
			compatible = &quot;qcom,msm-cdc-pinctrl&quot;;
			qcom,lpi-gpios;
			pinctrl-1 = &lt;0x506 0x507 0x508&gt;;
			phandle = &lt;0x4e2&gt;;
		};

rpmh-regulator-ldoa9 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa9&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l9 {
				regulator-max-microvolt = &lt;0xb98c0&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x98580&gt;;
				regulator-min-microvolt = &lt;0x98580&gt;;
				regulator-name = &quot;pm6150_l9&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0xb8&gt;;
			};
		};

dsi_panel_pwr_supply {
			#address-cells = &lt;0x01&gt;;
			#size-cells = &lt;0x00&gt;;
			phandle = &lt;0x520&gt;;

qcom,panel-supply-entry@1 {
				qcom,supply-disable-load = &lt;0x64&gt;;
				qcom,supply-enable-load = &lt;0x186a0&gt;;
				qcom,supply-name = &quot;lab&quot;;
				qcom,supply-max-voltage = &lt;0x5b8d80&gt;;
				reg = &lt;0x01&gt;;
				qcom,supply-min-voltage = &lt;0x4630c0&gt;;
			};

qcom,panel-supply-entry@2 {
				qcom,supply-disable-load = &lt;0x64&gt;;
				qcom,supply-enable-load = &lt;0x186a0&gt;;
				qcom,supply-name = &quot;ibb&quot;;
				qcom,supply-max-voltage = &lt;0x5b8d80&gt;;
				reg = &lt;0x02&gt;;
				qcom,supply-min-voltage = &lt;0x4630c0&gt;;
			};

qcom,panel-supply-entry@0 {
				qcom,supply-disable-load = &lt;0x50&gt;;
				qcom,supply-enable-load = &lt;0x7d00&gt;;
				qcom,supply-name = &quot;vddio&quot;;
				qcom,supply-max-voltage = &lt;0x1d0d80&gt;;
				reg = &lt;0x00&gt;;
				qcom,supply-min-voltage = &lt;0x1b7740&gt;;
			};
		};

rpmh-regulator-lmxlvl {
			compatible = &quot;qcom,rpmh-arc-regulator&quot;;
			qcom,resource-name = &quot;lmx.lvl&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm6150-l7 {
				regulator-max-microvolt = &lt;0x10000&gt;;
				regulator-min-microvolt = &lt;0x11&gt;;
				regulator-name = &quot;pm6150_l7_level&quot;;
				qcom,init-voltage-level = &lt;0x11&gt;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0xa0&gt;;
			};
		};

i2c@0x890000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x16f&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			interrupts = &lt;0x00 0x25d 0x00&gt;;
			clocks = &lt;0x27 0x4c 0x27 0x67 0x27 0x68&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x168&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,i2c-geni&quot;;
			pinctrl-1 = &lt;0x170&gt;;
			status = &quot;ok&quot;;
			reg = &lt;0x890000 0x4000&gt;;
			phandle = &lt;0x351&gt;;
			dmas = &lt;0x165 0x00 0x04 0x03 0x40 0x00 0x165 0x01 0x04 0x03 0x40 0x00&gt;;

aw882xx_smartpa@34 {
				pinctrl-names = &quot;default\0sleep&quot;;
				irq-gpio = &lt;0x174 0x5d 0x00&gt;;
				pinctrl-0 = &lt;0x51c&gt;;
				monitor-flag = &lt;0x01&gt;;
				interrupts = &lt;0x5d 0x00&gt;;
				interrupt-parent = &lt;0x174&gt;;
				reset-gpio = &lt;0x174 0x40 0x00&gt;;
				compatible = &quot;awinic,aw882xx_smartpa&quot;;
				sound-channel = &lt;0x00&gt;;
				pinctrl-1 = &lt;0x51d&gt;;
				status = &quot;ok&quot;;
				interrupt-names = &quot;smartpa_irq&quot;;
				reg = &lt;0x34&gt;;
				aw-cali-mode = &quot;aw_class&quot;;
			};

aw882xx_smartpa@35 {
				pinctrl-names = &quot;default\0sleep&quot;;
				irq-gpio = &lt;0x174 0x38 0x00&gt;;
				pinctrl-0 = &lt;0x51e&gt;;
				monitor-flag = &lt;0x01&gt;;
				interrupts = &lt;0x38 0x00&gt;;
				interrupt-parent = &lt;0x174&gt;;
				reset-gpio = &lt;0x174 0x48 0x00&gt;;
				compatible = &quot;awinic,aw882xx_smartpa&quot;;
				sound-channel = &lt;0x01&gt;;
				pinctrl-1 = &lt;0x51f&gt;;
				status = &quot;ok&quot;;
				interrupt-names = &quot;smartpa_irq&quot;;
				reg = &lt;0x35&gt;;
				aw-cali-mode = &quot;aw_class&quot;;
			};
		};

qcom,bus_proxy_client {
			qcom,msm-bus,name = &quot;bus-proxy-client&quot;;
			qcom,msm-bus,active-only;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x02&gt;;
			compatible = &quot;qcom,bus-proxy-client&quot;;
			status = &quot;ok&quot;;
			phandle = &lt;0x320&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x16 0x200 0x00 0x00 0x16 0x200 0x00 0x4c4b40&gt;;
		};

qcom,ipa@1e00000 {
			qcom,use-ipa-tethering-bridge;
			qcom,ipa-hw-mode = &lt;0x00&gt;;
			qcom,ipa-hw-ver = &lt;0x10&gt;;
			qcom,smmu-fast-map;
			reg-names = &quot;ipa-base\0gsi-base&quot;;
			qcom,bus-vector-names = &quot;MIN\0SVS2\0SVS\0NOMINAL\0TURBO&quot;;
			qcom,msm-bus,name = &quot;ipa&quot;;
			qcom,throughput-threshold = &lt;0x136 0x258 0x3e8&gt;;
			interrupts = &lt;0x00 0x137 0x00 0x00 0x1b0 0x00&gt;;
			qcom,use-ipa-pm;
			qcom,msm-bus,num-paths = &lt;0x04&gt;;
			qcom,msm-bus,num-cases = &lt;0x05&gt;;
			qcom,ipa-wdi2_over_gsi;
			compatible = &quot;qcom,ipa&quot;;
			qcom,arm-smmu;
			interrupt-names = &quot;ipa-irq\0gsi-irq&quot;;
			qcom,use-64-bit-dma-mask;
			qcom,bandwidth-vote-for-ipa;
			reg = &lt;0x1e00000 0x34000 0x1e04000 0x2c000&gt;;
			qcom,ipa-fltrt-not-hashable;
			phandle = &lt;0x30f&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x5a 0x200 0x00 0x00 0x5a 0x249 0x00 0x00 0x01 0x2a4 0x00 0x00 0x8f 0x309 0x00 0x00 0x5a 0x200 0x13880 0x71868 0x5a 0x249 0x13880 0x10bda 0x01 0x2a4 0x13880 0x1e 0x8f 0x309 0x00 0x1e 0x5a 0x200 0x13880 0x1e8480 0x5a 0x249 0x13880 0x414c5 0x01 0x2a4 0x13880 0x1ad42 0x8f 0x309 0x00 0x6d 0x5a 0x200 0x324b0 0x3d0900 0x5a 0x249 0x324b0 0xae101 0x01 0x2a4 0x324b0 0x78000 0x8f 0x309 0x00 0x1eb 0x5a 0x200 0x324b0 0x556eb4 0x5a 0x249 0x324b0 0x15eb41 0x01 0x2a4 0x324b0 0x78000 0x8f 0x309 0x00 0x1eb&gt;;
			qcom,ee = &lt;0x00&gt;;
			qcom,modem-cfg-emb-pipe-flt;
			qcom,scaling-exceptions;
			qcom,ipa-wdi2;
			qcom,ipa-endp-delay-wa;

qcom,smp2p_map_ipa_1_in {
				interrupts-extended = &lt;0xbb 0x00 0x00&gt;;
				compatible = &quot;qcom,smp2p-map-ipa-1-in&quot;;
				interrupt-names = &quot;ipa-smp2p-in&quot;;
			};

qcom,smp2p_map_ipa_1_out {
				qcom,smem-state-names = &quot;ipa-smp2p-out&quot;;
				compatible = &quot;qcom,smp2p-map-ipa-1-out&quot;;
				qcom,smem-states = &lt;0xba 0x00&gt;;
			};
		};

qcom,dsi-display@28 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x53c&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_xiaomi_f4_42_06_0c_fhd_cmd_display&quot;;
			phandle = &lt;0x553&gt;;
		};

qcom,msm-dai-q6-dp {
			compatible = &quot;qcom,msm-dai-q6-hdmi&quot;;
			qcom,msm-dai-q6-dev-id = &lt;0x6020&gt;;
			phandle = &lt;0x26b&gt;;
		};

syscon@1f40000 {
			compatible = &quot;syscon&quot;;
			reg = &lt;0x1f40000 0x20000&gt;;
			phandle = &lt;0x8f&gt;;
		};

wcd9xxx-irq {
			pinctrl-names = &quot;default&quot;;
			pinctrl-0 = &lt;0x3d4&gt;;
			qcom,gpio-connect = &lt;0x174 0x7a 0x00&gt;;
			interrupt-parent = &lt;0x174&gt;;
			compatible = &quot;qcom,wcd9xxx-irq&quot;;
			#interrupt-cells = &lt;0x01&gt;;
			status = &quot;disabled&quot;;
			phandle = &lt;0x50f&gt;;
			interrupt-controller;
		};

qcom,snoc_cnoc_keepalive {
			qcom,src-dst-ports = &lt;0x01 0x273&gt;;
			governor = &quot;powersave&quot;;
			compatible = &quot;qcom,devbw&quot;;
			status = &quot;ok&quot;;
			phandle = &lt;0x31f&gt;;
			qcom,active-only;
			operating-points-v2 = &lt;0xca&gt;;
		};

qcom,rmnet-ipa {
			qcom,ipa-napi-enable;
			qcom,rmnet-ipa-ssr;
			qcom,ipa-advertise-sg-support;
			compatible = &quot;qcom,rmnet-ipa3&quot;;
			qcom,ipa-platform-type-msm;
		};

cti@78f0000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-apss_cti1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x78f0000 0x1000&gt;;
			phandle = &lt;0x45f&gt;;
		};

rpmh-regulator-ldoc11 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoc11&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150l-l11 {
				regulator-max-microvolt = &lt;0x33e140&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x2d0370&gt;;
				regulator-min-microvolt = &lt;0x2d0370&gt;;
				regulator-name = &quot;pm6150l_l11&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x414&gt;;
			};
		};

qcom,mdss_dsi_pll@ae94a00 {
			clock-names = &quot;iface_clk&quot;;
			reg-names = &quot;pll_base\0phy_base\0gdsc_base\0dynamic_pll_base&quot;;
			cell-index = &lt;0x00&gt;;
			memory-region = &lt;0x1a5&gt;;
			clocks = &lt;0x2a 0x01&gt;;
			#clock-cells = &lt;0x01&gt;;
			label = &quot;MDSS DSI 0 PLL&quot;;
			compatible = &quot;qcom,mdss_dsi_pll_10nm&quot;;
			gdsc-supply = &lt;0xcb&gt;;
			clock-rate = &lt;0x00&gt;;
			reg = &lt;0xae94a00 0x1e0 0xae94400 0x800 0xaf03000 0x08 0xae94200 0x100&gt;;
			phandle = &lt;0x36a&gt;;

qcom,platform-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

i2c@0x888000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x16b&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			interrupts = &lt;0x00 0x25b 0x00&gt;;
			clocks = &lt;0x27 0x48 0x27 0x67 0x27 0x68&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x168&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,i2c-geni&quot;;
			pinctrl-1 = &lt;0x16c&gt;;
			status = &quot;ok&quot;;
			reg = &lt;0x888000 0x4000&gt;;
			phandle = &lt;0x34f&gt;;
			dmas = &lt;0x165 0x00 0x02 0x03 0x40 0x00 0x165 0x01 0x02 0x03 0x40 0x00&gt;;
			qcom,clk-freq-out = &lt;0xf4240&gt;;

nq@28 {
				pinctrl-names = &quot;nfc_active\0nfc_suspend&quot;;
				pinctrl-0 = &lt;0x3a9 0x3ab 0x3ad&gt;;
				qcom,nq-clkreq = &lt;0x174 0x1f 0x00&gt;;
				qcom,nq-firm = &lt;0x174 0x24 0x00&gt;;
				qcom,nq-irq = &lt;0x174 0x25 0x00&gt;;
				qcom,nq-ven = &lt;0x174 0x42 0x00&gt;;
				interrupts = &lt;0x25 0x00&gt;;
				interrupt-parent = &lt;0x174&gt;;
				compatible = &quot;qcom,nq-nci&quot;;
				pinctrl-1 = &lt;0x3aa 0x3ac 0x3ae&gt;;
				interrupt-names = &quot;nfc_irq&quot;;
				reg = &lt;0x28&gt;;
			};
		};

qcom,kgsl-busmon {
			label = &quot;kgsl-busmon&quot;;
			compatible = &quot;qcom,kgsl-busmon&quot;;
			phandle = &lt;0x4cf&gt;;
		};

qcom,dsi-display@6 {
			qcom,dsi-phy-num = &lt;0x00 0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x528&gt;;
			qcom,dsi-ctrl-num = &lt;0x00 0x01&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_dual_sim_cmd_display&quot;;
			phandle = &lt;0x545&gt;;
		};

qcom,dsi-display@18 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x533&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_ss_fhd_eb_f10_cmd_display&quot;;
			phandle = &lt;0x550&gt;;
		};

qcom,cpu6-cpu-ddr-latfloor {
			qcom,src-dst-ports = &lt;0x81 0x200&gt;;
			governor = &quot;performance&quot;;
			compatible = &quot;qcom,devbw&quot;;
			phandle = &lt;0xc6&gt;;
			qcom,active-only;
			operating-points-v2 = &lt;0xbe&gt;;
		};

slim@62e40000 {
			reg-names = &quot;slimbus_physical\0slimbus_bam_physical&quot;;
			cell-index = &lt;0x03&gt;;
			qcom,iommu-s1-bypass;
			interrupts = &lt;0x00 0x123 0x00 0x00 0x124 0x00&gt;;
			compatible = &quot;qcom,slim-ngd&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;slimbus_irq\0slimbus_bam_irq&quot;;
			reg = &lt;0x62e40000 0x2c000 0x62e04000 0x20000&gt;;
			phandle = &lt;0x2b8&gt;;

qcom,iommu_slim_ctrl_cb {
				iommus = &lt;0x30 0x1bf3 0x00&gt;;
				compatible = &quot;qcom,iommu-slim-ctrl-cb&quot;;
				phandle = &lt;0x2b9&gt;;
			};

wcn3990 {
				qcom,btfm-slim-ifd = &quot;btfmslim_slave_ifd&quot;;
				elemental-addr = [00 01 20 02 17 02];
				qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
				compatible = &quot;qcom,btfmslim_slave&quot;;
				phandle = &lt;0x2ba&gt;;
			};
		};

qcom,kgsl-iommu@5040000 {
			clock-names = &quot;iface_clk\0mem_clk\0mem_iface_clk&quot;;
			qcom,retention;
			clocks = &lt;0x27 0x28 0x27 0x1b 0x27 0x2b&gt;;
			qcom,micro-mmu-control = &lt;0x6000&gt;;
			qcom,protect = &lt;0x40000 0x10000&gt;;
			compatible = &quot;qcom,kgsl-smmu-v2&quot;;
			reg = &lt;0x5040000 0x10000&gt;;
			phandle = &lt;0x4d0&gt;;
			qcom,hyp_secure_alloc;
			qcom,secure_align_mask = &lt;0xfff&gt;;

gfx3d_user {
				iommus = &lt;0x1cd 0x00&gt;;
				label = &quot;gfx3d_user&quot;;
				compatible = &quot;qcom,smmu-kgsl-cb&quot;;
				phandle = &lt;0x4d1&gt;;
				qcom,gpu-offset = &lt;0x48000&gt;;
			};

gfx3d_secure {
				iommus = &lt;0x1cd 0x02&gt;;
				compatible = &quot;qcom,smmu-kgsl-cb&quot;;
				phandle = &lt;0x4d2&gt;;
			};
		};

rpmh-regulator-ldoc7 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoc7&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150l-l7 {
				regulator-max-microvolt = &lt;0x328980&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x328980&gt;;
				regulator-min-microvolt = &lt;0x328980&gt;;
				regulator-name = &quot;pm6150l_l7&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x411&gt;;
			};
		};

apps_iommu_test_device {
			iommus = &lt;0x30 0x21 0x00&gt;;
			compatible = &quot;iommu-debug-test&quot;;
		};

etm@7240000 {
			arm,primecell-periphid = &lt;0xbb95d&gt;;
			clock-names = &quot;apb_pclk&quot;;
			clocks = &lt;0x19 0x00&gt;;
			cpu = &lt;0x13&gt;;
			qcom,tupwr-disable;
			coresight-name = &quot;coresight-etm2&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7240000 0x1000&gt;;
			phandle = &lt;0x43e&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x21f&gt;;
					phandle = &lt;0x217&gt;;
				};
			};
		};

qcom,qmp-aop@c300000 {
			qcom,early-boot;
			reg-names = &quot;msgram\0irq-reg-base&quot;;
			interrupts = &lt;0x00 0x185 0x01&gt;;
			#mbox-cells = &lt;0x01&gt;;
			label = &quot;aop&quot;;
			mbox-desc-offset = &lt;0x00&gt;;
			priority = &lt;0x00&gt;;
			compatible = &quot;qcom,qmp-mbox&quot;;
			reg = &lt;0xc300000 0x1000 0x17c0000c 0x04&gt;;
			phandle = &lt;0x1c&gt;;
			qcom,irq-mask = &lt;0x01&gt;;
		};

qcedev@1de0000 {
			iommus = &lt;0x30 0x506 0x11 0x30 0x516 0x11&gt;;
			qcom,ce-hw-shared;
			qcom,ce-device = &lt;0x00&gt;;
			reg-names = &quot;crypto-base\0crypto-bam-base&quot;;
			qcom,msm-bus,name = &quot;qcedev-noc&quot;;
			qcom,bam-ee = &lt;0x00&gt;;
			interrupts = &lt;0x00 0x110 0x00&gt;;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x02&gt;;
			compatible = &quot;qcom,qcedev&quot;;
			qcom,no-clock-support;
			qcom,bam-pipe-pair = &lt;0x03&gt;;
			reg = &lt;0x1de0000 0x20000 0x1dc4000 0x24000&gt;;
			phandle = &lt;0x2df&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180&gt;;
			qcom,smmu-s1-enable;
			qcom,ce-hw-instance = &lt;0x00&gt;;
		};

rpmh-regulator-ldof5 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldof5&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm8009-l5 {
				regulator-max-microvolt = &lt;0x2c4fc0&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x292340&gt;;
				regulator-min-microvolt = &lt;0x292340&gt;;
				regulator-name = &quot;pm8009_l5&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x41a&gt;;
			};
		};

cti@6c20000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-venus-arm9&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6c20000 0x1000&gt;;
			phandle = &lt;0x475&gt;;
		};

csr@6001000 {
			qcom,set-byte-cntr-support;
			qcom,blk-size = &lt;0x01&gt;;
			qcom,hwctrl-set-support;
			reg-names = &quot;csr-base&quot;;
			coresight-name = &quot;coresight-csr&quot;;
			qcom,usb-bam-support;
			compatible = &quot;qcom,coresight-csr&quot;;
			reg = &lt;0x6001000 0x1000&gt;;
			phandle = &lt;0x1d6&gt;;
		};

qcom,cpu-cpu-llcc-bwmon@90b6300 {
			reg-names = &quot;base\0global_base&quot;;
			interrupts = &lt;0x00 0x245 0x04&gt;;
			compatible = &quot;qcom,bimc-bwmon4&quot;;
			qcom,hw-timer-hz = &lt;0x124f800&gt;;
			qcom,mport = &lt;0x00&gt;;
			qcom,count-unit = &lt;0x10000&gt;;
			reg = &lt;0x90b6300 0x300 0x90b6200 0x200&gt;;
			phandle = &lt;0x311&gt;;
			qcom,target-dev = &lt;0xbd&gt;;
		};

qcom,msm-dai-q6-spdif-pri-tx {
			compatible = &quot;qcom,msm-dai-q6-spdif&quot;;
			qcom,msm-dai-q6-dev-id = &lt;0x5001&gt;;
			phandle = &lt;0x4c9&gt;;
		};

jtagmm@7340000 {
			clock-names = &quot;core_clk&quot;;
			reg-names = &quot;etm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			compatible = &quot;qcom,jtagv8-mm&quot;;
			qcom,coresight-jtagmm-cpu = &lt;0x14&gt;;
			reg = &lt;0x7340000 0x1000&gt;;
			phandle = &lt;0x2ab&gt;;
		};

qcom,videocc@ab00000 {
			#reset-cells = &lt;0x01&gt;;
			reg-names = &quot;cc_base\0efuse&quot;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,videocc-sdmmagpie\0syscon&quot;;
			reg = &lt;0xab00000 0x10000 0x786018 0x04&gt;;
			phandle = &lt;0x28&gt;;
			vdd_cx-supply = &lt;0x1d&gt;;
		};

qcom,sde_rscc@af20000 {
			qcom,sde-rsc-version = &lt;0x02&gt;;
			clock-names = &quot;vsync_clk\0gdsc_clk\0iface_clk&quot;;
			reg-names = &quot;drv\0wrapper&quot;;
			cell-index = &lt;0x00&gt;;
			qcom,sde-dram-channels = &lt;0x02&gt;;
			clocks = &lt;0x2a 0x25 0x2a 0x1d 0x2a 0x24&gt;;
			vdd-supply = &lt;0xcb&gt;;
			compatible = &quot;qcom,sde-rsc&quot;;
			clock-rate = &lt;0x00 0x00 0x00&gt;;
			reg = &lt;0xaf20000 0x1c44 0xaf30000 0x3fd4&gt;;
			phandle = &lt;0x36d&gt;;
			mboxes = &lt;0xcf 0x00&gt;;
			mbox-names = &quot;disp_rsc&quot;;

qcom,sde-llcc-bus {
				qcom,msm-bus,name = &quot;disp_rsc_llcc&quot;;
				qcom,msm-bus,active-only;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x03&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0x4e21 0x5021 0x00 0x00 0x4e21 0x5021 0x00 0x61a800 0x4e21 0x5021 0x00 0x61a800&gt;;
			};

qcom,sde-data-bus {
				qcom,msm-bus,name = &quot;disp_rsc_mnoc&quot;;
				qcom,msm-bus,active-only;
				qcom,msm-bus,num-paths = &lt;0x02&gt;;
				qcom,msm-bus,num-cases = &lt;0x03&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0x4e23 0x5023 0x00 0x00 0x4e24 0x5023 0x00 0x00 0x4e23 0x5023 0x00 0x61a800 0x4e24 0x5023 0x00 0x61a800 0x4e23 0x5023 0x00 0x61a800 0x4e24 0x5023 0x00 0x61a800&gt;;
			};

qcom,sde-ebi-bus {
				qcom,msm-bus,name = &quot;disp_rsc_ebi&quot;;
				qcom,msm-bus,active-only;
				qcom,msm-bus,num-paths = &lt;0x01&gt;;
				qcom,msm-bus,num-cases = &lt;0x03&gt;;
				qcom,msm-bus,vectors-KBps = &lt;0x4e20 0x5020 0x00 0x00 0x4e20 0x5020 0x00 0x61a800 0x4e20 0x5020 0x00 0x61a800&gt;;
			};
		};

qcom,csid0@acb3000 {
			camss-supply = &lt;0x1ae&gt;;
			clock-control-debugfs = &quot;true&quot;;
			clock-names = &quot;ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_clk\0ife_axi_clk&quot;;
			reg-names = &quot;csid&quot;;
			reg-cam-base = &lt;0xb3000&gt;;
			ife0-supply = &lt;0x1b7&gt;;
			cell-index = &lt;0x00&gt;;
			interrupts = &lt;0x00 0x1d0 0x00&gt;;
			clocks = &lt;0x29 0x35 0x29 0x34 0x29 0x1b 0x29 0x33 0x29 0x32 0x29 0x31 0x29 0x30&gt;;
			clock-cntl-level = &quot;lowsvs\0svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,csid175_200&quot;;
			src-clock-name = &quot;ife_csid_clk_src&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;csid&quot;;
			reg = &lt;0xacb3000 0x1000&gt;;
			regulator-names = &quot;camss\0ife0&quot;;
			phandle = &lt;0x38d&gt;;
			clock-rates = &lt;0x11e1a300 0x00 0x00 0x00 0x16a65700 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x1e65fb80 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x25f7d940 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x2d4cae00 0x00 0x00&gt;;
		};

syscon@182a0018 {
			compatible = &quot;syscon&quot;;
			reg = &lt;0x182a0018 0x04&gt;;
			phandle = &lt;0x2d&gt;;
		};

qcom,vidc0 {
			qcom,allowed-clock-rates = &lt;0xe4e1c00 0x14257880 0x15c17540&gt;;
			iris-ctl-supply = &lt;0xb4&gt;;
			qcom,cx-ipeak-data = &lt;0x1a3 0x05&gt;;
			qcom,clock-freq-threshold = &lt;0x1fc4ef40&gt;;
			sku-index = &lt;0x00&gt;;
			clock-names = &quot;video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk&quot;;
			vcodec-supply = &lt;0x1a1&gt;;
			interrupts = &lt;0x00 0xae 0x04&gt;;
			cvp-supply = &lt;0x1a2&gt;;
			clocks = &lt;0x28 0x08 0x28 0x03 0x28 0x05 0x28 0x07 0x28 0x04 0x28 0x06 0x28 0x09&gt;;
			compatible = &quot;qcom,msm-vidc\0qcom,sdmmagpie-vidc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xaa00000 0x200000&gt;;
			phandle = &lt;0x368&gt;;
			qcom,proxy-clock-names = &quot;video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk&quot;;
			qcom,clock-configs = &lt;0x00 0x00 0x00 0x01 0x01 0x01 0x00&gt;;

qcom,msm-vidc,mem_cdsp {
				memory-region = &lt;0x1a4&gt;;
				compatible = &quot;qcom,msm-vidc,mem-cdsp&quot;;
			};

cti@601f000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti15&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x601f000 0x1000&gt;;
			phandle = &lt;0x484&gt;;
		};

qcom,llcc@9200000 {
			qcom,llcc-banks-off = &lt;0x00 0x80000&gt;;
			reg-names = &quot;llcc_base&quot;;
			qcom,llcc-broadcast-off = &lt;0x400000&gt;;
			compatible = &quot;qcom,llcc-core\0syscon\0simple-mfd&quot;;
			reg = &lt;0x9200000 0x450000&gt;;

qcom,sdmmagpie-llcc {
				max-slices = &lt;0x20&gt;;
				compatible = &quot;qcom,sdmmagpie-llcc&quot;;
				phandle = &lt;0x1a7&gt;;
				#cache-cells = &lt;0x01&gt;;
				cap-based-alloc-and-pwr-collapse;
			};

llcc_1_dcache {
				qcom,dump-size = &lt;0x6c000&gt;;
				phandle = &lt;0x51&gt;;
			};

qcom,llcc-erp {
				compatible = &quot;qcom,llcc-erp&quot;;
			};

llcc_2_dcache {
				qcom,dump-size = &lt;0x6c000&gt;;
				phandle = &lt;0x52&gt;;
			};

qcom,llcc-perfmon {
				clock-names = &quot;qdss_clk&quot;;
				clocks = &lt;0x19 0x00&gt;;
				compatible = &quot;qcom,llcc-perfmon&quot;;
			};

qcom,llcc-amon {
				compatible = &quot;qcom,llcc-amon&quot;;
			};
		};

qcom,msm-pcm-dsp-noirq {
			qcom,latency-level = &quot;ultra&quot;;
			compatible = &quot;qcom,msm-pcm-dsp-noirq&quot;;
			phandle = &lt;0x26a&gt;;
			qcom,msm-pcm-low-latency;
		};

thermal-message {
			board-sensor = &quot;VIRTUAL-SENSOR&quot;;
			phandle = &lt;0x5b4&gt;;
		};

qcom,gdsc@0b00814 {
			clock-names = &quot;ahb_clk&quot;;
			clocks = &lt;0x27 0x9b&gt;;
			regulator-name = &quot;mvsc_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xab00814 0x04&gt;;
			phandle = &lt;0xb4&gt;;
		};

qcom,gdsc@0f03000 {
			qcom,poll-cfg-gdscr;
			clock-names = &quot;ahb_clk&quot;;
			qcom,support-hw-trigger;
			clocks = &lt;0x27 0x1c&gt;;
			regulator-name = &quot;mdss_core_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			qcom,proxy-consumer-enable;
			reg = &lt;0xaf03000 0x04&gt;;
			phandle = &lt;0xcb&gt;;
			proxy-supply = &lt;0xcb&gt;;
		};

qcom,mpm2-sleep-counter@0xc221000 {
			clock-frequency = &lt;0x8000&gt;;
			compatible = &quot;qcom,mpm2-sleep-counter&quot;;
			reg = &lt;0xc221000 0x1000&gt;;
		};

rpmh-regulator-ldoa12 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa12&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l12 {
				regulator-max-microvolt = &lt;0x1dc900&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x19e100&gt;;
				regulator-min-microvolt = &lt;0x19e100&gt;;
				regulator-name = &quot;pm6150_l12&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x407&gt;;
			};
		};

tmc@6048000 {
			iommus = &lt;0x30 0x5e0 0x00 0x30 0x4a0 0x00&gt;;
			arm,buffer-size = &lt;0x400000&gt;;
			arm,primecell-periphid = &lt;0x3b961&gt;;
			coresight-ctis = &lt;0x1d5 0x1d5&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tmc-base\0bam-base&quot;;
			interrupts = &lt;0x00 0x10e 0x01&gt;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tmc-etr&quot;;
			compatible = &quot;arm,primecell&quot;;
			interrupt-names = &quot;byte-cntr-irq&quot;;
			reg = &lt;0x6048000 0x1000 0x6064000 0x15000&gt;;
			phandle = &lt;0x41f&gt;;
			coresight-csr = &lt;0x1d6&gt;;

port {

endpoint {
					slave-mode;
					remote-endpoint = &lt;0x1d7&gt;;
					phandle = &lt;0x1d0&gt;;
				};
			};
		};

funnel@6832000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-modem&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6832000 0x1000&gt;;
			phandle = &lt;0x424&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1e8&gt;;
						phandle = &lt;0x1e7&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1e9&gt;;
						phandle = &lt;0x1eb&gt;;
					};
				};

port@2 {
					reg = &lt;0x01&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1ea&gt;;
						phandle = &lt;0x1ed&gt;;
					};
				};
			};
		};

qcom,chd_sliver {
			qcom,config-arr = &lt;0x18000060 0x18010060 0x18020060 0x18030060 0x18040060 0x18050060&gt;;
			label = &quot;silver&quot;;
			qcom,threshold-arr = &lt;0x18000058 0x18010058 0x18020058 0x18030058 0x18040058 0x18050058&gt;;
			compatible = &quot;qcom,core-hang-detect&quot;;
		};

cti@601c000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti12&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x601c000 0x1000&gt;;
			phandle = &lt;0x481&gt;;
		};

qcom,qupv3_1_geni_se@0xac0000 {
			qcom,iommu-s1-bypass;
			qcom,bus-mas-id = &lt;0x98&gt;;
			qcom,bus-slv-id = &lt;0x200&gt;;
			compatible = &quot;qcom,qupv3-geni-se&quot;;
			reg = &lt;0xac0000 0x2000&gt;;
			phandle = &lt;0x182&gt;;

qcom,iommu_qupv3_1_geni_se_cb {
				iommus = &lt;0x30 0x4c3 0x00&gt;;
				compatible = &quot;qcom,qupv3-geni-se-cb&quot;;
				phandle = &lt;0x358&gt;;
			};
		};

wsa_spkr_en1_pinctrl {
			pinctrl-names = &quot;aud_active\0aud_sleep&quot;;
			pinctrl-0 = &lt;0x3d1&gt;;
			compatible = &quot;qcom,msm-cdc-pinctrl&quot;;
			pinctrl-1 = &lt;0x3d0&gt;;
			status = &quot;disabled&quot;;
			phandle = &lt;0x4e9&gt;;
		};

qcom,qup_uart@0x88c000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			pinctrl-0 = &lt;0x171 0x172 0x173&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			clocks = &lt;0x27 0x4a 0x27 0x67 0x27 0x68&gt;;
			qcom,wrapper-core = &lt;0x168&gt;;
			interrupts-extended = &lt;0x01 0x00 0x25c 0x00 0x174 0x29 0x00&gt;;
			compatible = &quot;qcom,msm-geni-serial-hs&quot;;
			pinctrl-1 = &lt;0x171 0x172 0x173&gt;;
			status = &quot;ok&quot;;
			reg = &lt;0x88c000 0x4000&gt;;
			phandle = &lt;0x352&gt;;
			qcom,wakeup-byte = &lt;0xfd&gt;;
		};

syscon@90b0000 {
			compatible = &quot;syscon&quot;;
			reg = &lt;0x90b0000 0x1000&gt;;
			phandle = &lt;0x2e&gt;;
		};

qcom,dp_display@0 {
			qcom,dp-gpio-aux-switch;
			qcom,aux-cfg1-settings = &lt;0x2413231d&gt;;
			pinctrl-names = &quot;mdss_dp_active\0mdss_dp_sleep&quot;;
			qcom,usbplug-cc-gpio = &lt;0x174 0x68 0x00&gt;;
			qcom,aux-cfg6-settings = [38 0a];
			pinctrl-0 = &lt;0x3ca 0x1ac&gt;;
			qcom,ext-disp = &lt;0x1ab&gt;;
			clock-names = &quot;core_aux_clk\0core_usb_ahb_clk\0core_usb_ref_clk_src\0core_usb_ref_clk\0core_usb_pipe_clk\0link_clk\0link_iface_clk\0crypto_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0pixel1_parent\0strm0_pixel_clk\0strm1_pixel_clk&quot;;
			reg-names = &quot;dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_mmss_cc\0qfprom_physical\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1&quot;;
			qcom,aux-cfg2-settings = [28 24];
			cell-index = &lt;0x00&gt;;
			interrupts = &lt;0x0c 0x00&gt;;
			clocks = &lt;0x2a 0x0b 0x27 0x97 0x2f 0x00 0x27 0x92 0x27 0x96 0x2a 0x0f 0x2a 0x11 0x2a 0x0d 0x2a 0x15 0x1aa 0x05 0x2a 0x13 0x1aa 0x05 0x2a 0x14 0x2a 0x12&gt;;
			qcom,max-pclk-frequency-khz = &lt;0xa4cb8&gt;;
			qcom,aux-cfg7-settings = [3c 03];
			interrupt-parent = &lt;0x1a6&gt;;
			qcom,aux-cfg3-settings = [2c 00];
			vdda-1p2-supply = &lt;0x1a8&gt;;
			qcom,aux-cfg8-settings = [40 bb];
			compatible = &quot;qcom,dp-display&quot;;
			pinctrl-1 = &lt;0x3cb 0x1ad&gt;;
			status = &quot;disabled&quot;;
			vdda-0p9-supply = &lt;0x1a9&gt;;
			qcom,aux-cfg4-settings = [30 0a];
			reg = &lt;0xae90000 0xdc 0xae90200 0xc0 0xae90400 0x508 0xae90a00 0x94 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0xaf02000 0x1e0 0x780000 0x621c 0x88ea030 0x10 0x88e8000 0x20 0xaee1000 0x34 0xae91000 0x94&gt;;
			phandle = &lt;0x377&gt;;
			qcom,aux-en-gpio = &lt;0x174 0x2a 0x00&gt;;
			qcom,aux-cfg9-settings = [44 03];
			qcom,aux-cfg0-settings = [20 00];
			qcom,dp-usbpd-detection = &lt;0x25b&gt;;
			qcom,aux-sel-gpio = &lt;0x174 0x21 0x00&gt;;
			qcom,aux-cfg5-settings = [34 26];

qcom,ctrl-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

qcom,phy-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

qcom,core-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

cp_qc30 {
			mi,support-qc3p5-without-smb;
			mi,qc3-bus-curr-max = &lt;0x834&gt;;
			mi,qc3-bus-volt-max = &lt;0x2ee0&gt;;
			compatible = &quot;xiaomi,cp-qc30&quot;;
			status = &quot;ok&quot;;
			mi,qc3-ffc-bat-volt-max = &lt;0x1176&gt;;
			mi,qc3-bat-curr-max = &lt;0x1518&gt;;
			mi,qc3-bat-volt-max = &lt;0x1162&gt;;
		};

qcom,msm-dai-tdm-quin-tx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9041&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9141&gt;;
			phandle = &lt;0x4c3&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-quin-tx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9041&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x28f&gt;;
			};
		};

qcom,dsi-display@26 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x53a&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_xiaomi_f4_41_06_0a_fhd_cmd_display&quot;;
			phandle = &lt;0x551&gt;;
		};

qcom,cci@ac4b000 {
			pinctrl-names = &quot;cam_default\0cam_suspend&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x1b4&gt;;
			clock-names = &quot;cci_clk\0cci_1_clk_src&quot;;
			reg-names = &quot;cci&quot;;
			reg-cam-base = &lt;0x4b000&gt;;
			cell-index = &lt;0x01&gt;;
			gpio-req-tbl-num = &lt;0x00 0x01&gt;;
			interrupts = &lt;0x00 0x1cd 0x00&gt;;
			clocks = &lt;0x29 0x17 0x29 0x18&gt;;
			gdscr-supply = &lt;0x1ae&gt;;
			#size-cells = &lt;0x00&gt;;
			gpio-req-tbl-label = &quot;CCI_I2C_DATA2\0CCI_I2C_CLK2&quot;;
			clock-cntl-level = &quot;lowsvs&quot;;
			compatible = &quot;qcom,cci&quot;;
			src-clock-name = &quot;cci_1_clk_src&quot;;
			pinctrl-1 = &lt;0x1b5&gt;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;cci&quot;;
			reg = &lt;0xac4b000 0x1000&gt;;
			regulator-names = &quot;gdscr&quot;;
			phandle = &lt;0x381&gt;;
			clock-rates = &lt;0x00 0x23c3460&gt;;
			gpio-req-tbl-flags = &lt;0x01 0x01&gt;;
			gpios = &lt;0x174 0x1b 0x00 0x174 0x1c 0x00&gt;;

qcom,i2c_custom_mode {
				hw-tsu-sto = &lt;0x28&gt;;
				cci-clk-src = &lt;0x23c3460&gt;;
				hw-tsp = &lt;0x03&gt;;
				hw-trdhld = &lt;0x06&gt;;
				hw-thigh = &lt;0x26&gt;;
				hw-tlow = &lt;0x38&gt;;
				status = &quot;ok&quot;;
				hw-thd-dat = &lt;0x16&gt;;
				hw-tsu-sta = &lt;0x28&gt;;
				hw-scl-stretch-en = &lt;0x01&gt;;
				phandle = &lt;0x384&gt;;
				hw-tbuf = &lt;0x3e&gt;;
				hw-thd-sta = &lt;0x23&gt;;
			};

qcom,cam-sensor@1 {
				cam_v_custom1-supply = &lt;0x57a&gt;;
				rgltr-max-voltage = &lt;0x1b7740 0x2ab980 0x1b7740 0x00&gt;;
				pinctrl-names = &quot;cam_default\0cam_suspend&quot;;
				eeprom-src = &lt;0x57d&gt;;
				pinctrl-0 = &lt;0x56c 0x57b 0x578&gt;;
				clock-names = &quot;cam_clk&quot;;
				cell-index = &lt;0x01&gt;;
				gpio-req-tbl-num = &lt;0x00 0x01 0x02&gt;;
				sensor-position-yaw = &lt;0xb4&gt;;
				cci-device = &lt;0x01&gt;;
				clocks = &lt;0x29 0x50&gt;;
				rgltr-load-current = &lt;0x2bf20 0x1d4c0 0x1b7740 0x00&gt;;
				cam_vio-supply = &lt;0x579&gt;;
				rgltr-cntrl-support;
				cam_vana-supply = &lt;0x56b&gt;;
				gpio-req-tbl-label = &quot;CAMIF_MCLK0\0CAMD_RESET\0CAMD_CUSTOM1&quot;;
				gpio-reset = &lt;0x01&gt;;
				csiphy-sd-index = &lt;0x03&gt;;
				clock-cntl-level = &quot;turbo&quot;;
				gpio-custom1 = &lt;0x02&gt;;
				cci-master = &lt;0x00&gt;;
				gpio-no-mux = &lt;0x00&gt;;
				compatible = &quot;qcom,cam-sensor&quot;;
				rgltr-min-voltage = &lt;0x1b7740 0x2ab980 0x1b7740 0x00&gt;;
				sensor-position-roll = &lt;0x5a&gt;;
				pinctrl-1 = &lt;0x56e 0x57c 0x575&gt;;
				status = &quot;ok&quot;;
				reg = &lt;0x01&gt;;
				regulator-names = &quot;cam_vio\0cam_vana\0cam_v_custom1\0cam_clk&quot;;
				sensor-position-pitch = &lt;0x00&gt;;
				cam_clk-supply = &lt;0x1ae&gt;;
				clock-rates = &lt;0x124f800&gt;;
				gpio-req-tbl-flags = &lt;0x01 0x00 0x00&gt;;
				gpios = &lt;0x174 0x0d 0x00 0x174 0x15 0x00 0x174 0x58 0x00&gt;;
			};

qcom,i2c_standard_mode {
				hw-tsu-sto = &lt;0xcc&gt;;
				cci-clk-src = &lt;0x23c3460&gt;;
				hw-tsp = &lt;0x03&gt;;
				hw-trdhld = &lt;0x06&gt;;
				hw-thigh = &lt;0xc9&gt;;
				hw-tlow = &lt;0xae&gt;;
				status = &quot;ok&quot;;
				hw-thd-dat = &lt;0x16&gt;;
				hw-tsu-sta = &lt;0xe7&gt;;
				hw-scl-stretch-en = &lt;0x00&gt;;
				phandle = &lt;0x382&gt;;
				hw-tbuf = &lt;0xe3&gt;;
				hw-thd-sta = &lt;0xa2&gt;;
			};

qcom,cam-res-mgr {
				compatible = &quot;qcom,cam-res-mgr&quot;;
				status = &quot;ok&quot;;
			};

qcom,cam-sensor@4 {
				rgltr-max-voltage = &lt;0x1b7740 0x00&gt;;
				pinctrl-names = &quot;cam_default\0cam_suspend&quot;;
				eeprom-src = &lt;0x57f&gt;;
				pinctrl-0 = &lt;0x580 0x581&gt;;
				clock-names = &quot;cam_clk&quot;;
				cell-index = &lt;0x04&gt;;
				gpio-req-tbl-num = &lt;0x00 0x01&gt;;
				sensor-position-yaw = &lt;0xb4&gt;;
				cci-device = &lt;0x01&gt;;
				clocks = &lt;0x29 0x52&gt;;
				rgltr-load-current = &lt;0x2bf20 0x00&gt;;
				cam_vio-supply = &lt;0x57a&gt;;
				rgltr-cntrl-support;
				gpio-req-tbl-label = &quot;CAMIF_MCLK1\0CAMU_RESET&quot;;
				gpio-reset = &lt;0x01&gt;;
				csiphy-sd-index = &lt;0x02&gt;;
				clock-cntl-level = &quot;turbo&quot;;
				sensor-mode = &lt;0x00&gt;;
				cci-master = &lt;0x00&gt;;
				gpio-no-mux = &lt;0x00&gt;;
				compatible = &quot;qcom,cam-sensor&quot;;
				rgltr-min-voltage = &lt;0x1b7740 0x00&gt;;
				led-flash-src = &lt;0x57e&gt;;
				sensor-position-roll = &lt;0x5a&gt;;
				pinctrl-1 = &lt;0x582 0x583&gt;;
				status = &quot;ok&quot;;
				reg = &lt;0x04&gt;;
				regulator-names = &quot;cam_vio\0cam_clk&quot;;
				sensor-position-pitch = &lt;0x00&gt;;
				cam_clk-supply = &lt;0x1ae&gt;;
				clock-rates = &lt;0x124f800&gt;;
				gpio-req-tbl-flags = &lt;0x01 0x00&gt;;
				gpios = &lt;0x174 0x0e 0x00 0x174 0x19 0x00&gt;;
			};

qcom,eeprom@1 {
				cam_v_custom1-supply = &lt;0x57a&gt;;
				rgltr-max-voltage = &lt;0x1b7740 0x2ab980 0x1b7740 0x00&gt;;
				pinctrl-names = &quot;cam_default\0cam_suspend&quot;;
				pinctrl-0 = &lt;0x56c 0x57b 0x578&gt;;
				clock-names = &quot;cam_clk&quot;;
				cell-index = &lt;0x01&gt;;
				gpio-req-tbl-num = &lt;0x00 0x01 0x02&gt;;
				cci-device = &lt;0x01&gt;;
				clocks = &lt;0x29 0x50&gt;;
				rgltr-load-current = &lt;0x2bf20 0x1d4c0 0x1b7740 0x00&gt;;
				cam_vio-supply = &lt;0x579&gt;;
				rgltr-cntrl-support;
				cam_vana-supply = &lt;0x56b&gt;;
				gpio-req-tbl-label = &quot;CAMIF_MCLK0\0CAMD_RESET\0CAMD_CUSTOM1&quot;;
				gpio-reset = &lt;0x01&gt;;
				csiphy-sd-index = &lt;0x03&gt;;
				clock-cntl-level = &quot;turbo&quot;;
				gpio-custom1 = &lt;0x02&gt;;
				cci-master = &lt;0x00&gt;;
				gpio-no-mux = &lt;0x00&gt;;
				compatible = &quot;qcom,eeprom&quot;;
				rgltr-min-voltage = &lt;0x1b7740 0x2ab980 0x1b7740 0x00&gt;;
				pinctrl-1 = &lt;0x56e 0x57c 0x575&gt;;
				status = &quot;ok&quot;;
				reg = &lt;0x01&gt;;
				regulator-names = &quot;cam_vio\0cam_vana\0cam_v_custom1\0cam_clk&quot;;
				phandle = &lt;0x57d&gt;;
				cam_clk-supply = &lt;0x1ae&gt;;
				clock-rates = &lt;0x124f800&gt;;
				gpio-req-tbl-flags = &lt;0x01 0x00 0x00&gt;;
				gpios = &lt;0x174 0x0d 0x00 0x174 0x15 0x00 0x174 0x58 0x00&gt;;
			};

qcom,i2c_fast_plus_mode {
				hw-tsu-sto = &lt;0x11&gt;;
				cci-clk-src = &lt;0x23c3460&gt;;
				hw-tsp = &lt;0x03&gt;;
				hw-trdhld = &lt;0x03&gt;;
				hw-thigh = &lt;0x10&gt;;
				hw-tlow = &lt;0x16&gt;;
				status = &quot;ok&quot;;
				hw-thd-dat = &lt;0x10&gt;;
				hw-tsu-sta = &lt;0x12&gt;;
				hw-scl-stretch-en = &lt;0x00&gt;;
				phandle = &lt;0x385&gt;;
				hw-tbuf = &lt;0x18&gt;;
				hw-thd-sta = &lt;0x0f&gt;;
			};

qcom,i2c_fast_mode {
				hw-tsu-sto = &lt;0x28&gt;;
				cci-clk-src = &lt;0x23c3460&gt;;
				hw-tsp = &lt;0x03&gt;;
				hw-trdhld = &lt;0x06&gt;;
				hw-thigh = &lt;0x26&gt;;
				hw-tlow = &lt;0x38&gt;;
				status = &quot;ok&quot;;
				hw-thd-dat = &lt;0x16&gt;;
				hw-tsu-sta = &lt;0x28&gt;;
				hw-scl-stretch-en = &lt;0x00&gt;;
				phandle = &lt;0x383&gt;;
				hw-tbuf = &lt;0x3e&gt;;
				hw-thd-sta = &lt;0x23&gt;;
			};

qcom,eeprom@4 {
				rgltr-max-voltage = &lt;0x1b7740&gt;;
				cell-index = &lt;0x04&gt;;
				cci-device = &lt;0x01&gt;;
				rgltr-load-current = &lt;0x2bf20&gt;;
				cam_vio-supply = &lt;0x57a&gt;;
				rgltr-cntrl-support;
				cci-master = &lt;0x00&gt;;
				compatible = &quot;qcom,eeprom&quot;;
				rgltr-min-voltage = &lt;0x1b7740&gt;;
				status = &quot;ok&quot;;
				reg = &lt;0x04&gt;;
				regulator-names = &quot;cam_vio&quot;;
				phandle = &lt;0x57f&gt;;
			};
		};

tpdm@6860000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-turing&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6860000 0x1000&gt;;
			phandle = &lt;0x452&gt;;
			qcom,msr-fix-req;

port {

endpoint {
					remote-endpoint = &lt;0x24a&gt;;
					phandle = &lt;0x246&gt;;
				};
			};
		};

qcom,cam-fd {
			compat-hw-name = &quot;qcom,fd&quot;;
			compatible = &quot;qcom,cam-fd&quot;;
			status = &quot;ok&quot;;
			num-fd = &lt;0x01&gt;;
		};

cti@6a10000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-ddr_dl_1_cti0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6a10000 0x1000&gt;;
			phandle = &lt;0x463&gt;;
		};

gpio-regulator@2 {
			regulator-max-microvolt = &lt;0x1b7740&gt;;
			gpio = &lt;0x2ec 0x04 0x00&gt;;
			regulator-enable-ramp-delay = &lt;0x64&gt;;
			enable-active-high;
			regulator-min-microvolt = &lt;0x1b7740&gt;;
			regulator-name = &quot;camera_v_swio_depth_regulator&quot;;
			compatible = &quot;regulator-fixed&quot;;
			reg = &lt;0x02 0x00&gt;;
			phandle = &lt;0x57a&gt;;
			vin-supply = &lt;0x3fe&gt;;
		};

qcom,msm-dai-q6-spdif-pri-rx {
			compatible = &quot;qcom,msm-dai-q6-spdif&quot;;
			qcom,msm-dai-q6-dev-id = &lt;0x5000&gt;;
			phandle = &lt;0x4c8&gt;;
		};

qcom,lrme@ac6b000 {
			camss-supply = &lt;0x1ae&gt;;
			clock-names = &quot;lrme_clk_src\0lrme_clk&quot;;
			reg-names = &quot;lrme&quot;;
			reg-cam-base = &lt;0x6b000&gt;;
			cell-index = &lt;0x00&gt;;
			interrupts = &lt;0x00 0x1dc 0x00&gt;;
			clocks = &lt;0x29 0x4f 0x29 0x4e&gt;;
			clock-cntl-level = &quot;lowsvs\0svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,lrme&quot;;
			src-clock-name = &quot;lrme_clk_src&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;lrme&quot;;
			reg = &lt;0xac6b000 0xa00&gt;;
			regulator-names = &quot;camss&quot;;
			phandle = &lt;0x39a&gt;;
			clock-rates = &lt;0xe4e1c00 0x00 0x11e1a300 0x00 0x1312d000 0x00 0x17d78400 0x00&gt;;
		};

qcom,gdsc@ad0c1c4 {
			qcom,poll-cfg-gdscr;
			clock-names = &quot;ahb_clk&quot;;
			clocks = &lt;0x27 0x0e&gt;;
			regulator-name = &quot;titan_top_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xad0c1c4 0x04&gt;;
			phandle = &lt;0x1ae&gt;;
		};

i2c@0xa90000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x18d&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			interrupts = &lt;0x00 0x165 0x00&gt;;
			clocks = &lt;0x27 0x5f 0x27 0x69 0x27 0x6a&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,i2c-geni&quot;;
			pinctrl-1 = &lt;0x18e&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0xa90000 0x4000&gt;;
			phandle = &lt;0x35f&gt;;
			dmas = &lt;0x183 0x00 0x04 0x03 0x40 0x00 0x183 0x01 0x04 0x03 0x40 0x00&gt;;
		};

suspendable-ddr-bw-opp-table {
			compatible = &quot;operating-points-v2&quot;;
			phandle = &lt;0xc7&gt;;

opp-1017 {
				opp-hz = &lt;0x00 0xf27&gt;;
			};

opp-300 {
				opp-hz = &lt;0x00 0x478&gt;;
			};

opp-451 {
				opp-hz = &lt;0x00 0x6b8&gt;;
			};

opp-1353 {
				opp-hz = &lt;0x00 0x1429&gt;;
			};

opp-1804 {
				opp-hz = &lt;0x00 0x1ae1&gt;;
			};

opp-768 {
				opp-hz = &lt;0x00 0xb71&gt;;
			};

opp-200 {
				opp-hz = &lt;0x00 0x2fa&gt;;
			};

opp-681 {
				opp-hz = &lt;0x00 0xa25&gt;;
			};

opp-1555 {
				opp-hz = &lt;0x00 0x172b&gt;;
			};

opp-547 {
				opp-hz = &lt;0x00 0x826&gt;;
			};

opp-0 {
				opp-hz = &lt;0x00 0x00&gt;;
			};
		};

qcom,cpu0-cpu-ddr-latfloor {
			qcom,src-dst-ports = &lt;0x81 0x200&gt;;
			governor = &quot;performance&quot;;
			compatible = &quot;qcom,devbw&quot;;
			phandle = &lt;0xc5&gt;;
			qcom,active-only;
			operating-points-v2 = &lt;0xbe&gt;;
		};

tpdm@6b52000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-dl-south&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b52000 0x1000&gt;;
			phandle = &lt;0x44f&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x244&gt;;
					phandle = &lt;0x243&gt;;
				};
			};
		};

qcom,dsi-display@4 {
			qcom,dsi-phy-num = &lt;0x00 0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x526&gt;;
			qcom,dsi-ctrl-num = &lt;0x00 0x01&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_dual_sim_vid_display&quot;;
			phandle = &lt;0x543&gt;;
		};

qcom,csiphy@ace4000 {
			clock-names = &quot;cphy_rx_clk_src\0csiphy0_clk\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk&quot;;
			reg-names = &quot;csiphy&quot;;
			reg-cam-base = &lt;0xe4000&gt;;
			csi-vdd-voltage = &lt;0x124f80&gt;;
			cell-index = &lt;0x02&gt;;
			interrupts = &lt;0x00 0x1df 0x00&gt;;
			clocks = &lt;0x29 0x1b 0x29 0x24 0x29 0x26 0x29 0x21 0x29 0x20&gt;;
			gdscr-supply = &lt;0x1ae&gt;;
			clock-cntl-level = &quot;svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,csiphy-v1.2\0qcom,csiphy&quot;;
			src-clock-name = &quot;csi2phytimer_clk_src&quot;;
			mipi-csi-vdd-supply = &lt;0x1a8&gt;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;csiphy&quot;;
			reg = &lt;0xace4000 0x2000&gt;;
			regulator-names = &quot;gdscr\0refgen&quot;;
			phandle = &lt;0x37a&gt;;
			refgen-supply = &lt;0x1af&gt;;
			clock-rates = &lt;0x16e36000 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00&gt;;
		};

qcom,dsi-display@16 {
			qcom,dsi-phy-num = &lt;0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk1\0mux_pixel_clk1&quot;;
			qcom,dsi-panel = &lt;0x530&gt;;
			qcom,dsi-ctrl-num = &lt;0x01&gt;;
			qcom,display-type = &quot;secondary&quot;;
			label = &quot;dsi_nt35695b_truly_fhd_cmd_sec_display&quot;;
			phandle = &lt;0x55d&gt;;
		};

aop-msg-client {
			compatible = &quot;qcom,debugfs-qmp-client&quot;;
			mboxes = &lt;0x1c 0x00&gt;;
			mbox-names = &quot;aop&quot;;
		};

qcom,bps {
			clock-control-debugfs = &quot;true&quot;;
			clock-names = &quot;bps_ahb_clk\0bps_areg_clk\0bps_axi_clk\0bps_clk_src\0bps_clk&quot;;
			reg-names = &quot;bps_top&quot;;
			reg-cam-base = &lt;0x6f000&gt;;
			cell-index = &lt;0x00&gt;;
			bps-vdd-supply = &lt;0x1bb&gt;;
			clocks = &lt;0x29 0x0d 0x29 0x0e 0x29 0x0f 0x29 0x11 0x29 0x10&gt;;
			clock-cntl-level = &quot;lowsvs\0svs\0svs_l1\0nominal\0turbo&quot;;
			compatible = &quot;qcom,cam-bps&quot;;
			src-clock-name = &quot;bps_clk_src&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xac6f000 0x3000&gt;;
			regulator-names = &quot;bps-vdd&quot;;
			phandle = &lt;0x396&gt;;
			qcom,cam-cx-ipeak = &lt;0x1a3 0x03&gt;;
			clock-rates = &lt;0x00 0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600 0x00&gt;;
		};

rpmh-regulator-ldoc5 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoc5&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150l-l5 {
				regulator-max-microvolt = &lt;0x2d0370&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x192580&gt;;
				regulator-min-microvolt = &lt;0x192580&gt;;
				regulator-name = &quot;pm6150l_l5&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x40f&gt;;
			};
		};

qcom,mdss_dsi_ss_fhd_ea_f10_cmd {
			qcom,ulps-enabled;
			qcom,disp-doze-backlight-threshold = &lt;0x08&gt;;
			qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = &quot;dsi_hs_mode&quot;;
			qcom,mdss-pan-physical-width-dimension = &lt;0x44&gt;;
			qcom,mdss-dsi-panel-name = &quot;ss ea fhd cmd dsi panel&quot;;
			qcom,mdss-pan-physical-height-dimension = &lt;0x93&gt;;
			qcom,mdss-dsi-panel-elvss-dimming-read-length = &lt;0x01&gt;;
			qcom,mdss-dsi-te-using-te-pin;
			qcom,samsung-prepare-hbm;
			qcom,mdss-dsi-te-dcs-command = &lt;0x01&gt;;
			qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
			qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = &quot;dsi_lp_mode&quot;;
			qcom,mdss-dsi-t-clk-post = &lt;0x0f&gt;;
			qcom,mdss-dsi-lane-2-state;
			qcom,mdss-dsi-te-check-enable;
			qcom,mdss-dsi-bllp-eof-power-mode;
			qcom,mdss-dsi-panel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-dispparam-hbm-fod-on-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 b0 03 39 00 00 00 00 00 02 b7 c9 39 00 00 00 00 00 02 b0 07 39 00 00 00 00 00 02 b7 91 39 00 00 00 00 00 03 b7 01 43 39 00 00 00 00 00 03 f0 a5 a5 39 01 00 00 01 00 02 53 e0];
			qcom,mdss-dsi-dispparam-hbm-fod-off-command = [39 01 00 00 00 00 02 53 20 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 b7 01 4b 39 00 00 00 00 00 02 b0 03 39 00 00 00 00 00 02 b7 49 39 00 00 00 00 00 02 b0 07 39 00 00 00 00 00 02 b7 91 39 01 00 00 01 00 03 f0 a5 a5];
			qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = &quot;dsi_hs_mode&quot;;
			qcom,mdss-dsi-panel-fod-dimlayer-enabled;
			qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
			qcom,bl-update-flag = &quot;delay_until_first_frame&quot;;
			qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
			qcom,disp-fod-off-dimming-delay = &lt;0x55&gt;;
			qcom,elvss_dimming_check_enable;
			qcom,dispparam-enabled;
			qcom,mdss-dsi-panel-peak-brightness = &lt;0x419ce0&gt;;
			qcom,mdss-dsi-lane-3-state;
			qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
			qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-bl-dcs-type-ss-ea;
			qcom,mdss-dsi-reset-sequence = &lt;0x00 0x01 0x01 0x0a&gt;;
			qcom,mdss-dsi-dispparam-elvss-dimming-read-command = &lt;0x6010001 0x1b7&gt;;
			qcom,mdss-dsi-panel-type = &quot;dsi_cmd_mode&quot;;
			qcom,mdss-dsi-lane-0-state;
			qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
			qcom,mdss-panel-on-dimming-delay = &lt;0x78&gt;;
			qcom,mdss-dsi-t-clk-pre = &lt;0x37&gt;;
			qcom,mdss-dsi-panel-hdr-enabled;
			qcom,mdss-dsi-panel-model = &quot;SS FHD EA CMD PANEL&quot;;
			qcom,mdss-dsi-te-pin-select = &lt;0x01&gt;;
			qcom,mdss-dsi-dispparam-elvss-dimming-offset-command = [39 01 00 00 00 00 02 b0 07];
			phandle = &lt;0x532&gt;;
			qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = &quot;dsi_lp_mode&quot;;
			qcom,mdss-dsi-bllp-power-mode;
			qcom,mdss-dsi-panel-sleepwrmod = &lt;0x00&gt;;
			qcom,mdss-dsi-stream = &lt;0x00&gt;;
			qcom,mdss-dsi-lp11-init;
			qcom,mdss-dsi-wr-mem-continue = &lt;0x3c&gt;;
			qcom,mdss-dsi-tx-eot-append;
			qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
			qcom,mdss-dsi-border-color = &lt;0x00&gt;;
			qcom,mdss-dsi-lane-1-state;
			qcom,mdss-dsi-wr-mem-start = &lt;0x2c&gt;;
			qcom,esd-err-irq-gpio = &lt;0x174 0x20 0x2002&gt;;
			qcom,mdss-dsi-bpp = &lt;0x18&gt;;
			qcom,mdss-brightness-max-level = &lt;0x7ff&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
					qcom,mdss-dsi-dispparam-hbm-fod2norm-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 b2 00 40 39 00 00 00 00 00 02 b0 04 39 00 00 00 00 00 02 b2 80 39 00 00 00 00 00 02 f7 03 39 01 00 00 00 00 03 f0 a5 a5];
					qcom,mdss-dsi-dispparam-acl-l3-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
					qcom,display-topology = &lt;0x01 0x00 0x01&gt;;
					qcom,mdss-dsi-dispparam-hbm-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-panel-framerate = &lt;0x3c&gt;;
					qcom,mdss-dsi-h-pulse-width = &lt;0x14&gt;;
					qcom,mdss-dsi-nolp-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00];
					qcom,mdss-dsi-dispparam-hbm-fod2norm-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-panel-jitter = &lt;0x05 0x01&gt;;
					qcom,mdss-dsi-nolp-command = [05 01 00 00 22 00 02 28 00 39 01 00 00 00 00 02 53 20 05 01 00 00 00 00 02 29 00];
					qcom,mdss-dsi-dispparam-crc-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-acl-l1-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-doze-hbm-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-doze-lbm-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 d4 8b 39 00 00 00 00 00 02 b0 a5 39 00 00 00 00 00 02 c7 00 39 00 00 00 00 00 02 b0 69 39 00 00 00 00 00 03 b9 08 8f 39 01 00 00 00 00 02 53 23 39 01 00 00 00 00 03 f0 a5 a5];
					qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 e8];
					qcom,mdss-dsi-dispparam-dimmingoff-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingon-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28];
					qcom,mdss-dsi-panel-height = &lt;0x924&gt;;
					qcom,mdss-dsi-on-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 fc 5a 5a 39 00 00 00 00 00 02 b0 0c 39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 b0 2f 39 01 00 00 00 00 02 d1 01 39 00 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 03 fc a5 a5 05 01 00 00 0a 00 02 11 00 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 35 00 39 00 00 00 00 00 03 b7 01 4b 39 00 00 00 00 00 02 b0 06 39 00 00 00 00 00 02 b7 10 39 01 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 05 2b 00 00 09 23 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 fc 5a 5a 39 00 00 00 00 00 02 b0 23 39 00 00 00 00 00 02 d1 11 39 00 00 00 00 00 0c e9 11 55 a6 75 a3 b9 a1 4a 00 1a b8 39 00 00 00 00 00 07 e1 00 00 02 02 42 02 39 00 00 00 00 00 07 e2 00 00 00 00 00 00 39 00 00 00 00 00 02 b0 0c 39 00 00 00 00 00 02 e1 19 39 00 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 03 fc a5 a5 39 00 00 00 00 00 02 53 20 39 00 00 00 00 00 03 51 00 00 39 01 00 00 43 00 02 55 00 05 01 00 00 00 00 02 29 00];
					qcom,mdss-dsi-h-front-porch = &lt;0x40&gt;;
					qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];
					qcom,mdss-dsi-h-back-porch = &lt;0x40&gt;;
					qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-hbm-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [39 01 00 00 00 00 02 81 91 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b1 00 39 01 00 00 00 00 02 b0 01 39 01 00 00 00 00 16 b1 ae 0c 05 3f c6 14 05 07 aa 4a dd c8 c3 14 c0 e8 dc 19 ff f4 d9 39 01 00 00 00 00 02 b0 16 39 01 00 00 00 00 16 b1 d2 0a 05 1a e6 00 04 07 f5 0c dc db e8 0f dd ee e9 05 ff ff ff 39 01 00 00 00 00 03 f0 a5 a5];
					qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];
					qcom,mdss-dsi-panel-clockrate = &lt;0x4190ab00&gt;;
					qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
					qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
					qcom,mdss-dsi-dispparam-acl-l2-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-v-pulse-width = &lt;0x14&gt;;
					qcom,mdss-dsi-doze-hbm-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 d4 8b 39 00 00 00 00 00 02 b0 a5 39 00 00 00 00 00 02 c7 00 39 00 00 00 00 00 02 b0 69 39 00 00 00 00 00 03 b9 08 8f 39 01 00 00 01 00 02 53 22 39 01 00 00 00 00 03 f0 a5 a5];
					qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-acl-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20];
					qcom,mdss-dsi-panel-phy-timings = &lt;0x240a0a 0x2625090a 0x6020400&gt;;
					qcom,mdss-dsi-v-back-porch = &lt;0x40&gt;;
					qcom,mdss-dsi-doze-lbm-command-state = &quot;dsi_lp_mode&quot;;
					qcom,default-topology-index = &lt;0x00&gt;;
					qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
					qcom,mdss-dsi-h-sync-pulse = &lt;0x00&gt;;
					qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00];
					qcom,mdss-dsi-dispparam-crc-srgb-on-command = [39 01 00 00 00 00 02 81 90 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b1 00 39 01 00 00 00 00 02 b0 01 39 01 00 00 00 00 16 b1 ae 0c 05 3f c6 14 05 07 aa 4a dd c8 c3 14 c0 e8 dc 19 ff f4 d9 39 01 00 00 00 00 02 b0 16 39 01 00 00 00 00 16 b1 bd 02 00 14 d1 00 04 07 aa 0c ec cb c8 0f dd d9 e4 05 ff ff ff 39 01 00 00 00 00 03 f0 a5 a5];
					qcom,mdss-dsi-dispparam-crc-off-command = [39 01 00 00 00 00 02 81 00 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b1 01 39 01 00 00 00 00 03 f0 a5 a5];
					qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28];
					qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-v-front-porch = &lt;0x40&gt;;
					qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];
					qcom,mdss-dsi-off-command-state = &quot;dsi_lp_mode&quot;;
				};
			};
		};

qcom,gdsc@17d040 {
			qcom,no-status-check-on-disable;
			qcom,gds-timeout = &lt;0x1f4&gt;;
			regulator-name = &quot;hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x17d040 0x04&gt;;
			phandle = &lt;0x1c8&gt;;
		};

i2c@0xa88000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x188&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			interrupts = &lt;0x00 0x163 0x00&gt;;
			clocks = &lt;0x27 0x5b 0x27 0x69 0x27 0x6a&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,i2c-geni&quot;;
			pinctrl-1 = &lt;0x189&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0xa88000 0x4000&gt;;
			phandle = &lt;0x35c&gt;;
			dmas = &lt;0x183 0x00 0x02 0x03 0x40 0x00 0x183 0x01 0x02 0x03 0x40 0x00&gt;;
		};

qcom,kgsl-3d0@5000000 {
			qcom,gpu-quirk-secvid-set-once;
			qcom,enable-ca-jump;
			qcom,ubwc-mode = &lt;0x02&gt;;
			qcom,gpu-speed-bin = &lt;0x41a0 0x1fe00000 0x15&gt;;
			vddcx-supply = &lt;0x1c5&gt;;
			clock-names = &quot;core_clk\0rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk&quot;;
			qcom,bus-width = &lt;0x20&gt;;
			reg-names = &quot;kgsl_3d0_reg_memory\0cx_dbgc\0cx_misc\0qfprom_memory&quot;;
			qcom,id = &lt;0x00&gt;;
			qcom,msm-bus,name = &quot;grp3d&quot;;
			qcom,highest-bank-bit = &lt;0x0e&gt;;
			interrupts = &lt;0x00 0x12c 0x04&gt;;
			clocks = &lt;0x2b 0x11 0x2b 0x0e 0x27 0x1b 0x27 0x2b 0x2b 0x0b&gt;;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,chipid = &lt;0x6010800&gt;;
			qcom,msm-bus,num-cases = &lt;0x0c&gt;;
			label = &quot;kgsl-3d0&quot;;
			vdd-supply = &lt;0x24e&gt;;
			qcom,pm-qos-active-latency = &lt;0x43&gt;;
			compatible = &quot;qcom,kgsl-3d0\0qcom,kgsl-3d&quot;;
			status = &quot;ok&quot;;
			qcom,gpu-qdss-stm = &lt;0x161c0000 0x40000&gt;;
			qcom,bus-control;
			interrupt-names = &quot;kgsl_3d0_irq&quot;;
			qcom,snapshot-size = &lt;0x200000&gt;;
			reg = &lt;0x5000000 0x40000 0x5061000 0x800 0x509e000 0x1000 0x780000 0x6300&gt;;
			regulator-names = &quot;vddcx\0vdd&quot;;
			phandle = &lt;0x21&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x1a 0x200 0x00 0x00 0x1a 0x200 0x00 0x61a80 0x1a 0x200 0x00 0xc3500 0x1a 0x200 0x00 0x124f80 0x1a 0x200 0x00 0x1b86e0 0x1a 0x200 0x00 0x2162e0 0x1a 0x200 0x00 0x2990a0 0x1a 0x200 0x00 0x325aa0 0x1a 0x200 0x00 0x3e12a0 0x1a 0x200 0x00 0x5294a0 0x1a 0x200 0x00 0x5ee8e0 0x1a 0x200 0x00 0x6e1b80&gt;;
			cache-slices = &lt;0x1a7 0x0c 0x1a7 0x0b&gt;;
			qcom,pm-qos-wakeup-latency = &lt;0x43&gt;;
			qcom,no-nap;
			qcom,idle-timeout = &lt;0x50&gt;;
			qcom,gpubw-dev = &lt;0x2a4&gt;;
			qcom,gpu-quirk-hfi-use-reg;
			qcom,min-access-length = &lt;0x20&gt;;
			#cooling-cells = &lt;0x02&gt;;
			qcom,ca-busy-penalty = &lt;0x2ee0&gt;;
			cache-slice-names = &quot;gpu\0gpuhtw&quot;;

qcom,gpu-mempools {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;
				compatible = &quot;qcom,gpu-mempools&quot;;

qcom,gpu-mempool@2 {
					reg = &lt;0x02&gt;;
					qcom,mempool-reserved = &lt;0x100&gt;;
					qcom,mempool-page-size = &lt;0x10000&gt;;
				};

qcom,gpu-mempool@0 {
					qcom,mempool-allocate;
					reg = &lt;0x00&gt;;
					qcom,mempool-page-size = &lt;0x1000&gt;;
				};

qcom,gpu-mempool@3 {
					reg = &lt;0x03&gt;;
					qcom,mempool-reserved = &lt;0x20&gt;;
					qcom,mempool-page-size = &lt;0x100000&gt;;
				};

qcom,gpu-mempool@1 {
					qcom,mempool-allocate;
					reg = &lt;0x01&gt;;
					qcom,mempool-page-size = &lt;0x2000&gt;;
				};
			};

qcom,gpu-pwrlevel-bins {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;
				compatible = &quot;qcom,gpu-pwrlevel-bins&quot;;

qcom,gpu-pwrlevels-4 {
					#address-cells = &lt;0x01&gt;;
					qcom,initial-pwrlevel = &lt;0x06&gt;;
					#size-cells = &lt;0x00&gt;;
					qcom,ca-target-pwrlevel = &lt;0x04&gt;;
					qcom,speed-bin = &lt;0xa7&gt;;

qcom,gpu-pwrlevel@1 {
						qcom,bus-min = &lt;0x08&gt;;
						qcom,bus-freq = &lt;0x0a&gt;;
						qcom,bus-max = &lt;0x0b&gt;;
						qcom,gpu-freq = &lt;0x26be3680&gt;;
						reg = &lt;0x01&gt;;
					};

qcom,gpu-pwrlevel@6 {
						qcom,bus-min = &lt;0x03&gt;;
						qcom,bus-freq = &lt;0x04&gt;;
						qcom,bus-max = &lt;0x04&gt;;
						qcom,gpu-freq = &lt;0xaba9500&gt;;
						reg = &lt;0x06&gt;;
					};

qcom,gpu-pwrlevel@4 {
						qcom,bus-min = &lt;0x05&gt;;
						qcom,bus-freq = &lt;0x07&gt;;
						qcom,bus-max = &lt;0x08&gt;;
						qcom,gpu-freq = &lt;0x1528dec0&gt;;
						reg = &lt;0x04&gt;;
					};

qcom,gpu-pwrlevel@2 {
						qcom,bus-min = &lt;0x08&gt;;
						qcom,bus-freq = &lt;0x09&gt;;
						qcom,bus-max = &lt;0x0a&gt;;
						qcom,gpu-freq = &lt;0x21ad3740&gt;;
						reg = &lt;0x02&gt;;
					};

qcom,gpu-pwrlevel@0 {
						qcom,bus-min = &lt;0x0a&gt;;
						qcom,bus-freq = &lt;0x0b&gt;;
						qcom,bus-max = &lt;0x0b&gt;;
						qcom,gpu-freq = &lt;0x2faf0800&gt;;
						reg = &lt;0x00&gt;;
					};

qcom,gpu-pwrlevel@7 {
						qcom,bus-min = &lt;0x00&gt;;
						qcom,bus-freq = &lt;0x00&gt;;
						qcom,bus-max = &lt;0x00&gt;;
						qcom,gpu-freq = &lt;0x00&gt;;
						reg = &lt;0x07&gt;;
					};

qcom,gpu-pwrlevel@5 {
						qcom,bus-min = &lt;0x04&gt;;
						qcom,bus-freq = &lt;0x06&gt;;
						qcom,bus-max = &lt;0x07&gt;;
						qcom,gpu-freq = &lt;0xfea18c0&gt;;
						reg = &lt;0x05&gt;;
					};

qcom,gpu-pwrlevel@3 {
						qcom,bus-min = &lt;0x07&gt;;
						qcom,bus-freq = &lt;0x08&gt;;
						qcom,bus-max = &lt;0x0a&gt;;
						qcom,gpu-freq = &lt;0x19a14780&gt;;
						reg = &lt;0x03&gt;;
					};
				};

qcom,gpu-pwrlevels-2 {
					#address-cells = &lt;0x01&gt;;
					qcom,initial-pwrlevel = &lt;0x06&gt;;
					#size-cells = &lt;0x00&gt;;
					qcom,ca-target-pwrlevel = &lt;0x04&gt;;
					qcom,speed-bin = &lt;0x92&gt;;

qcom,gpu-pwrlevel@0 {
						qcom,bus-min = &lt;0x0a&gt;;
						qcom,bus-freq = &lt;0x0b&gt;;
						qcom,bus-max = &lt;0x0b&gt;;
						qcom,gpu-freq = &lt;0x29b92700&gt;;
						reg = &lt;0x00&gt;;
					};

qcom,gpu-pwrlevel@7 {
						qcom,bus-min = &lt;0x00&gt;;
						qcom,bus-freq = &lt;0x00&gt;;
						qcom,bus-max = &lt;0x00&gt;;
						qcom,gpu-freq = &lt;0x00&gt;;
						reg = &lt;0x07&gt;;
					};

qcom,gpu-pwrlevels-0 {
					#address-cells = &lt;0x01&gt;;
					qcom,initial-pwrlevel = &lt;0x07&gt;;
					#size-cells = &lt;0x00&gt;;
					qcom,ca-target-pwrlevel = &lt;0x05&gt;;
					qcom,speed-bin = &lt;0x00&gt;;

qcom,gpu-pwrlevel@1 {
						qcom,bus-min = &lt;0x0a&gt;;
						qcom,bus-freq = &lt;0x0b&gt;;
						qcom,bus-max = &lt;0x0b&gt;;
						qcom,gpu-freq = &lt;0x2faf0800&gt;;
						reg = &lt;0x01&gt;;
					};

qcom,gpu-pwrlevel@8 {
						qcom,bus-min = &lt;0x00&gt;;
						qcom,bus-freq = &lt;0x00&gt;;
						qcom,bus-max = &lt;0x00&gt;;
						qcom,gpu-freq = &lt;0x00&gt;;
						reg = &lt;0x08&gt;;
					};

qcom,gpu-pwrlevel@6 {
						qcom,bus-min = &lt;0x04&gt;;
						qcom,bus-freq = &lt;0x06&gt;;
						qcom,bus-max = &lt;0x07&gt;;
						qcom,gpu-freq = &lt;0xfea18c0&gt;;
						reg = &lt;0x06&gt;;
					};

qcom,gpu-pwrlevel@4 {
						qcom,bus-min = &lt;0x07&gt;;
						qcom,bus-freq = &lt;0x08&gt;;
						qcom,bus-max = &lt;0x0a&gt;;
						qcom,gpu-freq = &lt;0x19a14780&gt;;
						reg = &lt;0x04&gt;;
					};

qcom,gpu-pwrlevel@2 {
						qcom,bus-min = &lt;0x08&gt;;
						qcom,bus-freq = &lt;0x0a&gt;;
						qcom,bus-max = &lt;0x0b&gt;;
						qcom,gpu-freq = &lt;0x26be3680&gt;;
						reg = &lt;0x02&gt;;
					};

qcom,gpu-pwrlevel@0 {
						qcom,bus-min = &lt;0x0a&gt;;
						qcom,bus-freq = &lt;0x0b&gt;;
						qcom,bus-max = &lt;0x0b&gt;;
						qcom,gpu-freq = &lt;0x312c8040&gt;;
						reg = &lt;0x00&gt;;
					};

qcom,gpu-pwrlevel@7 {
						qcom,bus-min = &lt;0x03&gt;;
						qcom,bus-freq = &lt;0x04&gt;;
						qcom,bus-max = &lt;0x04&gt;;
						qcom,gpu-freq = &lt;0xaba9500&gt;;
						reg = &lt;0x07&gt;;
					};

qcom,gpu-pwrlevel@5 {
						qcom,bus-min = &lt;0x05&gt;;
						qcom,bus-freq = &lt;0x07&gt;;
						qcom,bus-max = &lt;0x08&gt;;
						qcom,gpu-freq = &lt;0x1528dec0&gt;;
						reg = &lt;0x05&gt;;
					};

qcom,gpu-pwrlevel@3 {
						qcom,bus-min = &lt;0x08&gt;;
						qcom,bus-freq = &lt;0x09&gt;;
						qcom,bus-max = &lt;0x0a&gt;;
						qcom,gpu-freq = &lt;0x21ad3740&gt;;
						reg = &lt;0x03&gt;;
					};
				};

qcom,gpu-pwrlevels-3 {
					#address-cells = &lt;0x01&gt;;
					qcom,initial-pwrlevel = &lt;0x05&gt;;
					#size-cells = &lt;0x00&gt;;
					qcom,ca-target-pwrlevel = &lt;0x03&gt;;
					qcom,speed-bin = &lt;0x80&gt;;

qcom,gpu-pwrlevel@1 {
						qcom,bus-min = &lt;0x08&gt;;
						qcom,bus-freq = &lt;0x09&gt;;
						qcom,bus-max = &lt;0x0a&gt;;
						qcom,gpu-freq = &lt;0x21ad3740&gt;;
						reg = &lt;0x01&gt;;
					};

qcom,gpu-pwrlevel@6 {
						qcom,bus-min = &lt;0x00&gt;;
						qcom,bus-freq = &lt;0x00&gt;;
						qcom,bus-max = &lt;0x00&gt;;
						qcom,gpu-freq = &lt;0x00&gt;;
						reg = &lt;0x06&gt;;
					};

qcom,gpu-pwrlevel@4 {
						qcom,bus-min = &lt;0x04&gt;;
						qcom,bus-freq = &lt;0x06&gt;;
						qcom,bus-max = &lt;0x07&gt;;
						qcom,gpu-freq = &lt;0xfea18c0&gt;;
						reg = &lt;0x04&gt;;
					};

qcom,gpu-pwrlevel@2 {
						qcom,bus-min = &lt;0x07&gt;;
						qcom,bus-freq = &lt;0x08&gt;;
						qcom,bus-max = &lt;0x0a&gt;;
						qcom,gpu-freq = &lt;0x19a14780&gt;;
						reg = &lt;0x02&gt;;
					};

qcom,gpu-pwrlevel@0 {
						qcom,bus-min = &lt;0x0a&gt;;
						qcom,bus-freq = &lt;0x0b&gt;;
						qcom,bus-max = &lt;0x0b&gt;;
						qcom,gpu-freq = &lt;0x245bdc80&gt;;
						reg = &lt;0x00&gt;;
					};

qcom,gpu-pwrlevel@5 {
						qcom,bus-min = &lt;0x03&gt;;
						qcom,bus-freq = &lt;0x04&gt;;
						qcom,bus-max = &lt;0x04&gt;;
						qcom,gpu-freq = &lt;0xaba9500&gt;;
						reg = &lt;0x05&gt;;
					};

qcom,gpu-pwrlevel@3 {
						qcom,bus-min = &lt;0x05&gt;;
						qcom,bus-freq = &lt;0x07&gt;;
						qcom,bus-max = &lt;0x08&gt;;
						qcom,gpu-freq = &lt;0x1528dec0&gt;;
						reg = &lt;0x03&gt;;
					};
				};

qcom,gpu-pwrlevels-1 {
					#address-cells = &lt;0x01&gt;;
					qcom,initial-pwrlevel = &lt;0x07&gt;;
					#size-cells = &lt;0x00&gt;;
					qcom,ca-target-pwrlevel = &lt;0x05&gt;;
					qcom,speed-bin = &lt;0xac&gt;;

qcom,gpu-pwrlevel@8 {
						qcom,bus-min = &lt;0x00&gt;;
						qcom,bus-freq = &lt;0x00&gt;;
						qcom,bus-max = &lt;0x00&gt;;
						qcom,gpu-freq = &lt;0x00&gt;;
						reg = &lt;0x08&gt;;
					};

kgsl_iommu_test_device {
			iommus = &lt;0x1cd 0x07&gt;;
			compatible = &quot;iommu-debug-test&quot;;
		};

tpda@7832000 {
			arm,primecell-periphid = &lt;0x3b969&gt;;
			qcom,cmb-elem-size = &lt;0x00 0x40&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpda-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpda-olc&quot;;
			compatible = &quot;arm,primecell&quot;;
			qcom,tpda-atid = &lt;0x45&gt;;
			reg = &lt;0x7832000 0x1000&gt;;
			phandle = &lt;0x433&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x208&gt;;
						phandle = &lt;0x204&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x209&gt;;
						phandle = &lt;0x20a&gt;;
					};
				};
			};
		};

qcom,msm_gsi {
			compatible = &quot;qcom,msm_gsi&quot;;
		};

qcom,cpu-cpu-llcc-bw {
			qcom,src-dst-ports = &lt;0x01 0x302&gt;;
			governor = &quot;performance&quot;;
			compatible = &quot;qcom,devbw&quot;;
			phandle = &lt;0xbd&gt;;
			qcom,active-only;
			operating-points-v2 = &lt;0xbc&gt;;
		};

qcom,cdsp-cdsp-l3-lat {
			clock-names = &quot;devfreq_clk&quot;;
			clocks = &lt;0xc0 0x03&gt;;
			governor = &quot;powersave&quot;;
			compatible = &quot;devfreq-simple-dev&quot;;
			phandle = &lt;0x26&gt;;
		};

tpdm@6c28000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-dl-center&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6c28000 0x1000&gt;;
			phandle = &lt;0x44d&gt;;
			qcom,msr-fix-req;

port {

endpoint {
					remote-endpoint = &lt;0x241&gt;;
					phandle = &lt;0x230&gt;;
				};
			};
		};

qcom,smp2p_interrupt_rdbg_5_in {
			interrupts-extended = &lt;0x1bf 0x00 0x00&gt;;
			compatible = &quot;qcom,smp2p-interrupt-rdbg-5-in&quot;;
			interrupt-names = &quot;rdbg-smp2p-in&quot;;
		};

usb_nop_phy {
			compatible = &quot;usb-nop-xceiv&quot;;
			phandle = &lt;0x488&gt;;
		};

qcom,msm-dai-tdm-quin-rx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9040&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9140&gt;;
			phandle = &lt;0x4c2&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-quin-rx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9040&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x28e&gt;;
			};
		};

qcom,gdsc@17d030 {
			qcom,no-status-check-on-disable;
			qcom,gds-timeout = &lt;0x1f4&gt;;
			regulator-name = &quot;hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x17d030 0x04&gt;;
			phandle = &lt;0x1cb&gt;;
		};

qcom,csid1@acba000 {
			camss-supply = &lt;0x1ae&gt;;
			clock-control-debugfs = &quot;true&quot;;
			clock-names = &quot;ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_clk\0ife_axi_clk&quot;;
			reg-names = &quot;csid&quot;;
			reg-cam-base = &lt;0xba000&gt;;
			cell-index = &lt;0x01&gt;;
			ife1-supply = &lt;0x1b8&gt;;
			interrupts = &lt;0x00 0x1d2 0x00&gt;;
			clocks = &lt;0x29 0x3c 0x29 0x3b 0x29 0x1b 0x29 0x3a 0x29 0x39 0x29 0x38 0x29 0x37&gt;;
			clock-cntl-level = &quot;lowsvs\0svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,csid175_200&quot;;
			src-clock-name = &quot;ife_csid_clk_src&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;csid&quot;;
			reg = &lt;0xacba000 0x1000&gt;;
			regulator-names = &quot;camss\0ife1&quot;;
			phandle = &lt;0x38f&gt;;
			clock-rates = &lt;0x11e1a300 0x00 0x00 0x00 0x16a65700 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x1e65fb80 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x25f7d940 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x2d4cae00 0x00 0x00&gt;;
		};

cti@69C1000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-dlmm_cti0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x69c1000 0x1000&gt;;
			phandle = &lt;0x466&gt;;
		};

cti@6a02000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-ddr_dl_0_cti0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6a02000 0x1000&gt;;
			phandle = &lt;0x461&gt;;
		};

apps_iommu_coherent_test_device {
			iommus = &lt;0x30 0x23 0x00&gt;;
			dma-coherent;
			compatible = &quot;iommu-debug-test&quot;;
		};

qcom,dsi-display@34 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x53e&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_k6_38_0c_0a_fhd_dsc_video_display&quot;;
			phandle = &lt;0x55b&gt;;
		};

bt_wcn3990 {
			qca,bt-vdd-core-supply = &lt;0x32&gt;;
			qca,bt-vdd-core-current-level = &lt;0x01&gt;;
			qca,bt-vdd-pa-voltage-level = &lt;0x30d400 0x33e140&gt;;
			qca,bt-vdd-io-voltage-level = &lt;0x19f0a0 0x1cfde0&gt;;
			qca,bt-vdd-xtal-voltage-level = &lt;0x19f0a0 0x1cfde0&gt;;
			qca,bt-vdd-pa-supply = &lt;0x33&gt;;
			qca,bt-vdd-xtal-supply = &lt;0x34&gt;;
			compatible = &quot;qca,wcn3990&quot;;
			qca,bt-vdd-core-voltage-level = &lt;0x12ff48 0x149970&gt;;
			phandle = &lt;0x2b4&gt;;
			qca,bt-vdd-pa-current-level = &lt;0x01&gt;;
			qca,bt-vdd-io-supply = &lt;0x31&gt;;
			qca,bt-vdd-io-current-level = &lt;0x01&gt;;
			qca,bt-vdd-xtal-current-level = &lt;0x01&gt;;
		};

qcom,gdsc@177004 {
			qcom,poll-cfg-gdscr;
			regulator-name = &quot;ufs_phy_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x177004 0x04&gt;;
			phandle = &lt;0x9b&gt;;
		};

qcom,msm-stub-codec {
			compatible = &quot;qcom,msm-stub-codec&quot;;
			phandle = &lt;0x48c&gt;;
		};

rpmh-regulator-ldoa10 {
			qcom,mode-threshold-currents = &lt;0x00 0x2710&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa10&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l10 {
				regulator-max-microvolt = &lt;0x1bf440&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x1a3ec0&gt;;
				regulator-min-microvolt = &lt;0x1a3ec0&gt;;
				regulator-name = &quot;pm6150_l10&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x31&gt;;
			};
		};

qcom,smp2p_interrupt_rdbg_2_in {
			interrupts-extended = &lt;0x1bd 0x00 0x00&gt;;
			compatible = &quot;qcom,smp2p-interrupt-rdbg-2-in&quot;;
			interrupt-names = &quot;rdbg-smp2p-in&quot;;
		};

qcom,npu-npu-ddr-bw {
			qcom,src-dst-ports = &lt;0x9a 0x200&gt;;
			governor = &quot;performance&quot;;
			compatible = &quot;qcom,devbw&quot;;
			phandle = &lt;0xc8&gt;;
			operating-points-v2 = &lt;0xc7&gt;;
		};

tpdm@6b44000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-center&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b44000 0x1000&gt;;
			phandle = &lt;0x45c&gt;;
			qcom,msr-fix-req;

port {

endpoint {
					remote-endpoint = &lt;0x257&gt;;
					phandle = &lt;0x23b&gt;;
				};
			};
		};

qcom,smp2p-modem {
			qcom,local-pid = &lt;0x00&gt;;
			interrupts = &lt;0x00 0x1c3 0x01&gt;;
			qcom,remote-pid = &lt;0x01&gt;;
			compatible = &quot;qcom,smp2p&quot;;
			qcom,smem = &lt;0x1b3 0x1ac&gt;;
			qcom,ipc = &lt;0x99 0x00 0x0e&gt;;

qcom,smp2p-ipa-1-in {
				qcom,entry-name = &quot;ipa&quot;;
				#interrupt-cells = &lt;0x02&gt;;
				phandle = &lt;0xbb&gt;;
				interrupt-controller;
			};

slave-kernel {
				qcom,entry-name = &quot;slave-kernel&quot;;
				#interrupt-cells = &lt;0x02&gt;;
				phandle = &lt;0xb2&gt;;
				interrupt-controller;
			};

master-kernel {
				qcom,entry-name = &quot;master-kernel&quot;;
				#qcom,smem-state-cells = &lt;0x01&gt;;
				phandle = &lt;0xb3&gt;;
			};

qcom,smp2p-ipa-1-out {
				qcom,entry-name = &quot;ipa&quot;;
				#qcom,smem-state-cells = &lt;0x01&gt;;
				phandle = &lt;0xba&gt;;
			};

qcom,smp2p-wlan-1-in {
				qcom,entry-name = &quot;wlan&quot;;
				#interrupt-cells = &lt;0x02&gt;;
				phandle = &lt;0xb9&gt;;
				interrupt-controller;
			};
		};

dummy_sink {
			coresight-name = &quot;coresight-eud&quot;;
			qcom,dummy-sink;
			compatible = &quot;qcom,coresight-dummy&quot;;
			phandle = &lt;0x429&gt;;

port {

endpoint {
					slave-mode;
					remote-endpoint = &lt;0x1f2&gt;;
					phandle = &lt;0x1f3&gt;;
				};
			};
		};

cti@6019000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti9&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6019000 0x1000&gt;;
			phandle = &lt;0x47e&gt;;
		};

rpmh-regulator-ldoa5 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa5&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l5 {
				regulator-max-microvolt = &lt;0x2ab980&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x27ac40&gt;;
				regulator-min-microvolt = &lt;0x27ac40&gt;;
				regulator-name = &quot;pm6150_l5&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x405&gt;;
			};
		};

qcom,cam-jpeg {
			num-jpeg-enc = &lt;0x01&gt;;
			num-jpeg-dma = &lt;0x01&gt;;
			compat-hw-name = &quot;qcom,jpegenc\0qcom,jpegdma&quot;;
			compatible = &quot;qcom,cam-jpeg&quot;;
			status = &quot;ok&quot;;
		};

qcom,msm-imem@146aa000 {
			#address-cells = &lt;0x01&gt;;
			#size-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-imem&quot;;
			ranges = &lt;0x00 0x146aa000 0x1000&gt;;
			reg = &lt;0x146aa000 0x1000&gt;;

dload_type@1c {
				compatible = &quot;qcom,msm-imem-dload-type&quot;;
				reg = &lt;0x1c 0x04&gt;;
			};

restart_reason@65c {
				compatible = &quot;qcom,msm-imem-restart_reason&quot;;
				reg = &lt;0x65c 0x04&gt;;
			};

boot_stats@6b0 {
				compatible = &quot;qcom,msm-imem-boot_stats&quot;;
				reg = &lt;0x6b0 0x20&gt;;
			};

pil@94c {
				compatible = &quot;qcom,msm-imem-pil&quot;;
				reg = &lt;0x94c 0xc8&gt;;
			};

mem_dump_table@10 {
				compatible = &quot;qcom,msm-imem-mem_dump_table&quot;;
				reg = &lt;0x10 0x08&gt;;
			};

diag_dload@c8 {
				compatible = &quot;qcom,msm-imem-diag-dload&quot;;
				reg = &lt;0xc8 0xc8&gt;;
			};

kaslr_offset@6d0 {
				compatible = &quot;qcom,msm-imem-kaslr_offset&quot;;
				reg = &lt;0x6d0 0x0c&gt;;
			};
		};

qcom,cpu6-cpu-l3-latmon {
			qcom,cachemiss-ev = &lt;0x17&gt;;
			qcom,core-dev-table = &lt;0x10b170 0x21301800 0x1433e0 0x2dc6c000 0x1a1300 0x46f41000 0x1d9638 0x5265c000 0x253500 0x56f9a000&gt;;
			qcom,cpulist = &lt;0x17 0x18&gt;;
			compatible = &quot;qcom,arm-memlat-mon&quot;;
			phandle = &lt;0x314&gt;;
			qcom,target-dev = &lt;0x25&gt;;
		};

qcom,gdsc@ad0a004 {
			qcom,poll-cfg-gdscr;
			clock-names = &quot;ahb_clk&quot;;
			clocks = &lt;0x27 0x0e&gt;;
			regulator-name = &quot;ife_0_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xad0a004 0x04&gt;;
			phandle = &lt;0x1b7&gt;;
		};

funnel@6861000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-turing&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6861000 0x1000&gt;;
			phandle = &lt;0x450&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x245&gt;;
						phandle = &lt;0x232&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x246&gt;;
						phandle = &lt;0x24a&gt;;
					};
				};
			};
		};

qcom,dsi-display@24 {
			qcom,dsi-phy-num = &lt;0x00 0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x538&gt;;
			qcom,dsi-ctrl-num = &lt;0x00 0x01&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_sharp_qsync_fhd_video_display&quot;;
			phandle = &lt;0x559&gt;;
		};

ssusb@a600000 {
			iommus = &lt;0x30 0x540 0x00&gt;;
			qcom,smmu-s1-bypass;
			#address-cells = &lt;0x01&gt;;
			clock-names = &quot;core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk\0xo&quot;;
			reg-names = &quot;core_base&quot;;
			qcom,msm-bus,name = &quot;usb0&quot;;
			resets = &lt;0x27 0x04&gt;;
			interrupts = &lt;0x00 0x1e9 0x00 0x00 0x82 0x00 0x00 0x1e6 0x00 0x00 0x1e8 0x00&gt;;
			clocks = &lt;0x27 0x8d 0x27 0x15 0x27 0x0b 0x27 0x8f 0x27 0x91 0x27 0x92&gt;;
			qcom,use-pdc-interrupts;
			qcom,msm-bus,num-paths = &lt;0x03&gt;;
			extcon = &lt;0x25b 0x8a 0x25c&gt;;
			#size-cells = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x04&gt;;
			dpdm-supply = &lt;0x25a&gt;;
			qcom,pm-qos-latency = &lt;0x3e&gt;;
			qcom,gsi-disable-io-coherency;
			qcom,core-clk-rate-hs = &lt;0x3f940ab&gt;;
			qcom,num-gsi-evt-buffs = &lt;0x03&gt;;
			compatible = &quot;qcom,dwc-usb3-msm&quot;;
			ranges;
			interrupt-names = &quot;dp_hs_phy_irq\0pwr_event_irq\0ss_phy_irq\0dm_hs_phy_irq&quot;;
			qcom,core-clk-rate = &lt;0x7f28155&gt;;
			reg = &lt;0xa600000 0x100000&gt;;
			phandle = &lt;0x487&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x3d 0x200 0x00 0x00 0x3d 0x2a4 0x00 0x00 0x01 0x247 0x00 0x00 0x3d 0x200 0xf4240 0x2625a0 0x3d 0x2a4 0x00 0x960 0x01 0x247 0x00 0x9c40 0x3d 0x200 0x3a980 0xaae60 0x3d 0x2a4 0x00 0x960 0x01 0x247 0x00 0x9c40 0x3d 0x200 0x01 0x01 0x3d 0x2a4 0x01 0x01 0x01 0x247 0x01 0x01&gt;;
			qcom,dwc-usb3-msm-tx-fifo-size = &lt;0x5328&gt;;
			reset-names = &quot;core_reset&quot;;
			USB3_GDSC-supply = &lt;0x259&gt;;
			qcom,gsi-reg-offset = &lt;0xfc 0x110 0x120 0x130 0x144 0x1a4&gt;;

dwc3@a600000 {
				linux,sysdev_is_parent;
				snps,hird-threshold = [10];
				tx-fifo-resize;
				snps,dis_enblslpm_quirk;
				snps,usb3_lpm_capable;
				usb-core-id = &lt;0x00&gt;;
				snps,dis_u2_susphy_quirk;
				interrupts = &lt;0x00 0x85 0x00&gt;;
				num-gsi-eps = &lt;0x03&gt;;
				compatible = &quot;snps,dwc3&quot;;
				snps,disable-clk-gating;
				snps,has-lpm-erratum;
				reg = &lt;0xa600000 0xcd00&gt;;
				usb-phy = &lt;0x25a 0x488&gt;;
				dr_mode = &quot;otg&quot;;
				maximum-speed = &quot;high-speed&quot;;
			};

qcom,usbbam@a704000 {
				qcom,disable-clk-gating;
				qcom,usb-bam-num-pipes = &lt;0x04&gt;;
				interrupts = &lt;0x00 0x84 0x00&gt;;
				qcom,usb-bam-max-mbps-highspeed = &lt;0x190&gt;;
				compatible = &quot;qcom,usb-bam-msm&quot;;
				qcom,usb-bam-max-mbps-superspeed = &lt;0xe10&gt;;
				qcom,usb-bam-fifo-baseaddr = &lt;0x146a6000&gt;;
				qcom,reset-bam-on-connect;
				reg = &lt;0xa704000 0x17000&gt;;
				qcom,usb-bam-override-threshold = &lt;0x4001&gt;;

qcom,pipe0 {
					qcom,descriptor-fifo-offset = &lt;0x1800&gt;;
					qcom,data-fifo-offset = &lt;0x00&gt;;
					qcom,usb-bam-mem-type = &lt;0x02&gt;;
					qcom,src-bam-pipe-index = &lt;0x00&gt;;
					qcom,peer-bam-physical-address = &lt;0x6064000&gt;;
					qcom,peer-bam = &lt;0x00&gt;;
					qcom,dir = &lt;0x01&gt;;
					label = &quot;ssusb-qdss-in-0&quot;;
					qcom,dst-bam-pipe-index = &lt;0x00&gt;;
					qcom,data-fifo-size = &lt;0x1800&gt;;
					qcom,pipe-num = &lt;0x00&gt;;
					qcom,descriptor-fifo-size = &lt;0x800&gt;;
				};
			};
		};

gpio-regulator@0 {
			regulator-max-microvolt = &lt;0x1b7740&gt;;
			gpio = &lt;0x2ec 0x04 0x00&gt;;
			regulator-enable-ramp-delay = &lt;0x64&gt;;
			enable-active-high;
			regulator-min-microvolt = &lt;0x1b7740&gt;;
			regulator-name = &quot;camera_vddio_regulator&quot;;
			compatible = &quot;regulator-fixed&quot;;
			reg = &lt;0x00 0x00&gt;;
			phandle = &lt;0x562&gt;;
			vin-supply = &lt;0x3fe&gt;;
		};

tpda@6831000 {
			arm,primecell-periphid = &lt;0x3b969&gt;;
			qcom,cmb-elem-size = &lt;0x00 0x40&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpda-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpda-modem-0&quot;;
			qcom,dsb-elem-size = &lt;0x00 0x20&gt;;
			compatible = &quot;arm,primecell&quot;;
			qcom,tpda-atid = &lt;0x43&gt;;
			reg = &lt;0x6831000 0x1000&gt;;
			phandle = &lt;0x425&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1eb&gt;;
						phandle = &lt;0x1e9&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1ec&gt;;
						phandle = &lt;0x1ef&gt;;
					};
				};
			};
		};

etm@7140000 {
			arm,primecell-periphid = &lt;0xbb95d&gt;;
			clock-names = &quot;apb_pclk&quot;;
			clocks = &lt;0x19 0x00&gt;;
			cpu = &lt;0x12&gt;;
			qcom,tupwr-disable;
			coresight-name = &quot;coresight-etm1&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7140000 0x1000&gt;;
			phandle = &lt;0x43d&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x21e&gt;;
					phandle = &lt;0x216&gt;;
				};
			};
		};

cti@6016000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti6&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6016000 0x1000&gt;;
			phandle = &lt;0x47b&gt;;
		};

qcom,glink {
			#address-cells = &lt;0x01&gt;;
			#size-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,glink&quot;;
			ranges;

adsp {
				transport = &quot;smem&quot;;
				interrupts = &lt;0x00 0xaa 0x01&gt;;
				qcom,glink-label = &quot;lpass&quot;;
				label = &quot;adsp&quot;;
				qcom,remote-pid = &lt;0x02&gt;;
				phandle = &lt;0x94&gt;;
				mboxes = &lt;0x93 0x18&gt;;
				mbox-names = &quot;adsp_smem&quot;;

qcom,adsp_glink_ssr {
					qcom,notify-edges = &lt;0x96 0x95&gt;;
					qcom,glink-channels = &quot;glink_ssr&quot;;
				};

qcom,msm_fastrpc_rpmsg {
					qcom,intents = &lt;0x64 0x40&gt;;
					compatible = &quot;qcom,msm-fastrpc-rpmsg&quot;;
					qcom,glink-channels = &quot;fastrpcglink-apps-dsp&quot;;
				};

qcom,apr_tal_rpmsg {
					qcom,intents = &lt;0x200 0x14&gt;;
					qcom,glink-channels = &quot;apr_audio_svc&quot;;
				};

qcom,adsp_qrtr {
					qcom,intents = &lt;0x800 0x05 0x2000 0x03 0x4400 0x02&gt;;
					qcom,glink-channels = &quot;IPCRTR&quot;;
				};
			};

wdsp {
				transport = &quot;spi&quot;;
				qcom,glink-label = &quot;wdsp&quot;;
				label = &quot;wdsp&quot;;
				tx-descriptors = &lt;0x12000 0x12004&gt;;
				qcom,remote-pid = &lt;0x0a&gt;;
				phandle = &lt;0x2d6&gt;;
				rx-descriptors = &lt;0x1200c 0x12010&gt;;

qcom,diag_data {
					qcom,intents = &lt;0x4000 0x02&gt;;
					qcom,glink-channels = &quot;DIAG_DATA&quot;;
				};

qcom,wdsp_nild {
					qcom,glink-channels = &quot;g_glink_persistent_data_nild&quot;;
				};

qcom,wdsp_ctrl {
					qcom,intents = &lt;0x400 0x01&gt;;
					qcom,glink-channels = &quot;g_glink_ctrl&quot;;
				};

qcom,diag_ctrl {
					qcom,intents = &lt;0x4000 0x01&gt;;
					qcom,glink-channels = &quot;DIAG_CTRL&quot;;
				};

qcom,wdsp_ild {
					qcom,glink-channels = &quot;g_glink_persistent_data_ild&quot;;
				};

qcom,diag_cmd {
					qcom,intents = &lt;0x4000 0x01&gt;;
					qcom,glink-channels = &quot;DIAG_CMD&quot;;
				};

qcom,wdsp_data {
					qcom,intents = &lt;0x1000 0x02&gt;;
					qcom,glink-channels = &quot;g_glink_audio_data&quot;;
				};
			};

cdsp {
				transport = &quot;smem&quot;;
				interrupts = &lt;0x00 0x23e 0x01&gt;;
				qcom,glink-label = &quot;cdsp&quot;;
				label = &quot;cdsp&quot;;
				qcom,remote-pid = &lt;0x05&gt;;
				phandle = &lt;0x95&gt;;
				mboxes = &lt;0x93 0x04&gt;;
				mbox-names = &quot;cdsp_smem&quot;;

qcom,cdsp_qrtr {
					qcom,intents = &lt;0x800 0x05 0x2000 0x03 0x4400 0x02&gt;;
					qcom,glink-channels = &quot;IPCRTR&quot;;
				};

qcom,cdsp_glink_ssr {
					qcom,notify-edges = &lt;0x96 0x94&gt;;
					qcom,glink-channels = &quot;glink_ssr&quot;;
				};

qcom,msm_fastrpc_rpmsg {
					qcom,intents = &lt;0x64 0x40&gt;;
					compatible = &quot;qcom,msm-fastrpc-rpmsg&quot;;
					qcom,glink-channels = &quot;fastrpcglink-apps-dsp&quot;;
				};

qcom,msm_cdsprm_rpmsg {
					qcom,intents = &lt;0x20 0x0c&gt;;
					compatible = &quot;qcom,msm-cdsprm-rpmsg&quot;;
					qcom,glink-channels = &quot;cdsprmglink-apps-dsp&quot;;

qcom,msm_cdsp_rm {
						qcom,compute-priority-mode = &lt;0x02&gt;;
						qcom,qos-maxhold-ms = &lt;0x14&gt;;
						compatible = &quot;qcom,msm-cdsp-rm&quot;;
						qcom,compute-cx-limit-en;
						phandle = &lt;0x7d&gt;;
						#cooling-cells = &lt;0x02&gt;;
						qcom,qos-latency-us = &lt;0x2c&gt;;
					};

qcom,msm_hvx_rm {
						compatible = &quot;qcom,msm-hvx-rm&quot;;
						phandle = &lt;0x2d5&gt;;
						#cooling-cells = &lt;0x02&gt;;
					};

qcom,cdsp-cdsp-l3-gov {
						compatible = &quot;qcom,cdsp-l3&quot;;
						qcom,target-dev = &lt;0x26&gt;;
					};
				};
			};

modem {
				transport = &quot;smem&quot;;
				interrupts = &lt;0x00 0x1c1 0x01&gt;;
				qcom,glink-label = &quot;mpss&quot;;
				label = &quot;modem&quot;;
				qcom,remote-pid = &lt;0x01&gt;;
				phandle = &lt;0x96&gt;;
				mboxes = &lt;0x93 0x0c&gt;;
				mbox-names = &quot;mpss_smem&quot;;

qcom,modem_qrtr {
					qcom,intents = &lt;0x800 0x05 0x2000 0x03 0x4400 0x02&gt;;
					qcom,glink-channels = &quot;IPCRTR&quot;;
				};

qcom,msm_fastrpc_rpmsg {
					qcom,intents = &lt;0x64 0x40&gt;;
					compatible = &quot;qcom,msm-fastrpc-rpmsg&quot;;
					qcom,glink-channels = &quot;fastrpcglink-apps-dsp&quot;;
				};

qcom,modem_glink_ssr {
					qcom,notify-edges = &lt;0x94 0x95&gt;;
					qcom,glink-channels = &quot;glink_ssr&quot;;
				};

qcom,modem_ds {
					qcom,intents = &lt;0x4000 0x02&gt;;
					qcom,glink-channels = &quot;DS&quot;;
				};
			};
		};

qcom,qmp-npu-high@9818000 {
			reg-names = &quot;msgram\0irq-reg-base&quot;;
			interrupts = &lt;0x00 0x24d 0x01&gt;;
			#mbox-cells = &lt;0x01&gt;;
			label = &quot;npu_qmp_high&quot;;
			mbox-desc-offset = &lt;0x2000&gt;;
			priority = &lt;0x01&gt;;
			compatible = &quot;qcom,qmp-mbox&quot;;
			reg = &lt;0x9818000 0x8000 0x17c00010 0x04&gt;;
			phandle = &lt;0x2a6&gt;;
			qcom,irq-mask = &lt;0x40&gt;;
		};

rpmh-regulator-mxlvl {
			compatible = &quot;qcom,rpmh-arc-regulator&quot;;
			qcom,resource-name = &quot;mx.lvl&quot;;
			mboxes = &lt;0x1b 0x00&gt;;

regulator-pm6150-s3 {
				regulator-max-microvolt = &lt;0x10000&gt;;
				regulator-min-microvolt = &lt;0x11&gt;;
				regulator-name = &quot;pm6150_s3_level&quot;;
				qcom,init-voltage-level = &lt;0x11&gt;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x1f&gt;;
			};

regulator-pm6150-s3-level-ao {
				regulator-max-microvolt = &lt;0x10000&gt;;
				regulator-min-microvolt = &lt;0x11&gt;;
				regulator-name = &quot;pm6150_s3_level_ao&quot;;
				qcom,init-voltage-level = &lt;0x11&gt;;
				qcom,set = &lt;0x01&gt;;
				phandle = &lt;0x1ce&gt;;
			};

mx-cdev-lvl {
				compatible = &quot;qcom,regulator-cooling-device&quot;;
				phandle = &lt;0x68&gt;;
				regulator-cdev-supply = &lt;0x1f&gt;;
				regulator-levels = &lt;0x101 0x01&gt;;
				#cooling-cells = &lt;0x02&gt;;
			};
		};

jtagmm@7240000 {
			clock-names = &quot;core_clk&quot;;
			reg-names = &quot;etm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			compatible = &quot;qcom,jtagv8-mm&quot;;
			qcom,coresight-jtagmm-cpu = &lt;0x13&gt;;
			reg = &lt;0x7240000 0x1000&gt;;
			phandle = &lt;0x2aa&gt;;
		};

qcom,ghd {
			qcom,config-reg = &lt;0x17e00434&gt;;
			qcom,threshold-arr = &lt;0x17e0041c&gt;;
			compatible = &quot;qcom,gladiator-hang-detect-v3&quot;;
		};

qcom,cpu-llcc-ddr-bwmon@90cd000 {
			reg-names = &quot;base&quot;;
			interrupts = &lt;0x00 0x51 0x04&gt;;
			compatible = &quot;qcom,bimc-bwmon5&quot;;
			qcom,hw-timer-hz = &lt;0x124f800&gt;;
			qcom,count-unit = &lt;0x10000&gt;;
			reg = &lt;0x90cd000 0x1000&gt;;
			phandle = &lt;0x312&gt;;
			qcom,target-dev = &lt;0xbf&gt;;
		};

funnel@6b53000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-dl-south&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b53000 0x1000&gt;;
			phandle = &lt;0x44e&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x242&gt;;
						phandle = &lt;0x231&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x243&gt;;
						phandle = &lt;0x244&gt;;
					};
				};
			};
		};

qcom,smem {
			memory-region = &lt;0x90&gt;;
			compatible = &quot;qcom,smem&quot;;
			phandle = &lt;0x2d4&gt;;
			hwlocks = &lt;0x91 0x03&gt;;
		};

qcom,msm-dai-q6-afe-loopback-tx {
			compatible = &quot;qcom,msm-dai-q6-dev&quot;;
			qcom,msm-dai-q6-dev-id = &lt;0x6001&gt;;
			phandle = &lt;0x4cc&gt;;
		};

qcom,dsi-display@2 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x524&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_sw43404_amoled_fhd_plus_cmd_display&quot;;
			phandle = &lt;0x541&gt;;
		};

funnel@6b08000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-swao&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b08000 0x1000&gt;;
			phandle = &lt;0x42d&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1f8&gt;;
						phandle = &lt;0x1f7&gt;;
					};
				};

port@1 {
					reg = &lt;0x06&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1f9&gt;;
						phandle = &lt;0x1d3&gt;;
					};
				};

port@2 {
					reg = &lt;0x07&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1fa&gt;;
						phandle = &lt;0x1fb&gt;;
					};
				};
			};
		};

qcom,npucc {
			#reset-cells = &lt;0x01&gt;;
			reg-names = &quot;cc_base&quot;;
			#clock-cells = &lt;0x01&gt;;
			npu_gdsc-supply = &lt;0x23&gt;;
			compatible = &quot;qcom,npucc-sdmmagpie\0syscon&quot;;
			reg = &lt;0x9910000 0x10000&gt;;
			phandle = &lt;0x2c&gt;;
			vdd_cx-supply = &lt;0x1d&gt;;
		};

qcom,msm-rtb {
			compatible = &quot;qcom,msm-rtb&quot;;
			qcom,rtb-size = &lt;0x100000&gt;;
		};

qcom,dsi-display@14 {
			qcom,dsi-phy-num = &lt;0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk1\0mux_pixel_clk1&quot;;
			qcom,dsi-panel = &lt;0x530&gt;;
			qcom,dsi-ctrl-num = &lt;0x01&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_nt35695b_truly_fhd_cmd_display&quot;;
			phandle = &lt;0x54d&gt;;
		};

qcom,msm-hdmi-dba-codec-rx {
			compatible = &quot;qcom,msm-hdmi-dba-codec-rx&quot;;
			phandle = &lt;0x4b9&gt;;
			qcom,dba-bridge-chip = &quot;adv7533&quot;;
		};

cti@6013000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti3&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6013000 0x1000&gt;;
			phandle = &lt;0x478&gt;;
		};

qcom,dsi-display-secondary {
			vdda-3p3-supply = &lt;0x40c&gt;;
			pinctrl-names = &quot;panel_active\0panel_suspend&quot;;
			qcom,panel-te-source = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x3c8&gt;;
			clock-names = &quot;mux_byte_clk0\0mux_pixel_clk0\0mux_byte_clk1\0mux_pixel_clk1&quot;;
			clocks = &lt;0x36a 0x06 0x36a 0x09 0x36b 0x20 0x36b 0x23&gt;;
			qcom,dsi-display-list = &lt;0x55c 0x55d&gt;;
			label = &quot;secondary&quot;;
			ibb-supply = &lt;0x2f0&gt;;
			qcom,dsi-phy = &lt;0x374 0x375&gt;;
			compatible = &quot;qcom,dsi-display&quot;;
			vddio-supply = &lt;0x408&gt;;
			pinctrl-1 = &lt;0x3c9&gt;;
			lab-supply = &lt;0x2ef&gt;;
			phandle = &lt;0x560&gt;;
			qcom,dsi-ctrl = &lt;0x372 0x373&gt;;
			qcom,platform-te-gpio = &lt;0x174 0x0b 0x00&gt;;
		};

rpmh-regulator-ldoc3 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoc3&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150l-l3 {
				regulator-max-microvolt = &lt;0x132a40&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x1174c0&gt;;
				regulator-min-microvolt = &lt;0x1174c0&gt;;
				regulator-name = &quot;pm6150l_l3&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x1a8&gt;;
			};
		};

lpi_pinctrl@62b40000 {
			qcom,num-gpios = &lt;0x20&gt;;
			clock-names = &quot;lpass_core_hw_vote&quot;;
			gpio-controller;
			clocks = &lt;0x4cd 0x00&gt;;
			qcom,lpi-offset-tbl = &lt;0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000 0x1c000 0x1d000 0x1e000 0x1f000&gt;;
			compatible = &quot;qcom,lpi-pinctrl&quot;;
			reg = &lt;0x62b40000 0x00&gt;;
			phandle = &lt;0x4f6&gt;;
			#gpio-cells = &lt;0x02&gt;;

rx_swr_clk_active {
				phandle = &lt;0x4ff&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio21&quot;;
				};

config {
					pins = &quot;gpio21&quot;;
					drive-strength = &lt;0x08&gt;;
					bias-bus-hold;
				};
			};

rx_swr_clk_sleep {
				phandle = &lt;0x501&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio21&quot;;
				};

config {
					pins = &quot;gpio21&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-bus-hold;
				};
			};

dmic01_clk_active {
				phandle = &lt;0x4f7&gt;;

mux {
					function = &quot;func1&quot;;
					pins = &quot;gpio26&quot;;
				};

config {
					pins = &quot;gpio26&quot;;
					drive-strength = &lt;0x08&gt;;
					output-high;
				};
			};

dmic01_clk_sleep {
				phandle = &lt;0x4f9&gt;;

mux {
					function = &quot;func1&quot;;
					pins = &quot;gpio26&quot;;
				};

config {
					pins = &quot;gpio26&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
					output-low;
				};
			};

lpi_wcd934x_reset_active {
				phandle = &lt;0x509&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio29&quot;;
				};

config {
					pins = &quot;gpio29&quot;;
					drive-strength = &lt;0x10&gt;;
					output-high;
				};
			};

rx_swr_data_active {
				phandle = &lt;0x500&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio22\0gpio23&quot;;
				};

config {
					pins = &quot;gpio22\0gpio23&quot;;
					drive-strength = &lt;0x08&gt;;
					bias-bus-hold;
				};
			};

dmic23_data_sleep {
				phandle = &lt;0x4fe&gt;;

mux {
					function = &quot;func1&quot;;
					pins = &quot;gpio29&quot;;
				};

config {
					pins = &quot;gpio29&quot;;
					drive-strength = &lt;0x02&gt;;
					pull-down;
					input-enable;
				};
			};

rx_swr_data_sleep {
				phandle = &lt;0x502&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio22\0gpio23&quot;;
				};

config {
					pins = &quot;gpio22\0gpio23&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-bus-hold;
				};
			};

tx_swr_data1_sleep {
				phandle = &lt;0x507&gt;;

mux {
					function = &quot;func3&quot;;
					pins = &quot;gpio19&quot;;
				};

config {
					pins = &quot;gpio19&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-bus-hold;
				};
			};

dmic01_data_sleep {
				phandle = &lt;0x4fa&gt;;

mux {
					function = &quot;func1&quot;;
					pins = &quot;gpio27&quot;;
				};

config {
					pins = &quot;gpio27&quot;;
					drive-strength = &lt;0x02&gt;;
					pull-down;
					input-enable;
				};
			};

dmic23_data_active {
				phandle = &lt;0x4fc&gt;;

mux {
					function = &quot;func1&quot;;
					pins = &quot;gpio29&quot;;
				};

config {
					pins = &quot;gpio29&quot;;
					drive-strength = &lt;0x08&gt;;
					input-enable;
				};
			};

lpi_wcd937x_reset_active {
				phandle = &lt;0x50b&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio24&quot;;
				};

config {
					pins = &quot;gpio24&quot;;
					drive-strength = &lt;0x10&gt;;
					output-high;
				};
			};

tx_swr_clk_sleep {
				phandle = &lt;0x506&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio18&quot;;
				};

config {
					pins = &quot;gpio18&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-bus-hold;
				};
			};

tx_swr_clk_active {
				phandle = &lt;0x503&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio18&quot;;
				};

config {
					pins = &quot;gpio18&quot;;
					drive-strength = &lt;0x08&gt;;
					bias-bus-hold;
				};
			};

tx_swr_data1_active {
				phandle = &lt;0x504&gt;;

mux {
					function = &quot;func3&quot;;
					pins = &quot;gpio19&quot;;
				};

config {
					pins = &quot;gpio19&quot;;
					drive-strength = &lt;0x08&gt;;
					bias-bus-hold;
				};
			};

tx_swr_data2_sleep {
				phandle = &lt;0x508&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio20&quot;;
				};

config {
					pins = &quot;gpio20&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-bus-hold;
				};
			};

dmic23_clk_sleep {
				phandle = &lt;0x4fd&gt;;

mux {
					function = &quot;func1&quot;;
					pins = &quot;gpio28&quot;;
				};

config {
					pins = &quot;gpio28&quot;;
					drive-strength = &lt;0x02&gt;;
					bias-disable;
					output-low;
				};
			};

tx_swr_data2_active {
				phandle = &lt;0x505&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio20&quot;;
				};

config {
					pins = &quot;gpio20&quot;;
					drive-strength = &lt;0x08&gt;;
					bias-bus-hold;
				};
			};

lpi_wcd937x_reset_sleep {
				phandle = &lt;0x50c&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio24&quot;;
				};

config {
					pins = &quot;gpio24&quot;;
					drive-strength = &lt;0x10&gt;;
					bias-disable;
					output-low;
				};
			};

lpi_wcd934x_reset_sleep {
				phandle = &lt;0x50a&gt;;

mux {
					function = &quot;func2&quot;;
					pins = &quot;gpio29&quot;;
				};

config {
					pins = &quot;gpio29&quot;;
					drive-strength = &lt;0x10&gt;;
					bias-disable;
					output-low;
				};
			};

dmic23_clk_active {
				phandle = &lt;0x4fb&gt;;

mux {
					function = &quot;func1&quot;;
					pins = &quot;gpio28&quot;;
				};

config {
					pins = &quot;gpio28&quot;;
					drive-strength = &lt;0x08&gt;;
					output-high;
				};
			};

dmic01_data_active {
				phandle = &lt;0x4f8&gt;;

mux {
					function = &quot;func1&quot;;
					pins = &quot;gpio27&quot;;
				};

config {
					pins = &quot;gpio27&quot;;
					drive-strength = &lt;0x08&gt;;
					input-enable;
				};
			};
		};

qcrypto@1de0000 {
			iommus = &lt;0x30 0x504 0x11 0x30 0x514 0x11&gt;;
			qcom,ce-hw-shared;
			qcom,ce-device = &lt;0x00&gt;;
			reg-names = &quot;crypto-base\0crypto-bam-base&quot;;
			qcom,use-sw-aes-xts-algo;
			qcom,clk-mgmt-sus-res;
			qcom,msm-bus,name = &quot;qcrypto-noc&quot;;
			qcom,bam-ee = &lt;0x00&gt;;
			interrupts = &lt;0x00 0x110 0x00&gt;;
			qcom,use-sw-aead-algo;
			qcom,msm-bus,num-paths = &lt;0x01&gt;;
			qcom,msm-bus,num-cases = &lt;0x02&gt;;
			compatible = &quot;qcom,qcrypto&quot;;
			qcom,no-clock-support;
			qcom,bam-pipe-pair = &lt;0x02&gt;;
			qcom,use-sw-ahash-algo;
			qcom,use-sw-aes-ccm-algo;
			reg = &lt;0x1de0000 0x20000 0x1dc4000 0x24000&gt;;
			phandle = &lt;0x2e1&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180&gt;;
			qcom,smmu-s1-enable;
			qcom,use-sw-hmac-algo;
			qcom,use-sw-aes-cbc-ecb-ctr-algo;
			qcom,ce-hw-instance = &lt;0x00&gt;;
		};

qcom,cpu0-cpu-l3-lat {
			clock-names = &quot;devfreq_clk&quot;;
			clocks = &lt;0xc0 0x00&gt;;
			governor = &quot;performance&quot;;
			compatible = &quot;devfreq-simple-dev&quot;;
			phandle = &lt;0x24&gt;;
		};

qcom,msm-pcm-voice {
			qcom,destroy-cvd;
			compatible = &quot;qcom,msm-pcm-voice&quot;;
			phandle = &lt;0x262&gt;;
		};

spi@0x884000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x17a&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			interrupts = &lt;0x00 0x25a 0x00&gt;;
			clocks = &lt;0x27 0x46 0x27 0x67 0x27 0x68&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x168&gt;;
			spi-max-frequency = &lt;0x2faf080&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,spi-geni&quot;;
			pinctrl-1 = &lt;0x17b&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0x884000 0x4000&gt;;
			phandle = &lt;0x355&gt;;
			dmas = &lt;0x165 0x00 0x01 0x01 0x40 0x00 0x165 0x01 0x01 0x01 0x40 0x00&gt;;
		};

qcom,msm-dai-tdm-pri-tx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9001&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9101&gt;;
			phandle = &lt;0x4bb&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-pri-tx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9001&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x287&gt;;
			};
		};

sdhci@8804000 {
			pinctrl-names = &quot;active\0sleep&quot;;
			qcom,large-address-bus;
			qcom,vdd-voltage-level = &lt;0x2d0370 0x2d0370&gt;;
			pinctrl-0 = &lt;0x3e5 0x3e7 0x3e9 0x3eb&gt;;
			clock-names = &quot;iface_clk\0core_clk&quot;;
			qcom,bus-width = &lt;0x04&gt;;
			reg-names = &quot;hc_mem&quot;;
			qcom,msm-bus,name = &quot;sdhc2&quot;;
			qcom,pm-qos-irq-latency = &lt;0x43 0x43&gt;;
			qcom,pm-qos-legacy-latency-us = &lt;0x43 0x43 0x43 0x43&gt;;
			interrupts = &lt;0x00 0xcc 0x00 0x00 0xde 0x00&gt;;
			qcom,clk-rates = &lt;0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xc0a4680&gt;;
			clocks = &lt;0x27 0x70 0x27 0x71&gt;;
			qcom,msm-bus,num-paths = &lt;0x02&gt;;
			qcom,msm-bus,num-cases = &lt;0x08&gt;;
			qcom,vdd-io-current-level = &lt;0x00 0x55f0&gt;;
			qcom,bus-bw-vectors-bps = &lt;0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x60152b0 0xbebc200 0xffffffff&gt;;
			qcom,pm-qos-cpu-groups = &lt;0x3f 0xc0&gt;;
			qcom,pm-qos-irq-type = &quot;affine_irq&quot;;
			vdd-supply = &lt;0x413&gt;;
			compatible = &quot;qcom,sdhci-msm-v5&quot;;
			qcom,devfreq,freq-table = &lt;0x2faf080 0xc0a4680&gt;;
			vdd-io-supply = &lt;0x410&gt;;
			pinctrl-1 = &lt;0x3e6 0x3e8 0x3ea 0x3ec&gt;;
			qcom,vdd-current-level = &lt;0x00 0xc3500&gt;;
			status = &quot;ok&quot;;
			qcom,dll-hsr-list = &lt;0x7642c 0x00 0x00 0x10800 0x80040868&gt;;
			interrupt-names = &quot;hc_irq\0pwr_irq&quot;;
			reg = &lt;0x8804000 0x1000&gt;;
			phandle = &lt;0x2d9&gt;;
			qcom,msm-bus,vectors-KBps = &lt;0x51 0x200 0x00 0x00 0x01 0x260 0x00 0x00 0x51 0x200 0x3e8 0x7d0 0x01 0x260 0x640 0x4e20 0x51 0x200 0x4e20 0x9c40 0x01 0x260 0x4e20 0x9c40 0x51 0x200 0x9c40 0x13880 0x01 0x260 0x7530 0xea60 0x51 0x200 0xea60 0x1d4c0 0x01 0x260 0x9c40 0x13880 0x51 0x200 0x13880 0x27100 0x01 0x260 0xc350 0x186a0 0x51 0x200 0x186a0 0x30d40 0x01 0x260 0xea60 0x1d4c0 0x51 0x200 0x146cc2 0x3e8000 0x01 0x260 0x146cc2 0x3e8000&gt;;
			cd-gpios = &lt;0x174 0x45 0x00&gt;;
			qcom,bus-speed-mode = &quot;SDR12\0SDR25\0SDR50\0DDR50\0SDR104&quot;;
			qcom,vdd-io-voltage-level = &lt;0x1b7740 0x2d0370&gt;;
		};

rpmh-regulator-ldof1 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldof1&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm8009-l1 {
				regulator-max-microvolt = &lt;0x13e5c0&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x10c8e0&gt;;
				regulator-min-microvolt = &lt;0x10c8e0&gt;;
				regulator-name = &quot;pm8009_l1&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x417&gt;;
			};
		};

rpmh-regulator-ldoa19 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa19&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l19 {
				regulator-max-microvolt = &lt;0x326a40&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x2cec00&gt;;
				regulator-min-microvolt = &lt;0x2cec00&gt;;
				regulator-name = &quot;pm6150_l19&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x40d&gt;;
			};
		};

cdc_dmic23_pinctrl {
			pinctrl-names = &quot;aud_active\0aud_sleep&quot;;
			pinctrl-0 = &lt;0x4fb 0x4fc&gt;;
			compatible = &quot;qcom,msm-cdc-pinctrl&quot;;
			qcom,lpi-gpios;
			pinctrl-1 = &lt;0x4fd 0x4fe&gt;;
			phandle = &lt;0x4f0&gt;;
		};

llcc-pmu@90cc000 {
			reg-names = &quot;lagg-base&quot;;
			compatible = &quot;qcom,qcom-llcc-pmu&quot;;
			reg = &lt;0x90cc000 0x300&gt;;
			phandle = &lt;0x310&gt;;
		};

cti@6010000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6010000 0x1000&gt;;
			phandle = &lt;0x1d5&gt;;
		};

qcom,msm-dai-q6-spdif-sec-tx {
			compatible = &quot;qcom,msm-dai-q6-spdif&quot;;
			qcom,msm-dai-q6-dev-id = &lt;0x5003&gt;;
			phandle = &lt;0x4cb&gt;;
		};

cti@69a6000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-wcss_cti2&quot;;
			compatible = &quot;arm,primecell&quot;;
			status = &quot;disabled&quot;;
			reg = &lt;0x69a6000 0x1000&gt;;
			phandle = &lt;0x46c&gt;;
		};

funnel@6043000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-in2&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6043000 0x1000&gt;;
			phandle = &lt;0x431&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x200&gt;;
						phandle = &lt;0x1dd&gt;;
					};
				};

port@1 {
					reg = &lt;0x02&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x201&gt;;
						phandle = &lt;0x202&gt;;
					};
				};
			};
		};

tz-log@146aa720 {
			hyplog-address-offset = &lt;0x410&gt;;
			compatible = &quot;qcom,tz-log&quot;;
			qcom,hyplog-enabled;
			reg = &lt;0x146aa720 0x3000&gt;;
			phandle = &lt;0x2e2&gt;;
			hyplog-size-offset = &lt;0x414&gt;;
		};

csr@6b0e000 {
			qcom,blk-size = &lt;0x01&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;csr-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-swao-csr&quot;;
			qcom,timestamp-support;
			compatible = &quot;qcom,coresight-csr&quot;;
			reg = &lt;0x6b0e000 0x1000&gt;;
			phandle = &lt;0x42c&gt;;
		};

qcom,qup_uart@0xa94000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			pinctrl-0 = &lt;0x194 0x195 0x196&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			clocks = &lt;0x27 0x61 0x27 0x69 0x27 0x6a&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			interrupts-extended = &lt;0x01 0x00 0x166 0x00 0x174 0x5c 0x00&gt;;
			compatible = &quot;qcom,msm-geni-serial-hs&quot;;
			pinctrl-1 = &lt;0x194 0x195 0x196&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0xa94000 0x4000&gt;;
			phandle = &lt;0x362&gt;;
			qcom,wakeup-byte = &lt;0xfd&gt;;
		};

qcom,vfe-lite0@acc4000 {
			camss-supply = &lt;0x1ae&gt;;
			clock-control-debugfs = &quot;true&quot;;
			clock-names = &quot;ife_clk_src\0ife_clk&quot;;
			reg-names = &quot;ife-lite&quot;;
			reg-cam-base = &lt;0xc4000&gt;;
			cell-index = &lt;0x02&gt;;
			interrupts = &lt;0x00 0x1b2 0x00&gt;;
			clocks = &lt;0x29 0x3f 0x29 0x3e&gt;;
			clock-cntl-level = &quot;lowsvs\0svs\0svs_l1\0turbo&quot;;
			compatible = &quot;qcom,vfe-lite175&quot;;
			src-clock-name = &quot;ife_clk_src&quot;;
			status = &quot;ok&quot;;
			interrupt-names = &quot;ife-lite&quot;;
			reg = &lt;0xacc4000 0x4000&gt;;
			regulator-names = &quot;camss&quot;;
			phandle = &lt;0x392&gt;;
			clock-rates = &lt;0x1312d000 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x23c34600 0x00&gt;;
		};

funnel@7800000 {
			arm,primecell-periphid = &lt;0x3b908&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;funnel-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-funnel-apss&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7800000 0x1000&gt;;
			phandle = &lt;0x43b&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x214&gt;;
						phandle = &lt;0x203&gt;;
					};
				};

port@7 {
					reg = &lt;0x06&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x21b&gt;;
						phandle = &lt;0x223&gt;;
					};
				};

port@5 {
					reg = &lt;0x04&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x219&gt;;
						phandle = &lt;0x221&gt;;
					};
				};

port@3 {
					reg = &lt;0x02&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x217&gt;;
						phandle = &lt;0x21f&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x215&gt;;
						phandle = &lt;0x21d&gt;;
					};
				};

port@8 {
					reg = &lt;0x07&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x21c&gt;;
						phandle = &lt;0x224&gt;;
					};
				};

port@6 {
					reg = &lt;0x05&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x21a&gt;;
						phandle = &lt;0x222&gt;;
					};
				};

port@4 {
					reg = &lt;0x03&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x218&gt;;
						phandle = &lt;0x220&gt;;
					};
				};

port@2 {
					reg = &lt;0x01&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x216&gt;;
						phandle = &lt;0x21e&gt;;
					};
				};
			};
		};

qcom,msm-pcm-afe {
			compatible = &quot;qcom,msm-pcm-afe&quot;;
			phandle = &lt;0x266&gt;;
		};

etm@7740000 {
			arm,primecell-periphid = &lt;0xbb95d&gt;;
			clock-names = &quot;apb_pclk&quot;;
			clocks = &lt;0x19 0x00&gt;;
			cpu = &lt;0x18&gt;;
			qcom,tupwr-disable;
			coresight-name = &quot;coresight-etm7&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7740000 0x1000&gt;;
			phandle = &lt;0x443&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x224&gt;;
					phandle = &lt;0x21c&gt;;
				};
			};
		};

qcom,cpu0-computemon {
			qcom,core-dev-table = &lt;0xbb800 0x478 0x130b00 0x6b8 0x16d7a8 0x826 0x1b8a00 0xb71&gt;;
			qcom,cpulist = &lt;0x11 0x12 0x13 0x14 0x15 0x16&gt;;
			compatible = &quot;qcom,arm-cpu-mon&quot;;
			phandle = &lt;0x319&gt;;
			qcom,target-dev = &lt;0xc5&gt;;
		};

qcom,mdss_dsi_k6_38_0c_0a_fhd_dsc_video {
			mi,mdss-dsi-doze-lbm-brightness-value = &lt;0x16&gt;;
			qcom,mdss-dsi-bl-min-level = &lt;0x04&gt;;
			qcom,mdss-pan-physical-width-dimension = &lt;0x45&gt;;
			qcom,mdss-dsi-panel-name = &quot;xiaomi k6 38 0c 0a fhd dsc video dsi panel&quot;;
			qcom,mdss-pan-physical-height-dimension = &lt;0x9a&gt;;
			qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
			qcom,mdss-dsi-underflow-color = &lt;0xff&gt;;
			qcom,mdss-dsi-panel-hbm-off-51-index = &lt;0x01&gt;;
			qcom,mdss-dsi-t-clk-post = &lt;0x0f&gt;;
			qcom,mdss-dsi-lane-2-state;
			qcom,mdss-dsi-bllp-eof-power-mode;
			qcom,mdss-dsi-panel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-oled-panel-video-mode;
			qcom,mdss-dsi-mode-sel-gpio-state = &quot;single_port&quot;;
			qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
			qcom,mdss-dsi-bl-max-level = &lt;0x7ff&gt;;
			qcom,bl-update-flag = &quot;delay_until_first_frame&quot;;
			qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
			qcom,dispparam-enabled;
			qcom,platform-reset-gpio = &lt;0x2ec 0x09 0x00&gt;;
			qcom,mdss-dsi-panel-peak-brightness = &lt;0x401640&gt;;
			qcom,mdss-dsi-lane-3-state;
			qcom,mdss-dsi-pan-fps-update = &quot;dfps_immediate_porch_mode_vfp&quot;;
			qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
			qcom,mdss-dsi-pan-enable-dynamic-fps;
			qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-bl-dcs-type-ss-ea;
			qcom,mdss-dsi-reset-sequence = &lt;0x00 0x01 0x01 0x0a&gt;;
			qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
			qcom,mdss-dsi-lane-0-state;
			qcom,dsi-supported-dfps-list = &lt;0x78 0x3c&gt;;
			qcom,dispparam-f4-51-ctrl-flag;
			qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
			qcom,mdss-dsi-t-clk-pre = &lt;0x37&gt;;
			qcom,mdss-dsi-panel-hdr-enabled;
			phandle = &lt;0x53e&gt;;
			qcom,mdss-dsi-bllp-power-mode;
			qcom,panel-supply-entries = &lt;0x521&gt;;
			qcom,mdss-dsi-stream = &lt;0x00&gt;;
			qcom,mdss-dsi-lp11-init;
			qcom,mdss-dsi-bl-pmic-control-type = &quot;bl_ctrl_dcs&quot;;
			qcom,mdss-dsi-panel-dc-threshold = &lt;0x1e8&gt;;
			qcom,mdss-dsi-tx-eot-append;
			qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
			qcom,mdss-dsi-border-color = &lt;0x00&gt;;
			qcom,mdss-dsi-panel-k6-dc-flag;
			mi,mdss-dsi-doze-hbm-brightness-value = &lt;0x110&gt;;
			qcom,mdss-dsi-lane-1-state;
			qcom,platform-te-gpio = &lt;0x174 0x0a 0x00&gt;;
			qcom,esd-err-irq-gpio = &lt;0x174 0x20 0x2001&gt;;
			qcom,mdss-dsi-bpp = &lt;0x18&gt;;
			qcom,mdss-brightness-max-level = &lt;0x7ff&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
					qcom,mdss-dsi-dispparam-120hz-dc-crc-setting-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-dispparam-120hz-dc-crc-setting-command = &lt;0x39010000 0x3f0 0x5a5a3900 0x00 0x2800539 0x00 0x2b100 0x39000000 0x4b0 0x1b139 0x00 0x16b101 0x01 0x01 0x10101 0x10101 0x10101 0x39000000 0x3f0 0xa5a53901 0x00 0x35101e8&gt;;
					qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-60hz-dc-crc-setting-command = &lt;0x39000000 0x3f0 0x5a5a3900 0x00 0x2800539 0x00 0x2b100 0x39000000 0x4b0 0x1b139 0x00 0x16b101 0x01 0x01 0x10101 0x10101 0x10101 0x39000000 0x3f0 0xa5a53901 0x00 0x35101e8&gt;;
					qcom,display-topology = &lt;0x01 0x01 0x01&gt;;
					qcom,mdss-dsi-dispparam-hbm-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-panel-framerate = &lt;0x78&gt;;
					qcom,mdss-dsi-h-pulse-width = &lt;0x1c&gt;;
					qcom,mdss-dsi-dispparam-bc-120hz-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-crc-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,compression-mode = &quot;dsc&quot;;
					qcom,mdss-dsi-doze-hbm-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-bc-60hz-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-doze-lbm-command = [39 01 00 00 00 00 03 51 00 16];
					qcom,mdss-dsi-dispparam-hbm-on-command = &lt;0x39010000 0x253 0xe8390100 0x03 0x5107ff39 0x1000000 0x2f70b&gt;;
					qcom,mdss-dsi-dispparam-flat-mode-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingoff-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingon-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-hbm-off-command = [39 00 00 00 00 00 02 53 28 39 01 00 00 00 00 03 51 07 ff];
					qcom,mdss-dsi-panel-height = &lt;0x960&gt;;
					qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
					qcom,mdss-dsc-block-prediction-enable;
					qcom,mdss-dsi-on-command = [05 01 00 00 14 00 02 11 00 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 03 b2 01 31 39 01 00 00 00 00 06 df 09 30 95 46 e9 39 01 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 02 9d 01 39 01 00 00 00 00 5a 9e 11 00 00 89 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 00 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 60 21 39 01 00 00 00 00 02 f7 0b 39 01 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 04 b0 00 15 f6 39 01 00 00 00 00 02 f6 f0 39 01 00 00 00 00 04 b0 00 28 f6 39 01 00 00 00 00 02 f6 f0 39 01 00 00 00 00 04 b0 00 3b f6 39 01 00 00 00 00 02 f6 f0 39 01 00 00 00 00 04 b0 00 0a f4 39 01 00 00 00 00 02 f4 98 39 01 00 00 00 00 04 b0 00 11 f4 39 01 00 00 00 00 02 f4 ee 39 01 00 00 00 00 04 b0 00 18 b2 39 01 00 00 00 00 02 b2 1c 39 01 00 00 00 00 03 fc 5a 5a 39 00 00 00 00 00 04 b0 00 11 fe 39 00 00 00 00 00 02 fe 00 39 01 00 00 00 00 03 fc a5 a5 39 01 00 00 00 00 04 b0 00 0d b2 39 01 00 00 00 00 02 b2 20 39 01 00 00 00 00 04 b0 00 0c b2 39 01 00 00 00 00 02 b2 30 39 01 00 00 00 00 02 f7 0b 39 01 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 03 fc 5a 5a 39 01 00 00 00 00 08 e1 83 00 00 81 00 f9 f8 39 01 00 00 00 00 03 ed 00 01 39 01 00 00 00 00 04 b0 00 06 f4 39 01 00 00 00 00 02 f4 1f 39 01 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 03 fc a5 a5 39 01 00 00 00 00 02 53 28 39 01 00 00 64 00 03 51 00 00 05 01 00 00 00 00 02 29 00];
					qcom,mdss-dsi-h-front-porch = &lt;0x78&gt;;
					qcom,mdss-dsi-dispparam-bc-120hz-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 60 01 39 00 00 00 00 00 02 f7 0b 39 01 00 00 00 00 03 f0 a5 a5];
					qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
					qcom,mdss-dsi-h-back-porch = &lt;0x78&gt;;
					qcom,mdss-dsi-dispparam-flat-mode-off-command = [39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 04 b0 00 88 b1 39 01 00 00 00 00 29 b1 27 0d fb 0f a4 86 01 ff 10 33 ff 10 ff 35 34 5a 0a 0a 0a 29 29 29 37 37 37 41 41 41 45 45 45 1b 2f da 18 74 80 00 00 22 39 01 00 00 00 00 03 f0 a5 a5];
					qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-hbm-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
					qcom,mdss-dsc-slice-height = &lt;0x14&gt;;
					qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-flat-mode-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
					qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
					qcom,mdss-dsi-dispparam-60hz-dc-crc-setting-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-doze-hbm-command = [39 01 00 00 00 00 03 51 01 10];
					qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20];
					qcom,mdss-dsi-panel-phy-timings = &lt;0x240a0a 0x2625090a 0x6020400&gt;;
					qcom,mdss-dsi-v-back-porch = &lt;0x0a&gt;;
					qcom,mdss-dsi-doze-lbm-command-state = &quot;dsi_lp_mode&quot;;
					qcom,default-topology-index = &lt;0x00&gt;;
					qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
					qcom,mdss-dsc-slice-per-pkt = &lt;0x02&gt;;
					qcom,mdss-dsc-scr-version = &lt;0x00&gt;;
					qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 96 00 02 10 00];
					qcom,mdss-dsi-dispparam-bc-60hz-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 60 21 39 00 00 00 00 00 02 f7 0b 39 01 00 00 00 00 03 f0 a5 a5];
					qcom,mdss-dsi-dispparam-crc-off-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 80 00 39 00 00 00 00 00 02 b1 01 39 01 00 00 00 00 03 f0 a5 a5];
					qcom,mdss-dsi-dispparam-flat-mode-on-command = [39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 04 b0 00 88 b1 39 01 00 00 00 00 29 b1 27 2d fb 0f a4 86 01 ff 10 33 ff 10 ff 35 34 5a 0a 0a 0a 29 29 29 37 37 37 41 41 41 45 45 45 1b 2f da 18 74 80 00 00 22 39 01 00 00 00 00 03 f0 a5 a5];
					qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
					qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28];
					qcom,mdss-dsi-v-front-porch = &lt;0x14&gt;;
					qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsc-version = &lt;0x11&gt;;
				};
			};
		};

tpda@78c0000 {
			arm,primecell-periphid = &lt;0x3b969&gt;;
			qcom,cmb-elem-size = &lt;0x00 0x20&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpda-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpda-llm-silver&quot;;
			compatible = &quot;arm,primecell&quot;;
			qcom,tpda-atid = &lt;0x48&gt;;
			reg = &lt;0x78c0000 0x1000&gt;;
			phandle = &lt;0x437&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x20e&gt;;
						phandle = &lt;0x205&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x20f&gt;;
						phandle = &lt;0x210&gt;;
					};
				};
			};
		};

rpmh-regulator-ldoa3 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa3&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l3 {
				regulator-max-microvolt = &lt;0x103c40&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0xec540&gt;;
				regulator-min-microvolt = &lt;0xec540&gt;;
				regulator-name = &quot;pm6150_l3&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x404&gt;;
			};
		};

qcom,msm-dai-tdm-tert-tx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9021&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9121&gt;;
			phandle = &lt;0x4bf&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-tert-tx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9021&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x28b&gt;;
			};
		};

qcom,dsi-display@22 {
			qcom,dsi-phy-num = &lt;0x00 0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x536&gt;;
			qcom,dsi-ctrl-num = &lt;0x00 0x01&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_sharp_qsync_wqhd_cmd_display&quot;;
			phandle = &lt;0x557&gt;;
		};

qcom,gdsc@ad07004 {
			qcom,poll-cfg-gdscr;
			clock-names = &quot;ahb_clk&quot;;
			qcom,support-hw-trigger;
			clocks = &lt;0x27 0x0e&gt;;
			regulator-name = &quot;bps_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xad07004 0x04&gt;;
			phandle = &lt;0x1bb&gt;;
		};

qcom,msm-dai-tdm-pri-rx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9000&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9100&gt;;
			phandle = &lt;0x4ba&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-pri-rx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9000&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x286&gt;;
			};
		};

mailbox@18220000 {
			interrupts = &lt;0x00 0x05 0x00&gt;;
			#mbox-cells = &lt;0x01&gt;;
			label = &quot;apps_rsc&quot;;
			qcom,drv-id = &lt;0x02&gt;;
			compatible = &quot;qcom,tcs-drv&quot;;
			reg = &lt;0x18220000 0x100 0x18220d00 0x3000&gt;;
			phandle = &lt;0x1b&gt;;
			qcom,tcs-config = &lt;0x02 0x02 0x00 0x03 0x01 0x03 0x03 0x01&gt;;
		};

cxip-cdev@1fed000 {
			qcom,bypass-client-list = &lt;0x3004&gt;;
			compatible = &quot;qcom,cxip-lm-cooling-device&quot;;
			qcom,thermal-client-offset = &lt;0x8000&gt;;
			reg = &lt;0x1fed000 0x8004&gt;;
			phandle = &lt;0x7b&gt;;
			#cooling-cells = &lt;0x02&gt;;
		};

qcom,msm-dai-q6-spdif-sec-rx {
			compatible = &quot;qcom,msm-dai-q6-spdif&quot;;
			qcom,msm-dai-q6-dev-id = &lt;0x5002&gt;;
			phandle = &lt;0x4ca&gt;;
		};

fingerprint_fpc {
			pinctrl-names = &quot;fpc1020_reset_reset\0fpc1020_reset_active\0fpc1020_irq_active&quot;;
			pinctrl-2 = &lt;0x586&gt;;
			pinctrl-0 = &lt;0x584&gt;;
			interrupts = &lt;0x39 0x00&gt;;
			fpc,gpio_irq = &lt;0x174 0x39 0x00&gt;;
			interrupt-parent = &lt;0x174&gt;;
			compatible = &quot;fpc,fpc1020&quot;;
			pinctrl-1 = &lt;0x585&gt;;
			status = &quot;ok&quot;;
			fpc,gpio_rst = &lt;0x174 0x3a 0x00&gt;;
			fp_vdd_vreg-supply = &lt;0x411&gt;;
		};

cti@6b07000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-swao_cti3&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b07000 0x1000&gt;;
			phandle = &lt;0x472&gt;;
		};

qcom,qmp-npu-low@9818000 {
			reg-names = &quot;msgram\0irq-reg-base&quot;;
			interrupts = &lt;0x00 0x24c 0x01&gt;;
			#mbox-cells = &lt;0x01&gt;;
			label = &quot;npu_qmp_low&quot;;
			mbox-desc-offset = &lt;0x00&gt;;
			priority = &lt;0x00&gt;;
			compatible = &quot;qcom,qmp-mbox&quot;;
			reg = &lt;0x9818000 0x8000 0x17c00010 0x04&gt;;
			phandle = &lt;0x2a5&gt;;
			qcom,irq-mask = &lt;0x20&gt;;
		};

qcom,dsi-display@0 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0\0src_byte_clk0\0src_pixel_clk0\0shadow_byte_clk0\0shadow_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x522&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,dsi-display-active;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_sw43404_amoled_video_display&quot;;
			phandle = &lt;0x53f&gt;;
		};

qmi-tmd-devices {
			compatible = &quot;qcom,qmi-cooling-devices&quot;;

adsp {
				qcom,instance-id = &lt;0x01&gt;;

adsp_vdd {
					phandle = &lt;0x6a&gt;;
					qcom,qmi-dev-name = &quot;cpuv_restriction_cold&quot;;
					#cooling-cells = &lt;0x02&gt;;
				};
			};

cdsp {
				qcom,instance-id = &lt;0x43&gt;;

cdsp_vdd {
					phandle = &lt;0x6b&gt;;
					qcom,qmi-dev-name = &quot;cpuv_restriction_cold&quot;;
					#cooling-cells = &lt;0x02&gt;;
				};
			};

modem {
				qcom,instance-id = &lt;0x00&gt;;

modem_vdd {
					phandle = &lt;0x69&gt;;
					qcom,qmi-dev-name = &quot;cpuv_restriction_cold&quot;;
					#cooling-cells = &lt;0x02&gt;;
				};

modem_proc {
					phandle = &lt;0x88&gt;;
					qcom,qmi-dev-name = &quot;modem&quot;;
					#cooling-cells = &lt;0x02&gt;;
				};

modem_pa {
					phandle = &lt;0x84&gt;;
					qcom,qmi-dev-name = &quot;pa&quot;;
					#cooling-cells = &lt;0x02&gt;;
				};

modem_skin {
					phandle = &lt;0x48a&gt;;
					qcom,qmi-dev-name = &quot;modem_skin&quot;;
					#cooling-cells = &lt;0x02&gt;;
				};

modem_current {
					phandle = &lt;0x489&gt;;
					qcom,qmi-dev-name = &quot;modem_current&quot;;
					#cooling-cells = &lt;0x02&gt;;
				};
			};
		};

qcom,smp2p_interrupt_qvrexternal_5_out {
			qcom,smem-state-names = &quot;qvrexternal-smp2p-out&quot;;
			compatible = &quot;qcom,smp2p-interrupt-qvrexternal-5-out&quot;;
			qcom,smem-states = &lt;0x1c0 0x00&gt;;
		};

qcom,dsi-display@12 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x52e&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_rm69298_truly_amoled_cmd_display&quot;;
			phandle = &lt;0x54b&gt;;
		};

tx_npl_clk {
			qcom,codec-ext-clk-src = &lt;0x08&gt;;
			#clock-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,audio-ref-clk&quot;;
			phandle = &lt;0x4e1&gt;;
			qcom,codec-lpass-clk-id = &lt;0x30d&gt;;
			qcom,codec-lpass-ext-clk-freq = &lt;0x124f800&gt;;
		};

replicator@6046000 {
			arm,primecell-periphid = &lt;0x3b909&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;replicator-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-replicator&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6046000 0x1000&gt;;
			phandle = &lt;0x41d&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1d0&gt;;
						phandle = &lt;0x1d7&gt;;
					};
				};

port@1 {
					reg = &lt;0x01&gt;;

endpoint {
						remote-endpoint = &lt;0x1d1&gt;;
						phandle = &lt;0x1d4&gt;;
					};
				};

port@2 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1d2&gt;;
						phandle = &lt;0x1d8&gt;;
					};
				};
			};
		};

qcom,cpu0-cpu-llcc-latmon {
			qcom,cachemiss-ev = &lt;0x2a&gt;;
			qcom,core-dev-table = &lt;0x1433e0 0x11e1 0x16d7a8 0x1bc6 0x1b8a00 0x23c3&gt;;
			qcom,cpulist = &lt;0x11 0x12 0x13 0x14 0x15 0x16&gt;;
			compatible = &quot;qcom,arm-memlat-mon&quot;;
			phandle = &lt;0x315&gt;;
			qcom,target-dev = &lt;0xc1&gt;;
		};

rpmh-regulator-ldoc1 {
			qcom,mode-threshold-currents = &lt;0x00 0x2710&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoc1&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150l-l1 {
				regulator-max-microvolt = &lt;0x1e4600&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x18a880&gt;;
				regulator-min-microvolt = &lt;0x18a880&gt;;
				regulator-name = &quot;pm6150l_l1&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x34&gt;;
			};
		};

tpdm@6830000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-modem-0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6830000 0x1000&gt;;
			phandle = &lt;0x427&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x1ef&gt;;
					phandle = &lt;0x1ec&gt;;
				};
			};
		};

cti@6b04000 {
			arm,primecell-periphid = &lt;0x3b966&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;cti-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-cti-swao_cti0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x6b04000 0x1000&gt;;
			phandle = &lt;0x46f&gt;;
		};

qcom,msm-compress-dsp {
			compatible = &quot;qcom,msm-compress-dsp&quot;;
			phandle = &lt;0x264&gt;;
		};

qcom,camera-flash@1 {
			cell-index = &lt;0x01&gt;;
			torch-source = &lt;0x2f6&gt;;
			switch-source = &lt;0x2fb&gt;;
			compatible = &quot;qcom,camera-flash&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0x01 0x00&gt;;
			phandle = &lt;0x570&gt;;
			flash-source = &lt;0x2f3&gt;;
		};

turing_etm0 {
			qcom,inst-id = &lt;0x0d&gt;;
			coresight-name = &quot;coresight-turing-etm0&quot;;
			compatible = &quot;qcom,coresight-remote-etm&quot;;

port {

endpoint {
					remote-endpoint = &lt;0x249&gt;;
					phandle = &lt;0x248&gt;;
				};
			};
		};

rpmh-regulator-ldoa17 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			pm6150_l17-parent-supply = &lt;0x1cf&gt;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa17&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l17 {
				regulator-max-microvolt = &lt;0x315100&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x2dc6c0&gt;;
				regulator-min-microvolt = &lt;0x2dc6c0&gt;;
				regulator-name = &quot;pm6150_l17&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0xa5&gt;;
			};
		};

tsens@c223000 {
			reg-names = &quot;tsens_srot_physical\0tsens_tm_physical&quot;;
			interrupts = &lt;0x00 0x1fb 0x00 0x00 0x1fd 0x00&gt;;
			#thermal-sensor-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,tsens24xx&quot;;
			interrupt-names = &quot;tsens-upper-lower\0tsens-critical&quot;;
			reg = &lt;0xc223000 0x08 0xc265000 0x1ff&gt;;
			phandle = &lt;0x5a&gt;;
			tsens-reinit-wa;
		};

qcom,mdss_dsi_pll@ae96a00 {
			clock-names = &quot;iface_clk&quot;;
			reg-names = &quot;pll_base\0phy_base\0gdsc_base\0dynamic_pll_base&quot;;
			cell-index = &lt;0x01&gt;;
			clocks = &lt;0x2a 0x01&gt;;
			#clock-cells = &lt;0x01&gt;;
			label = &quot;MDSS DSI 1 PLL&quot;;
			compatible = &quot;qcom,mdss_dsi_pll_10nm&quot;;
			gdsc-supply = &lt;0xcb&gt;;
			clock-rate = &lt;0x00&gt;;
			reg = &lt;0xae96a00 0x1e0 0xae96400 0x800 0xaf03000 0x08 0xae96200 0x100&gt;;
			phandle = &lt;0x36b&gt;;

qcom,platform-supply-entries {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

qcom,cam-req-mgr {
			compatible = &quot;qcom,cam-req-mgr&quot;;
			status = &quot;ok&quot;;
		};

qcom,msm-dai-tdm-tert-rx {
			qcom,msm-cpudai-tdm-clk-rate = &lt;0x177000&gt;;
			qcom,msm-cpudai-tdm-data-out = &lt;0x00&gt;;
			qcom,msm-cpudai-tdm-data-delay = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-group-port-id = &lt;0x9020&gt;;
			qcom,msm-cpudai-tdm-group-num-ports = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-invert-sync = &lt;0x01&gt;;
			compatible = &quot;qcom,msm-dai-tdm&quot;;
			qcom,msm-cpudai-tdm-group-id = &lt;0x9120&gt;;
			phandle = &lt;0x4be&gt;;
			qcom,msm-cpudai-tdm-sync-src = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-clk-internal = &lt;0x01&gt;;
			qcom,msm-cpudai-tdm-sync-mode = &lt;0x01&gt;;

qcom,msm-dai-q6-tdm-tert-rx-0 {
				qcom,msm-cpudai-tdm-dev-id = &lt;0x9020&gt;;
				qcom,msm-cpudai-tdm-data-align = &lt;0x00&gt;;
				compatible = &quot;qcom,msm-dai-q6-tdm&quot;;
				phandle = &lt;0x28a&gt;;
			};
		};

spi@0xa84000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x199&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			reg-names = &quot;se_phys&quot;;
			interrupts = &lt;0x00 0x162 0x00&gt;;
			clocks = &lt;0x27 0x59 0x27 0x69 0x27 0x6a&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x182&gt;;
			spi-max-frequency = &lt;0x2faf080&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,spi-geni&quot;;
			pinctrl-1 = &lt;0x19a&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0xa84000 0x4000&gt;;
			phandle = &lt;0x364&gt;;
			dmas = &lt;0x183 0x00 0x01 0x01 0x40 0x00 0x183 0x01 0x01 0x01 0x40 0x00&gt;;
		};

qcom,msm-pcm-hostless {
			compatible = &quot;qcom,msm-pcm-hostless&quot;;
			phandle = &lt;0x265&gt;;
		};

restart@c264000 {
			reg-names = &quot;pshold-base\0tcsr-boot-misc-detect&quot;;
			compatible = &quot;qcom,pshold&quot;;
			reg = &lt;0xc264000 0x04 0x1fd3000 0x04&gt;;
		};

audio_ext_clk {
			pinctrl-names = &quot;active\0sleep&quot;;
			pinctrl-0 = &lt;0x2e7&gt;;
			clock-names = &quot;osr_clk&quot;;
			qcom,audio-ref-clk-gpio = &lt;0x2e6 0x08 0x00&gt;;
			qcom,codec-ext-clk-src = &lt;0x00&gt;;
			clocks = &lt;0xa9&gt;;
			#clock-cells = &lt;0x01&gt;;
			qcom,use-pinctrl = &lt;0x01&gt;;
			qcom,node_has_rpm_clock;
			compatible = &quot;qcom,audio-ref-clk&quot;;
			pmic-clock-names = &quot;pm6150_div_clk1&quot;;
			pinctrl-1 = &lt;0x2e7&gt;;
			status = &quot;disabled&quot;;
			phandle = &lt;0x511&gt;;
		};

etm@7040000 {
			arm,primecell-periphid = &lt;0xbb95d&gt;;
			clock-names = &quot;apb_pclk&quot;;
			clocks = &lt;0x19 0x00&gt;;
			cpu = &lt;0x11&gt;;
			qcom,tupwr-disable;
			coresight-name = &quot;coresight-etm0&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7040000 0x1000&gt;;
			phandle = &lt;0x43c&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x21d&gt;;
					phandle = &lt;0x215&gt;;
				};
			};
		};

mailbox@17c00000 {
			#mbox-cells = &lt;0x01&gt;;
			compatible = &quot;qcom,sm8150-apcs-hmss-global&quot;;
			reg = &lt;0x17c00000 0x1000&gt;;
			phandle = &lt;0x93&gt;;
		};

syscon@5091540 {
			compatible = &quot;syscon&quot;;
			reg = &lt;0x5091540 0x04&gt;;
			phandle = &lt;0xcc&gt;;
		};

qcom,msm-ext-disp {
			compatible = &quot;qcom,msm-ext-disp&quot;;
			phandle = &lt;0x1ab&gt;;

qcom,msm-ext-disp-audio-codec-rx {
				compatible = &quot;qcom,msm-ext-disp-audio-codec-rx&quot;;
				phandle = &lt;0x376&gt;;
			};
		};

qcom,gdsc@ab00874 {
			clock-names = &quot;ahb_clk&quot;;
			qcom,support-hw-trigger;
			clocks = &lt;0x27 0x9b&gt;;
			regulator-name = &quot;mvs0_gdsc&quot;;
			compatible = &quot;qcom,gdsc&quot;;
			status = &quot;ok&quot;;
			reg = &lt;0xab00874 0x04&gt;;
			phandle = &lt;0x1a1&gt;;
		};

qcom,msm-pcm-low-latency {
			qcom,msm-pcm-dsp-id = &lt;0x01&gt;;
			qcom,latency-level = &quot;regular&quot;;
			compatible = &quot;qcom,msm-pcm-dsp&quot;;
			phandle = &lt;0x25f&gt;;
			qcom,msm-pcm-low-latency;
		};

jtagmm@7140000 {
			clock-names = &quot;core_clk&quot;;
			reg-names = &quot;etm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			compatible = &quot;qcom,jtagv8-mm&quot;;
			qcom,coresight-jtagmm-cpu = &lt;0x12&gt;;
			reg = &lt;0x7140000 0x1000&gt;;
			phandle = &lt;0x2a9&gt;;
		};

ipa_smmu_wlan {
			iommus = &lt;0x30 0x521 0x00&gt;;
			qcom,smmu-s1-bypass;
			qcom,additional-mapping = &lt;0x1e60000 0x1e60000 0x80000&gt;;
			compatible = &quot;qcom,ipa-smmu-wlan-cb&quot;;
			phandle = &lt;0x31d&gt;;
		};

rx_swr_clk_data_pinctrl {
			pinctrl-names = &quot;aud_active\0aud_sleep&quot;;
			pinctrl-0 = &lt;0x4ff 0x500&gt;;
			compatible = &quot;qcom,msm-cdc-pinctrl&quot;;
			qcom,lpi-gpios;
			pinctrl-1 = &lt;0x501 0x502&gt;;
			phandle = &lt;0x4e5&gt;;
		};

qcom,msm-pri-auxpcm {
			qcom,msm-cpudai-auxpcm-quant = &lt;0x02 0x02&gt;;
			qcom,msm-cpudai-auxpcm-frame = &lt;0x05 0x04&gt;;
			qcom,msm-cpudai-auxpcm-sync = &lt;0x01 0x01&gt;;
			qcom,msm-auxpcm-interface = &quot;primary&quot;;
			qcom,msm-cpudai-auxpcm-slot-mapping = &lt;0x01 0x01&gt;;
			qcom,msm-cpudai-auxpcm-data = &lt;0x00 0x00&gt;;
			qcom,msm-cpudai-afe-clk-ver = &lt;0x02&gt;;
			qcom,msm-cpudai-auxpcm-num-slots = &lt;0x01 0x01&gt;;
			compatible = &quot;qcom,msm-auxpcm-dev&quot;;
			qcom,msm-cpudai-auxpcm-mode = &lt;0x00 0x00&gt;;
			phandle = &lt;0x271&gt;;
			qcom,msm-cpudai-auxpcm-pcm-clk-rate = &lt;0x1f4000 0x1f4000&gt;;
		};

rpmh-regulator-ldoa1 {
			qcom,mode-threshold-currents = &lt;0x00 0x01&gt;;
			qcom,regulator-type = &quot;pmic5-ldo&quot;;
			compatible = &quot;qcom,rpmh-vrm-regulator&quot;;
			qcom,resource-name = &quot;ldoa1&quot;;
			mboxes = &lt;0x1b 0x00&gt;;
			qcom,supported-modes = &lt;0x02 0x04&gt;;

regulator-pm6150-l1 {
				regulator-max-microvolt = &lt;0x13e5c0&gt;;
				qcom,init-mode = &lt;0x02&gt;;
				qcom,init-voltage = &lt;0x10b940&gt;;
				regulator-min-microvolt = &lt;0x10b940&gt;;
				regulator-name = &quot;pm6150_l1&quot;;
				qcom,set = &lt;0x03&gt;;
				phandle = &lt;0x402&gt;;
			};
		};

tpdm@7860000 {
			arm,primecell-periphid = &lt;0x3b968&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpdm-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpdm-apss&quot;;
			compatible = &quot;arm,primecell&quot;;
			reg = &lt;0x7860000 0x1000&gt;;
			phandle = &lt;0x436&gt;;

port {

endpoint {
					remote-endpoint = &lt;0x20d&gt;;
					phandle = &lt;0x20c&gt;;
				};
			};
		};

qcom,dsi-display@9 {
			qcom,dsi-phy-num = &lt;0x00 0x01&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x52b&gt;;
			qcom,dsi-ctrl-num = &lt;0x00 0x01&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_dual_sharp_wqhd_video_display&quot;;
			phandle = &lt;0x548&gt;;
		};

qcom,mdss_dsi_g7b_37_02_0a_dsc_video {
			qcom,mdss-pan-physical-width-dimension = &lt;0x46&gt;;
			qcom,mdss-dsi-panel-name = &quot;xiaomi 37 02 0a video mode dsc dsi panel&quot;;
			qcom,mdss-pan-physical-height-dimension = &lt;0x9a&gt;;
			qcom,mdss-dsi-color-order = &quot;rgb_swap_rgb&quot;;
			qcom,mdss-dsi-underflow-color = &lt;0x00&gt;;
			qcom,mdss-dsi-t-clk-post = &lt;0x0e&gt;;
			qcom,mdss-dsi-lane-2-state;
			qcom,mdss-dsi-bllp-eof-power-mode;
			qcom,mdss-dsi-panel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-pan-enable-smart-fps;
			qcom,mdss-dsi-mdp-trigger = &quot;none&quot;;
			qcom,mdss-dsi-panel-max-luminance = &lt;0x0f 0x20&gt;;
			qcom,bl-update-flag = &quot;delay_until_first_frame&quot;;
			qcom,mdss-dsi-panel-blackness-level = &lt;0xc9e&gt;;
			qcom,mdss-dsi-panel-xy-coordinate = &lt;0x0f 0x18&gt;;
			qcom,mdss-dsi-qsync-min-refresh-rate = &lt;0x3c&gt;;
			qcom,mdss-dsi-panel-max-luminance-valid = &lt;0x01 0x01&gt;;
			qcom,dispparam-enabled;
			qcom,mdss-dsi-panel-peak-brightness = &lt;0x401640&gt;;
			qcom,mdss-dsi-lane-3-state;
			qcom,mdss-dsi-pan-fps-update = &quot;dfps_immediate_porch_mode_vfp&quot;;
			qcom,mdss-dsi-panel-hdr-color-primaries = &lt;0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8&gt;;
			qcom,mdss-dsi-pan-enable-dynamic-fps;
			qcom,mdss-dsi-virtual-channel-id = &lt;0x00&gt;;
			qcom,mdss-dsi-reset-sequence = &lt;0x01 0x05 0x00 0x01 0x01 0x0a&gt;;
			qcom,mdss-dsi-panel-type = &quot;dsi_video_mode&quot;;
			qcom,is-tddi-flag;
			qcom,mdss-dsi-lane-0-state;
			qcom,dsi-supported-dfps-list = &lt;0x78 0x5a 0x3c 0x32 0x1e&gt;;
			qcom,mdss-dsi-dma-trigger = &quot;trigger_sw&quot;;
			qcom,mdss-panel-on-dimming-delay = &lt;0xc8&gt;;
			qcom,mdss-dsi-t-clk-pre = &lt;0x34&gt;;
			qcom,mdss-dsi-panel-hdr-enabled;
			qcom,cont-splash-enabled;
			qcom,mdss-dsi-panel-model = &quot;xiaomi 37 02 0a VIDEO PANEL&quot;;
			phandle = &lt;0x534&gt;;
			qcom,mdss-dsi-bllp-power-mode;
			qcom,mdss-dsi-stream = &lt;0x00&gt;;
			qcom,mdss-dsi-lp11-init;
			qcom,mdss-dsi-tx-eot-append;
			qcom,mdss-dsi-traffic-mode = &quot;burst_mode&quot;;
			qcom,mdss-dsi-border-color = &lt;0x00&gt;;
			qcom,mdss-dsi-lane-1-state;
			qcom,esd-err-irq-gpio = &lt;0x174 0x20 0x2002&gt;;
			qcom,mdss-dsi-bpp = &lt;0x18&gt;;
			qcom,disp-panel-offon-mode-enabled;
			qcom,mdss-brightness-max-level = &lt;0xfff&gt;;

qcom,mdss-dsi-display-timings {

timing@0 {
					qcom,mdss-dsi-dispparam-cabcstillon-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-v-bottom-border = &lt;0x00&gt;;
					qcom,display-topology = &lt;0x01 0x01 0x01&gt;;
					qcom,mdss-dsi-panel-framerate = &lt;0x78&gt;;
					qcom,mdss-dsi-h-pulse-width = &lt;0x0c&gt;;
					qcom,mdss-dsi-dispparam-xy-coordinate-command = [15 01 00 00 00 00 02 ff 10 06 01 00 01 05 00 02 a1 00];
					qcom,mdss-dsi-read-lockdown-info-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command = [39 01 00 00 00 00 03 51 0d b5];
					qcom,mdss-dsi-dispparam-xy-coordinate-command-state = &quot;dsi_hs_mode&quot;;
					qcom,compression-mode = &quot;dsc&quot;;
					qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-cabcmovieon-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-displayoff-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingoff-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingon-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-lcd-hbm-off-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-cabcmovieon-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 03];
					qcom,mdss-dsi-panel-height = &lt;0x960&gt;;
					qcom,mdss-dsc-bit-per-pixel = &lt;0x08&gt;;
					qcom,mdss-dsi-panel-xy-coordinate = &lt;0x0f 0x18&gt;;
					qcom,mdss-dsc-block-prediction-enable;
					qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 23 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 00 80 15 00 00 00 00 00 02 07 00 15 00 00 00 00 00 02 08 01 15 00 00 00 00 00 02 09 45 15 01 00 00 00 00 02 ff 20 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 01 66 15 00 00 00 00 00 02 32 4d 15 00 00 00 00 00 02 69 d1 15 00 00 00 00 00 02 f2 64 15 00 00 00 00 00 02 f4 64 15 00 00 00 00 00 02 f6 64 15 00 00 00 00 00 02 f9 64 15 01 00 00 00 00 02 ff 26 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 81 0e 15 00 00 00 00 00 02 84 03 15 00 00 00 00 00 02 86 03 15 00 00 00 00 00 02 88 07 15 01 00 00 00 00 02 ff 27 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 e3 01 15 00 00 00 00 00 02 e4 ec 15 00 00 00 00 00 02 e5 02 15 00 00 00 00 00 02 e6 e3 15 00 00 00 00 00 02 e7 01 15 00 00 00 00 00 02 e8 ec 15 00 00 00 00 00 02 e9 02 15 00 00 00 00 00 02 ea 22 15 00 00 00 00 00 02 eb 03 15 00 00 00 00 00 02 ec 32 15 00 00 00 00 00 02 ed 02 15 00 00 00 00 00 02 ee 22 15 01 00 00 00 00 02 ff 2a 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 0c 04 15 00 00 00 00 00 02 0f 01 15 00 00 00 00 00 02 11 e0 15 00 00 00 00 00 02 15 0e 15 00 00 00 00 00 02 16 78 15 00 00 00 00 00 02 19 0d 15 00 00 00 00 00 02 1a f4 15 00 00 00 00 00 02 37 6e 15 00 00 00 00 00 02 88 76 15 01 00 00 00 00 02 ff 2c 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 4d 1e 15 00 00 00 00 00 02 4e 04 15 00 00 00 00 00 02 4f 00 15 00 00 00 00 00 02 9d 1e 15 00 00 00 00 00 02 9e 04 15 00 00 00 00 00 02 9f 17 15 01 00 00 00 00 02 ff f0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 ff e0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 25 00 15 00 00 00 00 00 02 4e 02 15 00 00 00 00 00 02 85 02 15 01 00 00 00 00 02 ff d0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 09 ad 15 01 00 00 00 00 02 ff 20 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 f8 64 15 01 00 00 00 00 02 ff 2a 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 1a f0 15 00 00 00 00 00 02 30 5e 15 00 00 00 00 00 02 31 ca 15 00 00 00 00 00 02 34 fe 15 00 00 00 00 00 02 35 35 15 00 00 00 00 00 02 36 a2 15 00 00 00 00 00 02 37 f8 15 00 00 00 00 00 02 38 37 15 00 00 00 00 00 02 39 a0 15 00 00 00 00 00 02 3a 5e 15 00 00 00 00 00 02 53 d7 15 00 00 00 00 00 02 88 72 15 01 00 00 00 00 02 ff 24 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 c6 c0 15 01 00 00 00 00 02 ff 23 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 00 80 15 00 00 00 00 00 02 01 84 15 00 00 00 00 00 02 05 2d 15 00 00 00 00 00 02 06 00 15 00 00 00 00 00 02 07 00 15 00 00 00 00 00 02 08 01 15 00 00 00 00 00 02 09 45 15 00 00 00 00 00 02 11 01 15 00 00 00 00 00 02 12 95 15 00 00 00 00 00 02 15 68 15 00 00 00 00 00 02 16 0b 15 00 00 00 00 00 02 29 0a 15 00 00 00 00 00 02 30 ff 15 00 00 00 00 00 02 31 fe 15 00 00 00 00 00 02 32 fd 15 00 00 00 00 00 02 33 fb 15 00 00 00 00 00 02 34 f8 15 00 00 00 00 00 02 35 f5 15 00 00 00 00 00 02 36 f3 15 00 00 00 00 00 02 37 f2 15 00 00 00 00 00 02 38 f2 15 00 00 00 00 00 02 39 f2 15 00 00 00 00 00 02 3a ef 15 00 00 00 00 00 02 3b ec 15 00 00 00 00 00 02 3d e9 15 00 00 00 00 00 02 3f e5 15 00 00 00 00 00 02 40 e5 15 00 00 00 00 00 02 41 e5 15 00 00 00 00 00 02 2a 13 15 00 00 00 00 00 02 45 ff 15 00 00 00 00 00 02 46 f4 15 00 00 00 00 00 02 47 e7 15 00 00 00 00 00 02 48 da 15 00 00 00 00 00 02 49 cd 15 00 00 00 00 00 02 4a c0 15 00 00 00 00 00 02 4b b3 15 00 00 00 00 00 02 4c b2 15 00 00 00 00 00 02 4d b2 15 00 00 00 00 00 02 4e b2 15 00 00 00 00 00 02 4f 99 15 00 00 00 00 00 02 50 80 15 00 00 00 00 00 02 51 68 15 00 00 00 00 00 02 52 66 15 00 00 00 00 00 02 53 66 15 00 00 00 00 00 02 54 66 15 00 00 00 00 00 02 2b 0e 15 00 00 00 00 00 02 58 ff 15 00 00 00 00 00 02 59 fb 15 00 00 00 00 00 02 5a f7 15 00 00 00 00 00 02 5b f3 15 00 00 00 00 00 02 5c ef 15 00 00 00 00 00 02 5d e3 15 00 00 00 00 00 02 5e da 15 00 00 00 00 00 02 5f d8 15 00 00 00 00 00 02 60 d8 15 00 00 00 00 00 02 61 d8 15 00 00 00 00 00 02 62 cb 15 00 00 00 00 00 02 63 bf 15 00 00 00 00 00 02 64 b3 15 00 00 00 00 00 02 65 b2 15 00 00 00 00 00 02 66 b2 15 00 00 00 00 00 02 67 b2 15 01 00 00 00 00 02 ff c0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 9c 11 15 00 00 00 00 00 02 9d 11 15 01 00 00 00 00 02 ff f0 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 9c 00 15 01 00 00 00 00 02 ff 10 15 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 03 51 0b 6c 15 00 00 00 00 00 02 53 24 15 01 00 00 46 00 02 11 00 15 01 00 00 00 00 02 29 00 15 01 00 00 00 00 02 ff 27 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 3f 01 15 00 00 00 00 00 02 43 08 15 00 00 00 00 00 02 40 25 15 01 00 00 00 00 02 ff e0 15 00 00 00 00 00 02 35 82 15 01 00 00 00 00 02 ff 10];
					qcom,mdss-dsi-h-front-porch = &lt;0x28&gt;;
					qcom,mdss-dsc-slice-width = &lt;0x21c&gt;;
					qcom,mdss-dsi-h-back-porch = &lt;0x28&gt;;
					qcom,mdss-dsi-dispparam-cabcstillon-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 02];
					qcom,mdss-dsi-dispparam-cabcuion-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 01];
					qcom,mdss-dsi-h-left-border = &lt;0x00&gt;;
					qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command = [39 01 00 00 00 00 03 51 0e 8c];
					qcom,mdss-dsi-dispparam-lcd-hbm-off-command = [39 01 00 00 00 00 03 51 0b 6c];
					qcom,mdss-dsi-h-right-border = &lt;0x00&gt;;
					qcom,mdss-dsc-slice-height = &lt;0x14&gt;;
					qcom,mdss-dsi-h-sync-skew = &lt;0x00&gt;;
					qcom,mdss-dsi-panel-width = &lt;0x438&gt;;
					qcom,mdss-dsi-v-pulse-width = &lt;0x02&gt;;
					qcom,mdss-dsi-dispparam-cabcoff-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00];
					qcom,mdss-dsi-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 24];
					qcom,mdss-dsi-panel-phy-timings = &lt;0x1c0707 0x23210707 0x5020400&gt;;
					qcom,mdss-dsi-v-back-porch = &lt;0x1e&gt;;
					qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command-state = &quot;dsi_lp_mode&quot;;
					qcom,default-topology-index = &lt;0x00&gt;;
					qcom,mdss-dsi-v-top-border = &lt;0x00&gt;;
					qcom,mdss-dsc-slice-per-pkt = &lt;0x02&gt;;
					qcom,mdss-dsi-h-sync-pulse = &lt;0x01&gt;;
					qcom,mdss-dsc-scr-version = &lt;0x00&gt;;
					qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 27 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 3f 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 28 00 15 01 00 00 46 00 02 10 00];
					qcom,mdss-dsi-displayon-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-dispparam-cabcuion-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsc-bit-per-component = &lt;0x08&gt;;
					qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c];
					qcom,mdss-dsi-v-front-porch = &lt;0x20&gt;;
					qcom,mdss-dsi-displayoff-command = [15 01 00 00 20 00 02 28 00];
					qcom,mdss-dsi-displayon-command = [15 01 00 00 14 00 02 29 00];
					qcom,mdss-dsi-read-lockdown-info-command = [15 01 00 00 00 00 02 ff 21 06 01 00 00 00 00 01 f1];
					qcom,mdss-dsi-dispparam-cabcoff-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsi-off-command-state = &quot;dsi_hs_mode&quot;;
					qcom,mdss-dsc-version = &lt;0x11&gt;;
				};
			};
		};

i2c@0x884000 {
			pinctrl-names = &quot;default\0sleep&quot;;
			#address-cells = &lt;0x01&gt;;
			pinctrl-0 = &lt;0x169&gt;;
			clock-names = &quot;se-clk\0m-ahb\0s-ahb&quot;;
			interrupts = &lt;0x00 0x25a 0x00&gt;;
			clocks = &lt;0x27 0x46 0x27 0x67 0x27 0x68&gt;;
			#size-cells = &lt;0x00&gt;;
			qcom,wrapper-core = &lt;0x168&gt;;
			dma-names = &quot;tx\0rx&quot;;
			compatible = &quot;qcom,i2c-geni&quot;;
			pinctrl-1 = &lt;0x16a&gt;;
			status = &quot;disabled&quot;;
			reg = &lt;0x884000 0x4000&gt;;
			phandle = &lt;0x34e&gt;;
			dmas = &lt;0x165 0x00 0x01 0x03 0x40 0x00 0x165 0x01 0x01 0x03 0x40 0x00&gt;;
		};

tpda@6b01000 {
			arm,primecell-periphid = &lt;0x3b969&gt;;
			qcom,cmb-elem-size = &lt;0x00 0x40&gt;;
			clock-names = &quot;apb_pclk&quot;;
			reg-names = &quot;tpda-base&quot;;
			clocks = &lt;0x19 0x00&gt;;
			coresight-name = &quot;coresight-tpda-swao&quot;;
			qcom,dsb-elem-size = &lt;0x01 0x20&gt;;
			compatible = &quot;arm,primecell&quot;;
			qcom,tpda-atid = &lt;0x47&gt;;
			reg = &lt;0x6b01000 0x1000&gt;;
			phandle = &lt;0x42e&gt;;

ports {
				#address-cells = &lt;0x01&gt;;
				#size-cells = &lt;0x00&gt;;

port@0 {
					reg = &lt;0x00&gt;;

endpoint {
						remote-endpoint = &lt;0x1fb&gt;;
						phandle = &lt;0x1fa&gt;;
					};
				};

port@1 {
					reg = &lt;0x00&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1fc&gt;;
						phandle = &lt;0x1fe&gt;;
					};
				};

port@2 {
					reg = &lt;0x01&gt;;

endpoint {
						slave-mode;
						remote-endpoint = &lt;0x1fd&gt;;
						phandle = &lt;0x1ff&gt;;
					};
				};
			};
		};

qcom,camcc {
			#reset-cells = &lt;0x01&gt;;
			reg-names = &quot;cc_base&quot;;
			#clock-cells = &lt;0x01&gt;;
			vdd_mx-supply = &lt;0x1f&gt;;
			compatible = &quot;qcom,camcc-sdmmagpie\0syscon&quot;;
			reg = &lt;0xad00000 0x10000&gt;;
			phandle = &lt;0x29&gt;;
			vdd_cx-supply = &lt;0x1d&gt;;
		};

qcom,dsi-display@20 {
			qcom,dsi-phy-num = &lt;0x00&gt;;
			qcom,dsi-select-clocks = &quot;mux_byte_clk0\0mux_pixel_clk0&quot;;
			qcom,dsi-panel = &lt;0x534&gt;;
			qcom,dsi-ctrl-num = &lt;0x00&gt;;
			qcom,display-type = &quot;primary&quot;;
			label = &quot;dsi_g7b_37_02_0a_video_display&quot;;
			phandle = &lt;0x556&gt;;
		};

slim@62dc0000 {
			reg-names = &quot;slimbus_physical\0slimbus_bam_physical&quot;;
			cell-index = &lt;0x01&gt;;
			qcom,iommu-s1-bypass;
			interrupts = &lt;0x00 0xa3 0x00 0x00 0xa4 0x00&gt;;
			qcom,apps-ch-pipes = &lt;0x7c0000&gt;;
			compatible = &quot;qcom,slim-ngd&quot;;
			status = &quot;disabled&quot;;
			interrupt-names = &quot;slimbus_irq\0slimbus_bam_irq&quot;;
			reg = &lt;0x62dc0000 0x2c000 0x62d84000 0x2a000&gt;;
			phandle = &lt;0x2b5&gt;;
			qcom,ea-pc = &lt;0x300&gt;;

qcom,iommu_slim_ctrl_cb {
				iommus = &lt;0x30 0x1be6 0x08 0x30 0x1bed 0x02 0x30 0x1bf0 0x01&gt;;
				compatible = &quot;qcom,iommu-slim-ctrl-cb&quot;;
				phandle = &lt;0x2b6&gt;;
			};

tavil_codec {
				cdc-buck-sido-supply = &lt;0x512&gt;;
				qcom,cdc-buck-sido-voltage = &lt;0x1b7740 0x1b7740&gt;;
				qcom,cdc-vddpx-1-voltage = &lt;0x1b7740 0x1b7740&gt;;
				qcom,cdc-vdd-mic-bias-voltage = &lt;0x324b00 0x324b00&gt;;
				qcom,cdc-buck-sido-current = &lt;0x7a120&gt;;
				qcom,cdc-vddpx-1-current = &lt;0x2710&gt;;
				qcom,cdc-vdd-mic-bias-current = &lt;0x76c0 0xf4241&gt;;
				qcom,wcd-rst-gpio-node = &lt;0x510&gt;;
				qcom,wdsp-cmpnt-dev-name = &quot;tavil_codec&quot;;
				clock-names = &quot;wcd_clk&quot;;
				cdc-vdd-tx-h-supply = &lt;0x512&gt;;
				elemental-addr = [00 01 50 02 17 02];
				qcom,cdc-micbias2-mv = &lt;0x708&gt;;
				interrupts = &lt;0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f&gt;;
				clocks = &lt;0x511 0x00&gt;;
				cdc-vdd-buck-supply = &lt;0x512&gt;;
				qcom,cdc-mclk-clk-rate = &lt;0x927c00&gt;;
				cdc-vdd-rx-h-supply = &lt;0x512&gt;;
				qcom,cdc-mad-dmic-rate = &lt;0x927c0&gt;;
				interrupt-parent = &lt;0x50f&gt;;
				qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02];
				qcom,cdc-static-supplies = &quot;cdc-vdd-buck\0cdc-buck-sido\0cdc-vdd-tx-h\0cdc-vdd-rx-h\0cdc-vddpx-1&quot;;
				qcom,cdc-vdd-buck-voltage = &lt;0x1b7740 0x1b7740&gt;;
				compatible = &quot;qcom,tavil-slim-pgd&quot;;
				qcom,cdc-vdd-tx-h-voltage = &lt;0x1b7740 0x1b7740&gt;;
				qcom,cdc-vdd-buck-current = &lt;0x91050&gt;;
				qcom,cdc-micbias4-mv = &lt;0x708&gt;;
				cdc-vdd-mic-bias-supply = &lt;0x415&gt;;
				qcom,cdc-vdd-tx-h-current = &lt;0x61a8&gt;;
				qcom,cdc-micbias1-mv = &lt;0x708&gt;;
				status = &quot;disabled&quot;;
				cdc-vddpx-1-supply = &lt;0x512&gt;;
				qcom,cdc-dmic-sample-rate = &lt;0x493e00&gt;;
				phandle = &lt;0x50d&gt;;
				qcom,vreg-micb-supply = &lt;0x415&gt;;
				qcom,cdc-vdd-rx-h-voltage = &lt;0x1b7740 0x1b7740&gt;;
				qcom,cdc-on-demand-supplies = &quot;cdc-vdd-mic-bias&quot;;
				qcom,cdc-vdd-rx-h-current = &lt;0x61a8&gt;;
				qcom,cdc-slim-ifd = &quot;tavil-slim-ifd&quot;;
				qcom,cdc-micbias3-mv = &lt;0x708&gt;;

wcd_spi {
					qcom,chip-select = &lt;0x00&gt;;
					qcom,master-bus-num = &lt;0x00&gt;;
					qcom,mem-base-addr = &lt;0x100000&gt;;
					qcom,max-frequency = &lt;0x16e3600&gt;;
					compatible = &quot;qcom,wcd-spi-v2&quot;;
					phandle = &lt;0x50e&gt;;
				};
			};

msm_dai_slim {
				elemental-addr = [ff ff ff fe 17 02];
				compatible = &quot;qcom,msm-dai-slim&quot;;
				status = &quot;disabled&quot;;
				phandle = &lt;0x2b7&gt;;
			};
		};
	};

psci {
		method = &quot;smc&quot;;
		compatible = &quot;arm,psci-1.0&quot;;
	};

aliases {
		spi2 = &quot;/soc/spi@0xa88000&quot;;
		sdhc2 = &quot;/soc/sdhci@8804000&quot;;
		i2c1 = &quot;/soc/i2c@0xa84000&quot;;
		swr2 = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/tx-macro@62ec0000/tx_swr_master&quot;;
		spi0 = &quot;/soc/spi@0x880000&quot;;
		swr0 = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/wsa-macro@62f00000/wsa_swr_master&quot;;
		hsuart0 = &quot;/soc/qcom,qup_uart@0x88c000&quot;;
		i2c2 = &quot;/soc/i2c@0xa8c000&quot;;
		spi1 = &quot;/soc/spi@0x890000&quot;;
		sdhc1 = &quot;/soc/sdhci@7c4000&quot;;
		i2c0 = &quot;/soc/i2c@0x888000&quot;;
		swr1 = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/rx-macro@62ee0000/rx_swr_master&quot;;
		ufshc1 = &quot;/soc/ufshc@1d84000&quot;;
		serial0 = &quot;/soc/qcom,qup_uart@0xa88000&quot;;
	};

firmware {
		phandle = &lt;0x4d6&gt;;

android {
			compatible = &quot;android,firmware&quot;;

fstab {
				compatible = &quot;android,fstab&quot;;

vendor {
					fsmgr_flags = &quot;wait,avb&quot;;
					mnt_flags = &quot;ro,barrier=1,discard&quot;;
					dev = &quot;/dev/block/platform/soc/1d84000.ufshc/by-name/vendor&quot;;
					type = &quot;ext4&quot;;
					compatible = &quot;android,vendor&quot;;
					status = &quot;disabled&quot;;
				};
			};

vbmeta {
				parts = &quot;vbmeta,boot,system,vendor,dtbo,recovery&quot;;
				compatible = &quot;android,vbmeta&quot;;
			};
		};
	};

chosen {
		linux,initrd-end = &lt;0x00 0x855fee0d&gt;;
		bootargs = &quot;rcu_nocbs=0-7 androidboot.hardware=qcom androidboot.memcg=1 androidboot.usbcontroller=a600000.dwc3 loop.max_part=7 lpm_levels.sleep_disabled=1 service_locator.enable=1 swiotlb=1 msm_rtb.filter=0x237 kpti=off androidboot.fstab_suffix=qcom buildvariant=userdebug androidboot.verifiedbootstate=orange androidboot.keymaster=1  androidboot.bootdevice=1d84000.ufshc androidboot.fstab_suffix=default androidboot.boot_devices=soc/1d84000.ufshc androidboot.serialno=c1164428 androidboot.ramdump=disable androidboot.secureboot=1 androidboot.cpuid=0xfa1aafba androidboot.hwversion=10.19.6 androidboot.camera.config=0 androidboot.hwc=GLOBAL androidboot.hwlevel=MP androidboot.product.hardware.sku=pro androidboot.baseband=msm msm_drm.dsi_display0=dsi_k6_38_0c_0a_fhd_dsc_video_display: androidboot.dtbo_idx=18 androidboot.dtb_idx=11 androidboot.batt_verified_result=11 androidboot.profile_vendor_id=0A androidboot.dp=0x0&quot;;
		kaslr-seed = &lt;0x00 0x00&gt;;
		pureason = &lt;0x40011&gt;;
		linux,initrd-start = &lt;0x00 0x8544a000&gt;;
		rng-seed = &lt;0x59fd9f9e 0xfd1f857d 0xd7e555d9 0xcbfe1c4d 0x923a9a3a 0xc4ce6f00 0xd9c6e1ac 0x5b739e40 0x34d3d117 0x667be11b 0x6de75ac 0x609d5aa8 0x827fcfb3 0x4f2e9358 0xd9851a01 0x4f4803e0 0xeed5c420 0xf1258c5b 0xb37533e4 0xfc06d725 0xef31b301 0x3f8d3529 0x5cb36c07 0xb9294250 0xee59f5f6 0x9adb58ff 0x4ef3f57d 0xb22ea90b 0x16382d46 0x456d75f6 0x1966a8b0 0x63586a5d 0x7043c62e 0xfd4dff94 0x25ec36b7 0x5342a5c8 0xaf87bccd 0xa8a1d9cf 0x73137fd3 0x751481dc 0x19390780 0x88e3710c 0xdbb76e4d 0x3d12bd0f 0xd12e8173 0x178c28f 0x293ed102 0x8924b516 0x1919bab5 0xe582f648 0xf2f4a9a0 0xf2e928c2 0x9c43f83a 0x3a9e36fa 0xc5be173f 0x1cab1ec0 0x75c32daf 0x6e0c8f6c 0x9c77d703 0xccd6206f 0x340c6540 0x61617b73 0x9de96385 0xb86d145f 0x5b3dccb3 0xba36bddd 0xd1c34dde 0x2b6ca024 0xe3bd760b 0x28f77ecc 0xe322bffc 0x802582dd 0x463ff9c4 0xb80ce35d 0x404b98e3 0xf0250f8 0x66ee364 0x33d5fe37 0xb066588d 0xfb7d5a3b 0x8a294b1a 0xb65aa19b 0x5fae7b5e 0x3926b2d7 0xd3a15e3f 0xd8cf5e8 0xbb167a14 0x9f261c08 0x54ea8355 0x8592017b 0x7efafcb 0x4858dd56 0x1a0e8fbd 0xdb29180e 0xdb7a5691 0xb19188bc 0xc7070380 0x75edeccf 0xd9eace07 0xbb7bad4a 0x979d78f0 0x5cfb82b6 0xeba4db03 0x7f69c806 0xa89cfc21 0x6b078b8 0x9e93c6c4 0xa8911f5e 0xcf48ec07 0x74d9d613 0x94ea9f59 0x3c3a62ad 0x1e7e333c 0xbfda48cf 0x36100f60 0x2f1fe66c 0x5c5f842f 0x6be65d80 0x404eef6d 0x78d6d08b 0x5bca78d6 0x994c0c2 0x2678830f 0xed43768a 0x2940fc4b 0x120dd409 0x1fb29db1 0xbf195736&gt;;
	};

cpus {
		#address-cells = &lt;0x02&gt;;
		#size-cells = &lt;0x00&gt;;

cpu@300 {
			capacity-dmips-mhz = &lt;0x400&gt;;
			qcom,lmh-dcvs = &lt;0x05&gt;;
			device_type = &quot;cpu&quot;;
			sched-energy-costs = &lt;0x02 0x03&gt;;
			compatible = &quot;arm,armv8&quot;;
			next-level-cache = &lt;0x09&gt;;
			reg = &lt;0x00 0x300&gt;;
			enable-method = &quot;psci&quot;;
			phandle = &lt;0x14&gt;;
			#cooling-cells = &lt;0x02&gt;;

l2-cache {
				cache-level = &lt;0x02&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				next-level-cache = &lt;0x06&gt;;
				phandle = &lt;0x09&gt;;
			};

l1-dcache {
				qcom,dump-size = &lt;0x9000&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x40&gt;;
			};

l1-icache {
				qcom,dump-size = &lt;0x8800&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x38&gt;;
			};

l2-tlb {
				qcom,dump-size = &lt;0x5000&gt;;
				phandle = &lt;0x4c&gt;;
			};
		};

cpu@600 {
			capacity-dmips-mhz = &lt;0x6cc&gt;;
			qcom,lmh-dcvs = &lt;0x0f&gt;;
			device_type = &quot;cpu&quot;;
			sched-energy-costs = &lt;0x0c 0x0d&gt;;
			compatible = &quot;arm,armv8&quot;;
			next-level-cache = &lt;0x0e&gt;;
			reg = &lt;0x00 0x600&gt;;
			enable-method = &quot;psci&quot;;
			phandle = &lt;0x17&gt;;
			#cooling-cells = &lt;0x02&gt;;

l2-cache {
				qcom,dump-size = &lt;0x48000&gt;;
				cache-level = &lt;0x02&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				next-level-cache = &lt;0x06&gt;;
				phandle = &lt;0x0e&gt;;
			};

l1-dtlb {
				qcom,dump-size = &lt;0x480&gt;;
				phandle = &lt;0x47&gt;;
			};

l1-itlb {
				qcom,dump-size = &lt;0x300&gt;;
				phandle = &lt;0x45&gt;;
			};

l1-dcache {
				qcom,dump-size = &lt;0x12000&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x43&gt;;
			};

l1-icache {
				qcom,dump-size = &lt;0x11000&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x3b&gt;;
			};

l2-tlb {
				qcom,dump-size = &lt;0x7800&gt;;
				phandle = &lt;0x4f&gt;;
			};
		};

cpu-map {

cluster0 {

core5 {
					cpu = &lt;0x16&gt;;
				};

core3 {
					cpu = &lt;0x14&gt;;
				};

core1 {
					cpu = &lt;0x12&gt;;
				};

core4 {
					cpu = &lt;0x15&gt;;
				};

core2 {
					cpu = &lt;0x13&gt;;
				};

core0 {
					cpu = &lt;0x11&gt;;
				};
			};

cluster1 {

core1 {
					cpu = &lt;0x18&gt;;
				};

core0 {
					cpu = &lt;0x17&gt;;
				};
			};
		};

cpu@200 {
			capacity-dmips-mhz = &lt;0x400&gt;;
			qcom,lmh-dcvs = &lt;0x05&gt;;
			device_type = &quot;cpu&quot;;
			sched-energy-costs = &lt;0x02 0x03&gt;;
			compatible = &quot;arm,armv8&quot;;
			next-level-cache = &lt;0x08&gt;;
			reg = &lt;0x00 0x200&gt;;
			enable-method = &quot;psci&quot;;
			phandle = &lt;0x13&gt;;
			#cooling-cells = &lt;0x02&gt;;

l2-cache {
				cache-level = &lt;0x02&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				next-level-cache = &lt;0x06&gt;;
				phandle = &lt;0x08&gt;;
			};

l1-dcache {
				qcom,dump-size = &lt;0x9000&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x3f&gt;;
			};

l1-icache {
				qcom,dump-size = &lt;0x8800&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x37&gt;;
			};

l2-tlb {
				qcom,dump-size = &lt;0x5000&gt;;
				phandle = &lt;0x4b&gt;;
			};
		};

cpu@500 {
			capacity-dmips-mhz = &lt;0x400&gt;;
			qcom,lmh-dcvs = &lt;0x05&gt;;
			device_type = &quot;cpu&quot;;
			sched-energy-costs = &lt;0x02 0x03&gt;;
			compatible = &quot;arm,armv8&quot;;
			next-level-cache = &lt;0x0b&gt;;
			reg = &lt;0x00 0x500&gt;;
			enable-method = &quot;psci&quot;;
			phandle = &lt;0x16&gt;;
			#cooling-cells = &lt;0x02&gt;;

l2-cache {
				cache-level = &lt;0x02&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				next-level-cache = &lt;0x06&gt;;
				phandle = &lt;0x0b&gt;;
			};

l1-dcache {
				qcom,dump-size = &lt;0x9000&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x42&gt;;
			};

l1-icache {
				qcom,dump-size = &lt;0x8800&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x3a&gt;;
			};

l2-tlb {
				qcom,dump-size = &lt;0x5000&gt;;
				phandle = &lt;0x4e&gt;;
			};
		};

cpu@0 {
			capacity-dmips-mhz = &lt;0x400&gt;;
			qcom,lmh-dcvs = &lt;0x05&gt;;
			device_type = &quot;cpu&quot;;
			sched-energy-costs = &lt;0x02 0x03&gt;;
			compatible = &quot;arm,armv8&quot;;
			next-level-cache = &lt;0x04&gt;;
			reg = &lt;0x00 0x00&gt;;
			enable-method = &quot;psci&quot;;
			phandle = &lt;0x11&gt;;
			#cooling-cells = &lt;0x02&gt;;

l2-cache {
				cache-level = &lt;0x02&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				next-level-cache = &lt;0x06&gt;;
				phandle = &lt;0x04&gt;;

l3-cache {
					cache-level = &lt;0x03&gt;;
					compatible = &quot;arm,arch-cache&quot;;
					phandle = &lt;0x06&gt;;
				};
			};

l1-dcache {
				qcom,dump-size = &lt;0x9000&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x3d&gt;;
			};

l1-icache {
				qcom,dump-size = &lt;0x8800&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x35&gt;;
			};

l2-tlb {
				qcom,dump-size = &lt;0x5000&gt;;
				phandle = &lt;0x49&gt;;
			};
		};

cpu@100 {
			capacity-dmips-mhz = &lt;0x400&gt;;
			qcom,lmh-dcvs = &lt;0x05&gt;;
			device_type = &quot;cpu&quot;;
			sched-energy-costs = &lt;0x02 0x03&gt;;
			compatible = &quot;arm,armv8&quot;;
			next-level-cache = &lt;0x07&gt;;
			reg = &lt;0x00 0x100&gt;;
			enable-method = &quot;psci&quot;;
			phandle = &lt;0x12&gt;;
			#cooling-cells = &lt;0x02&gt;;

l2-cache {
				cache-level = &lt;0x02&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				next-level-cache = &lt;0x06&gt;;
				phandle = &lt;0x07&gt;;
			};

l1-dcache {
				qcom,dump-size = &lt;0x9000&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x3e&gt;;
			};

l1-icache {
				qcom,dump-size = &lt;0x8800&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x36&gt;;
			};

l2-tlb {
				qcom,dump-size = &lt;0x5000&gt;;
				phandle = &lt;0x4a&gt;;
			};
		};

cpu@400 {
			capacity-dmips-mhz = &lt;0x400&gt;;
			qcom,lmh-dcvs = &lt;0x05&gt;;
			device_type = &quot;cpu&quot;;
			sched-energy-costs = &lt;0x02 0x03&gt;;
			compatible = &quot;arm,armv8&quot;;
			next-level-cache = &lt;0x0a&gt;;
			reg = &lt;0x00 0x400&gt;;
			enable-method = &quot;psci&quot;;
			phandle = &lt;0x15&gt;;
			#cooling-cells = &lt;0x02&gt;;

l2-cache {
				cache-level = &lt;0x02&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				next-level-cache = &lt;0x06&gt;;
				phandle = &lt;0x0a&gt;;
			};

l1-dcache {
				qcom,dump-size = &lt;0x9000&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x41&gt;;
			};

l1-icache {
				qcom,dump-size = &lt;0x8800&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x39&gt;;
			};

l2-tlb {
				qcom,dump-size = &lt;0x5000&gt;;
				phandle = &lt;0x4d&gt;;
			};
		};

cpu@700 {
			capacity-dmips-mhz = &lt;0x6cc&gt;;
			qcom,lmh-dcvs = &lt;0x0f&gt;;
			device_type = &quot;cpu&quot;;
			sched-energy-costs = &lt;0x0c 0x0d&gt;;
			compatible = &quot;arm,armv8&quot;;
			next-level-cache = &lt;0x10&gt;;
			reg = &lt;0x00 0x700&gt;;
			enable-method = &quot;psci&quot;;
			phandle = &lt;0x18&gt;;
			#cooling-cells = &lt;0x02&gt;;

l2-cache {
				qcom,dump-size = &lt;0x48000&gt;;
				cache-level = &lt;0x02&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				next-level-cache = &lt;0x06&gt;;
				phandle = &lt;0x10&gt;;
			};

l1-dtlb {
				qcom,dump-size = &lt;0x480&gt;;
				phandle = &lt;0x48&gt;;
			};

l1-itlb {
				qcom,dump-size = &lt;0x300&gt;;
				phandle = &lt;0x46&gt;;
			};

l1-dcache {
				qcom,dump-size = &lt;0x12000&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x44&gt;;
			};

l1-icache {
				qcom,dump-size = &lt;0x11000&gt;;
				compatible = &quot;arm,arch-cache&quot;;
				phandle = &lt;0x3c&gt;;
			};

l2-tlb {
				qcom,dump-size = &lt;0x7800&gt;;
				phandle = &lt;0x50&gt;;
			};
		};
	};

__symbols__ {
		sdc1_cmd_on = &quot;/soc/pinctrl@3400000/sdc1_cmd_on&quot;;
		eud_in_replicator_swao = &quot;/soc/dummy_sink/port/endpoint&quot;;
		qupv3_se11_4uart_pins = &quot;/soc/pinctrl@3400000/qupv3_se11_4uart_pins&quot;;
		funnel_dl_south_1_out_funnel_qatb = &quot;/soc/funnel_1@6b53000/ports/port@0/endpoint&quot;;
		mdss_dsi0_pll = &quot;/soc/qcom,mdss_dsi_pll@ae94a00&quot;;
		smp2p_rdbg5_out = &quot;/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-out&quot;;
		qupv3_se11_spi_sleep = &quot;/soc/pinctrl@3400000/qupv3_se11_spi_pins/qupv3_se11_spi_sleep&quot;;
		tpda_olc = &quot;/soc/tpda@7832000&quot;;
		tdm_pri_tx = &quot;/soc/qcom,msm-dai-tdm-pri-tx&quot;;
		mas_qxm_camnoc_nrt = &quot;/soc/ad-hoc-bus/mas-qxm-camnoc-nrt&quot;;
		bcm_sn4 = &quot;/soc/ad-hoc-bus/bcm-sn4&quot;;
		cdsp_smp2p_in = &quot;/soc/qcom,smp2p-cdsp/slave-kernel&quot;;
		cti3 = &quot;/soc/cti@6013000&quot;;
		pm6150_l3 = &quot;/soc/rpmh-regulator-ldoa3/regulator-pm6150-l3&quot;;
		wled_switch = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800/qcom,wled-switch&quot;;
		qupv3_se2_i2c_sleep = &quot;/soc/pinctrl@3400000/qupv3_se2_i2c_pins/qupv3_se2_i2c_sleep&quot;;
		L1_DTLB_600 = &quot;/cpus/cpu@600/l1-dtlb&quot;;
		cpu6_cpu_l3_latmon = &quot;/soc/qcom,cpu6-cpu-l3-latmon&quot;;
		fpc_int_low = &quot;/soc/pinctrl@3400000/fpc_reset_int/int_low&quot;;
		qupv3_se7_i2c_sleep = &quot;/soc/pinctrl@3400000/qupv3_se7_i2c_pins/qupv3_se7_i2c_sleep&quot;;
		mdss_dp_pll = &quot;/soc/qcom,mdss_dp_pll@ae90000&quot;;
		va_cdc_dma_0_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-0-tx&quot;;
		i2c_freq_custom_cci0 = &quot;/soc/qcom,cci@ac4a000/qcom,i2c_custom_mode&quot;;
		icp_iova_mem_map = &quot;/soc/qcom,cam_smmu/msm_cam_smmu_icp/iova-mem-map&quot;;
		mas_qxm_camnoc_hf0_uncomp = &quot;/soc/ad-hoc-bus/mas-qxm-camnoc-hf0-uncomp&quot;;
		L2A = &quot;/soc/rpmh-regulator-ldoa2/regulator-pm6150-l2&quot;;
		slv_qhs_cpr_cx = &quot;/soc/ad-hoc-bus/slv-qhs-cpr-cx&quot;;
		msm_hvx_rm = &quot;/soc/qcom,glink/cdsp/qcom,msm_cdsprm_rpmsg/qcom,msm_hvx_rm&quot;;
		tpda_swao_in_tpdm_swao0 = &quot;/soc/tpda@6b01000/ports/port@1/endpoint&quot;;
		cti1_wcss = &quot;/soc/cti@69a5000&quot;;
		cpu5_config = &quot;/soc/thermal-zones/cpu-0-5-step/trips/cpu5-config&quot;;
		funnel_in0_in_tpdm_lpass = &quot;/soc/funnel@0x6041000/ports/port@1/endpoint&quot;;
		pm6150_qg = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/qpnp,qg&quot;;
		titan_top_gdsc = &quot;/soc/qcom,gdsc@ad0c1c4&quot;;
		fab_ipa_virt = &quot;/soc/ad-hoc-bus/fab-ipa_virt&quot;;
		pm6150_misc = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,misc@900&quot;;
		pm6150l_temp_alarm = &quot;/soc/thermal-zones/pm6150l-tz&quot;;
		tpda_modem_0_out_funnel_modem = &quot;/soc/tpda@6831000/ports/port@0/endpoint&quot;;
		S2C_LEVEL_AO = &quot;/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2-level-ao&quot;;
		etm7 = &quot;/soc/etm@7740000&quot;;
		tpda_apss_in_tpdm_apss = &quot;/soc/tpda@7862000/ports/port@1/endpoint&quot;;
		cdsp_sec_mem = &quot;/reserved-memory/cdsp_sec_regions@0x9f800000&quot;;
		msm_cdsp_rm = &quot;/soc/qcom,glink/cdsp/qcom,msm_cdsprm_rpmsg/qcom,msm_cdsp_rm&quot;;
		clock_dispcc = &quot;/soc/qcom,dispcc@af00000&quot;;
		cti1_ddr1 = &quot;/soc/cti@6a11000&quot;;
		pm6150l_l4 = &quot;/soc/rpmh-regulator-ldoc4/regulator-pm6150l-l4&quot;;
		thermal_zones = &quot;/soc/thermal-zones&quot;;
		qcom_msmhdcp = &quot;/soc/qcom,msm_hdcp&quot;;
		slv_qhs_qupv3_north = &quot;/soc/ad-hoc-bus/slv-qhs-qupv3-north&quot;;
		funnel_in2_in_funnel_apss_merg = &quot;/soc/funnel@6043000/ports/port@1/endpoint&quot;;
		tpda_modem_1_in_tpdm_modem_1 = &quot;/soc/tpda@6833000/ports/port@1/endpoint&quot;;
		intc = &quot;/soc/interrupt-controller@17a00000&quot;;
		tpda_in_funnel_dl_mm = &quot;/soc/tpda@6004000/ports/port@1/endpoint&quot;;
		flash_led = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300&quot;;
		mas_qhm_a2noc_cfg = &quot;/soc/ad-hoc-bus/mas-qhm-a2noc-cfg&quot;;
		gpu_gx_gdsc = &quot;/soc/qcom,gdsc@509100c&quot;;
		slv_qhs_tlmm_west = &quot;/soc/ad-hoc-bus/slv-qhs-tlmm-west&quot;;
		mas_qxm_rot_display = &quot;/soc/ad-hoc-bus/mas-qxm-rot_display&quot;;
		wsa_swr_clk_active = &quot;/soc/pinctrl@3400000/wsa_swr_clk_pin/wsa_swr_clk_active&quot;;
		L1_I_100 = &quot;/cpus/cpu@100/l1-icache&quot;;
		adsp_smp2p_in = &quot;/soc/qcom,smp2p-adsp/slave-kernel&quot;;
		jpeg_iova_mem_map = &quot;/soc/qcom,cam_smmu/msm_cam_smmu_jpeg/iova-mem-map&quot;;
		mas_xm_emmc = &quot;/soc/ad-hoc-bus/mas-xm-emmc&quot;;
		pm6150l_rgb_led = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d000&quot;;
		slv_qhs_glm = &quot;/soc/ad-hoc-bus/slv-qhs-glm&quot;;
		L1A = &quot;/soc/rpmh-regulator-ldoa1/regulator-pm6150-l1&quot;;
		slv_qns_cnoc = &quot;/soc/ad-hoc-bus/slv-qns-cnoc&quot;;
		fab_mc_virt_display = &quot;/soc/ad-hoc-bus/fab-mc_virt_display&quot;;
		pm6150l_torch2 = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,torch_2&quot;;
		cpu0_cpu_llcc_lat = &quot;/soc/qcom,cpu0-cpu-llcc-lat&quot;;
		sdc2_cmd_on = &quot;/soc/pinctrl@3400000/sdc2_cmd_on&quot;;
		rx_cdc_dma_6_rx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-6-rx&quot;;
		swao_csr = &quot;/soc/csr@6b0e000&quot;;
		pm6150l_switch0 = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,led_switch_0&quot;;
		adsp_tbu = &quot;/soc/apps-smmu@0x15000000/adsp_tbu@0x1519d000&quot;;
		tpdm_olc_out_tpda_olc = &quot;/soc/tpdm@7830000/port/endpoint&quot;;
		tpda_llm_silver_out_funnel_apss_merg = &quot;/soc/tpda@78c0000/ports/port@0/endpoint&quot;;
		pm6150_pdphy = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,usb-pdphy@1700&quot;;
		iommu_slim_qca_ctrl_cb = &quot;/soc/slim@62e40000/qcom,iommu_slim_ctrl_cb&quot;;
		q6_hvx_trip1 = &quot;/soc/thermal-zones/q6-hvx-step/trips/q6-hvx-trip1&quot;;
		tdm_pri_rx = &quot;/soc/qcom,msm-dai-tdm-pri-rx&quot;;
		mdss_dsi0 = &quot;/soc/qcom,mdss_dsi_ctrl0@ae94000&quot;;
		mas_qnm_snoc = &quot;/soc/ad-hoc-bus/mas-qnm-snoc&quot;;
		i2c_freq_100Khz_cci1 = &quot;/soc/qcom,cci@ac4b000/qcom,i2c_standard_mode&quot;;
		tpdm_swao0_out_tpda_swao = &quot;/soc/tpdm@6b02000/port/endpoint&quot;;
		replicator_swao = &quot;/soc/replicator@6b0a000&quot;;
		funnel_swao_in_replicator1_out = &quot;/soc/funnel@6b08000/ports/port@1/endpoint&quot;;
		funnel_gfx_out_tpda = &quot;/soc/funnel@6943000/ports/port@0/endpoint&quot;;
		voice = &quot;/soc/qcom,msm-pcm-voice&quot;;
		qupv3_se7_spi_sleep = &quot;/soc/pinctrl@3400000/qupv3_se7_spi_pins/qupv3_se7_spi_sleep&quot;;
		cpu7_0_config = &quot;/soc/thermal-zones/cpu-1-2-step/trips/cpu7-0-config&quot;;
		kgsl_msm_iommu = &quot;/soc/qcom,kgsl-iommu@5040000&quot;;
		pri_i2s_data0_sleep = &quot;/soc/pinctrl@3400000/pri_i2s_data0/pri_i2s_data0_sleep&quot;;
		qupv3_se6_spi_pins = &quot;/soc/pinctrl@3400000/qupv3_se6_spi_pins&quot;;
		dai_meta_mi2s1 = &quot;/soc/qcom,msm-dai-q6-meta-mi2s-sec&quot;;
		lcdb_ncp_vreg = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00/ncp&quot;;
		rx_cdc_dma_3_rx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-3-rx&quot;;
		qupv3_se3_4uart_pins = &quot;/soc/pinctrl@3400000/qupv3_se3_4uart_pins&quot;;
		cti10 = &quot;/soc/cti@601a000&quot;;
		tpda_llm_gold_in_tpdm_llm_gold = &quot;/soc/tpda@78d0000/ports/port@1/endpoint&quot;;
		slv_ipa_core_slave = &quot;/soc/ad-hoc-bus/slv-ipa-core-slave&quot;;
		tpda_llm_gold_out_funnel_apss_merg = &quot;/soc/tpda@78d0000/ports/port@0/endpoint&quot;;
		spkr_2_sd_n_active = &quot;/soc/pinctrl@3400000/spkr_2_sd_n/spkr_2_sd_n_active&quot;;
		modem_vdd = &quot;/soc/qmi-tmd-devices/modem/modem_vdd&quot;;
		mas_qhm_cnoc_dc_noc = &quot;/soc/ad-hoc-bus/mas-qhm-cnoc-dc-noc&quot;;
		anoc_2_tbu = &quot;/soc/apps-smmu@0x15000000/anoc_2_tbu@0x15189000&quot;;
		slv_qns_pcie_gemnoc = &quot;/soc/ad-hoc-bus/slv-qns-pcie-gemnoc&quot;;
		lmh_dcvs1 = &quot;/soc/qcom,cpucc@18321000/qcom,limits-dcvs@18350800&quot;;
		tsens0 = &quot;/soc/tsens@c222000&quot;;
		ipe_0_gdsc = &quot;/soc/qcom,gdsc@ad08004&quot;;
		funnel_merg_out_tmc_etf = &quot;/soc/funnel@6045000/ports/port@0/endpoint&quot;;
		bcm_mc0_display = &quot;/soc/ad-hoc-bus/bcm-mc0_display&quot;;
		pm6150l_s8 = &quot;/soc/rpmh-regulator-smpc8/regulator-pm6150l-s8&quot;;
		pm6150_l10 = &quot;/soc/rpmh-regulator-ldoa10/regulator-pm6150-l10&quot;;
		va_macro = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/va-macro@62f20000&quot;;
		pil_gpu_mem = &quot;/reserved-memory/gpu_region@97f15000&quot;;
		ts_int_suspend = &quot;/soc/pinctrl@3400000/pmx_ts_int_suspend/ts_int_suspend&quot;;
		incall_record_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-tx&quot;;
		hyp_region = &quot;/reserved-memory/hyp_region@85700000&quot;;
		tdm_quat_tx = &quot;/soc/qcom,msm-dai-tdm-quat-tx&quot;;
		green_led = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d000/green&quot;;
		tpda_llm_silver = &quot;/soc/tpda@78c0000&quot;;
		rx_cdc_dma_0_rx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-0-rx&quot;;
		VDD_CX_LEVEL_AO = &quot;/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2-level-ao&quot;;
		nfc_int_suspend = &quot;/soc/pinctrl@3400000/nfc/nfc_int_suspend&quot;;
		qupv3_se11_i2c_pins = &quot;/soc/pinctrl@3400000/qupv3_se11_i2c_pins&quot;;
		tpdm_ddr_out_funnel_ddr_0 = &quot;/soc/tpdm@6a00000/port/endpoint&quot;;
		dai_quin_auxpcm = &quot;/soc/qcom,msm-quin-auxpcm&quot;;
		replicator_swao_out_funnel_in1 = &quot;/soc/replicator@6b0a000/ports/port@1/endpoint&quot;;
		slim_aud = &quot;/soc/slim@62dc0000&quot;;
		npu_npu_ddr_bw = &quot;/soc/qcom,npu-npu-ddr-bw&quot;;
		funnel_modem_in_tpda_modem_1 = &quot;/soc/funnel@6832000/ports/port@2/endpoint&quot;;
		batt_trip4 = &quot;/soc/thermal-zones/quiet-therm-step/trips/batt-trip4&quot;;
		tpdm_north = &quot;/soc/tpdm@6b48000&quot;;
		pm6150_vadc = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/vadc@3100&quot;;
		VDD_MX_LEVEL_AO = &quot;/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3-level-ao&quot;;
		ipa_smmu_uc = &quot;/soc/ipa_smmu_uc&quot;;
		qupv3_se0_i2c = &quot;/soc/i2c@0x880000&quot;;
		qupv3_se2_i2c_pins = &quot;/soc/pinctrl@3400000/qupv3_se2_i2c_pins&quot;;
		glink_cdsp = &quot;/soc/qcom,glink/cdsp&quot;;
		funnel_apss_in_etm6 = &quot;/soc/funnel@7800000/ports/port@7/endpoint&quot;;
		bcm_sn2 = &quot;/soc/ad-hoc-bus/bcm-sn2&quot;;
		slv_qhs_prng = &quot;/soc/ad-hoc-bus/slv-qhs-prng&quot;;
		mas_qnm_gemnoc = &quot;/soc/ad-hoc-bus/mas-qnm-gemnoc&quot;;
		cti1 = &quot;/soc/cti@6011000&quot;;
		tpdm_olc = &quot;/soc/tpdm@7830000&quot;;
		mas_llcc_mc = &quot;/soc/ad-hoc-bus/mas-llcc-mc&quot;;
		pm6150_l1 = &quot;/soc/rpmh-regulator-ldoa1/regulator-pm6150-l1&quot;;
		cti0_swao = &quot;/soc/cti@6b04000&quot;;
		sdc2_data_on = &quot;/soc/pinctrl@3400000/sdc2_data_on&quot;;
		vph_lvl1 = &quot;/soc/thermal-zones/pm6150l-vph-lvl1/trips/vph-lvl1&quot;;
		qupv3_se11_i2c_active = &quot;/soc/pinctrl@3400000/qupv3_se11_i2c_pins/qupv3_se11_i2c_active&quot;;
		qupv3_se11_spi = &quot;/soc/spi@0xa94000&quot;;
		wled_torch = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800/qcom,wled-torch&quot;;
		etm2_out_funnel_apss = &quot;/soc/etm@7240000/port/endpoint&quot;;
		fab_aggre2_noc = &quot;/soc/ad-hoc-bus/fab-aggre2_noc&quot;;
		sb_8_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-tx&quot;;
		L7A_LEVEL = &quot;/soc/rpmh-regulator-lmxlvl/regulator-pm6150-l7&quot;;
		replicator_swao_in_tmc_etf_swao = &quot;/soc/replicator@6b0a000/ports/port@2/endpoint&quot;;
		funnel_apss_merg_in_tpda_olc = &quot;/soc/funnel@7810000/ports/port@2/endpoint&quot;;
		cx_ipeak_lm = &quot;/soc/cx_ipeak@01fed000&quot;;
		smmu_rot_unsec = &quot;/soc/qcom,mdss_rotator@ae00000/qcom,smmu_rot_unsec_cb&quot;;
		cpu7_1_config = &quot;/soc/thermal-zones/cpu-1-3-step/trips/cpu7-1-config&quot;;
		tpda_in_funnel_gfx = &quot;/soc/tpda@6004000/ports/port@6/endpoint&quot;;
		L2_TLB_0 = &quot;/cpus/cpu@0/l2-tlb&quot;;
		swr2 = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/tx-macro@62ec0000/tx_swr_master&quot;;
		funnel_in1_in_replicator_swao = &quot;/soc/funnel@6042000/ports/port@2/endpoint&quot;;
		pcm2 = &quot;/soc/qcom,msm-ultra-low-latency&quot;;
		etm5 = &quot;/soc/etm@7540000&quot;;
		mas_alc = &quot;/soc/ad-hoc-bus/mas-alc&quot;;
		sde_te_suspend = &quot;/soc/pinctrl@3400000/pmx_sde_te/sde_te_suspend&quot;;
		l_bcl_lvl2 = &quot;/soc/thermal-zones/pm6150l-bcl-lvl2/trips/l-bcl-lvl2&quot;;
		slv_qhs_tsif = &quot;/soc/ad-hoc-bus/slv-qhs-tsif&quot;;
		pm6150l_l2 = &quot;/soc/rpmh-regulator-ldoc2/regulator-pm6150l-l2&quot;;
		silver_trip = &quot;/soc/thermal-zones/quiet-therm-step/trips/silver-trip&quot;;
		mas_xm_pcie3_0 = &quot;/soc/ad-hoc-bus/mas-xm-pcie3-0&quot;;
		CPU_COST_0 = &quot;/energy-costs/core-cost0&quot;;
		sleepstate_smp2p_out = &quot;/soc/qcom,smp2p-adsp/sleepstate-out&quot;;
		hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = &quot;/soc/qcom,gdsc@17d048&quot;;
		mas_qnm_mnoc_hf = &quot;/soc/ad-hoc-bus/mas-qnm-mnoc-hf&quot;;
		L1_I_400 = &quot;/cpus/cpu@400/l1-icache&quot;;
		funnel_qatb_in_funnel_dl_south_1 = &quot;/soc/funnel@6005000/ports/port@2/endpoint&quot;;
		qupv3_se4_i2c = &quot;/soc/i2c@0x890000&quot;;
		sb_5_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-5-tx&quot;;
		mx_cdev = &quot;/soc/rpmh-regulator-mxlvl/mx-cdev-lvl&quot;;
		funnel_apss_out_funnel_apss_merg = &quot;/soc/funnel@7800000/ports/port@0/endpoint&quot;;
		L7F = &quot;/soc/rpmh-regulator-ldof7/regulator-pm8009-l7&quot;;
		L2_TLB_100 = &quot;/cpus/cpu@100/l2-tlb&quot;;
		BOB = &quot;/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob&quot;;
		L1_D_300 = &quot;/cpus/cpu@300/l1-dcache&quot;;
		incall_record_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-rx&quot;;
		mnoc_hf_1_tbu = &quot;/soc/apps-smmu@0x15000000/mnoc_hf_1_tbu@0x15191000&quot;;
		jtag_mm6 = &quot;/soc/jtagmm@7640000&quot;;
		pm6150_l8_level = &quot;/soc/rpmh-regulator-lcxlvl/regulator-pm6150-l8&quot;;
		pm6150l_torch0 = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,torch_0&quot;;
		tdm_quat_rx = &quot;/soc/qcom,msm-dai-tdm-quat-rx&quot;;
		cxip_cdev = &quot;/soc/cxip-cdev@1fed000&quot;;
		slv_qns_gemnoc_gc = &quot;/soc/ad-hoc-bus/slv-qns-gemnoc-gc&quot;;
		msm_vidc1 = &quot;/soc/qcom,vidc1&quot;;
		ufs_phy_gdsc = &quot;/soc/qcom,gdsc@177004&quot;;
		funnel_merg = &quot;/soc/funnel@6045000&quot;;
		pm6150_l19 = &quot;/soc/rpmh-regulator-ldoa19/regulator-pm6150-l19&quot;;
		nfc_enable_active = &quot;/soc/pinctrl@3400000/nfc/nfc_enable_active&quot;;
		mas_xm_gic = &quot;/soc/ad-hoc-bus/mas-xm-gic&quot;;
		ufs_dev_reset_assert = &quot;/soc/pinctrl@3400000/ufs_dev_reset_assert&quot;;
		qupv3_se6_spi = &quot;/soc/spi@0xa80000&quot;;
		funnel_dl_south_in_tpdm_dl_south = &quot;/soc/funnel@6b53000/ports/port@1/endpoint&quot;;
		qupv3_se11_4uart = &quot;/soc/qcom,qup_uart@0xa94000&quot;;
		q6_hvx_trip = &quot;/soc/thermal-zones/q6-hvx-lowf/trips/q6-hvx-trip&quot;;
		mas_qxm_camnoc_nrt_uncomp = &quot;/soc/ad-hoc-bus/mas-qxm-camnoc-nrt-uncomp&quot;;
		slv_qhs_usb3_0 = &quot;/soc/ad-hoc-bus/slv-qhs-usb3-0&quot;;
		cpu_cpu_llcc_bwmon = &quot;/soc/qcom,cpu-cpu-llcc-bwmon@90b6300&quot;;
		dfps_data_memory = &quot;/reserved-memory/dfps_data_region@9d700000&quot;;
		sb_2_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-2-tx&quot;;
		pm6150_s5 = &quot;/soc/rpmh-regulator-smpa5/regulator-pm6150-s5&quot;;
		qupv3_se4_spi_active = &quot;/soc/pinctrl@3400000/qupv3_se4_spi_pins/qupv3_se4_spi_active&quot;;
		pm8009_s2 = &quot;/soc/rpmh-regulator-smpf2/regulator-pm8009-s2&quot;;
		sdc1_rclk_off = &quot;/soc/pinctrl@3400000/sdc1_rclk_off&quot;;
		ts_reset_suspend = &quot;/soc/pinctrl@3400000/pmx_ts_reset_suspend/ts_reset_suspend&quot;;
		bcm_mm2 = &quot;/soc/ad-hoc-bus/bcm-mm2&quot;;
		adsp_smp2p_out = &quot;/soc/qcom,smp2p-adsp/master-kernel&quot;;
		rot_reg = &quot;/soc/qcom,mdss_rotator@ae00000/qcom,rot-reg-bus&quot;;
		S7C_LEVEL = &quot;/soc/rpmh-regulator-modemlvl/regulator-pm6150l-s7&quot;;
		funnel_swao_out_tmc_etf_swao = &quot;/soc/funnel@6b08000/ports/port@0/endpoint&quot;;
		afe_loopback_tx = &quot;/soc/qcom,msm-dai-q6-afe-loopback-tx&quot;;
		smem = &quot;/soc/qcom,smem&quot;;
		L8A_LEVEL = &quot;/soc/rpmh-regulator-lcxlvl/regulator-pm6150-l8&quot;;
		slv_qhs_ahb2phy_west = &quot;/soc/ad-hoc-bus/slv-qhs-ahb2phy-west&quot;;
		L6F = &quot;/soc/rpmh-regulator-ldof6/regulator-pm8009-l6&quot;;
		mas_qxm_ipa = &quot;/soc/ad-hoc-bus/mas-qxm-ipa&quot;;
		qupv3_se8_i2c = &quot;/soc/i2c@0xa88000&quot;;
		sb_8_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-rx&quot;;
		mas_xm_qdss_dap = &quot;/soc/ad-hoc-bus/mas-xm-qdss-dap&quot;;
		tmc_etr = &quot;/soc/tmc@6048000&quot;;
		slv_qhs_venus_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-venus-cfg&quot;;
		stm = &quot;/soc/stm@6002000&quot;;
		funnel_qatb_in_tpda = &quot;/soc/funnel@6005000/ports/port@1/endpoint&quot;;
		fab_camnoc_virt = &quot;/soc/ad-hoc-bus/fab-camnoc_virt&quot;;
		iommu_qupv3_1_geni_se_cb = &quot;/soc/qcom,qupv3_1_geni_se@0xac0000/qcom,iommu_qupv3_1_geni_se_cb&quot;;
		mas_xm_usb3_0 = &quot;/soc/ad-hoc-bus/mas-xm-usb3-0&quot;;
		pm8009_l7 = &quot;/soc/rpmh-regulator-ldof7/regulator-pm8009-l7&quot;;
		cti0_wcss = &quot;/soc/cti@69a4000&quot;;
		mas_ipa_core_master = &quot;/soc/ad-hoc-bus/mas-ipa-core-master&quot;;
		bcl_soc = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/bcl-soc&quot;;
		slv_qhs_tcsr = &quot;/soc/ad-hoc-bus/slv-qhs-tcsr&quot;;
		afe = &quot;/soc/qcom,msm-pcm-afe&quot;;
		dai_pri_auxpcm = &quot;/soc/qcom,msm-pri-auxpcm&quot;;
		qupv3_se3_i2c_active = &quot;/soc/pinctrl@3400000/qupv3_se3_i2c_pins/qupv3_se3_i2c_active&quot;;
		cpu_cpu_llcc_bw = &quot;/soc/qcom,cpu-cpu-llcc-bw&quot;;
		slv_srvc_mnoc = &quot;/soc/ad-hoc-bus/slv-srvc-mnoc&quot;;
		disp_rdump_memory = &quot;/reserved-memory/disp_rdump_region@9c000000&quot;;
		smem_region = &quot;/reserved-memory/smem@86000000&quot;;
		dai_sen_tdm_tx_0 = &quot;/soc/qcom,msm-dai-tdm-sen-tx/qcom,msm-dai-q6-tdm-sen-tx-0&quot;;
		mem_client_3_size = &quot;/soc/qcom,memshare/qcom,client_3&quot;;
		cti0_ddr1 = &quot;/soc/cti@6a10000&quot;;
		voip = &quot;/soc/qcom,msm-voip-dsp&quot;;
		fsa4480 = &quot;/soc/i2c@0xa8c000/fsa4480@43&quot;;
		sde_te1_active = &quot;/soc/pinctrl@3400000/pmx_sde_te/sde_te1_active&quot;;
		tpda_apss = &quot;/soc/tpda@7862000&quot;;
		slv_qhs_clk_ctl = &quot;/soc/ad-hoc-bus/slv-qhs-clk-ctl&quot;;
		bcm_alc = &quot;/soc/ad-hoc-bus/bcm-alc&quot;;
		sb_5_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-5-rx&quot;;
		tpda_modem0 = &quot;/soc/tpda@6831000&quot;;
		qupv3_se11_spi_pins = &quot;/soc/pinctrl@3400000/qupv3_se11_spi_pins&quot;;
		gpi_dma0 = &quot;/soc/qcom,gpi-dma@0x800000&quot;;
		qupv3_se7_i2c_pins = &quot;/soc/pinctrl@3400000/qupv3_se7_i2c_pins&quot;;
		qupv3_se8_2uart = &quot;/soc/qcom,qup_uart@0xa88000&quot;;
		slv_qhs_crypto0_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-crypto0-cfg&quot;;
		pri_i2s_sck_sleep = &quot;/soc/pinctrl@3400000/pri_i2s_sck_ws/pri_i2s_sck_sleep&quot;;
		batt_trip2 = &quot;/soc/thermal-zones/quiet-therm-step/trips/batt-trip2&quot;;
		L5F = &quot;/soc/rpmh-regulator-ldof5/regulator-pm8009-l5&quot;;
		tmc_etr_in_replicator = &quot;/soc/tmc@6048000/port/endpoint&quot;;
		qseecom_mem = &quot;/reserved-memory/qseecom_region@9e400000&quot;;
		fsa_usbc_ana_en = &quot;/soc/pinctrl@3400000/fsa_usbc_ana_en_n@42/fsa_usbc_ana_en&quot;;
		stm_out_funnel_in0 = &quot;/soc/stm@6002000/port/endpoint&quot;;
		dai_tert_tdm_rx_0 = &quot;/soc/qcom,msm-dai-tdm-tert-rx/qcom,msm-dai-q6-tdm-tert-rx-0&quot;;
		funnel_apss_in_etm4 = &quot;/soc/funnel@7800000/ports/port@5/endpoint&quot;;
		bcm_sn0 = &quot;/soc/ad-hoc-bus/bcm-sn0&quot;;
		L2_200 = &quot;/cpus/cpu@200/l2-cache&quot;;
		tdm_sec_tx = &quot;/soc/qcom,msm-dai-tdm-sec-tx&quot;;
		funnel_ddr_0_in_tpdm_ddr = &quot;/soc/funnel@6a05000/ports/port@1/endpoint&quot;;
		funnel_in1_in_modem_etm0 = &quot;/soc/funnel@6042000/ports/port@1/endpoint&quot;;
		fab_mc_virt = &quot;/soc/ad-hoc-bus/fab-mc_virt&quot;;
		tpdm_prng = &quot;/soc/tpdm@684c000&quot;;
		tpdm_prng_out_tpda = &quot;/soc/tpdm@684c000/port/endpoint&quot;;
		llcc_bw_opp_table = &quot;/soc/llcc-bw-opp-table&quot;;
		hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = &quot;/soc/qcom,gdsc@17d030&quot;;
		slv_qhs_venus_throttle_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-venus-throttle-cfg&quot;;
		dai_sen_auxpcm = &quot;/soc/qcom,msm-sen-auxpcm&quot;;
		dai_quat_tdm_rx_0 = &quot;/soc/qcom,msm-dai-tdm-quat-rx/qcom,msm-dai-q6-tdm-quat-rx-0&quot;;
		tx_cdc_dma_5_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-5-tx&quot;;
		slv_qhs_apss = &quot;/soc/ad-hoc-bus/slv-qhs-apss&quot;;
		qupv3_se0_i2c_sleep = &quot;/soc/pinctrl@3400000/qupv3_se0_i2c_pins/qupv3_se0_i2c_sleep&quot;;
		sb_2_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-2-rx&quot;;
		pm6150_rtc = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,pm6150_rtc&quot;;
		vbat_lvl1 = &quot;/soc/thermal-zones/pm6150-vbat-lvl1/trips/vbat-lvl1&quot;;
		rx_macro = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/rx-macro@62ee0000&quot;;
		swr0 = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/wsa-macro@62f00000/wsa_swr_master&quot;;
		dai_quin_tdm_rx_0 = &quot;/soc/qcom,msm-dai-tdm-quin-rx/qcom,msm-dai-q6-tdm-quin-rx-0&quot;;
		wsa_cdc_dma_1_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-1-tx&quot;;
		pcm0 = &quot;/soc/qcom,msm-pcm&quot;;
		etm3 = &quot;/soc/etm@7340000&quot;;
		pm6150a_amoled = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled&quot;;
		qupv3_se8_i2c_active = &quot;/soc/pinctrl@3400000/qupv3_se8_i2c_pins/qupv3_se8_i2c_active&quot;;
		mas_qxm_gpu = &quot;/soc/ad-hoc-bus/mas-qxm-gpu&quot;;
		mas_qnm_mnoc_hf_display = &quot;/soc/ad-hoc-bus/mas-qnm-mnoc-hf_display&quot;;
		qseecom_ta_mem = &quot;/reserved-memory/qseecom_ta_region&quot;;
		spkr_2_sd_n_sleep = &quot;/soc/pinctrl@3400000/spkr_2_sd_n/spkr_2_sd_n_sleep&quot;;
		L1_I_700 = &quot;/cpus/cpu@700/l1-icache&quot;;
		l_bcl_lvl0 = &quot;/soc/thermal-zones/pm6150l-bcl-lvl0/trips/l-bcl-lvl0&quot;;
		tpda_out_funnel_qatb = &quot;/soc/tpda@6004000/ports/port@0/endpoint&quot;;
		lcdb_bst_vreg = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00/bst&quot;;
		clock_aop = &quot;/soc/qcom,aopclk&quot;;
		L4F = &quot;/soc/rpmh-regulator-ldof4/regulator-pm8009-l4&quot;;
		sde_te1_suspend = &quot;/soc/pinctrl@3400000/pmx_sde_te/sde_te1_suspend&quot;;
		lcdb_ldo_vreg = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00/ldo&quot;;
		smp2p_rdbg2_out = &quot;/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-out&quot;;
		qupv3_se11_rts = &quot;/soc/pinctrl@3400000/qupv3_se11_4uart_pins/qupv3_se11_rts&quot;;
		L2_TLB_400 = &quot;/cpus/cpu@400/l2-tlb&quot;;
		system_heap = &quot;/soc/qcom,ion/qcom,ion-heap@25&quot;;
		tx_cdc_dma_2_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-2-tx&quot;;
		L1_D_600 = &quot;/cpus/cpu@600/l1-dcache&quot;;
		replicator1_in_replicator_out = &quot;/soc/replicator@604a000/ports/port@1/endpoint&quot;;
		smp2p_ipa_1_in = &quot;/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-in&quot;;
		smartpa_int_active = &quot;/soc/pinctrl@3400000/smartpa_int_active&quot;;
		ufs_ice = &quot;/soc/ufsice@1d90000&quot;;
		mdss_dsi_phy0 = &quot;/soc/qcom,mdss_dsi_phy0@ae94400&quot;;
		jtag_mm4 = &quot;/soc/jtagmm@7440000&quot;;
		tpdm_dl_mm_out_funnel_dl_mm = &quot;/soc/tpdm@69c0000/port/endpoint&quot;;
		smartpa_enable_active = &quot;/soc/pinctrl@3400000/smartpa_enable_active&quot;;
		funnel_apss_merg_in_funnel_apss = &quot;/soc/funnel@7810000/ports/port@1/endpoint&quot;;
		qcom_smcinvoke = &quot;/soc/smcinvoke@86d00000&quot;;
		slv_qhs_ahb2phy_south = &quot;/soc/ad-hoc-bus/slv-qhs-ahb2phy-south&quot;;
		sdhc_2 = &quot;/soc/sdhci@8804000&quot;;
		pm6150_l17 = &quot;/soc/rpmh-regulator-ldoa17/regulator-pm6150-l17&quot;;
		red_led = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d000/led&quot;;
		etm1_out_funnel_apss = &quot;/soc/etm@7140000/port/endpoint&quot;;
		lrme_iova_mem_map = &quot;/soc/qcom,cam_smmu/msm_cam_smmu_lrme/iova-mem-map&quot;;
		slv_ebi_display = &quot;/soc/ad-hoc-bus/slv-ebi_display&quot;;
		CPU6 = &quot;/cpus/cpu@600&quot;;
		tpdm_turing = &quot;/soc/tpdm@6860000&quot;;
		tdm_sec_rx = &quot;/soc/qcom,msm-dai-tdm-sec-rx&quot;;
		cam_a5 = &quot;/soc/qcom,a5@ac00000&quot;;
		funnel_in2 = &quot;/soc/funnel@6043000&quot;;
		bcm_mm0 = &quot;/soc/ad-hoc-bus/bcm-mm0&quot;;
		tpdm_wcss_out_funnel_dl_south_1 = &quot;/soc/tpdm@699c000/port/endpoint&quot;;
		slv_qhs_llcc = &quot;/soc/ad-hoc-bus/slv-qhs-llcc&quot;;
		ddr_bw_opp_table = &quot;/soc/ddr-bw-opp-table&quot;;
		tpdm_modem1 = &quot;/soc/tpdm@6834000&quot;;
		mas_qnm_aggre1_noc = &quot;/soc/ad-hoc-bus/mas-qnm-aggre1-noc&quot;;
		mdss_dsi1_pll = &quot;/soc/qcom,mdss_dsi_pll@ae96a00&quot;;
		bcm_mm0_display = &quot;/soc/ad-hoc-bus/bcm-mm0_display&quot;;
		qupv3_se0_spi_sleep = &quot;/soc/pinctrl@3400000/qupv3_se0_spi_pins/qupv3_se0_spi_sleep&quot;;
		mas_qnm_mnoc_sf = &quot;/soc/ad-hoc-bus/mas-qnm-mnoc-sf&quot;;
		smp2p_ipa_1_out = &quot;/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-out&quot;;
		sdc2_cd_off = &quot;/soc/pinctrl@3400000/cd_off&quot;;
		bcm_cn0 = &quot;/soc/ad-hoc-bus/bcm-cn0&quot;;
		VDD_CX_LEVEL = &quot;/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2&quot;;
		fab_gem_noc = &quot;/soc/ad-hoc-bus/fab-gem_noc&quot;;
		i2c_freq_400Khz_cci1 = &quot;/soc/qcom,cci@ac4b000/qcom,i2c_fast_mode&quot;;
		tcsr_mutex = &quot;/soc/hwlock&quot;;
		bcm_sn9 = &quot;/soc/ad-hoc-bus/bcm-sn9&quot;;
		L1_ITLB_600 = &quot;/cpus/cpu@600/l1-itlb&quot;;
		cti8 = &quot;/soc/cti@6018000&quot;;
		bcm_sh2 = &quot;/soc/ad-hoc-bus/bcm-sh2&quot;;
		fab_config_noc = &quot;/soc/ad-hoc-bus/fab-config_noc&quot;;
		pm8009_l5 = &quot;/soc/rpmh-regulator-ldof5/regulator-pm8009-l5&quot;;
		pm6150l_s7_level = &quot;/soc/rpmh-regulator-modemlvl/regulator-pm6150l-s7&quot;;
		slv_qns_cnoc_a2noc = &quot;/soc/ad-hoc-bus/slv-qns-cnoc-a2noc&quot;;
		wsa_cdc_dma_1_rx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-1-rx&quot;;
		qupv3_se10_spi_active = &quot;/soc/pinctrl@3400000/qupv3_se10_spi_pins/qupv3_se10_spi_active&quot;;
		qupv3_se4_ctsrx = &quot;/soc/pinctrl@3400000/qupv3_se4_4uart_pins/qupv3_se4_ctsrx&quot;;
		tpdm_npu = &quot;/soc/tpdm@69e1000&quot;;
		wlan_msa_mem = &quot;/reserved-memory/wlan_msa_region@97d00000&quot;;
		hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = &quot;/soc/qcom,gdsc@17d03c&quot;;
		pm6150l_flash2 = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,flash_2&quot;;
		mvs1_gdsc = &quot;/soc/qcom,gdsc@ab008b4&quot;;
		L2F = &quot;/soc/rpmh-regulator-ldof2/regulator-pm8009-l2&quot;;
		tpda_swao_out_funnel_swao = &quot;/soc/tpda@6b01000/ports/port@0/endpoint&quot;;
		gpubw = &quot;/soc/qcom,gpubw&quot;;
		compr = &quot;/soc/qcom,msm-compr-dsp&quot;;
		wsa_swr_data_active = &quot;/soc/pinctrl@3400000/wsa_swr_data_pin/wsa_swr_data_active&quot;;
		cpu6_cpu_ddr_latfloor = &quot;/soc/qcom,cpu6-cpu-ddr-latfloor&quot;;
		adsp_mem = &quot;/reserved-memory/adsp_region&quot;;
		sdc2_clk_off = &quot;/soc/pinctrl@3400000/sdc2_clk_off&quot;;
		modem_proc = &quot;/soc/qmi-tmd-devices/modem/modem_proc&quot;;
		mas_qxm_mdp0 = &quot;/soc/ad-hoc-bus/mas-qxm-mdp0&quot;;
		hwevent = &quot;/soc/hwevent@0x014066f0&quot;;
		hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = &quot;/soc/qcom,gdsc@17d040&quot;;
		q6core = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio&quot;;
		qupv3_se7_spi_pins = &quot;/soc/pinctrl@3400000/qupv3_se7_spi_pins&quot;;
		glink_modem = &quot;/soc/qcom,glink/modem&quot;;
		L2_500 = &quot;/cpus/cpu@500/l2-cache&quot;;
		batt_trip0 = &quot;/soc/thermal-zones/quiet-therm-step/trips/batt-trip0&quot;;
		funnel_swao_in_tpda_swao = &quot;/soc/funnel@6b08000/ports/port@2/endpoint&quot;;
		tpdm_north_out_tpda = &quot;/soc/tpdm@6b48000/port/endpoint&quot;;
		pm6150l_l9 = &quot;/soc/rpmh-regulator-ldoc9/regulator-pm6150l-l9&quot;;
		cam_sensor_mclk1_suspend = &quot;/soc/pinctrl@3400000/cam_sensor_mclk1_suspend&quot;;
		cti_mss_q6 = &quot;/soc/cti@683b000&quot;;
		L19A = &quot;/soc/rpmh-regulator-ldoa19/regulator-pm6150-l19&quot;;
		tpdm_center = &quot;/soc/tpdm@6b44000&quot;;
		funnel_apss_in_etm2 = &quot;/soc/funnel@7800000/ports/port@3/endpoint&quot;;
		mas_qxm_camnoc_rt = &quot;/soc/ad-hoc-bus/mas-qxm-camnoc-rt&quot;;
		pm6150_adc_tm = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/adc_tm@3500&quot;;
		slv_qhs_display_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-display-cfg&quot;;
		qcom_rng = &quot;/soc/qrng@793000&quot;;
		ipcb_tgu = &quot;/soc/tgu@6b0c000&quot;;
		adsp_vdd = &quot;/soc/qmi-tmd-devices/adsp/adsp_vdd&quot;;
		qupv3_se8_2uart_sleep = &quot;/soc/pinctrl@3400000/qupv3_se8_2uart_pins/qupv3_se8_2uart_sleep&quot;;
		cam_jpeg_dma = &quot;/soc/qcom,jpegdma@ac52000&quot;;
		L1F = &quot;/soc/rpmh-regulator-ldof1/regulator-pm8009-l1&quot;;
		CLUSTER_COST_0 = &quot;/energy-costs/cluster-cost0&quot;;
		funnel_ddr_0_out_tpda = &quot;/soc/funnel@6a05000/ports/port@0/endpoint&quot;;
		ife_iova_mem_map = &quot;/soc/qcom,cam_smmu/msm_cam_smmu_ife/iova-mem-map&quot;;
		mas_acm_apps = &quot;/soc/ad-hoc-bus/mas-acm-apps&quot;;
		tpdm_apss = &quot;/soc/tpdm@7860000&quot;;
		pm6150l_trip1 = &quot;/soc/thermal-zones/pm6150l-tz/trips/trip1&quot;;
		funnel_turing_in_tpdm_turing = &quot;/soc/funnel@6861000/ports/port@1/endpoint&quot;;
		wcd_intr_default = &quot;/soc/pinctrl@3400000/wcd9xxx_intr/wcd_intr_default&quot;;
		tpda = &quot;/soc/tpda@6004000&quot;;
		slv_qhs_a1_noc_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-a1-noc-cfg&quot;;
		etm1 = &quot;/soc/etm@7140000&quot;;
		btfmslim_codec = &quot;/soc/slim@62e40000/wcn3990&quot;;
		cam_ipe0 = &quot;/soc/qcom,ipe0&quot;;
		mas_qxm_camnoc_rt_uncomp = &quot;/soc/ad-hoc-bus/mas-qxm-camnoc-rt-uncomp&quot;;
		cpu0_cpu_l3_lat = &quot;/soc/qcom,cpu0-cpu-l3-lat&quot;;
		tx_macro = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/tx-macro@62ec0000&quot;;
		cam_vfe1 = &quot;/soc/qcom,vfe1@acb6000&quot;;
		sdc2_cmd_off = &quot;/soc/pinctrl@3400000/sdc2_cmd_off&quot;;
		funnel_merg_in_funnel_in1 = &quot;/soc/funnel@6045000/ports/port@2/endpoint&quot;;
		L2_TLB_700 = &quot;/cpus/cpu@700/l2-tlb&quot;;
		qupv3_se3_i2c_pins = &quot;/soc/pinctrl@3400000/qupv3_se3_i2c_pins&quot;;
		qmp_npu1 = &quot;/soc/qcom,qmp-npu-high@9818000&quot;;
		L18A = &quot;/soc/rpmh-regulator-ldoa18/regulator-pm6150-l18&quot;;
		qupv3_se3_4uart = &quot;/soc/qcom,qup_uart@0x88c000&quot;;
		slv_qhs_compute_dsp_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-compute-dsp-cfg&quot;;
		L1_I_0 = &quot;/cpus/cpu@0/l1-icache&quot;;
		clock_npucc = &quot;/soc/qcom,npucc&quot;;
		fab_dc_noc = &quot;/soc/ad-hoc-bus/fab-dc_noc&quot;;
		apcs_glb = &quot;/soc/mailbox@17c00000&quot;;
		slv_qhs_pdm = &quot;/soc/ad-hoc-bus/slv-qhs-pdm&quot;;
		smmu_rot_sec = &quot;/soc/qcom,mdss_rotator@ae00000/qcom,smmu_rot_sec_cb&quot;;
		ibat_lvl1 = &quot;/soc/thermal-zones/pm6150-ibat-lvl1/trips/ibat-lvl1&quot;;
		cti15 = &quot;/soc/cti@601f000&quot;;
		dai_mi2s4 = &quot;/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quin&quot;;
		modem_trip3 = &quot;/soc/thermal-zones/quiet-therm-step/trips/modem-trip3&quot;;
		mas_qhm_qdss_bam = &quot;/soc/ad-hoc-bus/mas-qhm-qdss-bam&quot;;
		tmc_etf_swao = &quot;/soc/tmc@6b09000&quot;;
		va_cdc_dma_2_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-2-tx&quot;;
		mas_qxm_mdp1_display = &quot;/soc/ad-hoc-bus/mas-qxm-mdp1_display&quot;;
		jtag_mm2 = &quot;/soc/jtagmm@7240000&quot;;
		pm6150l_l10 = &quot;/soc/rpmh-regulator-ldoc10/regulator-pm6150l-l10&quot;;
		qupv3_0 = &quot;/soc/qcom,qupv3_0_geni_se@0x8c0000&quot;;
		LPI_CX_LEVEL = &quot;/soc/rpmh-regulator-lcxlvl/regulator-pm6150-l8&quot;;
		funnel_gfx = &quot;/soc/funnel@6943000&quot;;
		slv_qhs_ipa = &quot;/soc/ad-hoc-bus/slv-qhs-ipa&quot;;
		afe_proxy_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-tx&quot;;
		tpdm_pimem_out_tpda = &quot;/soc/tpdm@6850000/port/endpoint&quot;;
		pm6150_l15 = &quot;/soc/rpmh-regulator-ldoa15/regulator-pm6150-l15&quot;;
		pm6150_s2_level = &quot;/soc/rpmh-regulator-gfxlvl/regulator-pm6150-s2-level&quot;;
		pil_ipa_gsi_mem = &quot;/reserved-memory/ipa_gsi_region@97f10000&quot;;
		tmc_etf = &quot;/soc/tmc@6047000&quot;;
		pri_i2s_data1_sleep = &quot;/soc/pinctrl@3400000/pri_i2s_data1/pri_i2s_data1_sleep&quot;;
		bcm_sn15 = &quot;/soc/ad-hoc-bus/bcm-sn15&quot;;
		CPU4 = &quot;/cpus/cpu@400&quot;;
		L17A = &quot;/soc/rpmh-regulator-ldoa17/regulator-pm6150-l17&quot;;
		bcm_sh0_display = &quot;/soc/ad-hoc-bus/bcm-sh0_display&quot;;
		kgsl_smmu = &quot;/soc/arm,smmu-kgsl@5040000&quot;;
		S2A_LEVEL = &quot;/soc/rpmh-regulator-gfxlvl/regulator-pm6150-s2-level&quot;;
		funnel_in0 = &quot;/soc/funnel@0x6041000&quot;;
		tcsr_mutex_block = &quot;/soc/syscon@1f40000&quot;;
		dai_tert_auxpcm = &quot;/soc/qcom,msm-tert-auxpcm&quot;;
		qupv3_se10_i2c = &quot;/soc/i2c@0xa90000&quot;;
		pm6150l_revid = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@4/qcom,revid@100&quot;;
		mas_qhm_snoc_cfg = &quot;/soc/ad-hoc-bus/mas-qhm-snoc-cfg&quot;;
		lpass_core_hw_vote = &quot;/soc/lpass_core_hw_vote&quot;;
		soc = &quot;/soc&quot;;
		tpda_in_tpdm_dl_center = &quot;/soc/tpda@6004000/ports/port@2/endpoint&quot;;
		funnel_dl_south_1 = &quot;/soc/funnel_1@6b53000&quot;;
		qupv3_se1_i2c = &quot;/soc/i2c@0x884000&quot;;
		sdc1_clk_on = &quot;/soc/pinctrl@3400000/sdc1_clk_on&quot;;
		modem_smp2p_out = &quot;/soc/qcom,smp2p-modem/master-kernel&quot;;
		cx_cdev = &quot;/soc/rpmh-regulator-cxlvl/regulator-cdev&quot;;
		cti6 = &quot;/soc/cti@6016000&quot;;
		bcm_sh0 = &quot;/soc/ad-hoc-bus/bcm-sh0&quot;;
		pm6150_l6 = &quot;/soc/rpmh-regulator-ldoa6/regulator-pm6150-l6&quot;;
		qupv3_se1_i2c_active = &quot;/soc/pinctrl@3400000/qupv3_se1_i2c_pins/qupv3_se1_i2c_active&quot;;
		slv_qhs_emmc_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-emmc-cfg&quot;;
		cpu0_cpu_ddr_latfloor = &quot;/soc/qcom,cpu0-cpu-ddr-latfloor&quot;;
		slv_qns_camnoc_uncomp = &quot;/soc/ad-hoc-bus/slv-qns-camnoc-uncomp&quot;;
		pwm_lpg2 = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,pwms@b100/lpg2&quot;;
		mccc_debug = &quot;/soc/syscon@90b0000&quot;;
		pm6150l_flash0 = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,flash_0&quot;;
		hlos1_vote_aggre_noc_mmu_tbu2_gdsc = &quot;/soc/qcom,gdsc@17d038&quot;;
		gpu_trip = &quot;/soc/thermal-zones/gpuss-max-step/trips/gpu-trip&quot;;
		funnel_ddr_0 = &quot;/soc/funnel@6a05000&quot;;
		L16A = &quot;/soc/rpmh-regulator-ldoa16/regulator-pm6150-l16&quot;;
		qupv3_se3_spi = &quot;/soc/spi@0x88c000&quot;;
		funnel_turing_1_in_turing_etm0 = &quot;/soc/funnel_1@6861000/ports/port@1/endpoint&quot;;
		pm6150_bcl = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/bcl@1d00&quot;;
		disp_pins_default = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@4/pinctrl@c000/disp_pins/disp_pins_default&quot;;
		slv_qhs_qdss_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-qdss-cfg&quot;;
		qupv3_se7_spi_active = &quot;/soc/pinctrl@3400000/qupv3_se7_spi_pins/qupv3_se7_spi_active&quot;;
		spmi_bus = &quot;/soc/qcom,spmi@c440000&quot;;
		proxy_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-proxy-tx&quot;;
		tpda_olc_out_funnel_apss_merg = &quot;/soc/tpda@7832000/ports/port@0/endpoint&quot;;
		qupv3_se4_tx = &quot;/soc/pinctrl@3400000/qupv3_se4_4uart_pins/qupv3_se4_tx&quot;;
		dai_quat_auxpcm = &quot;/soc/qcom,msm-quat-auxpcm&quot;;
		cdsp_mem = &quot;/reserved-memory/cdsp_region&quot;;
		pm6150l_l7 = &quot;/soc/rpmh-regulator-ldoc7/regulator-pm6150l-l7&quot;;
		iommu_slim_aud_ctrl_cb = &quot;/soc/slim@62dc0000/qcom,iommu_slim_ctrl_cb&quot;;
		etm0_out_funnel_apss = &quot;/soc/etm@7040000/port/endpoint&quot;;
		usb_qmp_dp_phy = &quot;/soc/ssphy@88e8000&quot;;
		cwlan_trip = &quot;/soc/thermal-zones/cwlan-lowf/trips/cwlan-trip&quot;;
		LLCC_1 = &quot;/soc/qcom,llcc@9200000/llcc_1_dcache&quot;;
		funnel_apss_in_etm0 = &quot;/soc/funnel@7800000/ports/port@1/endpoint&quot;;
		bcl_lvl1 = &quot;/soc/thermal-zones/pm6150-bcl-lvl1/trips/bcl-lvl1&quot;;
		rx_cdc_dma_5_rx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-5-rx&quot;;
		bcm_mm2_display = &quot;/soc/ad-hoc-bus/bcm-mm2_display&quot;;
		cpu0_cpu_l3_latmon = &quot;/soc/qcom,cpu0-cpu-l3-latmon&quot;;
		ibb_vreg = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled/ibb@dc00&quot;;
		afe_proxy_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-rx&quot;;
		modem_pa = &quot;/soc/qmi-tmd-devices/modem/modem_pa&quot;;
		slv_qhs_venus_cvp_throttle_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-venus-cvp-throttle-cfg&quot;;
		cam_cci0 = &quot;/soc/qcom,cci@ac4a000&quot;;
		pri_i2s_data0_active = &quot;/soc/pinctrl@3400000/pri_i2s_data0/pri_i2s_data0_active&quot;;
		S3A_LEVEL = &quot;/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3&quot;;
		qupv3_se6_i2c_active = &quot;/soc/pinctrl@3400000/qupv3_se6_i2c_pins/qupv3_se6_i2c_active&quot;;
		L15A = &quot;/soc/rpmh-regulator-ldoa15/regulator-pm6150-l15&quot;;
		mas_qxm_camnoc_hf = &quot;/soc/ad-hoc-bus/mas-qxm-camnoc-hf&quot;;
		usb_audio_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-tx&quot;;
		cdsp_vdd = &quot;/soc/qmi-tmd-devices/cdsp/cdsp_vdd&quot;;
		slv_qhs_camera_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-camera-cfg&quot;;
		ddr_trip = &quot;/soc/thermal-zones/ddr-lowf/trips/ddr-trip&quot;;
		mas_qhm_spdm = &quot;/soc/ad-hoc-bus/mas-qhm-spdm&quot;;
		fab_mmss_noc = &quot;/soc/ad-hoc-bus/fab-mmss_noc&quot;;
		slv_qhs_imem_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-imem-cfg&quot;;
		qupv3_se8_i2c_pins = &quot;/soc/pinctrl@3400000/qupv3_se8_i2c_pins&quot;;
		qupv3_se7_spi = &quot;/soc/spi@0xa84000&quot;;
		sdc2_clk_on = &quot;/soc/pinctrl@3400000/sdc2_clk_on&quot;;
		rx_cdc_dma_2_rx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-2-rx&quot;;
		qupv3_se3_i2c_sleep = &quot;/soc/pinctrl@3400000/qupv3_se3_i2c_pins/qupv3_se3_i2c_sleep&quot;;
		audio_apr = &quot;/soc/qcom,msm-audio-apr&quot;;
		pm6150_vib = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@1/qcom,vibrator@5300&quot;;
		tpdm_swao1 = &quot;/soc/tpdm@6b03000&quot;;
		cci1_suspend = &quot;/soc/pinctrl@3400000/cci1_suspend&quot;;
		pm6150l_lpg = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,pwms@b100&quot;;
		slv_qns_a2noc_snoc = &quot;/soc/ad-hoc-bus/slv-qns-a2noc-snoc&quot;;
		dai_slim = &quot;/soc/slim@62dc0000/msm_dai_slim&quot;;
		qupv3_se3_spi_pins = &quot;/soc/pinctrl@3400000/qupv3_se3_spi_pins&quot;;
		tpda_in_tpdm_pimem = &quot;/soc/tpda@6004000/ports/port@11/endpoint&quot;;
		qupv3_se8_i2c_sleep = &quot;/soc/pinctrl@3400000/qupv3_se8_i2c_pins/qupv3_se8_i2c_sleep&quot;;
		funnel_dl_south = &quot;/soc/funnel@6b53000&quot;;
		funnel_qatb = &quot;/soc/funnel@6005000&quot;;
		audio_etm0_out_funnel_in0 = &quot;/soc/audio_etm0/port/endpoint&quot;;
		compute_dsp_0_tbu = &quot;/soc/apps-smmu@0x15000000/compute_dsp_0_tbu@0x15199000&quot;;
		L11C = &quot;/soc/rpmh-regulator-ldoc11/regulator-pm6150l-l11&quot;;
		sde_dp_aux_suspend = &quot;/soc/pinctrl@3400000/sde_dp_aux_suspend&quot;;
		cam_csiphy2 = &quot;/soc/qcom,csiphy@ace4000&quot;;
		slv_qns2_mem_noc_display = &quot;/soc/ad-hoc-bus/slv-qns2-mem-noc_display&quot;;
		wsa_swr_data_sleep = &quot;/soc/pinctrl@3400000/wsa_swr_data_pin/wsa_swr_data_sleep&quot;;
		mas_qnm_snoc_gc = &quot;/soc/ad-hoc-bus/mas-qnm-snoc-gc&quot;;
		L3_0 = &quot;/cpus/cpu@0/l2-cache/l3-cache&quot;;
		cam_sensor_mclk3_suspend = &quot;/soc/pinctrl@3400000/cam_sensor_mclk3_suspend&quot;;
		etm7_out_funnel_apss = &quot;/soc/etm@7740000/port/endpoint&quot;;
		S8C = &quot;/soc/rpmh-regulator-smpc8/regulator-pm6150l-s8&quot;;
		modem_smp2p_in = &quot;/soc/qcom,smp2p-modem/slave-kernel&quot;;
		qcom_crypto = &quot;/soc/qcrypto@1de0000&quot;;
		routing = &quot;/soc/qcom,msm-pcm-routing&quot;;
		qupv3_se9_i2c = &quot;/soc/i2c@0xa8c000&quot;;
		cti13 = &quot;/soc/cti@601d000&quot;;
		dai_mi2s2 = &quot;/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-tert&quot;;
		camera_trip = &quot;/soc/thermal-zones/camera-lowf/trips/camera-trip&quot;;
		bcm_acv = &quot;/soc/ad-hoc-bus/bcm-acv&quot;;
		pm6150l_clkdiv = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@4/clock-controller@5b00&quot;;
		L14A = &quot;/soc/rpmh-regulator-ldoa14/regulator-pm6150-l14&quot;;
		jtag_mm0 = &quot;/soc/jtagmm@7040000&quot;;
		msm_bus = &quot;/soc/qcom,kgsl-busmon&quot;;
		smmu_sde_sec = &quot;/soc/qcom,mdss_mdp@ae00000/qcom,smmu_sde_sec_cb&quot;;
		mvs0_gdsc = &quot;/soc/qcom,gdsc@ab00874&quot;;
		L1_I_300 = &quot;/cpus/cpu@300/l1-icache&quot;;
		afe_pcm_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-tx&quot;;
		slv_qhs_gpuss_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-gpuss-cfg&quot;;
		proxy_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-proxy-rx&quot;;
		pm6150_charger = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,qpnp-smb5&quot;;
		cam_bps = &quot;/soc/qcom,bps&quot;;
		pm6150_l13 = &quot;/soc/rpmh-regulator-ldoa13/regulator-pm6150-l13&quot;;
		bcm_qup0 = &quot;/soc/ad-hoc-bus/bcm-qup0&quot;;
		gpu_cx_hw_ctrl = &quot;/soc/syscon@5091540&quot;;
		funnel_in2_out_funnel_merg = &quot;/soc/funnel@6043000/ports/port@0/endpoint&quot;;
		cpu_0_0_trip = &quot;/soc/thermal-zones/cpu-0-0-lowf/trips/cpu-0-0-trip&quot;;
		cpu0_computemon = &quot;/soc/qcom,cpu0-computemon&quot;;
		CPU2 = &quot;/cpus/cpu@200&quot;;
		cpu_pmu = &quot;/soc/cpu-pmu&quot;;
		tpdm_qdss = &quot;/soc/tpdm@6006000&quot;;
		L1_D_200 = &quot;/cpus/cpu@200/l1-dcache&quot;;
		cpu0_llcc_ddr_latmon = &quot;/soc/qcom,cpu0-llcc-ddr-latmon&quot;;
		L10C = &quot;/soc/rpmh-regulator-ldoc10/regulator-pm6150l-l10&quot;;
		slv_qns_mem_noc_hf_display = &quot;/soc/ad-hoc-bus/slv-qns-mem-noc-hf_display&quot;;
		pm6150_trip1 = &quot;/soc/thermal-zones/pm6150-tz/trips/trip1&quot;;
		dcc = &quot;/soc/dcc_v2@10a2000&quot;;
		slv_qhs_tlmm_north = &quot;/soc/ad-hoc-bus/slv-qhs-tlmm-north&quot;;
		nfc_int_active = &quot;/soc/pinctrl@3400000/nfc/nfc_int_active&quot;;
		funnel_apss_merg_in_tpda_apss = &quot;/soc/funnel@7810000/ports/port@5/endpoint&quot;;
		clock_gcc = &quot;/soc/qcom,gcc@100000&quot;;
		pri_i2s_data1_active = &quot;/soc/pinctrl@3400000/pri_i2s_data1/pri_i2s_data1_active&quot;;
		tpdm_dl_south_out_funnel_dl_south = &quot;/soc/tpdm@6b52000/port/endpoint&quot;;
		sb_7_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-tx&quot;;
		tdm_sen_tx = &quot;/soc/qcom,msm-dai-tdm-sen-tx&quot;;
		ext_disp = &quot;/soc/qcom,msm-ext-disp&quot;;
		L13A = &quot;/soc/rpmh-regulator-ldoa13/regulator-pm6150-l13&quot;;
		usb_audio_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-rx&quot;;
		modem_etm0_out_funnel_in1 = &quot;/soc/modem_etm0/port/endpoint&quot;;
		bps_gdsc = &quot;/soc/qcom,gdsc@ad07004&quot;;
		cti4 = &quot;/soc/cti@6014000&quot;;
		pm6150_l4 = &quot;/soc/rpmh-regulator-ldoa4/regulator-pm6150-l4&quot;;
		mdss_mdp = &quot;/soc/qcom,mdss_mdp@ae00000&quot;;
		cti_aop_m3 = &quot;/soc/cti@6b21000&quot;;
		cti2_apss = &quot;/soc/cti@7900000&quot;;
		pm8009_l1 = &quot;/soc/rpmh-regulator-ldof1/regulator-pm8009-l1&quot;;
		qupv3_se3_spi_sleep = &quot;/soc/pinctrl@3400000/qupv3_se3_spi_pins/qupv3_se3_spi_sleep&quot;;
		dai_sec_tdm_rx_0 = &quot;/soc/qcom,msm-dai-tdm-sec-rx/qcom,msm-dai-q6-tdm-sec-rx-0&quot;;
		funnel_in1_in_funnel_modem = &quot;/soc/funnel@6042000/ports/port@3/endpoint&quot;;
		replicator_in_tmc_etf = &quot;/soc/replicator@6046000/ports/port@2/endpoint&quot;;
		tpda_llm_silver_in_tpdm_llm_silver = &quot;/soc/tpda@78c0000/ports/port@1/endpoint&quot;;
		qupv3_se8_spi_sleep = &quot;/soc/pinctrl@3400000/qupv3_se8_spi_pins/qupv3_se8_spi_sleep&quot;;
		i2c_freq_custom_cci1 = &quot;/soc/qcom,cci@ac4b000/qcom,i2c_custom_mode&quot;;
		cam_csid0 = &quot;/soc/qcom,csid0@acb3000&quot;;
		slv_qhs_pimem_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-pimem-cfg&quot;;
		mdss_rotator = &quot;/soc/qcom,mdss_rotator@ae00000&quot;;
		pm6150l_flashlight = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,flashlight&quot;;
		tpda_swao_in_tpdm_swao1 = &quot;/soc/tpda@6b01000/ports/port@2/endpoint&quot;;
		tdm_quin_tx = &quot;/soc/qcom,msm-dai-tdm-quin-tx&quot;;
		snoc_cnoc_keepalive = &quot;/soc/qcom,snoc_cnoc_keepalive&quot;;
		funnel_modem = &quot;/soc/funnel@6832000&quot;;
		audio_trip = &quot;/soc/thermal-zones/audio-lowf/trips/audio-trip&quot;;
		sb_4_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-4-tx&quot;;
		clock_debug = &quot;/soc/qcom,cc-debug&quot;;
		slv_qns_mem_noc_hf = &quot;/soc/ad-hoc-bus/slv-qns-mem-noc-hf&quot;;
		cti1_dlct = &quot;/soc/cti@6c2a000&quot;;
		qupv3_se4_4uart_pins = &quot;/soc/pinctrl@3400000/qupv3_se4_4uart_pins&quot;;
		clock_cpucc = &quot;/soc/qcom,cpucc@18321000&quot;;
		fab_gem_noc_display = &quot;/soc/ad-hoc-bus/fab-gem_noc_display&quot;;
		mas_qnm_npu = &quot;/soc/ad-hoc-bus/mas-qnm-npu&quot;;
		pm6150l_l5 = &quot;/soc/rpmh-regulator-ldoc5/regulator-pm6150l-l5&quot;;
		pil_ipa_fw_mem = &quot;/reserved-memory/ips_fw_region@97f00000&quot;;
		smp2p_rdbg5_in = &quot;/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-in&quot;;
		pil_video_mem = &quot;/reserved-memory/pil_video_region@93400000&quot;;
		npu_core_gdsc = &quot;/soc/qcom,gdsc@9911028&quot;;
		funnel_apss = &quot;/soc/funnel@7800000&quot;;
		L12A = &quot;/soc/rpmh-regulator-ldoa12/regulator-pm6150-l12&quot;;
		fab_mmss_noc_display = &quot;/soc/ad-hoc-bus/fab-mmss_noc_display&quot;;
		afe_pcm_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-rx&quot;;
		pm6150_revid = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,revid@100&quot;;
		clock_camcc = &quot;/soc/qcom,camcc&quot;;
		mas_qnm_pcie = &quot;/soc/ad-hoc-bus/mas-qnm-pcie&quot;;
		ufsphy_mem = &quot;/soc/ufsphy_mem@1d87000&quot;;
		qupv3_se3_rts = &quot;/soc/pinctrl@3400000/qupv3_se3_4uart_pins/qupv3_se3_rts&quot;;
		cpu_1_0_trip = &quot;/soc/thermal-zones/cpu-1-0-lowf/trips/cpu-1-0-trip&quot;;
		dummy_eud = &quot;/soc/dummy_sink&quot;;
		sb_1_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-1-tx&quot;;
		ipa_smmu_ap = &quot;/soc/ipa_smmu_ap&quot;;
		pm6150l_tz = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@4/qcom,temp-alarm@2400&quot;;
		tpdm_swao1_out_tpda_swao = &quot;/soc/tpdm@6b03000/port/endpoint&quot;;
		smp2p_rdbg2_in = &quot;/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-in&quot;;
		L2_100 = &quot;/cpus/cpu@100/l2-cache&quot;;
		tpda_in_tpdm_npu = &quot;/soc/tpda@6004000/ports/port@12/endpoint&quot;;
		pm6150l_switch1 = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,led_switch_1&quot;;
		tpdm_llm_gold_out_tpda_llm_gold = &quot;/soc/tpdm@78b0000/port/endpoint&quot;;
		tpda_apss_out_funnel_apss_merg = &quot;/soc/tpda@7862000/ports/port@0/endpoint&quot;;
		qupv3_se8_spi_pins = &quot;/soc/pinctrl@3400000/qupv3_se8_spi_pins&quot;;
		cam_sensor_mclk0_active = &quot;/soc/pinctrl@3400000/cam_sensor_mclk0_active&quot;;
		mas_qnm_cmpnoc = &quot;/soc/ad-hoc-bus/mas-qnm-cmpnoc&quot;;
		mas_qnm_mnoc_sf_display = &quot;/soc/ad-hoc-bus/mas-qnm-mnoc-sf_display&quot;;
		tpda_modem_1_out_funnel_modem = &quot;/soc/tpda@6833000/ports/port@0/endpoint&quot;;
		sb_7_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-rx&quot;;
		mas_qxm_venus0 = &quot;/soc/ad-hoc-bus/mas-qxm-venus0&quot;;
		pm6150l_pwm = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,pwms@bc00&quot;;
		q6_hvx_trip2 = &quot;/soc/thermal-zones/q6-hvx-step/trips/q6-hvx-trip2&quot;;
		pm6150_temp_alarm = &quot;/soc/thermal-zones/pm6150-tz&quot;;
		mdss_dsi1 = &quot;/soc/qcom,mdss_dsi_ctrl1@ae96000&quot;;
		bcm_ce0 = &quot;/soc/ad-hoc-bus/bcm-ce0&quot;;
		tdm_sen_rx = &quot;/soc/qcom,msm-dai-tdm-sen-rx&quot;;
		L11A = &quot;/soc/rpmh-regulator-ldoa11/regulator-pm6150-l11&quot;;
		slv_qns_llcc_display = &quot;/soc/ad-hoc-bus/slv-qns-llcc_display&quot;;
		dai_sec_spdif_tx = &quot;/soc/qcom,msm-dai-q6-spdif-sec-tx&quot;;
		cam_csiphy0 = &quot;/soc/qcom,csiphy@ace0000&quot;;
		clock_gpucc = &quot;/soc/qcom,gpucc&quot;;
		slv_qhs_gemnoc = &quot;/soc/ad-hoc-bus/slv-qhs-gemnoc&quot;;
		video_trip = &quot;/soc/thermal-zones/video-lowf/trips/video-trip&quot;;
		pm6150l_lcdb = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00&quot;;
		dai_tert_tdm_tx_0 = &quot;/soc/qcom,msm-dai-tdm-tert-tx/qcom,msm-dai-q6-tdm-tert-tx-0&quot;;
		mas_qnm_aggre2_noc = &quot;/soc/ad-hoc-bus/mas-qnm-aggre2-noc&quot;;
		tpda_swao = &quot;/soc/tpda@6b01000&quot;;
		funnel_in0_in_funnel_qatb = &quot;/soc/funnel@0x6041000/ports/port@3/endpoint&quot;;
		i2c_freq_1Mhz_cci0 = &quot;/soc/qcom,cci@ac4a000/qcom,i2c_fast_plus_mode&quot;;
		cti11 = &quot;/soc/cti@601b000&quot;;
		dai_mi2s0 = &quot;/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-prim&quot;;
		L1_I_600 = &quot;/cpus/cpu@600/l1-icache&quot;;
		tdm_quin_rx = &quot;/soc/qcom,msm-dai-tdm-quin-rx&quot;;
		qupv3_se0_spi_active = &quot;/soc/pinctrl@3400000/qupv3_se0_spi_pins/qupv3_se0_spi_active&quot;;
		dai_quat_tdm_tx_0 = &quot;/soc/qcom,msm-dai-tdm-quat-tx/qcom,msm-dai-q6-tdm-quat-tx-0&quot;;
		hlos1_vote_aggre_noc_mmu_tbu1_gdsc = &quot;/soc/qcom,gdsc@17d034&quot;;
		tsens1 = &quot;/soc/tsens@c223000&quot;;
		sb_4_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-4-rx&quot;;
		bcm_mc0 = &quot;/soc/ad-hoc-bus/bcm-mc0&quot;;
		lsm = &quot;/soc/qcom,msm-lsm-client&quot;;
		L2_TLB_300 = &quot;/cpus/cpu@300/l2-tlb&quot;;
		pm6150_l11 = &quot;/soc/rpmh-regulator-ldoa11/regulator-pm6150-l11&quot;;
		eud = &quot;/soc/qcom,msm-eud@88e0000&quot;;
		dai_pri_tdm_rx_0 = &quot;/soc/qcom,msm-dai-tdm-pri-rx/qcom,msm-dai-q6-tdm-pri-rx-0&quot;;
		L1_D_500 = &quot;/cpus/cpu@500/l1-dcache&quot;;
		dai_quin_tdm_tx_0 = &quot;/soc/qcom,msm-dai-tdm-quin-tx/qcom,msm-dai-q6-tdm-quin-tx-0&quot;;
		mas_qxm_camnoc_sf = &quot;/soc/ad-hoc-bus/mas-qxm-camnoc-sf&quot;;
		qupv3_se4_i2c_pins = &quot;/soc/pinctrl@3400000/qupv3_se4_i2c_pins&quot;;
		ts_release = &quot;/soc/pinctrl@3400000/pmx_ts_release/ts_release&quot;;
		bcm_sn11 = &quot;/soc/ad-hoc-bus/bcm-sn11&quot;;
		CPU0 = &quot;/cpus/cpu@0&quot;;
		cpu6_llcc_ddr_lat = &quot;/soc/qcom,cpu6-llcc-ddr-lat&quot;;
		sdc1_data_on = &quot;/soc/pinctrl@3400000/sdc1_data_on&quot;;
		mas_qhm_mnoc_cfg = &quot;/soc/ad-hoc-bus/mas-qhm-mnoc-cfg&quot;;
		L10A = &quot;/soc/rpmh-regulator-ldoa10/regulator-pm6150-l10&quot;;
		msm_dai_mi2s = &quot;/soc/qcom,msm-dai-mi2s&quot;;
		slv_qhs_aop = &quot;/soc/ad-hoc-bus/slv-qhs-aop&quot;;
		ipa_hw = &quot;/soc/qcom,ipa@1e00000&quot;;
		tmc_etf_swao_out_replicator_swao = &quot;/soc/tmc@6b09000/ports/port@0/endpoint&quot;;
		sdcc1_ice = &quot;/soc/sdcc1ice@7C8000&quot;;
		gfx3d_user = &quot;/soc/qcom,kgsl-iommu@5040000/gfx3d_user&quot;;
		qupv3_se10_ctsrx = &quot;/soc/pinctrl@3400000/qupv3_se10_4uart_pins/qupv3_se10_ctsrx&quot;;
		wdog = &quot;/soc/qcom,wdt@17c10000&quot;;
		tx_cdc_dma_4_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-4-tx&quot;;
		qupv3_se10_i2c_sleep = &quot;/soc/pinctrl@3400000/qupv3_se10_i2c_pins/qupv3_se10_i2c_sleep&quot;;
		ad_hoc_bus = &quot;/soc/ad-hoc-bus&quot;;
		sb_1_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-1-rx&quot;;
		tpdm_qm = &quot;/soc/tpdm@69d0000&quot;;
		funnel_turing_out_tpda = &quot;/soc/funnel@6861000/ports/port@0/endpoint&quot;;
		incall_music_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-rx&quot;;
		slv_qhs_snoc_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-snoc-cfg&quot;;
		fpc_reset_low = &quot;/soc/pinctrl@3400000/fpc_reset_int/reset_low&quot;;
		cpu0_cpu_llcc_latmon = &quot;/soc/qcom,cpu0-cpu-llcc-latmon&quot;;
		funnel_apss_in_etm7 = &quot;/soc/funnel@7800000/ports/port@8/endpoint&quot;;
		cti2 = &quot;/soc/cti@6012000&quot;;
		wsa_cdc_dma_0_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-0-tx&quot;;
		pm6150_l2 = &quot;/soc/rpmh-regulator-ldoa2/regulator-pm6150-l2&quot;;
		cam_sensor_mclk1_active = &quot;/soc/pinctrl@3400000/cam_sensor_mclk1_active&quot;;
		etm6_out_funnel_apss = &quot;/soc/etm@7640000/port/endpoint&quot;;
		vph_lvl2 = &quot;/soc/thermal-zones/pm6150l-vph-lvl2/trips/vph-lvl2&quot;;
		funnel_apss_merg_in_tpda_llm_gold = &quot;/soc/funnel@7810000/ports/port@4/endpoint&quot;;
		oledb_vreg = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled/oledb@e000&quot;;
		mas_xm_sdc4 = &quot;/soc/ad-hoc-bus/mas-xm-sdc4&quot;;
		funnel_turing = &quot;/soc/funnel@6861000&quot;;
		tpdm_llm_gold = &quot;/soc/tpdm@78b0000&quot;;
		gmu_kernel = &quot;/soc/qcom,gmu@506a000/gmu_kernel&quot;;
		slv_ebi = &quot;/soc/ad-hoc-bus/slv-ebi&quot;;
		slv_qns_cdsp_gemnoc = &quot;/soc/ad-hoc-bus/slv-qns-cdsp-gemnoc&quot;;
		tpda_in_tpdm_vsense = &quot;/soc/tpda@6004000/ports/port@7/endpoint&quot;;
		sde_dp_aux_active = &quot;/soc/pinctrl@3400000/sde_dp_aux_active&quot;;
		pdc = &quot;/soc/interrupt-controller@b220000&quot;;
		tx_cdc_dma_1_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-1-tx&quot;;
		dai_sec_spdif_rx = &quot;/soc/qcom,msm-dai-q6-spdif-sec-rx&quot;;
		cam_fd = &quot;/soc/qcom,fd@ac5a000&quot;;
		etm6 = &quot;/soc/etm@7640000&quot;;
		skin_gpu_trip = &quot;/soc/thermal-zones/quiet-therm-step/trips/skin-gpu-trip&quot;;
		mdm_core_trip = &quot;/soc/thermal-zones/mdm-core-lowf/trips/mdm-core-trip&quot;;
		funnel_in0_in_stm = &quot;/soc/funnel@0x6041000/ports/port@4/endpoint&quot;;
		slv_qhs_qupv3_center = &quot;/soc/ad-hoc-bus/slv-qhs-qupv3-center&quot;;
		glink_spi_xprt_wdsp = &quot;/soc/qcom,glink/wdsp&quot;;
		cti1_ddr0 = &quot;/soc/cti@6a03000&quot;;
		pm6150_s3_level_ao = &quot;/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3-level-ao&quot;;
		pm6150l_l3 = &quot;/soc/rpmh-regulator-ldoc3/regulator-pm6150l-l3&quot;;
		pcie_0_gdsc = &quot;/soc/qcom,gdsc@16b004&quot;;
		funnel_in1_out_funnel_merg = &quot;/soc/funnel@6042000/ports/port@0/endpoint&quot;;
		CPU_COST_1 = &quot;/energy-costs/core-cost1&quot;;
		slv_qhs_sdc4 = &quot;/soc/ad-hoc-bus/slv-qhs-sdc4&quot;;
		sdc1_rclk_on = &quot;/soc/pinctrl@3400000/sdc1_rclk_on&quot;;
		slv_srvc_cnoc = &quot;/soc/ad-hoc-bus/slv-srvc-cnoc&quot;;
		funnel_turing1 = &quot;/soc/funnel_1@6861000&quot;;
		sleepstate_smp2p_in = &quot;/soc/qcom,smp2p-adsp/qcom,sleepstate-in&quot;;
		dai_pri_spdif_tx = &quot;/soc/qcom,msm-dai-q6-spdif-pri-tx&quot;;
		funnel_apss_merg_in_tpda_llm_silver = &quot;/soc/funnel@7810000/ports/port@3/endpoint&quot;;
		qupv3_se4_i2c_active = &quot;/soc/pinctrl@3400000/qupv3_se4_i2c_pins/qupv3_se4_i2c_active&quot;;
		mas_qhm_gemnoc_cfg = &quot;/soc/ad-hoc-bus/mas-qhm-gemnoc-cfg&quot;;
		spkr_1_sd_n_active = &quot;/soc/pinctrl@3400000/spkr_1_sd_n/spkr_1_sd_n_active&quot;;
		hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = &quot;/soc/qcom,gdsc@17d044&quot;;
		L2_400 = &quot;/cpus/cpu@400/l2-cache&quot;;
		pri_i2s_ws_active = &quot;/soc/pinctrl@3400000/pri_i2s_sck_ws/pri_i2s_ws_active&quot;;
		qupv3_se10_4uart_pins = &quot;/soc/pinctrl@3400000/qupv3_se10_4uart_pins&quot;;
		tpdm_gfx = &quot;/soc/tpdm@6940000&quot;;
		jtag_mm7 = &quot;/soc/jtagmm@7740000&quot;;
		pm6150l_torch1 = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,torch_1&quot;;
		funnel_apss_merg_out_funnel_in2 = &quot;/soc/funnel@7810000/ports/port@0/endpoint&quot;;
		slv_srvc_aggre1_noc = &quot;/soc/ad-hoc-bus/slv-srvc-aggre1-noc&quot;;
		qupv3_se4_4uart = &quot;/soc/qcom,qup_uart@0x890000&quot;;
		tpda_in_funnel_turing = &quot;/soc/tpda@6004000/ports/port@4/endpoint&quot;;
		cpu_llcc_ddr_bw = &quot;/soc/qcom,cpu-llcc-ddr-bw&quot;;
		qupv3_se0_spi = &quot;/soc/spi@0x880000&quot;;
		qupv3_se10_spi_sleep = &quot;/soc/pinctrl@3400000/qupv3_se10_spi_pins/qupv3_se10_spi_sleep&quot;;
		S5A = &quot;/soc/rpmh-regulator-smpa5/regulator-pm6150-s5&quot;;
		keepalive_opp_table = &quot;/soc/keepalive-opp-table&quot;;
		slv_qns_gemnoc_sf = &quot;/soc/ad-hoc-bus/slv-qns-gemnoc-sf&quot;;
		q6_hvx_trip0 = &quot;/soc/thermal-zones/q6-hvx-step/trips/q6-hvx-trip0&quot;;
		qupv3_se11_tx = &quot;/soc/pinctrl@3400000/qupv3_se11_4uart_pins/qupv3_se11_tx&quot;;
		cam_sensor_mclk2_active = &quot;/soc/pinctrl@3400000/cam_sensor_mclk2_active&quot;;
		pil_adsp_mem = &quot;/reserved-memory/pil_adsp_region@95700000&quot;;
		qupv3_se11_i2c = &quot;/soc/i2c@0xa94000&quot;;
		qupv3_se1_i2c_sleep = &quot;/soc/pinctrl@3400000/qupv3_se1_i2c_pins/qupv3_se1_i2c_sleep&quot;;
		i2c_freq_100Khz_cci0 = &quot;/soc/qcom,cci@ac4a000/qcom,i2c_standard_mode&quot;;
		bcm_mm3 = &quot;/soc/ad-hoc-bus/bcm-mm3&quot;;
		apcs = &quot;/soc/syscon@17c0000c&quot;;
		wsa_cdc_dma_0_rx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-0-rx&quot;;
		funnel_turing_1_out_funnel_qatb = &quot;/soc/funnel_1@6861000/ports/port@0/endpoint&quot;;
		qupv3_se6_i2c_sleep = &quot;/soc/pinctrl@3400000/qupv3_se6_i2c_pins/qupv3_se6_i2c_sleep&quot;;
		fab_system_noc = &quot;/soc/ad-hoc-bus/fab-system_noc&quot;;
		apps_rsc = &quot;/soc/mailbox@18220000&quot;;
		blue_led = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d000/blue&quot;;
		S1C = &quot;/soc/rpmh-regulator-smpc1/regulator-pm6150l-s1&quot;;
		qupv3_se2_i2c = &quot;/soc/i2c@0x888000&quot;;
		dai_meta_mi2s0 = &quot;/soc/qcom,msm-dai-q6-meta-mi2s-prim&quot;;
		bluetooth = &quot;/soc/bt_wcn3990&quot;;
		cti1_apss = &quot;/soc/cti@78f0000&quot;;
		cpu6_llcc_ddr_latmon = &quot;/soc/qcom,cpu6-llcc-ddr-latmon&quot;;
		pm6150_s3_level = &quot;/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3&quot;;
		L2_TLB_600 = &quot;/cpus/cpu@600/l2-tlb&quot;;
		sde_dp = &quot;/soc/qcom,dp_display@0&quot;;
		mdss_core_gdsc = &quot;/soc/qcom,gdsc@0f03000&quot;;
		bcm_sh5 = &quot;/soc/ad-hoc-bus/bcm-sh5&quot;;
		lmh_dcvs0 = &quot;/soc/qcom,cpucc@18321000/qcom,limits-dcvs@18358800&quot;;
		qupv3_se9_i2c_active = &quot;/soc/pinctrl@3400000/qupv3_se9_i2c_pins/qupv3_se9_i2c_active&quot;;
		disp_rsc = &quot;/soc/mailbox@af20000&quot;;
		qupv3_se9_i2c_pins = &quot;/soc/pinctrl@3400000/qupv3_se9_i2c_pins&quot;;
		mdm_dsp_trip = &quot;/soc/thermal-zones/mdm-dsp-lowf/trips/mdm-dsp-lowf-trip&quot;;
		hostless = &quot;/soc/qcom,msm-pcm-hostless&quot;;
		reserved_memory = &quot;/reserved-memory&quot;;
		qupv3_se4_spi_pins = &quot;/soc/pinctrl@3400000/qupv3_se4_spi_pins&quot;;
		pm6150l_bcl = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@4/bcl@3d00&quot;;
		cam_lrme = &quot;/soc/qcom,lrme@ac6b000&quot;;
		dai_hdmi_ms = &quot;/soc/qcom,msm-dai-q6-hdmi_ms&quot;;
		cti1_dlmm = &quot;/soc/cti@69C2000&quot;;
		tpdm_pimem = &quot;/soc/tpdm@6850000&quot;;
		cti0_dlct = &quot;/soc/cti@6c29000&quot;;
		qupv3_se4_spi = &quot;/soc/spi@0x890000&quot;;
		cti3_swao = &quot;/soc/cti@6b07000&quot;;
		replicator1_out_funnel_swao = &quot;/soc/replicator@604a000/ports/port@0/endpoint&quot;;
		dai_pri_spdif_rx = &quot;/soc/qcom,msm-dai-q6-spdif-pri-rx&quot;;
		gold_trip = &quot;/soc/thermal-zones/quiet-therm-step/trips/gold-trip&quot;;
		tpda_modem1 = &quot;/soc/tpda@6833000&quot;;
		gpi_dma1 = &quot;/soc/qcom,gpi-dma@0xa00000&quot;;
		dai_sec_auxpcm = &quot;/soc/qcom,msm-sec-auxpcm&quot;;
		tpdm_turing_out_funnel_turing = &quot;/soc/tpdm@6860000/port/endpoint&quot;;
		funnel_modem_in_tpda_modem_0 = &quot;/soc/funnel@6832000/ports/port@1/endpoint&quot;;
		batt_trip3 = &quot;/soc/thermal-zones/quiet-therm-step/trips/batt-trip3&quot;;
		tpdm_dl_south = &quot;/soc/tpdm@6b52000&quot;;
		suspendable_ddr_bw_opp_table = &quot;/soc/suspendable-ddr-bw-opp-table&quot;;
		tpdm_dl_center_out_tpda = &quot;/soc/tpdm@6c28000/port/endpoint&quot;;
		pm6150l_wled = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800&quot;;
		funnel_dl_south_out_tpda = &quot;/soc/funnel@6b53000/ports/port@0/endpoint&quot;;
		funnel_apss_in_etm5 = &quot;/soc/funnel@7800000/ports/port@6/endpoint&quot;;
		pil_modem_mem = &quot;/reserved-memory/modem_region@8b000000&quot;;
		bcm_sn1 = &quot;/soc/ad-hoc-bus/bcm-sn1&quot;;
		qupv3_se6_i2c = &quot;/soc/i2c@0xa80000&quot;;
		tmc_etf_out_replicator = &quot;/soc/tmc@6047000/ports/port@0/endpoint&quot;;
		pm6150l_gpios = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@4/pinctrl@c000&quot;;
		cti0 = &quot;/soc/cti@6010000&quot;;
		tpdm_lpass_out_funnel_in0 = &quot;/soc/dummy_source/port/endpoint&quot;;
		cti_venus_arm9 = &quot;/soc/cti@6c20000&quot;;
		llcc = &quot;/soc/qcom,llcc@9200000/qcom,sdmmagpie-llcc&quot;;
		mas_qxm_camnoc_sf_uncomp = &quot;/soc/ad-hoc-bus/mas-qxm-camnoc-sf-uncomp&quot;;
		vph_lvl0 = &quot;/soc/thermal-zones/pm6150l-vph-lvl0/trips/vph-lvl0&quot;;
		dai_dp = &quot;/soc/qcom,msm-dai-q6-dp&quot;;
		mas_xm_sdc2 = &quot;/soc/ad-hoc-bus/mas-xm-sdc2&quot;;
		cam_sensor_mclk3_active = &quot;/soc/pinctrl@3400000/cam_sensor_mclk3_active&quot;;
		tdm_tert_tx = &quot;/soc/qcom,msm-dai-tdm-tert-tx&quot;;
		qupv3_se1_spi_sleep = &quot;/soc/pinctrl@3400000/qupv3_se1_spi_pins/qupv3_se1_spi_sleep&quot;;
		qupv3_se0_i2c_pins = &quot;/soc/pinctrl@3400000/qupv3_se0_i2c_pins&quot;;
		vbat_lvl2 = &quot;/soc/thermal-zones/pm6150-vbat-lvl2/trips/vbat-lvl2&quot;;
		qupv3_se6_spi_sleep = &quot;/soc/pinctrl@3400000/qupv3_se6_spi_pins/qupv3_se6_spi_sleep&quot;;
		cpu0_llcc_ddr_lat = &quot;/soc/qcom,cpu0-llcc-ddr-lat&quot;;
		swr1 = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/rx-macro@62ee0000/rx_swr_master&quot;;
		replicator_out_tmc_etr = &quot;/soc/replicator@6046000/ports/port@0/endpoint&quot;;
		slv_xs_qdss_stm = &quot;/soc/ad-hoc-bus/slv-xs-qdss-stm&quot;;
		qupv3_se8_spi = &quot;/soc/spi@0xa88000&quot;;
		pcm1 = &quot;/soc/qcom,msm-pcm-low-latency&quot;;
		etm4 = &quot;/soc/etm@7440000&quot;;
		funnel_dl_mm = &quot;/soc/funnel@69C3000&quot;;
		VDD_GFX_LEVEL = &quot;/soc/rpmh-regulator-gfxlvl/regulator-pm6150-s2-level&quot;;
		bcm_alc_display = &quot;/soc/ad-hoc-bus/bcm-alc_display&quot;;
		qupv3_se8_2uart_pins = &quot;/soc/pinctrl@3400000/qupv3_se8_2uart_pins&quot;;
		l_bcl_lvl1 = &quot;/soc/thermal-zones/pm6150l-bcl-lvl1/trips/l-bcl-lvl1&quot;;
		pm6150l_l1 = &quot;/soc/rpmh-regulator-ldoc1/regulator-pm6150l-l1&quot;;
		va_cdc_dma_1_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-1-tx&quot;;
		slv_qhs_sdc2 = &quot;/soc/ad-hoc-bus/slv-qhs-sdc2&quot;;
		tpdm_qm_out_tpda = &quot;/soc/tpdm@69d0000/port/endpoint&quot;;
		slv_qhs_spdm = &quot;/soc/ad-hoc-bus/slv-qhs-spdm&quot;;
		qupv3_se11_spi_active = &quot;/soc/pinctrl@3400000/qupv3_se11_spi_pins/qupv3_se11_spi_active&quot;;
		tpdm_modem_1_out_tpda_modem_1 = &quot;/soc/tpdm@6834000/port/endpoint&quot;;
		L2_700 = &quot;/cpus/cpu@700/l2-cache&quot;;
		mas_xm_qdss_etr = &quot;/soc/ad-hoc-bus/mas-xm-qdss-etr&quot;;
		sde_dp_usbplug_cc_suspend = &quot;/soc/pinctrl@3400000/sde_dp_usbplug_cc_suspend&quot;;
		firmware = &quot;/firmware&quot;;
		cpu_llcc_ddr_bwmon = &quot;/soc/qcom,cpu-llcc-ddr-bwmon@90cd000&quot;;
		mdss_dsi_phy1 = &quot;/soc/qcom,mdss_dsi_phy1@ae96400&quot;;
		jtag_mm5 = &quot;/soc/jtagmm@7540000&quot;;
		cti_titan = &quot;/soc/cti@6c13000&quot;;
		msm_vidc0 = &quot;/soc/qcom,vidc0&quot;;
		anoc_1_pcie_tbu = &quot;/soc/apps-smmu@0x15000000/anoc_1_pcie_tbu@0x151a1000&quot;;
		slv_xs_sys_tcu_cfg = &quot;/soc/ad-hoc-bus/slv-xs-sys-tcu-cfg&quot;;
		pm6150_l18 = &quot;/soc/rpmh-regulator-ldoa18/regulator-pm6150-l18&quot;;
		etm5_out_funnel_apss = &quot;/soc/etm@7540000/port/endpoint&quot;;
		llcc_pmu = &quot;/soc/llcc-pmu@90cc000&quot;;
		ab_vreg = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled/ab@de00&quot;;
		tpdm_llm_silver_out_tpda_llm_silver = &quot;/soc/tpdm@78a0000/port/endpoint&quot;;
		qupv3_se10_i2c_active = &quot;/soc/pinctrl@3400000/qupv3_se10_i2c_pins/qupv3_se10_i2c_active&quot;;
		mas_llcc_mc_display = &quot;/soc/ad-hoc-bus/mas-llcc-mc_display&quot;;
		CPU7 = &quot;/cpus/cpu@700&quot;;
		pm8009_s1 = &quot;/soc/rpmh-regulator-smpf1/regulator-pm8009-s1&quot;;
		bcm_mm1 = &quot;/soc/ad-hoc-bus/bcm-mm1&quot;;
		L1_DTLB_700 = &quot;/cpus/cpu@700/l1-dtlb&quot;;
		tpdm_wcss = &quot;/soc/tpdm@699c000&quot;;
		ufshc_mem = &quot;/soc/ufshc@1d84000&quot;;
		rx_cdc_dma_7_rx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-7-rx&quot;;
		pil_cdsp_mem = &quot;/reserved-memory/cdsp_regions@93900000&quot;;
		tdm_tert_rx = &quot;/soc/qcom,msm-dai-tdm-tert-rx&quot;;
		funnel_in0_out_funnel_merg = &quot;/soc/funnel@0x6041000/ports/port@0/endpoint&quot;;
		sdc1_clk_off = &quot;/soc/pinctrl@3400000/sdc1_clk_off&quot;;
		BOB_AO = &quot;/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob-ao&quot;;
		tpda_modem_0_in_tpdm_modem_0 = &quot;/soc/tpda@6831000/ports/port@1/endpoint&quot;;
		slv_qhs_aoss = &quot;/soc/ad-hoc-bus/slv-qhs-aoss&quot;;
		sdc1_data_off = &quot;/soc/pinctrl@3400000/sdc1_data_off&quot;;
		cti9 = &quot;/soc/cti@6019000&quot;;
		bcm_sh3 = &quot;/soc/ad-hoc-bus/bcm-sh3&quot;;
		pm6150_l9 = &quot;/soc/rpmh-regulator-ldoa9/regulator-pm6150-l9&quot;;
		qupv3_se3_tx = &quot;/soc/pinctrl@3400000/qupv3_se3_4uart_pins/qupv3_se3_tx&quot;;
		pm8009_l6 = &quot;/soc/rpmh-regulator-ldof6/regulator-pm8009-l6&quot;;
		L2_0 = &quot;/cpus/cpu@0/l2-cache&quot;;
		cam_sensor_mclk0_suspend = &quot;/soc/pinctrl@3400000/cam_sensor_mclk0_suspend&quot;;
		ufs_dev_reset_deassert = &quot;/soc/pinctrl@3400000/ufs_dev_reset_deassert&quot;;
		rsc_disp = &quot;/soc/ad-hoc-bus/rsc-disp&quot;;
		refgen = &quot;/soc/refgen-regulator@ff1000&quot;;
		cpu6_cpu_llcc_latmon = &quot;/soc/qcom,cpu6-cpu-llcc-latmon&quot;;
		L9C = &quot;/soc/rpmh-regulator-ldoc9/regulator-pm6150l-l9&quot;;
		qmp_aop = &quot;/soc/qcom,qmp-aop@c300000&quot;;
		tpda_in_tpdm_prng = &quot;/soc/tpda@6004000/ports/port@8/endpoint&quot;;
		funnel_gfx_in_tpdm_gfx = &quot;/soc/funnel@6943000/ports/port@1/endpoint&quot;;
		rx_cdc_dma_4_rx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-4-rx&quot;;
		fpc_reset_high = &quot;/soc/pinctrl@3400000/fpc_reset_int/reset_high&quot;;
		tpdm_dl_mm = &quot;/soc/tpdm@69c0000&quot;;
		msm_audio_ion = &quot;/soc/qcom,msm-audio-apr/qcom,msm-audio-ion&quot;;
		modem_skin = &quot;/soc/qmi-tmd-devices/modem/modem_skin&quot;;
		npu_trip = &quot;/soc/thermal-zones/npu-lowf/trips/npu-trip&quot;;
		ife_1_gdsc = &quot;/soc/qcom,gdsc@ad0b004&quot;;
		cti0_ddr0 = &quot;/soc/cti@6a02000&quot;;
		mas_qxm_mdp1 = &quot;/soc/ad-hoc-bus/mas-qxm-mdp1&quot;;
		slim_qca = &quot;/soc/slim@62e40000&quot;;
		bolero = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc&quot;;
		tpdm_npu_out_tpda = &quot;/soc/tpdm@69e1000/port/endpoint&quot;;
		L1_I_200 = &quot;/cpus/cpu@200/l1-icache&quot;;
		smartpa_int_suspend = &quot;/soc/pinctrl@3400000/smartpa_int_suspend&quot;;
		loopback1 = &quot;/soc/qcom,msm-pcm-loopback-low-latency&quot;;
		funnel_dl_mm_out_tpda = &quot;/soc/funnel@69C3000/ports/port@0/endpoint&quot;;
		tpdm_lpass = &quot;/soc/dummy_source&quot;;
		batt_trip1 = &quot;/soc/thermal-zones/quiet-therm-step/trips/batt-trip1&quot;;
		slv_qhs_mnoc_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-mnoc-cfg&quot;;
		slv_qhs_cpr_mx = &quot;/soc/ad-hoc-bus/slv-qhs-cpr-mx&quot;;
		tpdm_qdss_out_tpda = &quot;/soc/tpdm@6006000/port/endpoint&quot;;
		tpda_in_funnel_ddr_0 = &quot;/soc/tpda@6004000/ports/port@5/endpoint&quot;;
		tpdm_modem_0_out_tpda_modem_0 = &quot;/soc/tpdm@6830000/port/endpoint&quot;;
		sm6150_snd = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/sound&quot;;
		qcom_seecom = &quot;/soc/qseecom@86d00000&quot;;
		funnel_apss_in_etm3 = &quot;/soc/funnel@7800000/ports/port@4/endpoint&quot;;
		tpdm_center_out_tpda = &quot;/soc/tpdm@6b44000/port/endpoint&quot;;
		tpdm_vsense_out_tpda = &quot;/soc/tpdm@6840000/port/endpoint&quot;;
		L1_D_100 = &quot;/cpus/cpu@100/l1-dcache&quot;;
		qupv3_se3_spi_active = &quot;/soc/pinctrl@3400000/qupv3_se3_spi_pins/qupv3_se3_spi_active&quot;;
		rx_cdc_dma_1_rx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-1-rx&quot;;
		sdc1_cmd_off = &quot;/soc/pinctrl@3400000/sdc1_cmd_off&quot;;
		qupv3_se4_rts = &quot;/soc/pinctrl@3400000/qupv3_se4_4uart_pins/qupv3_se4_rts&quot;;
		usb30_prim_gdsc = &quot;/soc/qcom,gdsc@10f004&quot;;
		tpda_in_tpdm_qm = &quot;/soc/tpda@6004000/ports/port@10/endpoint&quot;;
		usb0 = &quot;/soc/ssusb@a600000&quot;;
		L8C = &quot;/soc/rpmh-regulator-ldoc8/regulator-pm6150l-l8&quot;;
		smb5_vbus = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,qpnp-smb5/qcom,smb5-vbus&quot;;
		CLUSTER_COST_1 = &quot;/energy-costs/cluster-cost1&quot;;
		slv_qns_gem_noc_snoc = &quot;/soc/ad-hoc-bus/slv-qns-gem-noc-snoc&quot;;
		qupv3_se0_spi_pins = &quot;/soc/pinctrl@3400000/qupv3_se0_spi_pins&quot;;
		cpu6_cpu_l3_lat = &quot;/soc/qcom,cpu6-cpu-l3-lat&quot;;
		vbat_lvl0 = &quot;/soc/thermal-zones/pm6150-vbat-lvl0/trips/vbat-lvl0&quot;;
		usb_nop_phy = &quot;/soc/usb_nop_phy&quot;;
		cpu0_config = &quot;/soc/thermal-zones/cpu-0-0-step/trips/cpu0-config&quot;;
		etm2 = &quot;/soc/etm@7240000&quot;;
		cam_ipe1 = &quot;/soc/qcom,ipe1&quot;;
		iommu_qupv3_0_geni_se_cb = &quot;/soc/qcom,qupv3_0_geni_se@0x8c0000/qcom,iommu_qupv3_0_geni_se_cb&quot;;
		replicator_swao_out_eud = &quot;/soc/replicator@6b0a000/ports/port@0/endpoint&quot;;
		turing_etm0_out_funnel_turing_1 = &quot;/soc/turing_etm0/port/endpoint&quot;;
		funnel_merg_in_funnel_in2 = &quot;/soc/funnel@6045000/ports/port@3/endpoint&quot;;
		mas_qxm_mdp0_display = &quot;/soc/ad-hoc-bus/mas-qxm-mdp0_display&quot;;
		energy_costs = &quot;/energy-costs&quot;;
		sdc2_cd_on = &quot;/soc/pinctrl@3400000/cd_on&quot;;
		qupv3_se2_i2c_active = &quot;/soc/pinctrl@3400000/qupv3_se2_i2c_pins/qupv3_se2_i2c_active&quot;;
		pri_i2s_sck_active = &quot;/soc/pinctrl@3400000/pri_i2s_sck_ws/pri_i2s_sck_active&quot;;
		sb_9_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-9-tx&quot;;
		msm_dai_cdc_dma = &quot;/soc/qcom,msm-dai-cdc-dma&quot;;
		mas_qnm_cnoc = &quot;/soc/ad-hoc-bus/mas-qnm-cnoc&quot;;
		secure_display_memory = &quot;/reserved-memory/secure_display_region&quot;;
		funnel_dl_mm_in_tpdm_dl_mm = &quot;/soc/funnel@69C3000/ports/port@1/endpoint&quot;;
		cti0_apss = &quot;/soc/cti@78e0000&quot;;
		VDD_MX_LEVEL = &quot;/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3&quot;;
		glink_adsp = &quot;/soc/qcom,glink/adsp&quot;;
		mas_xm_ufs_mem = &quot;/soc/ad-hoc-bus/mas-xm-ufs-mem&quot;;
		pm6150l_bob = &quot;/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob&quot;;
		pm6150l_adc_tm = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@4/adc_tm@3500&quot;;
		mas_qhm_qup_north = &quot;/soc/ad-hoc-bus/mas-qhm-qup-north&quot;;
		L7C = &quot;/soc/rpmh-regulator-ldoc7/regulator-pm6150l-l7&quot;;
		dai_mi2s5 = &quot;/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-senary&quot;;
		dai_sec_tdm_tx_0 = &quot;/soc/qcom,msm-dai-tdm-sec-tx/qcom,msm-dai-q6-tdm-sec-tx-0&quot;;
		xbl_aop_mem = &quot;/reserved-memory/xbl_aop_mem@85e00000&quot;;
		cdsp_smp2p_out = &quot;/soc/qcom,smp2p-cdsp/master-kernel&quot;;
		slv_qhs_ddrss_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-ddrss-cfg&quot;;
		compress = &quot;/soc/qcom,msm-compress-dsp&quot;;
		qupv3_se8_spi_active = &quot;/soc/pinctrl@3400000/qupv3_se8_spi_pins/qupv3_se8_spi_active&quot;;
		jtag_mm3 = &quot;/soc/jtagmm@7340000&quot;;
		smp2p_wlan_1_in = &quot;/soc/qcom,smp2p-modem/qcom,smp2p-wlan-1-in&quot;;
		pm6150l_l11 = &quot;/soc/rpmh-regulator-ldoc11/regulator-pm6150l-l11&quot;;
		slv_qhs_display_throttle_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-display-throttle-cfg&quot;;
		qupv3_1 = &quot;/soc/qcom,qupv3_1_geni_se@0xac0000&quot;;
		pm6150_gpios = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/pinctrl@c000&quot;;
		cti0_dlmm = &quot;/soc/cti@69C1000&quot;;
		funnel_qatb_in_funnel_turing_1 = &quot;/soc/funnel@6005000/ports/port@3/endpoint&quot;;
		cam_csid_lite0 = &quot;/soc/qcom,csid-lite0@acc8000&quot;;
		cti2_swao = &quot;/soc/cti@6b06000&quot;;
		sdhc_1 = &quot;/soc/sdhci@7c4000&quot;;
		sec_apps_mem = &quot;/reserved-memory/sec_apps_region@85fff000&quot;;
		trans_loopback = &quot;/soc/qcom,msm-transcode-loopback&quot;;
		pm6150_l16 = &quot;/soc/rpmh-regulator-ldoa16/regulator-pm6150-l16&quot;;
		gpu_gx_domain_addr = &quot;/soc/syscon@0x5091508&quot;;
		funnel_apss_merg = &quot;/soc/funnel@7810000&quot;;
		bt_sco_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-tx&quot;;
		stub_codec = &quot;/soc/qcom,msm-stub-codec&quot;;
		mas_qxm_venus_arm9 = &quot;/soc/ad-hoc-bus/mas-qxm-venus-arm9&quot;;
		funnel_dl_south_1_in_tpdm_wcss = &quot;/soc/funnel_1@6b53000/ports/port@1/endpoint&quot;;
		CPU5 = &quot;/cpus/cpu@500&quot;;
		sde_rscc = &quot;/soc/qcom,sde_rscc@af20000&quot;;
		gmu = &quot;/soc/qcom,gmu@506a000&quot;;
		pm6150l_bob_ao = &quot;/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob-ao&quot;;
		funnel_in1 = &quot;/soc/funnel@6042000&quot;;
		slv_qhs_pcie_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-pcie-cfg&quot;;
		tpdm_modem0 = &quot;/soc/tpdm@6830000&quot;;
		sp_mem = &quot;/reserved-memory/sp_region&quot;;
		smartpa_enable_suspend = &quot;/soc/pinctrl@3400000/smartpa_enable_suspend&quot;;
		qupv3_se7_i2c_active = &quot;/soc/pinctrl@3400000/qupv3_se7_i2c_pins/qupv3_se7_i2c_active&quot;;
		L6C = &quot;/soc/rpmh-regulator-ldoc6/regulator-pm6150l-l6&quot;;
		qupv3_se4_i2c_sleep = &quot;/soc/pinctrl@3400000/qupv3_se4_i2c_pins/qupv3_se4_i2c_sleep&quot;;
		mas_qxm_rot = &quot;/soc/ad-hoc-bus/mas-qxm-rot&quot;;
		spkr_1_sd_n_sleep = &quot;/soc/pinctrl@3400000/spkr_1_sd_n/spkr_1_sd_n_sleep&quot;;
		i2c_freq_400Khz_cci0 = &quot;/soc/qcom,cci@ac4a000/qcom,i2c_fast_mode&quot;;
		npu_mem = &quot;/reserved-memory/npu_region@97e80000&quot;;
		nfc_enable_suspend = &quot;/soc/pinctrl@3400000/nfc/nfc_enable_suspend&quot;;
		sde_te_active = &quot;/soc/pinctrl@3400000/pmx_sde_te/sde_te_active&quot;;
		sb_3_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-3-tx&quot;;
		qupv3_se9_i2c_sleep = &quot;/soc/pinctrl@3400000/qupv3_se9_i2c_pins/qupv3_se9_i2c_sleep&quot;;
		funnel_swao = &quot;/soc/funnel@6b08000&quot;;
		cpu1_config = &quot;/soc/thermal-zones/cpu-0-1-step/trips/cpu1-config&quot;;
		cti7 = &quot;/soc/cti@6017000&quot;;
		anoc_1_tbu = &quot;/soc/apps-smmu@0x15000000/anoc_1_tbu@0x15185000&quot;;
		pm8009_l4 = &quot;/soc/rpmh-regulator-ldof4/regulator-pm8009-l4&quot;;
		bus_proxy_client = &quot;/soc/qcom,bus_proxy_client&quot;;
		bcm_ip0 = &quot;/soc/ad-hoc-bus/bcm-ip0&quot;;
		pwm_lpg3 = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,pwms@b100/lpg3&quot;;
		L9A = &quot;/soc/rpmh-regulator-ldoa9/regulator-pm6150-l9&quot;;
		pm6150l_flash1 = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,flash_1&quot;;
		qupv3_se11_ctsrx = &quot;/soc/pinctrl@3400000/qupv3_se11_4uart_pins/qupv3_se11_ctsrx&quot;;
		bcm_mm1_display = &quot;/soc/ad-hoc-bus/bcm-mm1_display&quot;;
		L1_I_500 = &quot;/cpus/cpu@500/l1-icache&quot;;
		cdsp_cdsp_l3_lat = &quot;/soc/qcom,cdsp-cdsp-l3-lat&quot;;
		sb_9_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-9-rx&quot;;
		msm_npu = &quot;/soc/qcom,msm_npu@9800000&quot;;
		mas_acm_sys_tcu = &quot;/soc/ad-hoc-bus/mas-acm-sys-tcu&quot;;
		slv_qxs_imem = &quot;/soc/ad-hoc-bus/slv-qxs-imem&quot;;
		ts_active = &quot;/soc/pinctrl@3400000/pmx_ts_active/ts_active&quot;;
		sleep_clk = &quot;/soc/clocks/sleep-clk&quot;;
		sb_0_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-0-tx&quot;;
		etm4_out_funnel_apss = &quot;/soc/etm@7440000/port/endpoint&quot;;
		L2_TLB_200 = &quot;/cpus/cpu@200/l2-tlb&quot;;
		pm6150l_l8 = &quot;/soc/rpmh-regulator-ldoc8/regulator-pm6150l-l8&quot;;
		L1_D_400 = &quot;/cpus/cpu@400/l1-dcache&quot;;
		L5C = &quot;/soc/rpmh-regulator-ldoc5/regulator-pm6150l-l5&quot;;
		mas_qhm_qup_center = &quot;/soc/ad-hoc-bus/mas-qhm-qup-center&quot;;
		LLCC_2 = &quot;/soc/qcom,llcc@9200000/llcc_2_dcache&quot;;
		L1_D_0 = &quot;/cpus/cpu@0/l1-dcache&quot;;
		funnel_apss_in_etm1 = &quot;/soc/funnel@7800000/ports/port@2/endpoint&quot;;
		bcl_lvl2 = &quot;/soc/thermal-zones/pm6150-bcl-lvl2/trips/bcl-lvl2&quot;;
		slv_qhs_tlmm_south = &quot;/soc/ad-hoc-bus/slv-qhs-tlmm-south&quot;;
		VDD_MSS_LEVEL = &quot;/soc/rpmh-regulator-modemlvl/regulator-pm6150l-s7&quot;;
		slv_qhs_ahb2phy_north = &quot;/soc/ad-hoc-bus/slv-qhs-ahb2phy-north&quot;;
		cci0_suspend = &quot;/soc/pinctrl@3400000/cci0_suspend&quot;;
		slv_qns_a1noc_snoc = &quot;/soc/ad-hoc-bus/slv-qns-a1noc-snoc&quot;;
		cpu6_0_config = &quot;/soc/thermal-zones/cpu-1-0-step/trips/cpu6-0-config&quot;;
		tpdm_gfx_out_funnel_gfx = &quot;/soc/tpdm@6940000/port/endpoint&quot;;
		fd_iova_mem_map = &quot;/soc/qcom,cam_smmu/msm_cam_smmu_fd/iova-mem-map&quot;;
		qcom_cedev = &quot;/soc/qcedev@1de0000&quot;;
		tpdm_ddr = &quot;/soc/tpdm@6a00000&quot;;
		sb_6_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-6-rx&quot;;
		cam_cci1 = &quot;/soc/qcom,cci@ac4b000&quot;;
		mas_qxm_crypto = &quot;/soc/ad-hoc-bus/mas-qxm-crypto&quot;;
		loopback = &quot;/soc/qcom,msm-pcm-loopback&quot;;
		bt_sco_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-rx&quot;;
		LPI_MX_LEVEL = &quot;/soc/rpmh-regulator-lmxlvl/regulator-pm6150-l7&quot;;
		qupv3_se10_spi = &quot;/soc/spi@0xa90000&quot;;
		wsa_swr_clk_sleep = &quot;/soc/pinctrl@3400000/wsa_swr_clk_pin/wsa_swr_clk_sleep&quot;;
		fab_aggre1_noc = &quot;/soc/ad-hoc-bus/fab-aggre1_noc&quot;;
		mas_qhm_tsif = &quot;/soc/ad-hoc-bus/mas-qhm-tsif&quot;;
		dai_pri_tdm_tx_0 = &quot;/soc/qcom,msm-dai-tdm-pri-tx/qcom,msm-dai-q6-tdm-pri-tx-0&quot;;
		rsc_apps = &quot;/soc/ad-hoc-bus/rsc-apps&quot;;
		slv_srvc_aggre2_noc = &quot;/soc/ad-hoc-bus/slv-srvc-aggre2-noc&quot;;
		cam_sensor_mclk2_suspend = &quot;/soc/pinctrl@3400000/cam_sensor_mclk2_suspend&quot;;
		pm6150l_trip0 = &quot;/soc/thermal-zones/pm6150l-tz/trips/trip0&quot;;
		tpda_in_funnel_dl_south = &quot;/soc/tpda@6004000/ports/port@3/endpoint&quot;;
		wled_flash = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800/qcom,wled-flash&quot;;
		qupv3_se1_spi = &quot;/soc/spi@0x884000&quot;;
		slv_qhs_mdsp_ms_mpu_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-mdsp-ms-mpu-cfg&quot;;
		etm0 = &quot;/soc/etm@7040000&quot;;
		cti2_wcss = &quot;/soc/cti@69a6000&quot;;
		slv_qxs_pimem = &quot;/soc/ad-hoc-bus/slv-qxs-pimem&quot;;
		qupv3_se4_spi_sleep = &quot;/soc/pinctrl@3400000/qupv3_se4_spi_pins/qupv3_se4_spi_sleep&quot;;
		cam_vfe0 = &quot;/soc/qcom,vfe0@acaf000&quot;;
		dai_sen_tdm_rx_0 = &quot;/soc/qcom,msm-dai-tdm-sen-rx/qcom,msm-dai-q6-tdm-sen-rx-0&quot;;
		funnel_merg_in_funnel_in0 = &quot;/soc/funnel@6045000/ports/port@1/endpoint&quot;;
		L4C = &quot;/soc/rpmh-regulator-ldoc4/regulator-pm6150l-l4&quot;;
		pm6150_l7_level = &quot;/soc/rpmh-regulator-lmxlvl/regulator-pm6150-l7&quot;;
		qmp_npu0 = &quot;/soc/qcom,qmp-npu-low@9818000&quot;;
		funnel_in0_in_audio_etm0 = &quot;/soc/funnel@0x6041000/ports/port@2/endpoint&quot;;
		cpu2_config = &quot;/soc/thermal-zones/cpu-0-2-step/trips/cpu2-config&quot;;
		dump_mem = &quot;/reserved-memory/mem_dump_region&quot;;
		slv_srvc_snoc = &quot;/soc/ad-hoc-bus/slv-srvc-snoc&quot;;
		replicator_qdss = &quot;/soc/replicator@6046000&quot;;
		sb_3_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-3-rx&quot;;
		smb5_vconn = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,qpnp-smb5/qcom,smb5-vconn&quot;;
		cam_csiphy3 = &quot;/soc/qcom,csiphy@ace6000&quot;;
		cti2_ddr1 = &quot;/soc/cti@6a12000&quot;;
		tpda_in_tpdm_center = &quot;/soc/tpda@6004000/ports/port@13/endpoint&quot;;
		pil_gpu = &quot;/soc/qcom,kgsl-hyp&quot;;
		qupv3_se10_4uart = &quot;/soc/qcom,qup_uart@0xa90000&quot;;
		qupv3_se3_i2c = &quot;/soc/i2c@0x88c000&quot;;
		wsa_cdc_dma_2_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-2-tx&quot;;
		qupv3_se10_i2c_pins = &quot;/soc/pinctrl@3400000/qupv3_se10_i2c_pins&quot;;
		ibat_lvl0 = &quot;/soc/thermal-zones/pm6150-ibat-lvl0/trips/ibat-lvl0&quot;;
		slv_qhs_a2_noc_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-a2-noc-cfg&quot;;
		tpda_in_tpdm_north = &quot;/soc/tpda@6004000/ports/port@9/endpoint&quot;;
		cam_jpeg_enc = &quot;/soc/qcom,jpegenc@ac4e000&quot;;
		cti14 = &quot;/soc/cti@601e000&quot;;
		dai_mi2s3 = &quot;/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quat&quot;;
		modem_trip2 = &quot;/soc/thermal-zones/quiet-therm-step/trips/modem-trip2&quot;;
		funnel_qatb_out_funnel_in0 = &quot;/soc/funnel@6005000/ports/port@0/endpoint&quot;;
		cci0_active = &quot;/soc/pinctrl@3400000/cci0_active&quot;;
		mas_qxm_pimem = &quot;/soc/ad-hoc-bus/mas-qxm-pimem&quot;;
		aoss0_trip = &quot;/soc/thermal-zones/aoss-0-lowf/trips/aoss0-trip&quot;;
		mas_qnm_snoc_sf = &quot;/soc/ad-hoc-bus/mas-qnm-snoc-sf&quot;;
		qupv3_se1_i2c_pins = &quot;/soc/pinctrl@3400000/qupv3_se1_i2c_pins&quot;;
		WCSS_CX = &quot;/soc/rpmh-regulator-ldoa9/regulator-pm6150-l9&quot;;
		jtag_mm1 = &quot;/soc/jtagmm@7140000&quot;;
		pm6150l_s2_level = &quot;/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2&quot;;
		mnoc_hf_0_tbu = &quot;/soc/apps-smmu@0x15000000/mnoc_hf_0_tbu@0x1518d000&quot;;
		cam_vfe_lite0 = &quot;/soc/qcom,vfe-lite0@acc4000&quot;;
		slv_qhs_camera_nrt_throttle_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-camera-nrt-thrott-cfg&quot;;
		slv_qhs_ufs_mem_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-ufs-mem-cfg&quot;;
		cmd_db = &quot;/soc/qcom,cmd-db@c3f000c&quot;;
		cpu6_computemon = &quot;/soc/qcom,cpu6-computemon&quot;;
		nfc_clk_req_active = &quot;/soc/pinctrl@3400000/nfc/nfc_clk_req_active&quot;;
		tpdm_apss_out_tpda_apss = &quot;/soc/tpdm@7860000/port/endpoint&quot;;
		tx_cdc_dma_3_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-3-tx&quot;;
		ife_0_gdsc = &quot;/soc/qcom,gdsc@ad0a004&quot;;
		pm6150_l14 = &quot;/soc/rpmh-regulator-ldoa14/regulator-pm6150-l14&quot;;
		sb_0_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-0-rx&quot;;
		slv_qns2_mem_noc = &quot;/soc/ad-hoc-bus/slv-qns2-mem-noc&quot;;
		L3C = &quot;/soc/rpmh-regulator-ldoc3/regulator-pm6150l-l3&quot;;
		slv_srvc_gemnoc = &quot;/soc/ad-hoc-bus/slv-srvc-gemnoc&quot;;
		bcm_sn14 = &quot;/soc/ad-hoc-bus/bcm-sn14&quot;;
		L2_300 = &quot;/cpus/cpu@300/l2-cache&quot;;
		CPU3 = &quot;/cpus/cpu@300&quot;;
		cpu6_1_config = &quot;/soc/thermal-zones/cpu-1-1-step/trips/cpu6-1-config&quot;;
		pm8009_gpios = &quot;/soc/qcom,spmi@c440000/qcom,pm8009@a/pinctrl@c000&quot;;
		soc_trip = &quot;/soc/thermal-zones/soc/trips/soc-trip&quot;;
		pm6150l_vadc = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@4/vadc@3100&quot;;
		gpuss_0_trip = &quot;/soc/thermal-zones/gpuss-0-lowf/trips/gpuss-0-trip&quot;;
		S2C_LEVEL = &quot;/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2&quot;;
		npu_npu_ddr_bwmon = &quot;/soc/qcom,npu-npu-ddr-bwmon@9960300&quot;;
		qusb_phy0 = &quot;/soc/qusb@88e2000&quot;;
		replicator_out_replicator1_in = &quot;/soc/replicator@6046000/ports/port@1/endpoint&quot;;
		L6A = &quot;/soc/rpmh-regulator-ldoa6/regulator-pm6150-l6&quot;;
		tlmm = &quot;/soc/pinctrl@3400000&quot;;
		bcm_sh10 = &quot;/soc/ad-hoc-bus/bcm-sh10&quot;;
		int_fm_tx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-tx&quot;;
		qupv3_se7_i2c = &quot;/soc/i2c@0xa84000&quot;;
		tx_cdc_dma_0_tx = &quot;/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-0-tx&quot;;
		cti5 = &quot;/soc/cti@6015000&quot;;
		apps_smmu = &quot;/soc/apps-smmu@0x15000000&quot;;
		pm6150_l5 = &quot;/soc/rpmh-regulator-ldoa5/regulator-pm6150-l5&quot;;
		pm8009_l2 = &quot;/soc/rpmh-regulator-ldof2/regulator-pm8009-l2&quot;;
		pm6150l_s1 = &quot;/soc/rpmh-regulator-smpc1/regulator-pm6150l-s1&quot;;
		tmc_etf_in_funnel_merg = &quot;/soc/tmc@6047000/ports/port@1/endpoint&quot;;
		cpu3_config = &quot;/soc/thermal-zones/cpu-0-3-step/trips/cpu3-config&quot;;
		cam_csid1 = &quot;/soc/qcom,csid1@acba000&quot;;
		msm_cam_smmu = &quot;/soc/qcom,cam_smmu&quot;;
		L2C = &quot;/soc/rpmh-regulator-ldoc2/regulator-pm6150l-l2&quot;;
		ipe_1_gdsc = &quot;/soc/qcom,gdsc@ad09004&quot;;
		removed_region = &quot;/reserved-memory/removed_region@86200000&quot;;
		slv_qns_llcc = &quot;/soc/ad-hoc-bus/slv-qns-llcc&quot;;
		gfx3d_secure = &quot;/soc/qcom,kgsl-iommu@5040000/gfx3d_secure&quot;;
		cpu6_cpu_llcc_lat = &quot;/soc/qcom,cpu6-cpu-llcc-lat&quot;;
		pcm_dtmf = &quot;/soc/qcom,msm-pcm-dtmf&quot;;
		L2_TLB_500 = &quot;/cpus/cpu@500/l2-tlb&quot;;
		L1_D_700 = &quot;/cpus/cpu@700/l1-dcache&quot;;
		nfc_clk_req_suspend = &quot;/soc/pinctrl@3400000/nfc/nfc_clk_req_suspend&quot;;
		csr = &quot;/soc/csr@6001000&quot;;
		gpu_cx_gdsc = &quot;/soc/qcom,gdsc@509106c&quot;;
		cont_splash_memory = &quot;/reserved-memory/cont_splash_region@9c000000&quot;;
		pm6150_tz = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,temp-alarm@2400&quot;;
		cci1_active = &quot;/soc/pinctrl@3400000/cci1_active&quot;;
		clock_videocc = &quot;/soc/qcom,videocc@ab00000&quot;;
		pm6150l_l6 = &quot;/soc/rpmh-regulator-ldoc6/regulator-pm6150l-l6&quot;;
		L5A = &quot;/soc/rpmh-regulator-ldoa5/regulator-pm6150-l5&quot;;
		qupv3_se1_spi_active = &quot;/soc/pinctrl@3400000/qupv3_se1_spi_pins/qupv3_se1_spi_active&quot;;
		gpu_bw_tbl = &quot;/soc/gpu-bw-tbl&quot;;
		dai_hdmi = &quot;/soc/qcom,msm-dai-q6-hdmi&quot;;
		funnel_modem_out_funnel_in1 = &quot;/soc/funnel@6832000/ports/port@0/endpoint&quot;;
		sdc2_data_off = &quot;/soc/pinctrl@3400000/sdc2_data_off&quot;;
		bcl_lvl0 = &quot;/soc/thermal-zones/pm6150-bcl-lvl0/trips/bcl-lvl0&quot;;
		slv_qhs_camera_rt_throttle_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-camera-rt-throttle-cfg&quot;;
		cpas_cdm_iova_mem_map = &quot;/soc/qcom,cam_smmu/msm_cam_smmu_cpas_cdm/iova-mem-map&quot;;
		fab_compute_noc = &quot;/soc/ad-hoc-bus/fab-compute_noc&quot;;
		cpucc_debug = &quot;/soc/syscon@182a0018&quot;;
		S2F = &quot;/soc/rpmh-regulator-smpf2/regulator-pm8009-s2&quot;;
		pm6150_clkdiv = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/clock-controller@5b00&quot;;
		wsa_macro = &quot;/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/wsa-macro@62f00000&quot;;
		tpda_llm_gold = &quot;/soc/tpda@78d0000&quot;;
		qupv3_se10_tx = &quot;/soc/pinctrl@3400000/qupv3_se10_4uart_pins/qupv3_se10_tx&quot;;
		replicator_qdss1 = &quot;/soc/replicator@604a000&quot;;
		L1C = &quot;/soc/rpmh-regulator-ldoc1/regulator-pm6150l-l1&quot;;
		cti1_swao = &quot;/soc/cti@6b05000&quot;;
		qupv3_se11_i2c_sleep = &quot;/soc/pinctrl@3400000/qupv3_se11_i2c_pins/qupv3_se11_i2c_sleep&quot;;
		tpdm_dl_center = &quot;/soc/tpdm@6c28000&quot;;
		smp2p_qvrexternal5_out = &quot;/soc/qcom,smp2p-cdsp/qcom,smp2p-qvrexternal5-out&quot;;
		mnoc_sf_0_tbu = &quot;/soc/apps-smmu@0x15000000/mnoc_sf_0_tbu@0x15195000&quot;;
		pm6150l_switch2 = &quot;/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,led_switch_2&quot;;
		qcom_tzlog = &quot;/soc/tz-log@146aa720&quot;;
		msm_gpu = &quot;/soc/qcom,kgsl-3d0@5000000&quot;;
		sde_dp_usbplug_cc_active = &quot;/soc/pinctrl@3400000/sde_dp_usbplug_cc_active&quot;;
		bcm_mm3_display = &quot;/soc/ad-hoc-bus/bcm-mm3_display&quot;;
		gmu_user = &quot;/soc/qcom,gmu@506a000/gmu_user&quot;;
		gpu_gx_sw_reset = &quot;/soc/syscon@0x5091008&quot;;
		qupv3_se0_i2c_active = &quot;/soc/pinctrl@3400000/qupv3_se0_i2c_pins/qupv3_se0_i2c_active&quot;;
		tpdm_swao0 = &quot;/soc/tpdm@6b02000&quot;;
		L4A = &quot;/soc/rpmh-regulator-ldoa4/regulator-pm6150-l4&quot;;
		mas_qxm_venus1 = &quot;/soc/ad-hoc-bus/mas-qxm-venus1&quot;;
		int_fm_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-rx&quot;;
		tpda_olc_in_tpdm_olc = &quot;/soc/tpda@7832000/ports/port@1/endpoint&quot;;
		L1_ITLB_700 = &quot;/cpus/cpu@700/l1-itlb&quot;;
		modem_trip1_hvx_trip = &quot;/soc/thermal-zones/quiet-therm-step/trips/modem-trip1-hvx-trip&quot;;
		ext_disp_audio_codec = &quot;/soc/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx&quot;;
		cam_csiphy1 = &quot;/soc/qcom,csiphy@ace2000&quot;;
		qupv3_se10_rts = &quot;/soc/pinctrl@3400000/qupv3_se10_4uart_pins/qupv3_se10_rts&quot;;
		hdmi_dba = &quot;/soc/qcom,msm-hdmi-dba-codec-rx&quot;;
		cpu4_config = &quot;/soc/thermal-zones/cpu-0-4-step/trips/cpu4-config&quot;;
		clock_rpmh = &quot;/soc/qcom,rpmh&quot;;
		tpda_in_tpdm_qdss = &quot;/soc/tpda@6004000/ports/port@14/endpoint&quot;;
		slv_qhs_vsense_ctrl_cfg = &quot;/soc/ad-hoc-bus/slv-qhs-vsense-ctrl-cfg&quot;;
		incall_music_2_rx = &quot;/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-2-rx&quot;;
		qupv3_se10_spi_pins = &quot;/soc/pinctrl@3400000/qupv3_se10_spi_pins&quot;;
		qupv3_se6_spi_active = &quot;/soc/pinctrl@3400000/qupv3_se6_spi_pins/qupv3_se6_spi_active&quot;;
		S1F = &quot;/soc/rpmh-regulator-smpf1/regulator-pm8009-s1&quot;;
		qupv3_se6_i2c_pins = &quot;/soc/pinctrl@3400000/qupv3_se6_i2c_pins&quot;;
		etm3_out_funnel_apss = &quot;/soc/etm@7340000/port/endpoint&quot;;
		i2c_freq_1Mhz_cci1 = &quot;/soc/qcom,cci@ac4b000/qcom,i2c_fast_plus_mode&quot;;
		pcm_noirq = &quot;/soc/qcom,msm-pcm-dsp-noirq&quot;;
		cti12 = &quot;/soc/cti@601c000&quot;;
		dai_mi2s1 = &quot;/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-sec&quot;;
		modem_trip0 = &quot;/soc/thermal-zones/quiet-therm-step/trips/modem-trip0&quot;;
		pil_modem = &quot;/soc/qcom,mss@4080000&quot;;
		qupv3_se1_spi_pins = &quot;/soc/pinctrl@3400000/qupv3_se1_spi_pins&quot;;
		cci2_suspend = &quot;/soc/pinctrl@3400000/cci2_suspend&quot;;
		icnss = &quot;/soc/qcom,icnss@18800000&quot;;
		ipa_smmu_wlan = &quot;/soc/ipa_smmu_wlan&quot;;
		mvsc_gdsc = &quot;/soc/qcom,gdsc@0b00814&quot;;
		modem_current = &quot;/soc/qmi-tmd-devices/modem/modem_current&quot;;
		bcm_sh8 = &quot;/soc/ad-hoc-bus/bcm-sh8&quot;;
		tpdm_llm_silver = &quot;/soc/tpdm@78a0000&quot;;
		bcm_acv_display = &quot;/soc/ad-hoc-bus/bcm-acv_display&quot;;
		tmc_etf_swao_in_funnel_swao = &quot;/soc/tmc@6b09000/ports/port@1/endpoint&quot;;
		cci2_active = &quot;/soc/pinctrl@3400000/cci2_active&quot;;
		wcd934x_mclk_default = &quot;/soc/qcom,spmi@c440000/qcom,pm6150@0/pinctrl@c000/wcd934x_mclk/wcd934x_mclk_default&quot;;
		L2_600 = &quot;/cpus/cpu@600/l2-cache&quot;;
		pm6150_l12 = &quot;/soc/rpmh-regulator-ldoa12/regulator-pm6150-l12&quot;;
		pm6150l_s2_level_ao = &quot;/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2-level-ao&quot;;
		mas_qhm_a1noc_cfg = &quot;/soc/ad-hoc-bus/mas-qhm-a1noc-cfg&quot;;
		qupv3_se8_2uart_active = &quot;/soc/pinctrl@3400000/qupv3_se8_2uart_pins/qupv3_se8_2uart_active&quot;;
		pil_camera_mem = &quot;/reserved-memory/camera_region@8ab00000&quot;;
		S3A_LEVEL_AO = &quot;/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3-level-ao&quot;;
		npu_trip0 = &quot;/soc/thermal-zones/npu-step/trips/npu-trip0&quot;;
		L3A = &quot;/soc/rpmh-regulator-ldoa3/regulator-pm6150-l3&quot;;
		tpdm_vsense = &quot;/soc/tpdm@6840000&quot;;
		bcm_sn12 = &quot;/soc/ad-hoc-bus/bcm-sn12&quot;;
		CPU1 = &quot;/cpus/cpu@100&quot;;
		pri_i2s_ws_sleep = &quot;/soc/pinctrl@3400000/pri_i2s_sck_ws/pri_i2s_ws_sleep&quot;;
		pm6150_trip0 = &quot;/soc/thermal-zones/pm6150-tz/trips/trip0&quot;;
		qupv3_se3_ctsrx = &quot;/soc/pinctrl@3400000/qupv3_se3_4uart_pins/qupv3_se3_ctsrx&quot;;
		cti_turing = &quot;/soc/cti@6867000&quot;;
	};

reserved-memory {
		#address-cells = &lt;0x02&gt;;
		#size-cells = &lt;0x02&gt;;
		ranges;
		phandle = &lt;0x4d7&gt;;

linux,cma {
			linux,cma-default;
			alignment = &lt;0x00 0x400000&gt;;
			alloc-ranges = &lt;0x00 0x00 0x00 0xffffffff&gt;;
			compatible = &quot;shared-dma-pool&quot;;
			size = &lt;0x00 0x2000000&gt;;
			reusable;
		};

pil_adsp_region@95700000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x95700000 0x00 0x2600000&gt;;
			phandle = &lt;0xa1&gt;;
			no-map;
		};

cdsp_region {
			alignment = &lt;0x00 0x400000&gt;;
			alloc-ranges = &lt;0x00 0x00 0x00 0xffffffff&gt;;
			compatible = &quot;shared-dma-pool&quot;;
			size = &lt;0x00 0x400000&gt;;
			phandle = &lt;0x1a4&gt;;
			reusable;
		};

xbl_aop_mem@85e00000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x85e00000 0x00 0x1ff000&gt;;
			phandle = &lt;0x4d9&gt;;
			no-map;
		};

cont_splash_region@9c000000 {
			label = &quot;cont_splash_region&quot;;
			reg = &lt;0x00 0x9c000000 0x00 0x1700000&gt;;
			phandle = &lt;0x4de&gt;;
		};

secure_display_region {
			alignment = &lt;0x00 0x400000&gt;;
			alloc-ranges = &lt;0x00 0x00 0x00 0xffffffff&gt;;
			compatible = &quot;shared-dma-pool&quot;;
			size = &lt;0x00 0x8c00000&gt;;
			phandle = &lt;0x1c3&gt;;
			reusable;
		};

adsp_region {
			alignment = &lt;0x00 0x400000&gt;;
			alloc-ranges = &lt;0x00 0x00 0x00 0xffffffff&gt;;
			compatible = &quot;shared-dma-pool&quot;;
			size = &lt;0x00 0xc00000&gt;;
			phandle = &lt;0x92&gt;;
			reusable;
		};

gpu_region@97f15000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x97f15000 0x00 0x2000&gt;;
			phandle = &lt;0x4dd&gt;;
			no-map;
		};

pil_video_region@93400000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x93400000 0x00 0x500000&gt;;
			phandle = &lt;0xb5&gt;;
			no-map;
		};

dfps_data_region@9d700000 {
			label = &quot;dfps_data_region&quot;;
			reg = &lt;0x00 0x9d700000 0x00 0x100000&gt;;
			phandle = &lt;0x1a5&gt;;
		};

smem@86000000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x86000000 0x00 0x200000&gt;;
			phandle = &lt;0x90&gt;;
			no-map;
		};

hyp_region@85700000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x85700000 0x00 0x600000&gt;;
			phandle = &lt;0x4d8&gt;;
			no-map;
		};

disp_rdump_region@9c000000 {
			label = &quot;disp_rdump_region&quot;;
			reg = &lt;0x00 0x9c000000 0x00 0x1800000&gt;;
			phandle = &lt;0x4df&gt;;
		};

cdsp_sec_regions@0x9f800000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x9f800000 0x00 0x1e00000&gt;;
			phandle = &lt;0x1c4&gt;;
			no-map;
		};

npu_region@97e80000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x97e80000 0x00 0x80000&gt;;
			phandle = &lt;0xb6&gt;;
			no-map;
		};

removed_region@86200000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x86200000 0x00 0x4900000&gt;;
			phandle = &lt;0x4db&gt;;
			no-map;
		};

qseecom_region@9e400000 {
			compatible = &quot;shared-dma-pool&quot;;
			reg = &lt;0x00 0x9e400000 0x00 0x1400000&gt;;
			phandle = &lt;0x9a&gt;;
			no-map;
		};

ramdump_fb_region@af000000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0xaf000000 0x00 0x1000000&gt;;
			phandle = &lt;0x59f&gt;;
			no-map;
		};

xbl_dump_mem@85d00000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x85d00000 0x00 0x100000&gt;;
			phandle = &lt;0x5a0&gt;;
			no-map;
		};

sec_apps_region@85fff000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x85fff000 0x00 0x1000&gt;;
			phandle = &lt;0x4da&gt;;
			no-map;
		};

sp_region {
			alignment = &lt;0x00 0x400000&gt;;
			alloc-ranges = &lt;0x00 0x00 0x00 0xffffffff&gt;;
			compatible = &quot;shared-dma-pool&quot;;
			size = &lt;0x00 0x800000&gt;;
			phandle = &lt;0x1c2&gt;;
			reusable;
		};

ips_fw_region@97f00000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x97f00000 0x00 0x10000&gt;;
			phandle = &lt;0xc9&gt;;
			no-map;
		};

qseecom_ta_region {
			alignment = &lt;0x00 0x400000&gt;;
			alloc-ranges = &lt;0x00 0x00 0x00 0xffffffff&gt;;
			compatible = &quot;shared-dma-pool&quot;;
			size = &lt;0x00 0x1000000&gt;;
			phandle = &lt;0x1c1&gt;;
			reusable;
		};

ipa_gsi_region@97f10000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x97f10000 0x00 0x5000&gt;;
			phandle = &lt;0x4dc&gt;;
			no-map;
		};

wlan_msa_region@97d00000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x97d00000 0x00 0x180000&gt;;
			phandle = &lt;0xb7&gt;;
			no-map;
		};

camera_region@8ab00000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x8ab00000 0x00 0x500000&gt;;
			phandle = &lt;0x1b6&gt;;
			no-map;
		};

modem_region@8b000000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x8b000000 0x00 0x8400000&gt;;
			phandle = &lt;0xb1&gt;;
			no-map;
		};

cdsp_regions@93900000 {
			compatible = &quot;removed-dma-pool&quot;;
			reg = &lt;0x00 0x93900000 0x00 0x1e00000&gt;;
			phandle = &lt;0xad&gt;;
			no-map;
		};

mem_dump_region {
			compatible = &quot;shared-dma-pool&quot;;
			size = &lt;0x00 0x2400000&gt;;
			phandle = &lt;0x53&gt;;
			reusable;
		};
	};

memory {
		ddr_device_type = &lt;0x07&gt;;
		device_type = &quot;memory&quot;;
		reg = &lt;0x00 0x80000000 0x01 0x00 0x01 0x80000000 0x00 0xfbb00000&gt;;
	};
};

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