Starting C simulation ...
C:/Xilinx/Vitis_HLS/2022.2/bin/vitis_hls.bat C:/Users/Alex/Documents/VitisHls/Task_1/solution1/csim.tcl
INFO: [HLS 200-10] Running 'C:/Xilinx/Vitis_HLS/2022.2/bin/unwrapped/win64.o/vitis_hls.exe'
INFO: [HLS 200-10] For user 'Alex' on host 'desktop-8m0u2qg' (Windows NT_amd64 version 6.2) on Wed Nov 16 11:56:03 +0200 2022
INFO: [HLS 200-10] In directory 'C:/Users/Alex/Documents/VitisHls'
Sourcing Tcl script 'C:/Users/Alex/Documents/VitisHls/Task_1/solution1/csim.tcl'
INFO: [HLS 200-1510] Running: source C:/Users/Alex/Documents/VitisHls/Task_1/solution1/csim.tcl
INFO: [HLS 200-1510] Running: open_project Task_1
INFO: [HLS 200-10] Opening project 'C:/Users/Alex/Documents/VitisHls/Task_1'.
INFO: [HLS 200-1510] Running: set_top do_for_hw
INFO: [HLS 200-1510] Running: add_files ../ClionProjects/VitisHls/Task_1/do_for.cpp
INFO: [HLS 200-10] Adding design file '../ClionProjects/VitisHls/Task_1/do_for.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb ../ClionProjects/VitisHls/Task_1/do_for_tests.cpp
INFO: [HLS 200-10] Adding test bench file '../ClionProjects/VitisHls/Task_1/do_for_tests.cpp' to the project
INFO: [HLS 200-1510] Running: open_solution solution1 -flow_target vivado
INFO: [HLS 200-10] Opening solution 'C:/Users/Alex/Documents/VitisHls/Task_1/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-1611] Setting target device to 'xc7z020-clg400-1'
INFO: [HLS 200-1505] Using flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2022.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xc7z020clg400-1
INFO: [HLS 200-1510] Running: create_clock -period 10 -name default
INFO: [HLS 200-1510] Running: csim_design -quiet
Running Dispatch Server on port: 51673
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
make: 'csim.exe' is up to date.
************************************************************
Running three of the loop in hardware
Final int = 1953125000
************************************************************
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 3.77 seconds; current allocated memory: 0.203 MB.
INFO: [HLS 200-112] Total CPU user time: 4 seconds. Total CPU system time: 1 seconds. Total elapsed time: 17.677 seconds; peak allocated memory: 574.977 MB.
Finished C simulation.
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