- module file1( input clock ,
- output reg divided_clock = 0 ,
- output divided_clock_2 ,
- // input reset,
- output reg [5:0] d1 =6'b000000,//changed 6'b000000
- output reg minutes_clock = 0 ,
- output reg [3:0] d0 =4'b0000 ,//chaged 4'b0000
- output reg minutes_counter = 0,
- output reg hours_clock = 0 ,
- output reg [5:0]hours_counter = 6'b000000,//6'b000000
- //output reg more_hours_counter = 0
- output reg [3:0] d2 =4'b0000,// changed 4'b0000
- output reg [3:0] d3 =4'b0000, //changed 4'b0000
- output reg [3:0] d4 =4'b0000,
- output [3:0] x,
- output [7:0] y
- );
- integer counter = 0;
- sevenseg uut ( .clock(clock),
- .divided_clock(divided_clock),
- .divided_clock_2(divided_clock_2),
- .d0(d0),
- .d2(d2),
- .d3(d3),
- .d4(d4),
- .x(x),
- .y(y)
- );
- always @(posedge clock)
- begin
- if(counter == 62000)
- counter<=0;
- else
- counter <= counter+1;
- if(counter == 0)
- divided_clock <= ~divided_clock;
- else
- divided_clock <= divided_clock;
- end
- reg h = 0 ;
- always@(posedge divided_clock)
- begin
- if(d1 == 6'b111011)
- d1<=6'b0;
- else
- d1<=d1+4'b0001;
- minutes_clock <= (d1 == 6'b111011)?1'b1:1'b0;
- end
- always@(posedge minutes_clock)
- begin
- if(d0 == 4'b1001)
- d0 <= 4'b0000 ;
- else
- d0 <= d0+4'b0001;
- minutes_counter <= (d0 == 4'b1001)?1'b1:1'b0;
- end
- always@(posedge minutes_counter)
- begin
- if(d2 == 4'b0101 && d0 == 4'b1001)
- d2<= 4'b0000 ;
- else
- d2<= d2+4'b0001;
- end
- always@(posedge minutes_clock)
- begin
- if(hours_counter == 6'b111011)
- hours_counter <=6'b0;
- else
- hours_counter<=hours_counter+6'b000001;
- hours_clock <= (hours_counter>= 6'b111011)?1'b1:1'b0;
- end
- always@(posedge hours_clock)
- begin
- if(d4 == 4'b0010)
- begin
- if(d3 == 4'b0100)
- begin
- d3 <= 4'b0000;
- d4 <= 4'b0000;
- end
- else
- d3 <= d3+4'b0001;
- end
- else
- begin
- if(d3 == 4'b1001)
- begin
- d3 <=0 ;
- d4<=d4+4'b0001;
- end
- else
- d3 <=d3+4'b0001;
- end
- end
- always@(posedge divided_clock )
- begin
- h = ~h;
- end
- endmodule
- module sevenseg(
- input clock,
- input divided_clock,
- output reg divided_clock_2 = 0,
- input [3:0]d0,
- input [3:0]d2,
- input [3:0]d3,
- input [3:0]d4,
- output reg[3:0]x = 4'b1110,
- output reg[7:0]y = 8'b11111111
- );
- integer counter = 0 ;
- reg [3:0] digit;
- reg [1:0]refresh_rate_counter = 2'b00 ;
- reg [3:0] dig =4'b0000;
- always @(posedge clock)
- begin
- if(counter == 2048)
- counter<=0;
- else
- counter <= counter+1;
- // 12499999;
- if(counter == 0)
- divided_clock_2 <= ~divided_clock_2;
- else
- divided_clock_2 <= divided_clock_2;
- end
- always@(posedge divided_clock_2)
- begin
- refresh_rate_counter <= refresh_rate_counter+2'b01;
- end
- always@(refresh_rate_counter)
- begin
- case(refresh_rate_counter)
- 2'b00: x = 4'b1110;
- 2'b01: x = 4'b1101;
- 2'b10: x = 4'b1011;
- 2'b11: x = 4'b0111;
- endcase
- end
- always@(refresh_rate_counter , d0 , d2, d3 , d4)
- begin
- case(refresh_rate_counter)
- 2'b00: digit = d0;
- 2'b01: digit = d2;
- 2'b10: digit = d3;
- 2'b11: digit = d4;
- endcase
- end
- always@(digit,x,y,divided_clock)
- begin
- if(x == 4'b1011)
- begin
- case(digit)
- 4'b0000: y = {7'b0000001, divided_clock};
- 4'b0001: y = {7'b1001111, divided_clock};
- 4'b0010: y = {7'b0010010, divided_clock};
- 4'b0011: y = {7'b0000110, divided_clock};
- 4'b0100: y = {7'b1001100, divided_clock};
- 4'b0101: y = {7'b0100100, divided_clock};
- 4'b0110: y = {7'b0100000, divided_clock};
- 4'b0111: y = {7'b0001111, divided_clock};
- 4'b1000: y = {7'b0000000, divided_clock};
- 4'b1001: y = {7'b0000100, divided_clock};
- default y = {7'b1111111, divided_clock};
- endcase
- end
- else
- begin
- case(digit)
- 4'b0000: y = 8'b00000011;
- 4'b0001: y = 8'b10011111;
- 4'b0010: y = 8'b00100101;
- 4'b0011: y = 8'b00001101;
- 4'b0100: y = 8'b10011001;
- 4'b0101: y = 8'b01001001;
- 4'b0110: y = 8'b01000001;
- 4'b0111: y = 8'b00011111;
- 4'b1000: y = 8'b00000001;
- 4'b1001: y = 8'b00001001;
- default y = 8'b11111111;
- endcase
- end
- end
- endmodule