1. module file1( input clock ,
2. output reg divided_clock = 0 ,
3. output divided_clock_2 ,
4. // input reset,
5. output reg [5:0] d1 =6'b000000,//changed 6'b000000
6. output reg minutes_clock = 0 ,
7. output reg [3:0] d0 =4'b0000 ,//chaged 4'b0000
8. output reg minutes_counter = 0,
9. output reg hours_clock = 0 ,
10. output reg [5:0]hours_counter = 6'b000000,//6'b000000
11. //output reg more_hours_counter = 0
12. output reg [3:0] d2 =4'b0000,// changed 4'b0000
13. output reg [3:0] d3 =4'b0000, //changed 4'b0000
14. output reg [3:0] d4 =4'b0000,
15. output [3:0] x,
16. output [7:0] y
17. );
18. integer counter = 0;
19. sevenseg uut ( .clock(clock),
20. .divided_clock(divided_clock),
21. .divided_clock_2(divided_clock_2),
22. .d0(d0),
23. .d2(d2),
24. .d3(d3),
25. .d4(d4),
26. .x(x),
27. .y(y)
28. );
29. always @(posedge clock)
30. begin
31.  
32. if(counter == 62000)
33. counter<=0;
34. else
35. counter <= counter+1;
36.  
37. if(counter == 0)
38. divided_clock <= ~divided_clock;
39. else
40. divided_clock <= divided_clock;
41. end
42.  
43. reg h = 0 ;
44. always@(posedge divided_clock)
45. begin
46. if(d1 == 6'b111011)
47. d1<=6'b0;
48. else
49. d1<=d1+4'b0001;
50. minutes_clock <= (d1 == 6'b111011)?1'b1:1'b0;
51. end
52. always@(posedge minutes_clock)
53. begin
54. if(d0 == 4'b1001)
55. d0 <= 4'b0000 ;
56. else
57. d0 <= d0+4'b0001;
58. minutes_counter <= (d0 == 4'b1001)?1'b1:1'b0;
59. end
60. always@(posedge minutes_counter)
61. begin
62. if(d2 == 4'b0101 && d0 == 4'b1001)
63. d2<= 4'b0000 ;
64. else
65. d2<= d2+4'b0001;
66. end
67. always@(posedge minutes_clock)
68. begin
69. if(hours_counter == 6'b111011)
70. hours_counter <=6'b0;
71. else
72. hours_counter<=hours_counter+6'b000001;
73. hours_clock <= (hours_counter>= 6'b111011)?1'b1:1'b0;
74. end
75. always@(posedge hours_clock)
76. begin
77. if(d4 == 4'b0010)
78. begin
79. if(d3 == 4'b0100)
80. begin
81. d3 <= 4'b0000;
82. d4 <= 4'b0000;
83. end
84. else
85. d3 <= d3+4'b0001;
86. end
87. else
88. begin
89. if(d3 == 4'b1001)
90. begin
91. d3 <=0 ;
92. d4<=d4+4'b0001;
93. end
94. else
95. d3 <=d3+4'b0001;
96. end
97. end
98. always@(posedge divided_clock )
99. begin
100. h = ~h;
101. end
102.  
103. endmodule
104.  
105.  
106. module sevenseg(
107. input clock,
108. input divided_clock,
109. output reg divided_clock_2 = 0,
110. input [3:0]d0,
111. input [3:0]d2,
112. input [3:0]d3,
113. input [3:0]d4,
114. output reg[3:0]x = 4'b1110,
115. output reg[7:0]y = 8'b11111111
116. );
117. integer counter = 0 ;
118. reg [3:0] digit;
119. reg [1:0]refresh_rate_counter = 2'b00 ;
120. reg [3:0] dig =4'b0000;
121. always @(posedge clock)
122. begin
123. if(counter == 2048)
124. counter<=0;
125. else
126. counter <= counter+1;
127. // 12499999;
128. if(counter == 0)
129. divided_clock_2 <= ~divided_clock_2;
130. else
131. divided_clock_2 <= divided_clock_2;
132. end
133. always@(posedge divided_clock_2)
134. begin
135. refresh_rate_counter <= refresh_rate_counter+2'b01;
136. end
137. always@(refresh_rate_counter)
138. begin
139. case(refresh_rate_counter)
140. 2'b00: x = 4'b1110;
141. 2'b01: x = 4'b1101;
142. 2'b10: x = 4'b1011;
143. 2'b11: x = 4'b0111;
144. endcase
145. end
146. always@(refresh_rate_counter , d0 , d2, d3 , d4)
147. begin
148. case(refresh_rate_counter)
149. 2'b00: digit = d0;
150. 2'b01: digit = d2;
151. 2'b10: digit = d3;
152. 2'b11: digit = d4;
153. endcase
154. end
155. always@(digit,x,y,divided_clock)
156. begin
157. if(x == 4'b1011)
158. begin
159. case(digit)
160. 4'b0000: y = {7'b0000001, divided_clock};
161. 4'b0001: y = {7'b1001111, divided_clock};
162. 4'b0010: y = {7'b0010010, divided_clock};
163. 4'b0011: y = {7'b0000110, divided_clock};
164. 4'b0100: y = {7'b1001100, divided_clock};
165. 4'b0101: y = {7'b0100100, divided_clock};
166. 4'b0110: y = {7'b0100000, divided_clock};
167. 4'b0111: y = {7'b0001111, divided_clock};
168. 4'b1000: y = {7'b0000000, divided_clock};
169. 4'b1001: y = {7'b0000100, divided_clock};
170. default y = {7'b1111111, divided_clock};
171. endcase
172. end
173. else
174. begin
175. case(digit)
176. 4'b0000: y = 8'b00000011;
177. 4'b0001: y = 8'b10011111;
178. 4'b0010: y = 8'b00100101;
179. 4'b0011: y = 8'b00001101;
180. 4'b0100: y = 8'b10011001;
181. 4'b0101: y = 8'b01001001;
182. 4'b0110: y = 8'b01000001;
183. 4'b0111: y = 8'b00011111;
184. 4'b1000: y = 8'b00000001;
185. 4'b1001: y = 8'b00001001;
186. default y = 8'b11111111;
187. endcase
188. end
189. end
190. endmodule
191.  
192.