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From Cute Macaw, 5 Years ago, written in Plain Text.
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4. entity comparator2 is
  5. port(a,b: in std_logic_vector(1 downto 0);
  6.      ut_a, ut_b, ut_c, ut_d, ut_e, ut_f, ut_g:out std_logic);
  7.  end comparator2;
  8.  
  9.  architecture Expression of comparator2 is
  10.  begin
  11.  ut_e <= ((not(b(1))) and (a(0))) or ((not(b(1))) and (a(1))) or ((a(0)) and (a(1))) or ((not(b(1))) and (not(b(0)))) or ((b(1)) and (a(1)) and (not(b(0))));
  12.  
  13.  ut_c <= ((not(a(1))) and (b(1))) or ((not(a(1))) and (b(0))) or ((not(a(1))) and (not(a(0)))) or ((b(1)) and (b(0))) or ((b(1)) and (a(1)) and (not(a(0))));
  14.  
  15.  ut_g <= '0';
  16.  ut_d <= '0';
  17.  ut_a <= '1';
  18.  ut_b <= '1';
  19.  ut_f <= '1';
  20.  
  21.  end Expression;
  22.