Facebook
From Speedy Sheep, 8 Months ago, written in Plain Text.
Embed
Download Paste or View Raw
Hits: 95
  1. --------------------------------------------------------------------------------
  2.  
  3. -- Company:
  4.  
  5. -- Engineer:
  6.  
  7. --
  8.  
  9. -- Create Date:   15:08:17 03/03/2018
  10.  
  11. -- Design Name:  
  12.  
  13. -- Module Name:   C:/Users/Janek/Desktop/iup4/iup4/d_test.vhd
  14.  
  15. -- Project Name:  iup4
  16.  
  17. -- Target Device:  
  18.  
  19. -- Tool versions:  
  20.  
  21. -- Description:  
  22.  
  23. --
  24.  
  25. -- VHDL Test Bench Created by ISE for module: dff
  26.  
  27. --
  28.  
  29. -- Dependencies:
  30.  
  31. --
  32.  
  33. -- Revision:
  34.  
  35. -- Revision 0.01 - File Created
  36.  
  37. -- Additional Comments:
  38.  
  39. --
  40.  
  41. -- Notes:
  42.  
  43. -- This testbench has been automatically generated using types std_logic and
  44.  
  45. -- std_logic_vector for the ports of the unit under test.  Xilinx recommends
  46.  
  47. -- that these types always be used for the top-level I/O of a design in order
  48.  
  49. -- to guarantee that the testbench will bind correctly to the post-implementation
  50.  
  51. -- simulation model.
  52.  
  53. --------------------------------------------------------------------------------
  54.  
  55. LIBRARY ieee;
  56.  
  57. USE ieee.std_logic_1164.ALL;
  58.  
  59.  
  60.  
  61. -- Uncomment the following library declaration if using
  62.  
  63. -- arithmetic functions with Signed or Unsigned values
  64.  
  65. --USE ieee.numeric_std.ALL;
  66.  
  67.  
  68.  
  69. ENTITY d_test IS
  70.  
  71. END d_test;
  72.  
  73.  
  74.  
  75. ARCHITECTURE behavior OF d_test IS
  76.  
  77.  
  78.  
  79.     -- Component Declaration for the Unit Under Test (UUT)
  80.  
  81.  
  82.  
  83.     COMPONENT dff
  84.  
  85.     PORT(
  86.  
  87.          rst : IN  std_logic;
  88.  
  89.          d : IN  std_logic;
  90.  
  91.          clk : IN  std_logic;
  92.  
  93.          outd : OUT  std_logic
  94.  
  95.         );
  96.  
  97.     END COMPONENT;
  98.  
  99.    
  100.  
  101.  
  102.  
  103.    --Inputs
  104.  
  105.    signal rst : std_logic := '0';
  106.  
  107.    signal d : std_logic := '0';
  108.  
  109.    signal clk : std_logic := '0';
  110.  
  111.  
  112.  
  113.         --Outputs
  114.  
  115.    signal outd : std_logic;
  116.  
  117.  
  118.  
  119.    -- Clock period definitions
  120.  
  121.    constant clk_period : time := 100 ns;
  122.  
  123.  
  124.  
  125. BEGIN
  126.  
  127.  
  128.  
  129.         -- Instantiate the Unit Under Test (UUT)
  130.  
  131.    uut: dff PORT MAP (
  132.  
  133.           rst => rst,
  134.  
  135.           d => d,
  136.  
  137.           clk => clk,
  138.  
  139.           outd => outd
  140.  
  141.         );
  142.  
  143.  
  144.  
  145.    -- Clock process definitions
  146.  
  147.    clk_process :process
  148.  
  149.    begin
  150.  
  151.                 clk <= '0';
  152.  
  153.                 wait for clk_period/2;
  154.  
  155.                 clk <= '1';
  156.  
  157.                 wait for clk_period/2;
  158.  
  159.    end process;
  160.  
  161.  
  162.  
  163.  
  164.  
  165.    -- Stimulus process
  166.  
  167.    stim_proc: process
  168.  
  169.    begin               
  170.  
  171.       -- hold reset state for 100 ns.
  172.  
  173.       wait for 100 ns; 
  174.  
  175.  
  176.  
  177.       --wait for clk_period*10;
  178.  
  179.                 d <= '1';
  180.  
  181.                
  182.  
  183.                 wait for 305 ns;
  184.  
  185.                
  186.  
  187.                 rst <= '1';
  188.  
  189.                
  190.  
  191.                 wait for 20 ns;
  192.  
  193.                
  194.  
  195.                 rst <= not rst;
  196.  
  197.                
  198.  
  199.                 wait for 80 ns;
  200.  
  201.                 d <= '0';
  202.  
  203.       -- insert stimulus here
  204.  
  205.  
  206.  
  207.       wait;
  208.  
  209.    end process;
  210.  
  211.  
  212.  
  213. END;
  214.  
  215.