1. Starting C/RTL cosimulation ...
2. C:/Xilinx/Vitis_HLS/2022.2/bin/vitis_hls.bat C:/Users/Alex/Documents/VitisHls/Task_1/solution1/cosim.tcl
3. INFO: [HLS 200-10] Running 'C:/Xilinx/Vitis_HLS/2022.2/bin/unwrapped/win64.o/vitis_hls.exe'
4. INFO: [HLS 200-10] For user 'Alex' on host 'desktop-8m0u2qg' (Windows NT_amd64 version 6.2) on Wed Nov 16 12:00:15 +0200 2022
5. INFO: [HLS 200-10] In directory 'C:/Users/Alex/Documents/VitisHls'
6. Sourcing Tcl script 'C:/Users/Alex/Documents/VitisHls/Task_1/solution1/cosim.tcl'
7. INFO: [HLS 200-1510] Running: source C:/Users/Alex/Documents/VitisHls/Task_1/solution1/cosim.tcl
8. INFO: [HLS 200-1510] Running: open_project Task_1
9. INFO: [HLS 200-10] Opening project 'C:/Users/Alex/Documents/VitisHls/Task_1'.
10. INFO: [HLS 200-1510] Running: set_top do_for_hw
11. INFO: [HLS 200-1510] Running: add_files ../ClionProjects/VitisHls/Task_1/do_for.cpp
12. INFO: [HLS 200-10] Adding design file '../ClionProjects/VitisHls/Task_1/do_for.cpp' to the project
13. INFO: [HLS 200-1510] Running: add_files -tb ../ClionProjects/VitisHls/Task_1/do_for_tests.cpp
14. INFO: [HLS 200-10] Adding test bench file '../ClionProjects/VitisHls/Task_1/do_for_tests.cpp' to the project
15. INFO: [HLS 200-1510] Running: open_solution solution1 -flow_target vivado
16. INFO: [HLS 200-10] Opening solution 'C:/Users/Alex/Documents/VitisHls/Task_1/solution1'.
17. INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
18. INFO: [HLS 200-1611] Setting target device to 'xc7z020-clg400-1'
19. INFO: [HLS 200-1505] Using flow_target 'vivado'
20. Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2022.2;t=hls+guidance;d=200-1505.html
21. INFO: [HLS 200-1510] Running: set_part xc7z020clg400-1
22. INFO: [HLS 200-1510] Running: create_clock -period 10 -name default
23. INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
24. INFO: [HLS 200-1510] Running: cosim_design -rtl vhdl
25. Running Dispatch Server on port: 51697
26. INFO: [COSIM 212-47] Using XSIM for RTL simulation.
27. INFO: [COSIM 212-14] Instrumenting C test bench ...
28.    Build using "C:/Xilinx/Vitis_HLS/2022.2/tps/win64/msys64/mingw64/bin/g++"
29.    Compiling do_for_tests.cpp_pre.cpp.tb.cpp
30.    Compiling apatb_do_for_hw.cpp
31.    Compiling do_for.cpp_pre.cpp.tb.cpp
32.    Compiling apatb_do_for_hw_ir.ll
33.    Generating cosim.tv.exe
34. INFO: [COSIM 212-302] Starting C TB testing ...
35. ************************************************************
36. Running three of the loop in hardware
37. Final int = 1953125000
38. ************************************************************
39. INFO: [COSIM 212-333] Generating C post check test bench ...
40. INFO: [COSIM 212-12] Generating RTL test bench ...
41. INFO: [COSIM 212-1] *** C/RTL co-simulation file generation completed. ***
42. INFO: [COSIM 212-322] Starting VHDL simulation.
43. INFO: [COSIM 212-15] Starting XSIM ...
44.  
45. C:UsersAlexDocumentsVitisHlsTask_1solution1simvhdl>set PATH=
46.  
47. C:UsersAlexDocumentsVitisHlsTask_1solution1simvhdl>call C:/Xilinx/Vivado/2022.2/bin/xelab xil_defaultlib.apatb_do_for_hw_top glbl -Oenable_linking_all_libraries  -prj do_for_hw.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims -L unisims_ver -L xpm  -L floating_point_v7_0_20 -L floating_point_v7_1_15 --lib "ieee_proposed=./ieee_proposed" -s do_for_hw  
48. Vivado Simulator v2022.2
49. Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
50. Running: C:/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe xil_defaultlib.apatb_do_for_hw_top glbl -Oenable_linking_all_libraries -prj do_for_hw.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims -L unisims_ver -L xpm -L floating_point_v7_0_20 -L floating_point_v7_1_15 --lib ieee_proposed=./ieee_proposed -s do_for_hw
51. Multi-threading is on. Using 2 slave threads.
52. Determining compilation order of HDL files.
53. INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/glbl.v" into library work
54. INFO: [VRFC 10-311] analyzing module glbl
55. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/AESL_sim_pkg.vhd" into library xil_defaultlib
56. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/do_for_hw.autotb.vhd" into library xil_defaultlib
57. INFO: [VRFC 10-3107] analyzing entity 'apatb_do_for_hw_top'
58. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/do_for_hw.vhd" into library xil_defaultlib
59. INFO: [VRFC 10-3107] analyzing entity 'do_for_hw'
60. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/do_for_hw_mul_32s_32s_32_2_1.vhd" into library xil_defaultlib
61. INFO: [VRFC 10-3107] analyzing entity 'do_for_hw_mul_32s_32s_32_2_1'
62. Starting static elaboration
63. Pass Through NonSizing Optimizer
64. Completed static elaboration
65. Starting simulation data flow analysis
66. Completed simulation data flow analysis
67. Time Resolution for simulation is 1ps
68. Compiling package std.standard
69. Compiling package std.textio
70. Compiling package ieee.std_logic_1164
71. Compiling package ieee.std_logic_arith
72. Compiling package ieee.std_logic_unsigned
73. Compiling package ieee.numeric_std
74. Compiling package ieee.std_logic_textio
75. Compiling module work.glbl
76. Compiling architecture behav of entity xil_defaultlib.do_for_hw_mul_32s_32s_32_2_1 [do_for_hw_mul_32s_32s_32_2_1(nu...]
77. Compiling architecture behav of entity xil_defaultlib.do_for_hw [do_for_hw_default]
78. Compiling architecture behav of entity xil_defaultlib.apatb_do_for_hw_top
79. Built simulation snapshot do_for_hw
80.  
81. ****** xsim v2022.2 (64-bit)
82.   **** SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
83.   **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
84.     ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
85.  
86. source xsim.dir/do_for_hw/xsim_script.tcl
87. # xsim {do_for_hw} -autoloadwcfg -tclbatch {do_for_hw.tcl}
88. Time resolution is 1 ps
89. source do_for_hw.tcl
90. ## run all
91. Note: simulation done!
92. Time: 265 ns  Iteration: 1  Process: /apatb_do_for_hw_top/generate_sim_done_proc  File: C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/do_for_hw.autotb.vhd
93. Failure: NORMAL EXIT (note: failure is to force the simulator to stop)
94. Time: 265 ns  Iteration: 1  Process: /apatb_do_for_hw_top/generate_sim_done_proc  File: C:/Users/Alex/Documents/VitisHls/Task_1/solution1/sim/vhdl/do_for_hw.autotb.vhd
95. $finish called at time : 265 ns
96. ## quit
97. INFO: [Common 17-206] Exiting xsim at Wed Nov 16 12:00:46 2022...
98. INFO: [COSIM 212-316] Starting C post checking ...
99. ************************************************************
100. Running three of the loop in hardware
101. Final int = 1953125000
102. ************************************************************
103. INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
104. INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
105. INFO: [HLS 200-111] Finished Command cosim_design CPU user time: 1 seconds. CPU system time: 0 seconds. Elapsed time: 17.567 seconds; current allocated memory: 5.863 MB.
106. INFO: [HLS 200-112] Total CPU user time: 4 seconds. Total CPU system time: 1 seconds. Total elapsed time: 31.507 seconds; peak allocated memory: 580.090 MB.
107. Finished C/RTL cosimulation