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Untitled safest cryptocurrency exchange

From Wet Lechwe, 4 Years ago, written in VHDL.
URL https://pastebin.pl/view/d9302dcf
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  1. library IEEE;
  2. use IEEE.std_logic_1164.ALL;
  3.  
  4. entity system_testbench is
  5. end entity system_testbench;
  6.  
  7. architecture behaviour of system_testbench is
  8. component system
  9. port (clk, reset, x : in std_logic;
  10. Y : out std_logic_vector (2 downto 0));
  11. end component;
  12.  
  13. signal clk, reset, x : std_logic;
  14. signal Y : std_logic_vector (2 downto 0);
  15.  
  16. begin
  17.  
  18. lb11: entity work.system
  19. port map (clk, reset, x, Y);
  20.  
  21. clk <= '0'after 0 ns,
  22. '1' after 5 ns when clk /= '1'
  23. else '0' after 5 ns;
  24.  
  25. reset <= '1' after 0 ns,
  26. '0' after 20 ns;
  27.  
  28. x <= '0' after 0 ns,
  29. '1' after 30 ns,
  30. '0' after 40 ns,
  31. '0' after 50 ns,
  32. '1' after 60 ns,
  33. '1' after 70 ns,
  34. '0' after 80 ns,
  35. '1' after 90 ns,
  36. '0' after 100 ns,
  37. '1' after 110 ns,
  38. '1' after 120 ns,
  39. '0' after 130 ns,
  40. '0' after 140 ns;
  41.  
  42. end architecture behaviour;
  43.  

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