1. rdAddr: process(resetAddrManager, RX_FRAMECLK_I)
2.   variable timer         : integer range 0 to RX_GB_READ_DLY;
3.     variable readAddress   : integer range 0 to  7;
4.  
5.  begin
6.  
7.   if resetAddrManager = '1' then
8.    readAddress    := 1;
9.    readRSM_s      <= e0_wait;
10.    timer          := 0;
11.    READY_O        <= '0';
12.    READ_ADDRESS_O <= (others => '0');
13.    
14.   elsif rising_edge(RX_FRAMECLK_I) then
15.  
16.      if RX_CLKEN_i = '1' then
17.     case readRSM_s is
18.    
19.      when e0_wait => if timer >= RX_GB_READ_DLY then
20.             readRSM_s <= e1_read;
21.            
22.            else
23.             timer := timer + 1;
24.            end if;
25.    
26.      when e1_read   => readAddress := readAddress + 1;
27.            if readAddress = 1 then  -- Ready after one full read to be sure that all register contains true data
28.               READY_O     <= '1';
29.            end if;
30.            
31.     end case;
32.    
33.     READ_ADDRESS_O  <= std_logic_Vector(to_unsigned(readAddress, 3));
34.    end if;
35.    
36.   end if;
37.  
38.  end process;